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DFCIR/DFCxx type system rework #12

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Muxianesty opened this issue Jun 21, 2024 · 1 comment
Open

DFCIR/DFCxx type system rework #12

Muxianesty opened this issue Jun 21, 2024 · 1 comment
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@Muxianesty
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enhancement New feature or request stage III For issues applicable to Stage III of the project

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@Muxianesty
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Current DFCIR/DFCxx type system doesn't fully support concepts like floating-point arithmetic, counters, memory access and many others. Its implementation is poorly implemented as well.

Further discussions required.
@Muxianesty Muxianesty added the enhancement New feature or request label Jun 21, 2024
@Muxianesty Muxianesty self-assigned this Jun 21, 2024
@Muxianesty
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At some point it is obvious this braindead approach of having custom latencies for combinational logic has to go.

  • AND - Logical conjunction
  • OR - Logical disjunction
  • XOR - Exclusive logical disjunction
  • NOT - Logical inversion

@Muxianesty Muxianesty changed the title [Utopia EDA Integration] DFCIR/DFCxx type system rework [Stage III] DFCIR/DFCxx type system rework Jun 28, 2024
@Muxianesty Muxianesty changed the title [Stage III] DFCIR/DFCxx type system rework DFCIR/DFCxx type system rework Jun 28, 2024
@Muxianesty Muxianesty added the stage III For issues applicable to Stage III of the project label Jun 28, 2024
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@Muxianesty Muxianesty

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enhancement New feature or request stage III For issues applicable to Stage III of the project
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@Muxianesty