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Fragment or parameterize DFCxx -> SystemVerilog translation pipeline #23

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Muxianesty opened this issue Jun 28, 2024 · 1 comment
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Fragment or parameterize DFCxx -> SystemVerilog translation pipeline #23

Muxianesty opened this issue Jun 28, 2024 · 1 comment
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Currently the process of translating a top-level DFCxx kernel is hidden behind .compile-method. All optimizations, as well as scheduling, cannot be accessed without calling .compile-method.
In #22 it was proposed to add more output formats, so DFCxx -> SystemVerilog translation pipeline has to be either fragmented or parametrizable to produce different artifacts.
@Muxianesty Muxianesty added the enhancement New feature or request label Jun 28, 2024
@Muxianesty Muxianesty self-assigned this Jun 28, 2024
@Muxianesty Muxianesty mentioned this issue Jun 28, 2024
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@ssmolov ssmolov changed the title Fragment or parametrize DFCxx -> SystemVerilog translation pipeline Fragment or parameterize DFCxx -> SystemVerilog translation pipeline Jul 1, 2024
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Closed with #24.

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