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VHDL output format #28

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Muxianesty opened this issue Jul 1, 2024 · 2 comments
Closed

VHDL output format #28

Muxianesty opened this issue Jul 1, 2024 · 2 comments
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@Muxianesty
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enhancement New feature or request reopen later Reopen when needed

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Separate issue for VHDL output format, mentioned in #22.
@Muxianesty Muxianesty added enhancement New feature or request stage II For issues applicable to Stage II of the project labels Jul 1, 2024
@Muxianesty Muxianesty self-assigned this Jul 1, 2024
@Muxianesty Muxianesty mentioned this issue Aug 2, 2024
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Currently VHDL cannot be generated via CIRCT. This issue is deemed to be removed from stage II of the plan.

@Muxianesty Muxianesty removed the stage II For issues applicable to Stage II of the project label Aug 2, 2024
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Closed until further notice.

@Muxianesty Muxianesty closed this as not planned Won't fix, can't repro, duplicate, stale Aug 2, 2024
@Muxianesty Muxianesty added the reopen later Reopen when needed label Aug 6, 2024
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