Fix neg and not opts.

Author: jacobly0

llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp

@@ -104,8 +104,8 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
       .clampScalar(1, s8, sMax);
 
   getActionDefinitionsBuilder({G_ADD, G_SUB})
-      .legalFor(LegalScalars)
-      .customFor({s32, s64})
+      .legalFor({s8})
+      .customFor(LegalLibcallScalars)
       .clampScalar(0, s8, sMax);
 
   getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE,
@@ -288,14 +288,18 @@ Z80LegalizerInfo::legalizeAddSub(LegalizerHelper &Helper, MachineInstr &MI,
                                  LostDebugLocObserver &LocObserver) const {
   assert((MI.getOpcode() == G_ADD || MI.getOpcode() == G_SUB) &&
          "Unexpected opcode");
+  Function &F = Helper.MIRBuilder.getMF().getFunction();
   MachineRegisterInfo &MRI = *Helper.MIRBuilder.getMRI();
   Register DstReg = MI.getOperand(0).getReg();
   LLT LLTy = MRI.getType(DstReg);
+  unsigned Size = LLTy.getSizeInBits();
+  bool LegalSize = Size == 16 || (Subtarget.is24Bit() && Size == 24);
   Register LHSReg;
   if (mi_match(MI, MRI, m_Neg(m_Reg(LHSReg)))) {
-    auto &Ctx = Helper.MIRBuilder.getMF().getFunction().getContext();
+    if (!F.hasOptSize() && LegalSize)
+      return LegalizerHelper::Legalized;
+    auto &Ctx = F.getContext();
     RTLIB::Libcall Libcall;
-    unsigned Size = LLTy.getSizeInBits();
     switch (Size) {
     case 16:
       Libcall = RTLIB::NEG_I16;
@@ -318,6 +322,8 @@ Z80LegalizerInfo::legalizeAddSub(LegalizerHelper &Helper, MachineInstr &MI,
     MI.eraseFromParent();
     return LegalizerHelper::Legalized;
   }
+  if (LegalSize)
+    return LegalizerHelper::Legalized;
   return Helper.libcall(MI, LocObserver);
 }
 
@@ -327,18 +333,26 @@ Z80LegalizerInfo::legalizeBitwise(LegalizerHelper &Helper, MachineInstr &MI,
   assert((MI.getOpcode() == G_AND || MI.getOpcode() == G_OR ||
           MI.getOpcode() == G_XOR) &&
          "Unexpected opcode");
+  Function &F = Helper.MIRBuilder.getMF().getFunction();
+  bool OptSize = F.hasOptSize();
   MachineRegisterInfo &MRI = *Helper.MIRBuilder.getMRI();
   Register DstReg = MI.getOperand(0).getReg();
   LLT LLTy = MRI.getType(DstReg);
-  if (!MI.getParent()->getParent()->getFunction().hasOptSize() &&
-      LLTy == LLT::scalar(16))
+  if (!OptSize && LLTy == LLT::scalar(16))
     if (Helper.narrowScalar(MI, 0, LLT::scalar(8)) ==
         LegalizerHelper::Legalized)
       return LegalizerHelper::Legalized;
   Register LHSReg;
   if (mi_match(MI, MRI, m_Not(m_Reg(LHSReg)))) {
-    auto &Ctx = Helper.MIRBuilder.getMF().getFunction().getContext();
     unsigned Size = LLTy.getSizeInBits();
+    if (!OptSize && (Size == 16 || (Subtarget.is24Bit() && Size == 24))) {
+      Helper.MIRBuilder.buildSub(DstReg,
+                                 Helper.MIRBuilder.buildConstant(LLTy, -1),
+                                 MI.getOperand(1).getReg());
+      MI.eraseFromParent();
+      return LegalizerHelper::Legalized;
+    }
+    auto &Ctx = F.getContext();
     RTLIB::Libcall Libcall;
     switch (Size) {
     case 16:

llvm/lib/Target/Z80/Z80InstrInfo.td

@@ -400,7 +400,8 @@ let isMoveImm = 1, isReMaterializable = 1 in {
     def LD24r0  : Pseudo<"ld", "\t$dst, 0",  "",
                          (outs R24:$dst), (ins), [(set R24:$dst,  0)]>;
     def LD24r_1 : Pseudo<"ld", "\t$dst, -1", "",
-                         (outs R24:$dst), (ins), [(set R24:$dst, -1)]>;
+                         (outs R24:$dst), (ins), [(set R24:$dst,
+                                                       !sub(!shl(1, 24), 1))]>;
   }
   def LD8ri  : I8i <Idx0Pre, 0x06, "ld", "\t$dst, $src", "",
                     (outs  R8:$dst), (ins  i8imm:$src),