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RISC-V : Test every instructions in a same fashion as it was done for ARM #789

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clebreto opened this issue Apr 29, 2024 · 1 comment

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RISC-V : Test every instructions in a same fashion as it was done for ARM #789

clebreto opened this issue Apr 29, 2024 · 1 comment

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clebreto commented Apr 29, 2024

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Basic description of RISC-V32 I + M + ZIFENCEI ISA #698

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clebreto commented Apr 29, 2024 •

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add / intrinsic_add:
- Conditionals add do not exist, flags either
- We dont do these shifts: x = arg0 + (arg1 << 0); => asmgen: invalid rexpr for oprd (x11 <<32u ((8u) 0))
- Too large immediates used in intrinsics / or even through lowering are not captured by the compiler, only by llvm-mc:
  error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] addi ra, ra, -892679478

vbgl added the risc-v label

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