Improved config file; All common library files are in one location(data/); Clean up;

Author: judefdiv

Diff for: README.md

@@ -58,6 +58,20 @@ std blif (.blif) -> SFQ blif (.blif)
 * Convert LEF/DEF to GDS
 * Convert LEF/DEF to JoSIM
 
+
+
+## Required files
+
+| **File**    | **Description**           | Required by                 |
+| ----------- | ------------------------- | --------------------------- |
+| .genlib     | logic gate description    | ABC(ViPeR)                  |
+| .toml       | physical gate description | ViPeR                       |
+| .cfg        | qRouter config            | qRouter                     |
+| .lef        | standard gate description | qRouter, Die2Sim, chipSmith |
+| config.toml | configuration for ViPeR   | ViPeR                       |
+
+
+
 ## Examples
 Examples of how to execute ViPeR:
 

Diff for: ViPer_Notes.md

@@ -43,7 +43,18 @@ If splitters are inserted first, its a huge mess. The circuit has to be cleaned
 
 Stacking all possible routes including splitters.
 
-Must investigate the order of the stacking
+
+
+#### Order of priority if sorting:
+
+   *   predefined input order
+   * predefined output order
+   * longest route
+
+#### Sorting
+
+* Creating subsets per priority
+* use insertion for sorting per subset
 
 ### Layout
 
@@ -84,34 +95,34 @@ Look for widest row, calculate each row length. divide by the number of gaps, ad
 ### config file
 
 **Route Segment Cost** *value*
-     
 
-Cost of a route of the length of one track pitch on any metal  layer in the preferred direction of the route layer.  This  should be the lowest of all the costs.  Default value 2.     
+
+Cost of a route of the length of one track pitch on any metal  layer in the preferred direction of the route layer.  This  should be the lowest of all the costs.  Default value 2.
 
 **Route Via Cost** *value*
-     
 
-Cost to switch routing layers up or down using a via.  Default  value 10.     
+
+Cost to switch routing layers up or down using a via.  Default  value 10.
 
 **Route Jog Cost** *value*
-     
 
-Cost of a route of the length of one track pitch on any metal  layer against the preferred direction of the route layer.  This cost should be relatively high;  however, it should be  less than (Route Segment Cost + 2 * Route Via Cost) to allow  a jog of a single track pitch to be preferred over switching  to another layer.  Default value 20.     
+
+Cost of a route of the length of one track pitch on any metal  layer against the preferred direction of the route layer.  This cost should be relatively high;  however, it should be  less than (Route Segment Cost + 2 * Route Via Cost) to allow  a jog of a single track pitch to be preferred over switching  to another layer.  Default value 20.
 
 **Route Crossover Cost** *value*
-     
 
-Cost of routing directly over or under an unrouted pin  connection to a cell.  This helps prevent pins from getting  boxed in before they are routed, making them unroutable.  Default value 8.     
+
+Cost of routing directly over or under an unrouted pin  connection to a cell.  This helps prevent pins from getting  boxed in before they are routed, making them unroutable.  Default value 8.
 
 **Route Block Cost** *value*
-     
 
-Cost of routing directly over or under an unrouted pin  connection to a cell, when that connection is the only  available vertical connection to the pin.  Default value 25.     
+
+Cost of routing directly over or under an unrouted pin  connection to a cell, when that connection is the only  available vertical connection to the pin.  Default value 25.
 
 **Route Collision Cost** *value*
-     
 
-Cost of shorting another net.  This happens during the second  routing stage.  All nets that are shorted by this net will  have to be ripped up and rerouted.  The value should be large  to avoid a large number of existing routes needing to be ripped  up.  Default value 50. 
+
+Cost of shorting another net.  This happens during the second  routing stage.  All nets that are shorted by this net will  have to be ripped up and rerouted.  The value should be large  to avoid a large number of existing routes needing to be ripped  up.  Default value 50.
 
 
 
@@ -122,21 +133,21 @@ Cost of shorting another net.  This happens during the second  routing stage.  A
 [TRACKS
 [{X | Y} start DO numtracks STEP space
  [LAYER layerName ...]
-;] ...] 
+;] ...]
 
-Defines the routing grid for a standard cell-based design. 
+Defines the routing grid for a standard cell-based design.
 The track spacing is the PITCH value for the layer defined in LEF.
 
--{X | Y} start 
-Specifies the location and direction of the first track defined. X indicates vertical lines; Y indicates horizontal lines. 
-start is the X or Y coordinate of the first line. 
-For example, X 3000 creates a set of vertical lines, with the first line going through (3000 0). 
+-{X | Y} start
+Specifies the location and direction of the first track defined. X indicates vertical lines; Y indicates horizontal lines.
+start is the X or Y coordinate of the first line.
+For example, X 3000 creates a set of vertical lines, with the first line going through (3000 0).
 
-DO numTracks 
+DO numTracks
 Specifies the number of tracks to create for the grid. You cannot specify 0 numtracks.
 
--STEP space 
+-STEP space
 Specifies the spacing between the tracks.
 
--LAYER layerName 
+-LAYER layerName
 Specifies the routing layer used for the tracks. You can specify more than one layer.

Diff for: config.toml

@@ -10,49 +10,53 @@
 # version = 0.1
 
 [run_parameters]
-	Command   = "blif2gds" # verilog2gds; blif2gds; runABC; gdf2lef;
-
-	# Working directory, all file names will be referenced with this
-	# work_dir = "data/adder3bit/"
-	# work_dir = "data/adder6bit/"
-	work_dir = "data/rca2/"
-	# work_dir = "data/KSA/4/"
-
-	gds_file  = "outGDS.gds"     # GDS file to be created
-	# blif_file = "adder3bit.blif" # Standard blif that will be converted to SFQblif
-	# blif_file = "adder6bit.blif" # Standard blif that will be converted to SFQblif
-	# blif_file = "KSA4.blif" # Standard blif that will be converted to SFQblif
-	blif_file = "rca2.blif" # Standard blif that will be converted to SFQblif
-	# sfqblif_file = ""            # The SFQblif file that will be converted to GDS
-	# veri_file = "KSA4.v"	              # Verilog file for ABC to convert to a standard blif
-	# cell_dis  = "LSmitll.genlib" # cell/gate description for ABC
-	cell_dis_gds = "LSmitll_cell_lib.toml"
-	# NOTE: all directories are relative to the current directory
-
-
-	# Converting a GDF(Gate Definition File) to LEF
-	# cell_dis_gds = "LSmitll_cell_lib.toml"fg
-	lef_file = "SUN.lef"
-
-[Layout_parameters]
-	input_order = ["a0", "b0", "clk", "a1", "b1"]
-	output_order = ["s0", "s1", "s2"]
-
-[wafer_parameters]
+	# Command   = "blif2gds"
+	Command   = "gdf2lef"
+	# Command   = "verilog2gds"
+	# Command   = "runABC"
+
+
+[Circuit_Files]
+	# work_dir  = "data/.../"   # Working directory, all file names will be referenced with this
+	# blif_file = ".blif"       # Standard blif that will be converted to SFQblif
+	# veri_file = ".v"	        # Verilog file for ABC to convert to a standard blif
+
+	gds_file    = "outGDS.gds"     # GDS file to be created
+
+	# work_dir  = "data/adder3bit/"
+	# blif_file = "adder3bit.blif"
+
+	# work_dir  = "data/adder6bit/"
+	# blif_file = "adder6bit.blif"
+
+	# work_dir  = "data/rca2/"
+	# blif_file = "rca2.blif"
+
+	work_dir    = "data/KSA4/"
+	blif_file   = "KSA4.blif"
+	# veri_file = "KSA4.v"
+
+
+[General_Config_File]
+	cell_dis     = "data/LSmitll.genlib"          # Logic cell/gate description for ABC
+	cell_dis_gds = "data/LSmitll_cell_lib.toml"   # Homebrewed description for physical cell layout
+	lef_file     = "data/SUNobs.lef"                 # Used for converting a GDF(Gate Definition File) to LEF
+
+[Layout_Parameters]
+	# RCA2
+	# input_order = ["a0", "b0", "a1", "b1"]
+	# output_order = ["s0", "s1", "s2"]
+
+	# KSA4
+	input_order = ["cin", "a0", "b0", "a1", "b1", "a2", "b2", "a3", "b3"]
+	output_order = ["sum0", "sum1", "sum2", "sum3", "cout"]
+
+[Wafer_Parameters]
 	x_offset       = 5
 	y_offset       = 5
 	vertical_gap   = 0         # Spacing between cells
 	horizontal_gap = 40         # Spacing between cells
 	cell_height    = 50        # The height of the cells
-	row_align      = "left" # Row alignment {left, centre, justify}
+	row_align      = "left"    # Row alignment {left, centre, justify}
 	pad_ver_gap    = 35        # The vertical distance between the pads and the gates/circuit
-	pad_hor_gap    = 10         # the horizontal gap between the pins/pads
-
-
-# [NOTES]
-# ALL MEASUREMENTS are in um.
-# Pin location is at the CENTRE of the port.
-# Routing connection to the pin must be a PTL on layer M3 with M2 and M4 as shielding groundplanes.
-# The biasing pillars are on layer M5.
-# Pillars are considered as obstructions.
-# The the names for the gates in the .genlib file must match the gates of the gates in the runParameter.toml(this) file
+	pad_hor_gap    = 10        # the horizontal gap between the pins/pads