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CalculatePixGain.vhf
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : sch2hdl
-- / / Filename : CalculatePixGain.vhf
-- /___/ /\ Timestamp : 06/19/2023 15:05:24
-- \ \ / \
-- \___\/\___\
--
--Command: sch2hdl -sympath /home/user/workspace/melexis_mlx90641/ipcore_dir -intstyle ise -family virtex4 -flat -suppress -vhdl /home/user/workspace/melexis_mlx90641/CalculatePixGain.vhf -w /home/user/workspace/melexis_mlx90641/CalculatePixGain.sch
--Design Name: CalculatePixGain
--Device: virtex4
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity M2_1_MXILINX_CalculatePixGain is
port ( D0 : in std_logic;
D1 : in std_logic;
S0 : in std_logic;
O : out std_logic);
end M2_1_MXILINX_CalculatePixGain;
architecture BEHAVIORAL of M2_1_MXILINX_CalculatePixGain is
attribute BOX_TYPE : string ;
signal M0 : std_logic;
signal M1 : std_logic;
component AND2B1
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
component OR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
begin
I_36_7 : AND2B1
port map (I0=>S0,
I1=>D0,
O=>M0);
I_36_8 : OR2
port map (I0=>M1,
I1=>M0,
O=>O);
I_36_9 : AND2
port map (I0=>D1,
I1=>S0,
O=>M1);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity CalculatePixGain is
port ( divfpr : in std_logic_vector (31 downto 0);
divfprdy : in std_logic;
fixed2floatr : in std_logic_vector (31 downto 0);
fixed2floatrdy : in std_logic;
i_addr : in std_logic_vector (9 downto 0);
i_clock : in std_logic;
i_reset : in std_logic;
i_run : in std_logic;
i2c_mem_douta : in std_logic_vector (7 downto 0);
mulfpr : in std_logic_vector (31 downto 0);
mulfprdy : in std_logic;
divfpa : out std_logic_vector (31 downto 0);
divfpb : out std_logic_vector (31 downto 0);
divfpce : out std_logic;
divfpond : out std_logic;
divfpsclr : out std_logic;
fixed2floata : out std_logic_vector (63 downto 0);
fixed2floatce : out std_logic;
fixed2floatond : out std_logic;
fixed2floatsclr : out std_logic;
i2c_mem_addra : out std_logic_vector (11 downto 0);
i2c_mem_ena : out std_logic;
mulfpa : out std_logic_vector (31 downto 0);
mulfpb : out std_logic_vector (31 downto 0);
mulfpce : out std_logic;
mulfpond : out std_logic;
mulfpsclr : out std_logic;
o_do : out std_logic_vector (31 downto 0);
o_rdy : out std_logic);
end CalculatePixGain;
architecture BEHAVIORAL of CalculatePixGain is
attribute DOA_REG : string ;
attribute DOB_REG : string ;
attribute INIT_00 : string ;
attribute INIT_01 : string ;
attribute INIT_02 : string ;
attribute INIT_03 : string ;
attribute INIT_04 : string ;
attribute INIT_05 : string ;
attribute INIT_06 : string ;
attribute INIT_07 : string ;
attribute INIT_08 : string ;
attribute INIT_09 : string ;
attribute INIT_0A : string ;
attribute INIT_0B : string ;
attribute INIT_0C : string ;
attribute INIT_0D : string ;
attribute INIT_0E : string ;
attribute INIT_0F : string ;
attribute INIT_10 : string ;
attribute INIT_11 : string ;
attribute INIT_12 : string ;
attribute INIT_13 : string ;
attribute INIT_14 : string ;
attribute INIT_15 : string ;
attribute INIT_16 : string ;
attribute INIT_17 : string ;
attribute INIT_18 : string ;
attribute INIT_19 : string ;
attribute INIT_1A : string ;
attribute INIT_1B : string ;
attribute INIT_1C : string ;
attribute INIT_1D : string ;
attribute INIT_1E : string ;
attribute INIT_1F : string ;
attribute INIT_20 : string ;
attribute INIT_21 : string ;
attribute INIT_22 : string ;
attribute INIT_23 : string ;
attribute INIT_24 : string ;
attribute INIT_25 : string ;
attribute INIT_26 : string ;
attribute INIT_27 : string ;
attribute INIT_28 : string ;
attribute INIT_29 : string ;
attribute INIT_2A : string ;
attribute INIT_2B : string ;
attribute INIT_2C : string ;
attribute INIT_2D : string ;
attribute INIT_2E : string ;
attribute INIT_2F : string ;
attribute INIT_30 : string ;
attribute INIT_31 : string ;
attribute INIT_32 : string ;
attribute INIT_33 : string ;
attribute INIT_34 : string ;
attribute INIT_35 : string ;
attribute INIT_36 : string ;
attribute INIT_37 : string ;
attribute INIT_38 : string ;
attribute INIT_39 : string ;
attribute INIT_3A : string ;
attribute INIT_3B : string ;
attribute INIT_3C : string ;
attribute INIT_3D : string ;
attribute INIT_3E : string ;
attribute INIT_3F : string ;
attribute INIT_A : string ;
attribute INIT_B : string ;
attribute INITP_00 : string ;
attribute INITP_01 : string ;
attribute INITP_02 : string ;
attribute INITP_03 : string ;
attribute INITP_04 : string ;
attribute INITP_05 : string ;
attribute INITP_06 : string ;
attribute INITP_07 : string ;
attribute INIT_FILE : string ;
attribute INVERT_CLK_DOA_REG : string ;
attribute INVERT_CLK_DOB_REG : string ;
attribute RAM_EXTENSION_A : string ;
attribute RAM_EXTENSION_B : string ;
attribute READ_WIDTH_A : string ;
attribute READ_WIDTH_B : string ;
attribute SRVAL_A : string ;
attribute SRVAL_B : string ;
attribute WRITE_MODE_A : string ;
attribute WRITE_MODE_B : string ;
attribute WRITE_WIDTH_A : string ;
attribute WRITE_WIDTH_B : string ;
attribute SIM_COLLISION_CHECK : string ;
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal mux_addr : std_logic_vector (9 downto 0);
signal XLXN_44 : std_logic_vector (14 downto 0);
signal XLXN_45 : std_logic_vector (14 downto 0);
signal XLXN_59 : std_logic;
signal XLXN_78 : std_logic_vector (31 downto 0);
signal XLXN_79 : std_logic_vector (31 downto 0);
signal XLXN_86 : std_logic_vector (9 downto 0);
signal XLXN_88 : std_logic_vector (31 downto 0);
signal XLXN_109 : std_logic;
signal XLXN_112 : std_logic;
signal XLXN_113 : std_logic;
signal XLXN_114 : std_logic_vector (11 downto 0);
signal XLXN_115 : std_logic_vector (11 downto 0);
signal XLXN_117 : std_logic;
signal XLXN_118 : std_logic_vector (63 downto 0);
signal XLXN_119 : std_logic_vector (63 downto 0);
signal XLXN_132 : std_logic;
signal XLXN_133 : std_logic;
signal XLXN_134 : std_logic;
signal XLXN_135 : std_logic;
signal XLXN_136 : std_logic;
signal XLXN_137 : std_logic;
signal XLXN_139 : std_logic_vector (3 downto 0);
signal XLXN_140 : std_logic;
signal XLXN_141 : std_logic_vector (31 downto 0);
signal XLXN_155 : std_logic;
signal XLXN_157 : std_logic_vector (31 downto 0);
signal XLXN_158 : std_logic_vector (31 downto 0);
signal o_rdy_DUMMY : std_logic;
signal mem_KGain_1_ADDRB_openSignal : std_logic_vector (14 downto 0);
signal mem_KGain_1_CASCADEINA_openSignal : std_logic;
signal mem_KGain_1_CASCADEINB_openSignal : std_logic;
signal mem_KGain_1_CLKB_openSignal : std_logic;
signal mem_KGain_1_DIB_openSignal : std_logic_vector (31 downto 0);
signal mem_KGain_1_DIPA_openSignal : std_logic_vector (3 downto 0);
signal mem_KGain_1_DIPB_openSignal : std_logic_vector (3 downto 0);
signal mem_KGain_1_ENB_openSignal : std_logic;
signal mem_KGain_1_REGCEA_openSignal : std_logic;
signal mem_KGain_1_REGCEB_openSignal : std_logic;
signal mem_KGain_1_SSRB_openSignal : std_logic;
signal mem_KGain_1_WEB_openSignal : std_logic_vector (3 downto 0);
signal mem_KGain_2_ADDRB_openSignal : std_logic_vector (14 downto 0);
signal mem_KGain_2_CASCADEINA_openSignal : std_logic;
signal mem_KGain_2_CASCADEINB_openSignal : std_logic;
signal mem_KGain_2_CLKB_openSignal : std_logic;
signal mem_KGain_2_DIB_openSignal : std_logic_vector (31 downto 0);
signal mem_KGain_2_DIPA_openSignal : std_logic_vector (3 downto 0);
signal mem_KGain_2_DIPB_openSignal : std_logic_vector (3 downto 0);
signal mem_KGain_2_ENB_openSignal : std_logic;
signal mem_KGain_2_REGCEA_openSignal : std_logic;
signal mem_KGain_2_REGCEB_openSignal : std_logic;
signal mem_KGain_2_SSRB_openSignal : std_logic;
signal mem_KGain_2_WEB_openSignal : std_logic_vector (3 downto 0);
component CalculateKGain_process_p0
port ( i_clock : in std_logic;
i_reset : in std_logic;
i_run : in std_logic;
fixed2floatrdy : in std_logic;
divfprdy : in std_logic;
i2c_mem_douta : in std_logic_vector (7 downto 0);
fixed2floatr : in std_logic_vector (31 downto 0);
divfpr : in std_logic_vector (31 downto 0);
i2c_mem_ena : out std_logic;
o_rdy : out std_logic;
fixed2floatond : out std_logic;
fixed2floatsclr : out std_logic;
fixed2floatce : out std_logic;
divfpond : out std_logic;
divfpsclr : out std_logic;
divfpce : out std_logic;
i2c_mem_addra : out std_logic_vector (11 downto 0);
o_KGain : out std_logic_vector (31 downto 0);
fixed2floata : out std_logic_vector (63 downto 0);
divfpa : out std_logic_vector (31 downto 0);
divfpb : out std_logic_vector (31 downto 0));
end component;
component CalculatePixGain_process_p0
port ( i_clock : in std_logic;
i_reset : in std_logic;
i_run : in std_logic;
CalculateKGain_rdy : in std_logic;
fixed2floatrdy : in std_logic;
mulfprdy : in std_logic;
i2c_mem_douta : in std_logic_vector (7 downto 0);
CalculateKGain_KGain : in std_logic_vector (31 downto 0);
fixed2floatr : in std_logic_vector (31 downto 0);
mulfpr : in std_logic_vector (31 downto 0);
i2c_mem_ena : out std_logic;
CalculateKGain_run : out std_logic;
CalculateKGain_mux : out std_logic;
o_rdy : out std_logic;
o_write_enable : out std_logic;
fixed2floatond : out std_logic;
fixed2floatsclr : out std_logic;
fixed2floatce : out std_logic;
mulfpond : out std_logic;
mulfpsclr : out std_logic;
mulfpce : out std_logic;
i2c_mem_addra : out std_logic_vector (11 downto 0);
o_addra : out std_logic_vector (9 downto 0);
o_dia : out std_logic_vector (31 downto 0);
fixed2floata : out std_logic_vector (63 downto 0);
mulfpa : out std_logic_vector (31 downto 0);
mulfpb : out std_logic_vector (31 downto 0));
end component;
component RAMB16
-- synopsys translate_off
generic( DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_00 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := x"000000000";
INIT_B : bit_vector := x"000000000";
INITP_00 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_FILE : string := "NONE";
INVERT_CLK_DOA_REG : boolean := FALSE;
INVERT_CLK_DOB_REG : boolean := FALSE;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SRVAL_A : bit_vector := x"000000000";
SRVAL_B : bit_vector := x"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL");
-- synopsys translate_on
port ( ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_logic;
CASCADEINB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
REGCEB : in std_logic;
ENB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0);
CASCADEOUTA : out std_logic;
CASCADEOUTB : out std_logic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0));
end component;
attribute DOA_REG of RAMB16 : component is "0";
attribute DOB_REG of RAMB16 : component is "0";
attribute INIT_00 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_A of RAMB16 : component is "000000000";
attribute INIT_B of RAMB16 : component is "000000000";
attribute INITP_00 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_01 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_FILE of RAMB16 : component is "NONE";
attribute INVERT_CLK_DOA_REG of RAMB16 : component is "FALSE";
attribute INVERT_CLK_DOB_REG of RAMB16 : component is "FALSE";
attribute RAM_EXTENSION_A of RAMB16 : component is "NONE";
attribute RAM_EXTENSION_B of RAMB16 : component is "NONE";
attribute READ_WIDTH_A of RAMB16 : component is "0";
attribute READ_WIDTH_B of RAMB16 : component is "0";
attribute SRVAL_A of RAMB16 : component is "000000000";
attribute SRVAL_B of RAMB16 : component is "000000000";
attribute WRITE_MODE_A of RAMB16 : component is "WRITE_FIRST";
attribute WRITE_MODE_B of RAMB16 : component is "WRITE_FIRST";
attribute WRITE_WIDTH_A of RAMB16 : component is "0";
attribute WRITE_WIDTH_B of RAMB16 : component is "0";
attribute SIM_COLLISION_CHECK of RAMB16 : component is "ALL";
attribute BOX_TYPE of RAMB16 : component is "BLACK_BOX";
component M2_1_MXILINX_CalculatePixGain
port ( D0 : in std_logic;
D1 : in std_logic;
S0 : in std_logic;
O : out std_logic);
end component;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component BUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUF : component is "BLACK_BOX";
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
attribute WRITE_WIDTH_B of mem_KGain_1 : label is "36";
attribute WRITE_WIDTH_A of mem_KGain_1 : label is "36";
attribute WRITE_MODE_B of mem_KGain_1 : label is "READ_FIRST";
attribute WRITE_MODE_A of mem_KGain_1 : label is "READ_FIRST";
attribute READ_WIDTH_B of mem_KGain_1 : label is "36";
attribute READ_WIDTH_A of mem_KGain_1 : label is "36";
attribute WRITE_WIDTH_B of mem_KGain_2 : label is "36";
attribute WRITE_WIDTH_A of mem_KGain_2 : label is "36";
attribute WRITE_MODE_B of mem_KGain_2 : label is "READ_FIRST";
attribute WRITE_MODE_A of mem_KGain_2 : label is "READ_FIRST";
attribute READ_WIDTH_B of mem_KGain_2 : label is "36";
attribute READ_WIDTH_A of mem_KGain_2 : label is "36";
attribute HU_SET of MUX_DIA_0 : label is "MUX_DIA_0_1623";
attribute HU_SET of MUX_DIA_1 : label is "MUX_DIA_1_1622";
attribute HU_SET of MUX_DIA_2 : label is "MUX_DIA_2_1621";
attribute HU_SET of MUX_DIA_3 : label is "MUX_DIA_3_1620";
attribute HU_SET of MUX_DIA_4 : label is "MUX_DIA_4_1619";
attribute HU_SET of MUX_DIA_5 : label is "MUX_DIA_5_1618";
attribute HU_SET of MUX_DIA_6 : label is "MUX_DIA_6_1617";
attribute HU_SET of MUX_DIA_7 : label is "MUX_DIA_7_1616";
attribute HU_SET of MUX_DIA_8 : label is "MUX_DIA_8_1615";
attribute HU_SET of MUX_DIA_9 : label is "MUX_DIA_9_1614";
attribute HU_SET of MUX_DIA_10 : label is "MUX_DIA_10_1613";
attribute HU_SET of MUX_DIA_11 : label is "MUX_DIA_11_1612";
attribute HU_SET of MUX_DIA_12 : label is "MUX_DIA_12_1611";
attribute HU_SET of MUX_DIA_13 : label is "MUX_DIA_13_1610";
attribute HU_SET of MUX_DIA_14 : label is "MUX_DIA_14_1609";
attribute HU_SET of MUX_DIA_15 : label is "MUX_DIA_15_1608";
attribute HU_SET of MUX_DIA_16 : label is "MUX_DIA_16_1607";
attribute HU_SET of MUX_DIA_17 : label is "MUX_DIA_17_1606";
attribute HU_SET of MUX_DIA_18 : label is "MUX_DIA_18_1605";
attribute HU_SET of MUX_DIA_19 : label is "MUX_DIA_19_1604";
attribute HU_SET of MUX_DIA_20 : label is "MUX_DIA_20_1603";
attribute HU_SET of MUX_DIA_21 : label is "MUX_DIA_21_1602";
attribute HU_SET of MUX_DIA_22 : label is "MUX_DIA_22_1601";
attribute HU_SET of MUX_DIA_23 : label is "MUX_DIA_23_1600";
attribute HU_SET of MUX_DIA_24 : label is "MUX_DIA_24_1599";
attribute HU_SET of MUX_DIA_25 : label is "MUX_DIA_25_1598";
attribute HU_SET of MUX_DIA_26 : label is "MUX_DIA_26_1597";
attribute HU_SET of MUX_DIA_27 : label is "MUX_DIA_27_1596";
attribute HU_SET of MUX_DIA_28 : label is "MUX_DIA_28_1595";
attribute HU_SET of MUX_DIA_29 : label is "MUX_DIA_29_1594";
attribute HU_SET of MUX_DIA_30 : label is "MUX_DIA_30_1593";
attribute HU_SET of MUX_DIA_31 : label is "MUX_DIA_31_1592";
attribute HU_SET of MUX_DO_0 : label is "MUX_DO_0_1581";
attribute HU_SET of MUX_DO_1 : label is "MUX_DO_1_1580";
attribute HU_SET of MUX_DO_2 : label is "MUX_DO_2_1579";
attribute HU_SET of MUX_DO_3 : label is "MUX_DO_3_1578";
attribute HU_SET of MUX_DO_4 : label is "MUX_DO_4_1577";
attribute HU_SET of MUX_DO_5 : label is "MUX_DO_5_1576";
attribute HU_SET of MUX_DO_6 : label is "MUX_DO_6_1575";
attribute HU_SET of MUX_DO_7 : label is "MUX_DO_7_1574";
attribute HU_SET of MUX_DO_8 : label is "MUX_DO_8_1573";
attribute HU_SET of MUX_DO_9 : label is "MUX_DO_9_1572";
attribute HU_SET of MUX_DO_10 : label is "MUX_DO_10_1571";
attribute HU_SET of MUX_DO_11 : label is "MUX_DO_11_1570";
attribute HU_SET of MUX_DO_12 : label is "MUX_DO_12_1569";
attribute HU_SET of MUX_DO_13 : label is "MUX_DO_13_1568";
attribute HU_SET of MUX_DO_14 : label is "MUX_DO_14_1567";
attribute HU_SET of MUX_DO_15 : label is "MUX_DO_15_1566";
attribute HU_SET of MUX_DO_16 : label is "MUX_DO_16_1565";
attribute HU_SET of MUX_DO_17 : label is "MUX_DO_17_1564";
attribute HU_SET of MUX_DO_18 : label is "MUX_DO_18_1563";
attribute HU_SET of MUX_DO_19 : label is "MUX_DO_19_1562";
attribute HU_SET of MUX_DO_20 : label is "MUX_DO_20_1561";
attribute HU_SET of MUX_DO_21 : label is "MUX_DO_21_1560";
attribute HU_SET of MUX_DO_22 : label is "MUX_DO_22_1559";
attribute HU_SET of MUX_DO_23 : label is "MUX_DO_23_1558";
attribute HU_SET of MUX_DO_24 : label is "MUX_DO_24_1557";
attribute HU_SET of MUX_DO_25 : label is "MUX_DO_25_1556";
attribute HU_SET of MUX_DO_26 : label is "MUX_DO_26_1555";
attribute HU_SET of MUX_DO_27 : label is "MUX_DO_27_1554";
attribute HU_SET of MUX_DO_28 : label is "MUX_DO_28_1553";
attribute HU_SET of MUX_DO_29 : label is "MUX_DO_29_1552";
attribute HU_SET of MUX_DO_30 : label is "MUX_DO_30_1551";
attribute HU_SET of MUX_DO_31 : label is "MUX_DO_31_1550";
attribute HU_SET of MUX_F2FA_0 : label is "MUX_F2FA_0_1700";
attribute HU_SET of MUX_F2FA_1 : label is "MUX_F2FA_1_1699";
attribute HU_SET of MUX_F2FA_2 : label is "MUX_F2FA_2_1698";
attribute HU_SET of MUX_F2FA_3 : label is "MUX_F2FA_3_1697";
attribute HU_SET of MUX_F2FA_4 : label is "MUX_F2FA_4_1696";
attribute HU_SET of MUX_F2FA_5 : label is "MUX_F2FA_5_1695";
attribute HU_SET of MUX_F2FA_6 : label is "MUX_F2FA_6_1694";
attribute HU_SET of MUX_F2FA_7 : label is "MUX_F2FA_7_1693";
attribute HU_SET of MUX_F2FA_8 : label is "MUX_F2FA_8_1692";
attribute HU_SET of MUX_F2FA_9 : label is "MUX_F2FA_9_1691";
attribute HU_SET of MUX_F2FA_10 : label is "MUX_F2FA_10_1690";
attribute HU_SET of MUX_F2FA_11 : label is "MUX_F2FA_11_1689";
attribute HU_SET of MUX_F2FA_12 : label is "MUX_F2FA_12_1688";
attribute HU_SET of MUX_F2FA_13 : label is "MUX_F2FA_13_1687";
attribute HU_SET of MUX_F2FA_14 : label is "MUX_F2FA_14_1686";
attribute HU_SET of MUX_F2FA_15 : label is "MUX_F2FA_15_1685";
attribute HU_SET of MUX_F2FA_16 : label is "MUX_F2FA_16_1684";
attribute HU_SET of MUX_F2FA_17 : label is "MUX_F2FA_17_1683";
attribute HU_SET of MUX_F2FA_18 : label is "MUX_F2FA_18_1682";
attribute HU_SET of MUX_F2FA_19 : label is "MUX_F2FA_19_1681";
attribute HU_SET of MUX_F2FA_20 : label is "MUX_F2FA_20_1680";
attribute HU_SET of MUX_F2FA_21 : label is "MUX_F2FA_21_1679";
attribute HU_SET of MUX_F2FA_22 : label is "MUX_F2FA_22_1678";
attribute HU_SET of MUX_F2FA_23 : label is "MUX_F2FA_23_1677";
attribute HU_SET of MUX_F2FA_24 : label is "MUX_F2FA_24_1676";
attribute HU_SET of MUX_F2FA_25 : label is "MUX_F2FA_25_1675";
attribute HU_SET of MUX_F2FA_26 : label is "MUX_F2FA_26_1674";
attribute HU_SET of MUX_F2FA_27 : label is "MUX_F2FA_27_1673";
attribute HU_SET of MUX_F2FA_28 : label is "MUX_F2FA_28_1672";
attribute HU_SET of MUX_F2FA_29 : label is "MUX_F2FA_29_1671";
attribute HU_SET of MUX_F2FA_30 : label is "MUX_F2FA_30_1670";
attribute HU_SET of MUX_F2FA_31 : label is "MUX_F2FA_31_1669";
attribute HU_SET of MUX_F2FA_32 : label is "MUX_F2FA_32_1668";
attribute HU_SET of MUX_F2FA_33 : label is "MUX_F2FA_33_1667";
attribute HU_SET of MUX_F2FA_34 : label is "MUX_F2FA_34_1666";
attribute HU_SET of MUX_F2FA_35 : label is "MUX_F2FA_35_1665";
attribute HU_SET of MUX_F2FA_36 : label is "MUX_F2FA_36_1664";
attribute HU_SET of MUX_F2FA_37 : label is "MUX_F2FA_37_1663";
attribute HU_SET of MUX_F2FA_38 : label is "MUX_F2FA_38_1662";
attribute HU_SET of MUX_F2FA_39 : label is "MUX_F2FA_39_1661";
attribute HU_SET of MUX_F2FA_40 : label is "MUX_F2FA_40_1660";
attribute HU_SET of MUX_F2FA_41 : label is "MUX_F2FA_41_1659";
attribute HU_SET of MUX_F2FA_42 : label is "MUX_F2FA_42_1658";
attribute HU_SET of MUX_F2FA_43 : label is "MUX_F2FA_43_1657";
attribute HU_SET of MUX_F2FA_44 : label is "MUX_F2FA_44_1656";
attribute HU_SET of MUX_F2FA_45 : label is "MUX_F2FA_45_1655";
attribute HU_SET of MUX_F2FA_46 : label is "MUX_F2FA_46_1654";
attribute HU_SET of MUX_F2FA_47 : label is "MUX_F2FA_47_1653";
attribute HU_SET of MUX_F2FA_48 : label is "MUX_F2FA_48_1652";
attribute HU_SET of MUX_F2FA_49 : label is "MUX_F2FA_49_1651";
attribute HU_SET of MUX_F2FA_50 : label is "MUX_F2FA_50_1650";
attribute HU_SET of MUX_F2FA_51 : label is "MUX_F2FA_51_1649";
attribute HU_SET of MUX_F2FA_52 : label is "MUX_F2FA_52_1648";
attribute HU_SET of MUX_F2FA_53 : label is "MUX_F2FA_53_1647";
attribute HU_SET of MUX_F2FA_54 : label is "MUX_F2FA_54_1646";
attribute HU_SET of MUX_F2FA_55 : label is "MUX_F2FA_55_1645";
attribute HU_SET of MUX_F2FA_56 : label is "MUX_F2FA_56_1644";
attribute HU_SET of MUX_F2FA_57 : label is "MUX_F2FA_57_1643";
attribute HU_SET of MUX_F2FA_58 : label is "MUX_F2FA_58_1642";
attribute HU_SET of MUX_F2FA_59 : label is "MUX_F2FA_59_1641";
attribute HU_SET of MUX_F2FA_60 : label is "MUX_F2FA_60_1640";
attribute HU_SET of MUX_F2FA_61 : label is "MUX_F2FA_61_1639";
attribute HU_SET of MUX_F2FA_62 : label is "MUX_F2FA_62_1638";
attribute HU_SET of MUX_F2FA_63 : label is "MUX_F2FA_63_1637";
attribute HU_SET of MUX_I2C_ADDR_0 : label is "MUX_I2C_ADDR_0_1636";
attribute HU_SET of MUX_I2C_ADDR_1 : label is "MUX_I2C_ADDR_1_1635";
attribute HU_SET of MUX_I2C_ADDR_2 : label is "MUX_I2C_ADDR_2_1634";
attribute HU_SET of MUX_I2C_ADDR_3 : label is "MUX_I2C_ADDR_3_1633";
attribute HU_SET of MUX_I2C_ADDR_4 : label is "MUX_I2C_ADDR_4_1632";
attribute HU_SET of MUX_I2C_ADDR_5 : label is "MUX_I2C_ADDR_5_1631";
attribute HU_SET of MUX_I2C_ADDR_6 : label is "MUX_I2C_ADDR_6_1630";
attribute HU_SET of MUX_I2C_ADDR_7 : label is "MUX_I2C_ADDR_7_1629";
attribute HU_SET of MUX_I2C_ADDR_8 : label is "MUX_I2C_ADDR_8_1628";
attribute HU_SET of MUX_I2C_ADDR_9 : label is "MUX_I2C_ADDR_9_1627";
attribute HU_SET of MUX_I2C_ADDR_10 : label is "MUX_I2C_ADDR_10_1626";
attribute HU_SET of MUX_I2C_ADDR_11 : label is "MUX_I2C_ADDR_11_1625";
attribute HU_SET of mux2_addra_0 : label is "mux2_addra_0_1591";
attribute HU_SET of mux2_addra_1 : label is "mux2_addra_1_1590";
attribute HU_SET of mux2_addra_2 : label is "mux2_addra_2_1589";
attribute HU_SET of mux2_addra_3 : label is "mux2_addra_3_1588";
attribute HU_SET of mux2_addra_4 : label is "mux2_addra_4_1587";
attribute HU_SET of mux2_addra_5 : label is "mux2_addra_5_1586";
attribute HU_SET of mux2_addra_6 : label is "mux2_addra_6_1585";
attribute HU_SET of mux2_addra_7 : label is "mux2_addra_7_1584";
attribute HU_SET of mux2_addra_8 : label is "mux2_addra_8_1583";
attribute HU_SET of mux2_addra_9 : label is "mux2_addra_9_1582";
attribute HU_SET of XLXI_21 : label is "XLXI_21_1624";
attribute HU_SET of XLXI_24 : label is "XLXI_24_1701";
attribute HU_SET of XLXI_26 : label is "XLXI_26_1702";
attribute HU_SET of XLXI_27 : label is "XLXI_27_1703";
begin
XLXN_158(31 downto 0) <= x"00000000";
o_rdy <= o_rdy_DUMMY;
inst_CalcKGain_proc0 : CalculateKGain_process_p0
port map (divfpr(31 downto 0)=>divfpr(31 downto 0),
divfprdy=>divfprdy,
fixed2floatr(31 downto 0)=>fixed2floatr(31 downto 0),
fixed2floatrdy=>fixed2floatrdy,
i_clock=>i_clock,
i_reset=>i_reset,
i_run=>XLXN_117,
i2c_mem_douta(7 downto 0)=>i2c_mem_douta(7 downto 0),
divfpa(31 downto 0)=>divfpa(31 downto 0),
divfpb(31 downto 0)=>divfpb(31 downto 0),
divfpce=>divfpce,
divfpond=>divfpond,
divfpsclr=>divfpsclr,
fixed2floata(63 downto 0)=>XLXN_119(63 downto 0),
fixed2floatce=>XLXN_137,
fixed2floatond=>XLXN_135,
fixed2floatsclr=>XLXN_136,
i2c_mem_addra(11 downto 0)=>XLXN_115(11 downto 0),
i2c_mem_ena=>XLXN_112,
o_KGain(31 downto 0)=>XLXN_141(31 downto 0),
o_rdy=>XLXN_155);
inst_CalcPixGain_proc0 : CalculatePixGain_process_p0
port map (CalculateKGain_KGain(31 downto 0)=>XLXN_141(31 downto 0),
CalculateKGain_rdy=>XLXN_155,
fixed2floatr(31 downto 0)=>fixed2floatr(31 downto 0),
fixed2floatrdy=>fixed2floatrdy,
i_clock=>i_clock,
i_reset=>i_reset,
i_run=>i_run,
i2c_mem_douta(7 downto 0)=>i2c_mem_douta(7 downto 0),
mulfpr(31 downto 0)=>mulfpr(31 downto 0),
mulfprdy=>mulfprdy,
CalculateKGain_mux=>XLXN_113,
CalculateKGain_run=>XLXN_117,
fixed2floata(63 downto 0)=>XLXN_118(63 downto 0),
fixed2floatce=>XLXN_133,
fixed2floatond=>XLXN_132,
fixed2floatsclr=>XLXN_134,
i2c_mem_addra(11 downto 0)=>XLXN_114(11 downto 0),
i2c_mem_ena=>XLXN_109,
mulfpa(31 downto 0)=>mulfpa(31 downto 0),
mulfpb(31 downto 0)=>mulfpb(31 downto 0),
mulfpce=>mulfpce,
mulfpond=>mulfpond,
mulfpsclr=>mulfpsclr,
o_addra(9 downto 0)=>XLXN_86(9 downto 0),
o_dia(31 downto 0)=>XLXN_157(31 downto 0),
o_rdy=>o_rdy_DUMMY,
o_write_enable=>XLXN_140);
mem_KGain_1 : RAMB16
-- synopsys translate_off
generic map( WRITE_WIDTH_B => 36,
WRITE_WIDTH_A => 36,
WRITE_MODE_B => "READ_FIRST",
WRITE_MODE_A => "READ_FIRST",
READ_WIDTH_B => 36,
READ_WIDTH_A => 36)
-- synopsys translate_on
port map (ADDRA(14 downto 0)=>XLXN_44(14 downto 0),
ADDRB(14 downto 0)=>mem_KGain_1_ADDRB_openSignal(14 downto 0),
CASCADEINA=>mem_KGain_1_CASCADEINA_openSignal,
CASCADEINB=>mem_KGain_1_CASCADEINB_openSignal,
CLKA=>i_clock,
CLKB=>mem_KGain_1_CLKB_openSignal,
DIA(31 downto 0)=>XLXN_88(31 downto 0),
DIB(31 downto 0)=>mem_KGain_1_DIB_openSignal(31 downto 0),
DIPA(3 downto 0)=>mem_KGain_1_DIPA_openSignal(3 downto 0),
DIPB(3 downto 0)=>mem_KGain_1_DIPB_openSignal(3 downto 0),
ENA=>XLXN_59,
ENB=>mem_KGain_1_ENB_openSignal,
REGCEA=>mem_KGain_1_REGCEA_openSignal,
REGCEB=>mem_KGain_1_REGCEB_openSignal,
SSRA=>i_reset,
SSRB=>mem_KGain_1_SSRB_openSignal,
WEA(3 downto 0)=>XLXN_139(3 downto 0),
WEB(3 downto 0)=>mem_KGain_1_WEB_openSignal(3 downto 0),
CASCADEOUTA=>open,
CASCADEOUTB=>open,
DOA(31 downto 0)=>XLXN_79(31 downto 0),
DOB=>open,
DOPA=>open,
DOPB=>open);
mem_KGain_2 : RAMB16
-- synopsys translate_off
generic map( WRITE_WIDTH_B => 36,
WRITE_WIDTH_A => 36,
WRITE_MODE_B => "READ_FIRST",
WRITE_MODE_A => "READ_FIRST",
READ_WIDTH_B => 36,
READ_WIDTH_A => 36)
-- synopsys translate_on
port map (ADDRA(14 downto 0)=>XLXN_45(14 downto 0),
ADDRB(14 downto 0)=>mem_KGain_2_ADDRB_openSignal(14 downto 0),
CASCADEINA=>mem_KGain_2_CASCADEINA_openSignal,
CASCADEINB=>mem_KGain_2_CASCADEINB_openSignal,
CLKA=>i_clock,
CLKB=>mem_KGain_2_CLKB_openSignal,
DIA(31 downto 0)=>XLXN_88(31 downto 0),
DIB(31 downto 0)=>mem_KGain_2_DIB_openSignal(31 downto 0),
DIPA(3 downto 0)=>mem_KGain_2_DIPA_openSignal(3 downto 0),
DIPB(3 downto 0)=>mem_KGain_2_DIPB_openSignal(3 downto 0),
ENA=>mux_addr(9),
ENB=>mem_KGain_2_ENB_openSignal,
REGCEA=>mem_KGain_2_REGCEA_openSignal,
REGCEB=>mem_KGain_2_REGCEB_openSignal,
SSRA=>i_reset,
SSRB=>mem_KGain_2_SSRB_openSignal,
WEA(3 downto 0)=>XLXN_139(3 downto 0),
WEB(3 downto 0)=>mem_KGain_2_WEB_openSignal(3 downto 0),
CASCADEOUTA=>open,
CASCADEOUTB=>open,
DOA(31 downto 0)=>XLXN_78(31 downto 0),
DOB=>open,
DOPA=>open,
DOPB=>open);
MUX_DIA_0 : M2_1_MXILINX_CalculatePixGain
port map (D0=>XLXN_157(0),
D1=>XLXN_158(0),
S0=>o_rdy_DUMMY,
O=>XLXN_88(0));
MUX_DIA_1 : M2_1_MXILINX_CalculatePixGain
port map (D0=>XLXN_157(1),
D1=>XLXN_158(1),
S0=>o_rdy_DUMMY,
O=>XLXN_88(1));
MUX_DIA_2 : M2_1_MXILINX_CalculatePixGain
port map (D0=>XLXN_157(2),
D1=>XLXN_158(2),
S0=>o_rdy_DUMMY,