Instruction tracking debugging interface

[piotro888]

Debugging assembly tests (incl. regression tests) on traces is hard.

It would be great to create tool that prints information about each executed instruction (and maybe inserted and flushed ones in verbose mode) with current register state.

Implementation proposition (there may be better ways to do that):
Collect instruction information via calling methods in a similar way that our hardware logging works at a few points:

1. Collect raw instruction at exit of fetch unit
2. Maybe assign some temopary id in pipeline and map it in ROB insertion when rob_id is known.
3. Report rob_ids of commited instruction in Retirement and current RRAT state.
4. Optional: Collect reported exceptions and OpTypes
   (synthesis of extra features enabled in configuration)

Instructions from raw bits could be decoded and preety-printed externally.

It would be great if it worked both in python and faster verilator simulation, but I don't know if it is possible.