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RISC-V Debug Specification #764

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6 tasks

piotro888 opened this issue Nov 26, 2024 · 0 comments

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piotro888 commented Nov 26, 2024

Take a look into implementing RISC-V Debug Specification
https://github.com/riscv/riscv-debug-spec/

It would be great to debug larger software running on FPGAs with openOCD&gdb via JTAG.

Possible parts of the task:

Allow core to be halted
Implement Debug Privilege Mode in the core
Implement Program Buffer that allows arbitrary instructions to be inserted in debug mode (there are alternatives, but this one looks the simplest to me)
Implement debug CSR-like registers
Provide access to current GPRegisters state
Implement JTAG access interface

piotro888 added the enhancement label

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