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labrinealabrinea
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[FMV][AArch64] Simplify version selection according to ACLE.
Currently, the more features a version has, the higher its priority is. We are changing ACLE ARM-software/acle#370 as follows: "Among any two versions, the higher priority version is determined by identifying the highest priority feature that is specified in exactly one of the versions, and selecting that version."
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7 files changed

+183
-134
lines changed

7 files changed

+183
-134
lines changed

‎clang/test/CodeGen/attr-target-clones-aarch64.c‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -64,20 +64,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
6464
// CHECK-NEXT: resolver_entry:
6565
// CHECK-NEXT: call void @__init_cpu_features_resolver()
6666
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
67-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33664
68-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33664
67+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352
68+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352
6969
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
7070
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
7171
// CHECK: resolver_return:
72-
// CHECK-NEXT: ret ptr @ftc._MaesMlse
72+
// CHECK-NEXT: ret ptr @ftc._Msve2
7373
// CHECK: resolver_else:
7474
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
75-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 69793284352
76-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 69793284352
75+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664
76+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664
7777
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
7878
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
7979
// CHECK: resolver_return1:
80-
// CHECK-NEXT: ret ptr @ftc._Msve2
80+
// CHECK-NEXT: ret ptr @ftc._MaesMlse
8181
// CHECK: resolver_else2:
8282
// CHECK-NEXT: ret ptr @ftc.default
8383
//
@@ -411,20 +411,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
411411
// CHECK-NEXT: resolver_entry:
412412
// CHECK-NEXT: call void @__init_cpu_features_resolver()
413413
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
414-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817985280
415-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817985280
414+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624
415+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624
416416
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
417417
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
418418
// CHECK: resolver_return:
419-
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
419+
// CHECK-NEXT: ret ptr @ftc_inline3._Mbti
420420
// CHECK: resolver_else:
421421
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
422-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
423-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
422+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 70369817985280
423+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 70369817985280
424424
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
425425
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
426426
// CHECK: resolver_return1:
427-
// CHECK-NEXT: ret ptr @ftc_inline3._Mbti
427+
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
428428
// CHECK: resolver_else2:
429429
// CHECK-NEXT: ret ptr @ftc_inline3.default
430430
//
@@ -521,20 +521,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
521521
// CHECK-MTE-BTI-NEXT: resolver_entry:
522522
// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver()
523523
// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
524-
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33664
525-
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33664
524+
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352
525+
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352
526526
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
527527
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
528528
// CHECK-MTE-BTI: resolver_return:
529-
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._MaesMlse
529+
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._Msve2
530530
// CHECK-MTE-BTI: resolver_else:
531531
// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
532-
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 69793284352
533-
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 69793284352
532+
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664
533+
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664
534534
// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
535535
// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
536536
// CHECK-MTE-BTI: resolver_return1:
537-
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._Msve2
537+
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._MaesMlse
538538
// CHECK-MTE-BTI: resolver_else2:
539539
// CHECK-MTE-BTI-NEXT: ret ptr @ftc.default
540540
//
@@ -868,20 +868,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
868868
// CHECK-MTE-BTI-NEXT: resolver_entry:
869869
// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver()
870870
// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
871-
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817985280
872-
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817985280
871+
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624
872+
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624
873873
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
874874
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
875875
// CHECK-MTE-BTI: resolver_return:
876-
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._MsbMsve
876+
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._Mbti
877877
// CHECK-MTE-BTI: resolver_else:
878878
// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
879-
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
880-
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
879+
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 70369817985280
880+
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 70369817985280
881881
// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
882882
// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
883883
// CHECK-MTE-BTI: resolver_return1:
884-
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._Mbti
884+
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._MsbMsve
885885
// CHECK-MTE-BTI: resolver_else2:
886886
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3.default
887887
//

‎clang/test/CodeGen/attr-target-version.c‎

Lines changed: 39 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -463,12 +463,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
463463
// CHECK-NEXT: resolver_entry:
464464
// CHECK-NEXT: call void @__init_cpu_features_resolver()
465465
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
466-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 66315
467-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66315
466+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144119586256651008
467+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 144119586256651008
468468
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
469469
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
470470
// CHECK: resolver_return:
471-
// CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng
471+
// CHECK-NEXT: ret ptr @fmv._Msme2
472472
// CHECK: resolver_else:
473473
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
474474
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 72061992218723078
@@ -495,44 +495,44 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
495495
// CHECK-NEXT: ret ptr @fmv._McrcMls64
496496
// CHECK: resolver_else6:
497497
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
498-
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 17592186110728
499-
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 17592186110728
498+
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 1125899906842624
499+
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1125899906842624
500500
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
501501
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
502502
// CHECK: resolver_return7:
503-
// CHECK-NEXT: ret ptr @fmv._Mfp16fmlMmemtag
503+
// CHECK-NEXT: ret ptr @fmv._Mbti
504504
// CHECK: resolver_else8:
505505
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
506-
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 33536
507-
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 33536
506+
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 17592186110728
507+
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 17592186110728
508508
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
509509
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
510510
// CHECK: resolver_return9:
511-
// CHECK-NEXT: ret ptr @fmv._MaesMfp
511+
// CHECK-NEXT: ret ptr @fmv._Mfp16fmlMmemtag
512512
// CHECK: resolver_else10:
513513
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
514-
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 4992
515-
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 4992
514+
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 66315
515+
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 66315
516516
// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]]
517517
// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
518518
// CHECK: resolver_return11:
519-
// CHECK-NEXT: ret ptr @fmv._MlseMsha2
519+
// CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng
520520
// CHECK: resolver_else12:
521521
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
522-
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 144119586256651008
523-
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 144119586256651008
522+
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 33536
523+
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 33536
524524
// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]]
525525
// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
526526
// CHECK: resolver_return13:
527-
// CHECK-NEXT: ret ptr @fmv._Msme2
527+
// CHECK-NEXT: ret ptr @fmv._MaesMfp
528528
// CHECK: resolver_else14:
529529
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
530-
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 1125899906842624
531-
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 1125899906842624
530+
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 4992
531+
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 4992
532532
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
533533
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
534534
// CHECK: resolver_return15:
535-
// CHECK-NEXT: ret ptr @fmv._Mbti
535+
// CHECK-NEXT: ret ptr @fmv._MlseMsha2
536536
// CHECK: resolver_else16:
537537
// CHECK-NEXT: ret ptr @fmv.default
538538
//
@@ -773,60 +773,60 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
773773
// CHECK-NEXT: resolver_entry:
774774
// CHECK-NEXT: call void @__init_cpu_features_resolver()
775775
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
776-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4398182892352
777-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4398182892352
776+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 864708720653762560
777+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 864708720653762560
778778
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
779779
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
780780
// CHECK: resolver_return:
781-
// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme
781+
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3
782782
// CHECK: resolver_else:
783783
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
784-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 864708720653762560
785-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864708720653762560
784+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 19861002584864
785+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 19861002584864
786786
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
787787
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
788788
// CHECK: resolver_return1:
789-
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3
789+
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMsve2-sm4
790790
// CHECK: resolver_else2:
791791
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
792-
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 894427038464
793-
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 894427038464
792+
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4398182892352
793+
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4398182892352
794794
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
795795
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
796796
// CHECK: resolver_return3:
797-
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm
797+
// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme
798798
// CHECK: resolver_else4:
799799
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
800-
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 35433583360
801-
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 35433583360
800+
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 1444182864640
801+
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 1444182864640
802802
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
803803
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
804804
// CHECK: resolver_return5:
805-
// CHECK-NEXT: ret ptr @fmv_inline._MaesMf64mmMsha2
805+
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
806806
// CHECK: resolver_else6:
807807
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
808-
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 18320798464
809-
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 18320798464
808+
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 894427038464
809+
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 894427038464
810810
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
811811
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
812812
// CHECK: resolver_return7:
813-
// CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3
813+
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm
814814
// CHECK: resolver_else8:
815815
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
816-
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 19861002584864
817-
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 19861002584864
816+
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 35433583360
817+
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 35433583360
818818
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
819819
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
820820
// CHECK: resolver_return9:
821-
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMsve2-sm4
821+
// CHECK-NEXT: ret ptr @fmv_inline._MaesMf64mmMsha2
822822
// CHECK: resolver_else10:
823823
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
824-
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 1444182864640
825-
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 1444182864640
824+
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 18320798464
825+
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 18320798464
826826
// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]]
827827
// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
828828
// CHECK: resolver_return11:
829-
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
829+
// CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3
830830
// CHECK: resolver_else12:
831831
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
832832
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1208025856

‎llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc‎

Lines changed: 55 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,13 @@
1515
// changes in this file, first modify the primary copy and copy it over to
1616
// compiler-rt. compiler-rt tests will fail if the two files are not synced up.
1717
//
18+
// Additionally this file enumerates the feature priorities in ascending order,
19+
// as defined in the ACLE specification.
20+
//
1821
//===----------------------------------------------------------------------===//
1922

20-
#ifndef AARCH64_CPU_FEATURS_INC_H
21-
#define AARCH64_CPU_FEATURS_INC_H
23+
#ifndef AARCH64_CPU_FEATURES_INC_H
24+
#define AARCH64_CPU_FEATURES_INC_H
2225

2326
// Function Multi Versioning CPU features.
2427
enum CPUFeatures {
@@ -88,4 +91,54 @@ enum CPUFeatures {
8891
FEAT_INIT // Used as flag of features initialization completion
8992
};
9093

94+
// Function Multi Versioning feature priorities in ascending order.
95+
enum FeatPriorities {
96+
PRIOR_RNG,
97+
PRIOR_FLAGM,
98+
PRIOR_FLAGM2,
99+
PRIOR_LSE,
100+
PRIOR_FP,
101+
PRIOR_SIMD,
102+
PRIOR_DOTPROD,
103+
PRIOR_SM4,
104+
PRIOR_RDM,
105+
PRIOR_CRC,
106+
PRIOR_SHA2,
107+
PRIOR_SHA3,
108+
PRIOR_PMULL,
109+
PRIOR_FP16,
110+
PRIOR_FP16FML,
111+
PRIOR_DIT,
112+
PRIOR_DPB,
113+
PRIOR_DPB2,
114+
PRIOR_JSCVT,
115+
PRIOR_FCMA,
116+
PRIOR_RCPC,
117+
PRIOR_RCPC2,
118+
PRIOR_RCPC3,
119+
PRIOR_FRINTTS,
120+
PRIOR_I8MM,
121+
PRIOR_BF16,
122+
PRIOR_SVE,
123+
PRIOR_SVE_F32MM,
124+
PRIOR_SVE_F64MM,
125+
PRIOR_SVE2,
126+
PRIOR_SVE_PMULL128,
127+
PRIOR_SVE_BITPERM,
128+
PRIOR_SVE_SHA3,
129+
PRIOR_SVE_SM4,
130+
PRIOR_SME,
131+
PRIOR_MEMTAG2,
132+
PRIOR_SB,
133+
PRIOR_PREDRES,
134+
PRIOR_SSBS2,
135+
PRIOR_BTI,
136+
PRIOR_LS64_ACCDATA,
137+
PRIOR_WFXT,
138+
PRIOR_SME_F64,
139+
PRIOR_SME_I64,
140+
PRIOR_SME2,
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PRIOR_MOPS
142+
};
143+
91144
#endif

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -70,12 +70,12 @@ struct ExtensionInfo {
7070

7171
struct FMVInfo {
7272
StringRef Name; // The target_version/target_clones spelling.
73-
CPUFeatures Bit; // Index of the bit in the FMV feature bitset.
73+
CPUFeatures FeatureBit; // Index of the bit in the FMV feature bitset.
74+
FeatPriorities PriorityBit; // Index of the bit in the FMV priority bitset.
7475
std::optional<ArchExtKind> ID; // The architecture extension to enable.
75-
unsigned Priority; // FMV priority.
76-
FMVInfo(StringRef Name, CPUFeatures Bit, std::optional<ArchExtKind> ID,
77-
unsigned Priority)
78-
: Name(Name), Bit(Bit), ID(ID), Priority(Priority) {};
76+
FMVInfo(StringRef Name, CPUFeatures FeatureBit, FeatPriorities PriorityBit,
77+
std::optional<ArchExtKind> ID)
78+
: Name(Name), FeatureBit(FeatureBit), PriorityBit(PriorityBit), ID(ID) {};
7979
};
8080

8181
const std::vector<FMVInfo> &getFMVInfo();

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