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[FMV][AArch64] Unify ls64, ls64_v and ls64_accdata.
Originally I tried spliting these features in the compiler with llvm#101712, but I realized that there's no way to preserve backwards compatibility, therefore we decided to lump those features in the ACLE specification too ARM-software/acle#346. Since there are no hardware implementations out there which implement ls64 without ls64_v or ls64_accdata, this shouldn't be a regression for feature detection.
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12 files changed

+119
-136
lines changed

12 files changed

+119
-136
lines changed

‎clang/test/CodeGen/aarch64-cpu-supports.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,8 @@
2626
// CHECK-NEXT: br label [[RETURN]]
2727
// CHECK: if.end2:
2828
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
29-
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 166633186212708352
30-
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 166633186212708352
29+
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 42784196460019712
30+
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 42784196460019712
3131
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
3232
// CHECK-NEXT: br i1 [[TMP11]], label [[IF_THEN3:%.*]], label [[IF_END4:%.*]]
3333
// CHECK: if.then3:
@@ -52,7 +52,7 @@ int main(void) {
5252
if (__builtin_cpu_supports("sve2-pmull128+memtag"))
5353
return 2;
5454

55-
if (__builtin_cpu_supports("sme2+ls64_v+wfxt"))
55+
if (__builtin_cpu_supports("sme2+ls64+wfxt"))
5656
return 3;
5757

5858
if (__builtin_cpu_supports("avx2"))

‎clang/test/CodeGen/aarch64-fmv-dependencies.c‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -66,15 +66,9 @@ __attribute__((target_version("i8mm"))) int fmv(void) { return 0; }
6666
// CHECK: define dso_local i32 @fmv._Mjscvt() #[[jscvt:[0-9]+]] {
6767
__attribute__((target_version("jscvt"))) int fmv(void) { return 0; }
6868

69-
// CHECK: define dso_local i32 @fmv._Mls64() #[[ATTR0:[0-9]+]] {
69+
// CHECK: define dso_local i32 @fmv._Mls64() #[[ls64:[0-9]+]] {
7070
__attribute__((target_version("ls64"))) int fmv(void) { return 0; }
7171

72-
// CHECK: define dso_local i32 @fmv._Mls64_accdata() #[[ls64_accdata:[0-9]+]] {
73-
__attribute__((target_version("ls64_accdata"))) int fmv(void) { return 0; }
74-
75-
// CHECK: define dso_local i32 @fmv._Mls64_v() #[[ATTR0:[0-9]+]] {
76-
__attribute__((target_version("ls64_v"))) int fmv(void) { return 0; }
77-
7872
// CHECK: define dso_local i32 @fmv._Mlse() #[[lse:[0-9]+]] {
7973
__attribute__((target_version("lse"))) int fmv(void) { return 0; }
8074

@@ -210,7 +204,7 @@ int caller() {
210204
// CHECK: attributes #[[frintts]] = { {{.*}} "target-features"="+fp-armv8,+fptoint,+neon,+outline-atomics,+v8a"
211205
// CHECK: attributes #[[i8mm]] = { {{.*}} "target-features"="+fp-armv8,+i8mm,+neon,+outline-atomics,+v8a"
212206
// CHECK: attributes #[[jscvt]] = { {{.*}} "target-features"="+fp-armv8,+jsconv,+neon,+outline-atomics,+v8a"
213-
// CHECK: attributes #[[ls64_accdata]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a"
207+
// CHECK: attributes #[[ls64]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a"
214208
// CHECK: attributes #[[lse]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a"
215209
// CHECK: attributes #[[memtag2]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
216210
// CHECK: attributes #[[mops]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a"

‎clang/test/CodeGen/attr-target-clones-aarch64.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -336,8 +336,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
336336
// CHECK-NEXT: resolver_entry:
337337
// CHECK-NEXT: call void @__init_cpu_features_resolver()
338338
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
339-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456
340-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456
339+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4503737066323968
340+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4503737066323968
341341
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
342342
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
343343
// CHECK: resolver_return:
@@ -758,8 +758,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
758758
// CHECK-MTE-BTI-NEXT: resolver_entry:
759759
// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver()
760760
// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
761-
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456
762-
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456
761+
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4503737066323968
762+
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4503737066323968
763763
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
764764
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
765765
// CHECK-MTE-BTI: resolver_return:

‎clang/test/CodeGen/attr-target-version.c‎

Lines changed: 72 additions & 70 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp‎

Lines changed: 31 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 5
22
// RUN: %clang_cc1 -std=c++11 -triple aarch64-linux-gnu -emit-llvm %s -o - | FileCheck %s
33

4-
int __attribute__((target_clones("ls64_v+fp16", "default"))) foo_ovl(int) { return 1; }
5-
int __attribute__((target_clones("ls64_accdata+ls64"))) foo_ovl(void) { return 2; }
4+
int __attribute__((target_clones("ls64+fp16", "default"))) foo_ovl(int) { return 1; }
5+
int __attribute__((target_clones("fp16+ls64"))) foo_ovl(void) { return 2; }
66

77
int bar() {
88
return foo_ovl(1) + foo_ovl();
@@ -45,7 +45,7 @@ void run_foo_tml() {
4545
// CHECK: @_ZN7MyClassIssE7foo_tmlEv = weak_odr ifunc i32 (ptr), ptr @_ZN7MyClassIssE7foo_tmlEv.resolver
4646
// CHECK: @_ZN7MyClassIisE7foo_tmlEv = weak_odr ifunc i32 (ptr), ptr @_ZN7MyClassIisE7foo_tmlEv.resolver
4747
//.
48-
// CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovli._Mfp16Mls64_v(
48+
// CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovli._Mfp16Mls64(
4949
// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
5050
// CHECK-NEXT: [[ENTRY:.*:]]
5151
// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
@@ -57,18 +57,18 @@ void run_foo_tml() {
5757
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
5858
// CHECK-NEXT: call void @__init_cpu_features_resolver()
5959
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
60-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4503599627436032
61-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4503599627436032
60+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2251799813750784
61+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2251799813750784
6262
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
6363
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
6464
// CHECK: [[RESOLVER_RETURN]]:
65-
// CHECK-NEXT: ret ptr @_Z7foo_ovli._Mfp16Mls64_v
65+
// CHECK-NEXT: ret ptr @_Z7foo_ovli._Mfp16Mls64
6666
// CHECK: [[RESOLVER_ELSE]]:
6767
// CHECK-NEXT: ret ptr @_Z7foo_ovli.default
6868
//
6969
//
70-
// CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovlv._Mls64Mls64_accdata(
71-
// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
70+
// CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovlv._Mfp16Mls64(
71+
// CHECK-SAME: ) #[[ATTR0]] {
7272
// CHECK-NEXT: [[ENTRY:.*:]]
7373
// CHECK-NEXT: ret i32 2
7474
//
@@ -77,18 +77,18 @@ void run_foo_tml() {
7777
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
7878
// CHECK-NEXT: call void @__init_cpu_features_resolver()
7979
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
80-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 11258999068426240
81-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 11258999068426240
80+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2251799813750784
81+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2251799813750784
8282
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
8383
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
8484
// CHECK: [[RESOLVER_RETURN]]:
85-
// CHECK-NEXT: ret ptr @_Z7foo_ovlv._Mls64Mls64_accdata
85+
// CHECK-NEXT: ret ptr @_Z7foo_ovlv._Mfp16Mls64
8686
// CHECK: [[RESOLVER_ELSE]]:
8787
// CHECK-NEXT: ret ptr @_Z7foo_ovlv.default
8888
//
8989
//
9090
// CHECK-LABEL: define dso_local noundef i32 @_Z3barv(
91-
// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
91+
// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
9292
// CHECK-NEXT: [[ENTRY:.*:]]
9393
// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z7foo_ovli(i32 noundef 1)
9494
// CHECK-NEXT: [[CALL1:%.*]] = call noundef i32 @_Z7foo_ovlv()
@@ -97,7 +97,7 @@ void run_foo_tml() {
9797
//
9898
//
9999
// CHECK-LABEL: define dso_local void @_Z11run_foo_tmlv(
100-
// CHECK-SAME: ) #[[ATTR2]] {
100+
// CHECK-SAME: ) #[[ATTR1]] {
101101
// CHECK-NEXT: [[ENTRY:.*:]]
102102
// CHECK-NEXT: [[MC1:%.*]] = alloca [[STRUCT_MYCLASS:%.*]], align 1
103103
// CHECK-NEXT: [[MC2:%.*]] = alloca [[STRUCT_MYCLASS_0:%.*]], align 1
@@ -111,7 +111,7 @@ void run_foo_tml() {
111111
//
112112
//
113113
// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIfsE7foo_tmlEv(
114-
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2]] comdat {
114+
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR1]] comdat {
115115
// CHECK-NEXT: [[ENTRY:.*:]]
116116
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
117117
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
@@ -120,7 +120,7 @@ void run_foo_tml() {
120120
//
121121
//
122122
// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIdfE7foo_tmlEv(
123-
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2]] comdat {
123+
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR1]] comdat {
124124
// CHECK-NEXT: [[ENTRY:.*:]]
125125
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
126126
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
@@ -129,21 +129,21 @@ void run_foo_tml() {
129129
//
130130
//
131131
// CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovli.default(
132-
// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR2]] {
132+
// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR1]] {
133133
// CHECK-NEXT: [[ENTRY:.*:]]
134134
// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
135135
// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
136136
// CHECK-NEXT: ret i32 1
137137
//
138138
//
139139
// CHECK-LABEL: define dso_local noundef i32 @_Z7foo_ovlv.default(
140-
// CHECK-SAME: ) #[[ATTR2]] {
140+
// CHECK-SAME: ) #[[ATTR1]] {
141141
// CHECK-NEXT: [[ENTRY:.*:]]
142142
// CHECK-NEXT: ret i32 2
143143
//
144144
//
145145
// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIssE7foo_tmlEv._Mfrintts(
146-
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat {
146+
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat {
147147
// CHECK-NEXT: [[ENTRY:.*:]]
148148
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
149149
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
@@ -152,7 +152,7 @@ void run_foo_tml() {
152152
//
153153
//
154154
// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIssE7foo_tmlEv._Msme-f64f64Mssbs(
155-
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR4:[0-9]+]] comdat {
155+
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat {
156156
// CHECK-NEXT: [[ENTRY:.*:]]
157157
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
158158
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
@@ -161,7 +161,7 @@ void run_foo_tml() {
161161
//
162162
//
163163
// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIssE7foo_tmlEv.default(
164-
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2]] comdat {
164+
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR1]] comdat {
165165
// CHECK-NEXT: [[ENTRY:.*:]]
166166
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
167167
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
@@ -173,8 +173,8 @@ void run_foo_tml() {
173173
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
174174
// CHECK-NEXT: call void @__init_cpu_features_resolver()
175175
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
176-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36310271995674624
177-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36310271995674624
176+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 9288674231451648
177+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9288674231451648
178178
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
179179
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
180180
// CHECK: [[RESOLVER_RETURN]]:
@@ -192,7 +192,7 @@ void run_foo_tml() {
192192
//
193193
//
194194
// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIisE7foo_tmlEv._Mfrintts(
195-
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR3]] comdat {
195+
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2]] comdat {
196196
// CHECK-NEXT: [[ENTRY:.*:]]
197197
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
198198
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
@@ -201,7 +201,7 @@ void run_foo_tml() {
201201
//
202202
//
203203
// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIisE7foo_tmlEv._Msme-f64f64Mssbs(
204-
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR4]] comdat {
204+
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR3]] comdat {
205205
// CHECK-NEXT: [[ENTRY:.*:]]
206206
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
207207
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
@@ -210,7 +210,7 @@ void run_foo_tml() {
210210
//
211211
//
212212
// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7MyClassIisE7foo_tmlEv.default(
213-
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR2]] comdat {
213+
// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR1]] comdat {
214214
// CHECK-NEXT: [[ENTRY:.*:]]
215215
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
216216
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
@@ -222,8 +222,8 @@ void run_foo_tml() {
222222
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
223223
// CHECK-NEXT: call void @__init_cpu_features_resolver()
224224
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
225-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36310271995674624
226-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36310271995674624
225+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 9288674231451648
226+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9288674231451648
227227
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
228228
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
229229
// CHECK: [[RESOLVER_RETURN]]:
@@ -240,11 +240,10 @@ void run_foo_tml() {
240240
// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv.default
241241
//
242242
//.
243-
// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
244-
// CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ls64" }
245-
// CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
246-
// CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint" }
247-
// CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme-f64f64" }
243+
// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+ls64,+neon" }
244+
// CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
245+
// CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint" }
246+
// CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme-f64f64" }
248247
//.
249248
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
250249
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}

‎clang/test/CodeGenCXX/attr-target-version.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -235,8 +235,8 @@ int bar() {
235235
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
236236
// CHECK-NEXT: call void @__init_cpu_features_resolver()
237237
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
238-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36028797153181696
239-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36028797153181696
238+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 9007199388958720
239+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9007199388958720
240240
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
241241
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
242242
// CHECK: [[RESOLVER_RETURN]]:

‎clang/test/CodeGenCXX/fmv-namespace.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -90,8 +90,8 @@ __attribute((target_version("mops"))) int bar() { return 1; }
9090
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
9191
// CHECK-NEXT: call void @__init_cpu_features_resolver()
9292
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
93-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423488
94-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423488
93+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144115188075855872
94+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 144115188075855872
9595
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
9696
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
9797
// CHECK: [[RESOLVER_RETURN]]:

‎clang/test/Sema/attr-target-clones-aarch64.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ void __attribute__((target_clones("fp16+sve2-aes", "sb+sve2-sha3+rcpc3+mops", "r
55
// expected-warning@+1 {{unsupported 'default' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
66
void __attribute__((target_clones("default+sha3"))) warn1(void);
77
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
8-
void __attribute__((target_clones("ssbs+ls64"))) warn2(void);
8+
void __attribute__((target_clones("ssbs"))) warn2(void);
99

1010
// expected-error@+2 {{'target_clones' and 'target_version' attributes are not compatible}}
1111
// expected-note@+1 {{conflicting attribute is here}}
@@ -24,7 +24,7 @@ int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void)
2424
// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
2525
// expected-note@-2 {{previous declaration is here}}
2626
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
27-
int __attribute__((target_clones("dgh+memtag+rpres+ls64_v", "ebf16+dpb+sha1", "default"))) redecl4(void) { return 1; }
27+
int __attribute__((target_clones("dgh+memtag+rpres", "ebf16+dpb+sha1", "default"))) redecl4(void) { return 1; }
2828

2929
int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
3030
// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}

‎compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,6 @@ enum CPUFeatures {
7373
FEAT_SSBS,
7474
FEAT_SSBS2,
7575
FEAT_BTI,
76-
FEAT_LS64,
77-
FEAT_LS64_V,
7876
FEAT_LS64_ACCDATA,
7977
FEAT_WFXT,
8078
FEAT_SME_F64,

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -110,12 +110,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
110110
/* ID_AA64ISAR1_EL1.SPECRES >= 0b0001 */
111111
if (extractBits(ftr, 40, 4) >= 0x1)
112112
setCPUFeature(FEAT_PREDRES);
113-
/* ID_AA64ISAR1_EL1.LS64 >= 0b0001 */
114-
if (extractBits(ftr, 60, 4) >= 0x1)
115-
setCPUFeature(FEAT_LS64);
116-
/* ID_AA64ISAR1_EL1.LS64 >= 0b0010 */
117-
if (extractBits(ftr, 60, 4) >= 0x2)
118-
setCPUFeature(FEAT_LS64_V);
119113
/* ID_AA64ISAR1_EL1.LS64 >= 0b0011 */
120114
if (extractBits(ftr, 60, 4) >= 0x3)
121115
setCPUFeature(FEAT_LS64_ACCDATA);

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