Via drill hole preset

[mavenboard]

Minimum drill size for vias are .15mm not .1, and they said they cant change it in production. Please change it to .15mm from .1mm

[Cimos]

You will need to explain who "They" are. Which DRU Rules are you referring too?

[mavenboard]

The fab is jlcpcb. They are not able to change production files.

[Cimos]

Ok thanks, I will look at this and see if there is a fix needed.

Do you know the specific rule that you are referring too?

[Cimos]

Checked against JLCPCB's published capabilities. The minimum via drill they support depends on the order tier:

• 1-2 layer: 0.3mm
• 4-6 layer (preferred): 0.2mm
• 4-6 layer (more costly): 0.15mm

This rule file in upstream has Hole diameter set to (min 0.2mm) (max 6.3mm), which already rejects 0.1mm. So if your project allowed a 0.1mm via drill through DRC, the rules either weren't loaded or were overridden somewhere — KiCad's own Board Setup > Constraints values can override looser settings independently of the custom rules.

The maintained fork at https://github.com/Cimos/KiCad-CustomDesignRules has JLCPCB: Via Hole Size as a separate rule with the three tier options as comments, so users can pick the variant that matches their order. Closing-side note since labtroll is no longer maintaining this — feel free to follow up on the fork if you still see the issue with that file in place.