From a7dbdc394774bcffe7c1d69d03efe564a7986b97 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 25 Sep 2020 18:10:18 -0700 Subject: [PATCH 1/4] Add support for passing args to fsdbDumpvars --- fault/system_verilog_target.py | 8 ++++++-- tests/test_system_verilog_target.py | 9 ++++++--- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 4c93dd63..aedc26ab 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -61,7 +61,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/", disp_type='on_error', waveform_file=None, coverage=False, use_kratos=False, use_sva=False, skip_run=False, no_top_module=False, vivado_use_system_verilog=True, - disable_ndarray=False): + disable_ndarray=False, fsdb_dumpvars_args=""): """ circuit: a magma circuit @@ -160,6 +160,9 @@ def __init__(self, circuit, circuit_name=None, directory="build/", Default is False except when the simulator is "iverilog" when it is always True (since iverilog does not currently support unpacked arrays) + + fsdb_dumpvars_args: (optional) arguments to the `fsdbDumpvars()` + function """ # set default for list of external sources if include_verilog_libraries is None: @@ -264,6 +267,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/", raise ImportError("Cannot find kratos-runtime in the system. " "Please do \"pip install kratos-runtime\" " "to install.") + self.fsdb_dumpvars_args = fsdb_dumpvars_args # set up cadence tools command self.ncsim_cmd = self.cadence_cmd("irun") @@ -662,7 +666,7 @@ def generate_code(self, actions, power_args): f'$vcdplusmemon();'] if self.waveform_type == "fsdb": initial_body += [f'$fsdbDumpfile("{self.waveform_file}");', - f'$fsdbDumpvars();'] + f'$fsdbDumpvars({self.fsdb_dumpvars_args});'] elif self.dump_waveforms and self.simulator in {"iverilog", "vivado"}: # https://iverilog.fandom.com/wiki/GTKWAVE initial_body += [f'$dumpfile("{self.waveform_file}");', diff --git a/tests/test_system_verilog_target.py b/tests/test_system_verilog_target.py index f6c64a6a..62fef1cc 100644 --- a/tests/test_system_verilog_target.py +++ b/tests/test_system_verilog_target.py @@ -27,6 +27,7 @@ def test_waves(simulator, waveform_type, use_sva): tester.circuit.I = 1 tester.step(2) flags = [] + kwargs = {} if waveform_type == "fsdb": # Note this will only work on kiwi/buildkite env, users should set # their specific link flags @@ -34,12 +35,13 @@ def test_waves(simulator, waveform_type, use_sva): flags += ['-P', f' {verdi_home}/share/PLI/vcs_latest/LINUX64/novas.tab', f' {verdi_home}/share/PLI/vcs_latest/LINUX64/pli.a'] + kwargs["fsdb_dumpvars_args"] = '0, "BasicClkCircuit"' # Test default with tempfile.TemporaryDirectory(dir=".") as _dir: tester.compile_and_run(target="system-verilog", simulator=simulator, directory=_dir, use_sva=use_sva, waveform_type=waveform_type, - dump_waveforms=True, flags=flags) + dump_waveforms=True, flags=flags, **kwargs) assert os.path.exists(os.path.join(_dir, f"waveforms.{waveform_type}")) @@ -49,13 +51,14 @@ def test_waves(simulator, waveform_type, use_sva): directory=_dir, waveform_file=f"waves.{waveform_type}", use_sva=use_sva, waveform_type=waveform_type, - dump_waveforms=True, flags=flags) + dump_waveforms=True, flags=flags, **kwargs) assert os.path.exists(os.path.join(_dir, f"waves.{waveform_type}")) # Test off with tempfile.TemporaryDirectory(dir=".") as _dir: tester.compile_and_run(target="system-verilog", simulator=simulator, directory=_dir, dump_waveforms=False, - use_sva=use_sva, waveform_type=waveform_type) + use_sva=use_sva, waveform_type=waveform_type, + **kwargs) assert not os.path.exists(os.path.join(_dir, f"waveforms.{waveform_type}")) From 57b98f0340fecf82cc7e3bc4e4735aa1effb4550 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 25 Sep 2020 18:13:17 -0700 Subject: [PATCH 2/4] Add doc --- README.md | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/README.md b/README.md index 1436ea9b..0eb432d4 100644 --- a/README.md +++ b/README.md @@ -279,6 +279,23 @@ tester.compile_and_run(target="system-verilog", simulator="vcs", waveform_type="fsdb", dump_waveforms=True, flags=flags) ``` +To configure fsdb dumping, use the `fsdb_dumpvars_args` parameter of the +compile_and_run command to pass a string to the `$fsdbDumpvars()` function. + +For example: +```python +tester.compile_and_run(target="system-verilog", simulator="vcs", + waveform_type="fsdb", dump_waveforms=True, + fsdb_dumpvars_args='0, "top"') +``` + +will produce: +```verilog + $fsdbDumpvars(0, "top"); +``` + +inside the generated test bench. + ### How do I pass through flags to the simulator? The `verilator` and `system-verilog` target support the parameter `flags` which accepts a list of flags (strings) that will be passed through to the simulator From e837461c0b1ce248d8579de475b03878b350cb23 Mon Sep 17 00:00:00 2001 From: "Leonard (Lenny) Truong" Date: Fri, 25 Sep 2020 18:51:29 -0700 Subject: [PATCH 3/4] Update test_system_verilog_target.py --- tests/test_system_verilog_target.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/test_system_verilog_target.py b/tests/test_system_verilog_target.py index 62fef1cc..1eee70eb 100644 --- a/tests/test_system_verilog_target.py +++ b/tests/test_system_verilog_target.py @@ -35,7 +35,7 @@ def test_waves(simulator, waveform_type, use_sva): flags += ['-P', f' {verdi_home}/share/PLI/vcs_latest/LINUX64/novas.tab', f' {verdi_home}/share/PLI/vcs_latest/LINUX64/pli.a'] - kwargs["fsdb_dumpvars_args"] = '0, "BasicClkCircuit"' + kwargs["fsdb_dumpvars_args"] = '0, "dut"' # Test default with tempfile.TemporaryDirectory(dir=".") as _dir: tester.compile_and_run(target="system-verilog", simulator=simulator, From cef8b3e31eb894f834f274421896ebe19f816d6e Mon Sep 17 00:00:00 2001 From: "Leonard (Lenny) Truong" Date: Fri, 25 Sep 2020 18:51:47 -0700 Subject: [PATCH 4/4] Update README.md --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 0eb432d4..561ea705 100644 --- a/README.md +++ b/README.md @@ -286,12 +286,12 @@ For example: ```python tester.compile_and_run(target="system-verilog", simulator="vcs", waveform_type="fsdb", dump_waveforms=True, - fsdb_dumpvars_args='0, "top"') + fsdb_dumpvars_args='0, "dut"') ``` will produce: ```verilog - $fsdbDumpvars(0, "top"); + $fsdbDumpvars(0, "dut"); ``` inside the generated test bench.