diff --git a/.gitignore b/.gitignore index 9d91ac5720..a23ea2a120 100644 --- a/.gitignore +++ b/.gitignore @@ -6,3 +6,10 @@ actual.out qemu.log rusty-tags.vi +.vscode-ctags +.gdb_history +.idea +bin +lib +lib64 +/.cargo \ No newline at end of file diff --git a/Cargo.lock b/Cargo.lock index 12d08af516..dd517b3394 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -4,18 +4,24 @@ version = 3 [[package]] name = "aarch64-cpu" -version = "9.3.1" +version = "9.4.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "eb711c57d60565ba8f6523eb371e6243639617d817b4df1ae09af250af1af411" +checksum = "ac42a04a61c19fc8196dd728022a784baecc5d63d7e256c01ad1b3fbfab26287" dependencies = [ - "tock-registers", + "tock-registers 0.8.1", ] +[[package]] +name = "accessor" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bd8b2abd55bf1f9cffbf00fd594566c51a9d31402553284920c1309ca8351086" + [[package]] name = "aho-corasick" -version = "1.0.4" +version = "1.1.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6748e8def348ed4d14996fa801f4122cd763fff530258cdc03f64b25f89d3a5a" +checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916" dependencies = [ "memchr", ] @@ -56,9 +62,9 @@ checksum = "4b46cbb362ab8752921c97e041f5e366ee6297bd428a31275b9fcf1e380f7299" [[package]] name = "anstyle" -version = "1.0.1" +version = "1.0.7" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3a30da5c5f2d5e72842e00bcb57657162cdabef0931f40e2deb9b4140440cecd" +checksum = "038dfcf04a5feb68e9c60b21c9625a54c2c0616e79b72b0fd87075a056ae1d1b" [[package]] name = "arceos-bwbench" @@ -72,7 +78,11 @@ dependencies = [ name = "arceos-cli" version = "0.1.0" dependencies = [ + "axfeat", "axstd", + "driver_i2c", + "driver_usb", + "xhci", ] [[package]] @@ -141,14 +151,6 @@ dependencies = [ "axstd", ] -[[package]] -name = "arceos-raspi4" -version = "0.1.0" -dependencies = [ - "arm_pl011", - "axstd", -] - [[package]] name = "arceos-shell" version = "0.1.0" @@ -232,30 +234,30 @@ dependencies = [ name = "arm_gic" version = "0.1.0" dependencies = [ - "tock-registers", + "tock-registers 0.8.1", ] [[package]] name = "arm_pl011" version = "0.1.0" dependencies = [ - "tock-registers", + "tock-registers 0.8.1", ] [[package]] name = "atomic-polyfill" -version = "0.1.11" +version = "1.0.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e3ff7eb3f316534d83a8a2c3d1674ace8a5a71198eba31e2e2b597833f699b28" +checksum = "8cf2bce30dfe09ef0bfaef228b9d414faaf7e563035494d7fe092dba54b300f4" dependencies = [ "critical-section", ] [[package]] name = "autocfg" -version = "1.1.0" +version = "1.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa" +checksum = "f1fdabc7756949593fe60f30ec81974b613357de856987752631dea1e3394c80" [[package]] name = "axalloc" @@ -264,6 +266,7 @@ dependencies = [ "allocator", "axerrno", "cfg-if", + "lazy_static", "log", "memory_addr", "spinlock", @@ -301,6 +304,7 @@ dependencies = [ "driver_display", "driver_net", "driver_pci", + "driver_usb", "driver_virtio", "log", ] @@ -373,7 +377,7 @@ name = "axfs_vfs" version = "0.1.0" dependencies = [ "axerrno", - "bitflags 2.4.0", + "bitflags 2.5.0", "log", ] @@ -387,7 +391,7 @@ dependencies = [ "axalloc", "axconfig", "axlog", - "bitflags 2.4.0", + "bitflags 2.5.0", "cfg-if", "crate_interface", "dw_apb_uart", @@ -400,12 +404,12 @@ dependencies = [ "page_table_entry", "percpu", "ratio", - "raw-cpuid 11.0.1", + "raw-cpuid 11.0.2", "riscv", "sbi-rt", "spinlock", "static_assertions", - "tock-registers", + "tock-registers 0.8.1", "x2apic", "x86", "x86_64", @@ -538,7 +542,7 @@ source = "git+https://github.com/lhw2002426/bcm2835-sdhci.git?rev=e974f16#e974f1 dependencies = [ "aarch64-cpu", "log", - "tock-registers", + "tock-registers 0.8.1", "volatile 0.2.7", ] @@ -548,7 +552,7 @@ version = "0.66.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "f2b84e06fc203107bfbad243f4aba2af864eb7db3b1cf46ea0a023b0b433d2a7" dependencies = [ - "bitflags 2.4.0", + "bitflags 2.5.0", "cexpr", "clang-sys", "lazy_static", @@ -561,7 +565,7 @@ dependencies = [ "regex", "rustc-hash", "shlex", - "syn 2.0.29", + "syn 2.0.60", "which", ] @@ -585,9 +589,9 @@ checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" [[package]] name = "bitflags" -version = "2.4.0" +version = "2.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b4682ae6287fcf752ecaabbfcc7b6f9b72aa33933dc23a554d853aea8eea8635" +checksum = "cf4b9d6a944f767f8e5e0db018570623c85f3d925ac718db4e06d0187adb21c1" [[package]] name = "bitmap-allocator" @@ -599,34 +603,40 @@ dependencies = [ [[package]] name = "bitmaps" -version = "3.2.0" +version = "3.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "703642b98a00b3b90513279a8ede3fcfa479c126c5fb46e78f3051522f021403" +checksum = "a1d084b0137aaa901caf9f1e8b21daa6aa24d41cd806e111335541eff9683bd6" [[package]] name = "buddy_system_allocator" -version = "0.9.0" +version = "0.9.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "43f9365b6b0c9e1663ca4ca9440c00eda46bc85a3407070be8b5e0d8d1f29629" +checksum = "d44d578cadd17312c75e7d0ef489361f160ace58f7139aa32001fee1a51b89b5" [[package]] name = "bumpalo" -version = "3.13.0" +version = "3.16.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a3e2c3daef883ecc1b5d58c15adae93470a91d425f3532ba1695849656af3fc1" +checksum = "79296716171880943b8470b5f8d03aa55eb2e645a4874bdbb28adb49162e012c" + +[[package]] +name = "byte-slice-cast" +version = "0.3.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b0a5e3906bcbf133e33c1d4d95afc664ad37fbdb9f6568d8043e7ea8c27d93d3" [[package]] name = "byteorder" -version = "1.4.3" +version = "1.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610" +checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b" [[package]] name = "capability" version = "0.1.0" dependencies = [ "axerrno", - "bitflags 2.4.0", + "bitflags 2.5.0", ] [[package]] @@ -637,12 +647,9 @@ checksum = "37b2a672a2cb129a2e41c10b1224bb368f9f37a2b16b612598138befd7b37eb5" [[package]] name = "cc" -version = "1.0.83" +version = "1.0.96" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f1174fb0b6ec23863f8b971027804a42614e347eafb0a95bf0b12cdae21fc4d0" -dependencies = [ - "libc", -] +checksum = "065a29261d53ba54260972629f9ca6bffa69bac13cd1fed61420f7fa68b9f8bd" [[package]] name = "cexpr" @@ -661,24 +668,23 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd" [[package]] name = "chrono" -version = "0.4.26" +version = "0.4.38" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ec837a71355b28f6556dbd569b37b3f363091c0bd4b2e735674521b4c5fd9bc5" +checksum = "a21f936df1771bf62b77f047b726c4625ff2e8aa607c01ec06e5a05bd8463401" dependencies = [ "android-tzdata", "iana-time-zone", "js-sys", "num-traits", - "time", "wasm-bindgen", - "winapi", + "windows-targets", ] [[package]] name = "ciborium" -version = "0.2.1" +version = "0.2.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "effd91f6c78e5a4ace8a5d3c0b6bfaec9e2baaef55f3efc00e45fb2e477ee926" +checksum = "42e69ffd6f0917f5c029256a24d0161db17cea3997d185db0d35926308770f0e" dependencies = [ "ciborium-io", "ciborium-ll", @@ -687,15 +693,15 @@ dependencies = [ [[package]] name = "ciborium-io" -version = "0.2.1" +version = "0.2.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "cdf919175532b369853f5d5e20b26b43112613fd6fe7aee757e35f7a44642656" +checksum = "05afea1e0a06c9be33d539b876f1ce3692f4afea2cb41f740e7743225ed1c757" [[package]] name = "ciborium-ll" -version = "0.2.1" +version = "0.2.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "defaa24ecc093c77630e6c15e17c51f5e187bf35ee514f4e2d67baaa96dae22b" +checksum = "57663b653d948a338bfb3eeba9bb2fd5fcfaecb9e199e87e1eda4d9e8b240fd9" dependencies = [ "ciborium-io", "half", @@ -703,9 +709,9 @@ dependencies = [ [[package]] name = "clang-sys" -version = "1.6.1" +version = "1.7.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c688fc74432808e3eb684cae8830a86be1d66a2bd58e1f248ed0960a590baf6f" +checksum = "67523a3b4be3ce1989d607a828d036249522dd9c1c8de7f4dd2dae43a37369d1" dependencies = [ "glob", "libc", @@ -714,18 +720,18 @@ dependencies = [ [[package]] name = "clap" -version = "4.3.23" +version = "4.5.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "03aef18ddf7d879c15ce20f04826ef8418101c7e528014c3eeea13321047dca3" +checksum = "90bc066a67923782aa8515dbaea16946c5bcc5addbd668bb80af688e53e548a0" dependencies = [ "clap_builder", ] [[package]] name = "clap_builder" -version = "4.3.23" +version = "4.5.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f8ce6fffb678c9b80a70b6b6de0aad31df727623a70fd9a842c30cd573e2fa98" +checksum = "ae129e2e766ae0ec03484e609954119f123cc1fe650337e155d03b022f24f7b4" dependencies = [ "anstyle", "clap_lex", @@ -733,9 +739,24 @@ dependencies = [ [[package]] name = "clap_lex" -version = "0.5.0" +version = "0.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "98cc8fbded0c607b7ba9dd60cd98df59af97e84d24e49c8557331cfc26d301ce" + +[[package]] +name = "conquer-once" +version = "0.4.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5d008a441c0f269f36ca13712528069a86a3e60dffee1d98b976eb3b0b2160b4" +dependencies = [ + "conquer-util", +] + +[[package]] +name = "conquer-util" +version = "0.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2da6da31387c7e4ef160ffab6d5e7f00c42626fe39aea70a7b0f1773f7dd6c1b" +checksum = "e763eef8846b13b380f37dfecda401770b0ca4e56e95170237bd7c25c7db3582" [[package]] name = "const-default" @@ -745,9 +766,9 @@ checksum = "0b396d1f76d455557e1218ec8066ae14bba60b4b36ecd55577ba979f5db7ecaa" [[package]] name = "core-foundation-sys" -version = "0.8.4" +version = "0.8.6" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e496a50fda8aacccc86d7529e2c1e0892dbd0f898a6b5645b5561b89c3210efa" +checksum = "06ea2b9bc92be3c2baa9334a323ebca2d6f074ff852cd1d7b11064035cd3868f" [[package]] name = "core_detect" @@ -761,7 +782,7 @@ version = "0.1.1" dependencies = [ "proc-macro2", "quote", - "syn 2.0.29", + "syn 2.0.60", ] [[package]] @@ -807,53 +828,85 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "7059fff8937831a9ae6f0fe4d658ffabf58f2ca96aa9dec1c889f936f705f216" [[package]] -name = "crossbeam-channel" -version = "0.5.8" +name = "crossbeam-deque" +version = "0.8.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a33c2bf77f2df06183c3aa30d1e96c0695a313d4f9c453cc3762a6db39f99200" +checksum = "613f8cc01fe9cf1a3eb3d7f488fd2fa8388403e97039e2f73692932e291a770d" dependencies = [ - "cfg-if", + "crossbeam-epoch", "crossbeam-utils", ] [[package]] -name = "crossbeam-deque" -version = "0.8.3" +name = "crossbeam-epoch" +version = "0.9.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ce6fd6f855243022dcecf8702fef0c297d4338e226845fe067f6341ad9fa0cef" +checksum = "5b82ac4a3c2ca9c3460964f020e1402edd5753411d7737aa39c3714ad1b5420e" dependencies = [ - "cfg-if", - "crossbeam-epoch", "crossbeam-utils", ] [[package]] -name = "crossbeam-epoch" -version = "0.9.15" +name = "crossbeam-queue" +version = "0.3.11" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ae211234986c545741a7dc064309f67ee1e5ad243d0e48335adc0484d960bcc7" +checksum = "df0346b5d5e76ac2fe4e327c5fd1118d6be7c51dfb18f9b7922923f287471e35" dependencies = [ - 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"tock-registers", + "tock-registers 0.8.1", ] [[package]] name = "either" -version = "1.9.0" +version = "1.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a26ae43d7bcc3b814de94796a5e736d4029efb0ee900c12e2d54c993ad1a1e07" +checksum = "a47c1c47d2f5964e29c61246e81db715514cd532db6b5116a25ea3c03d6780a2" [[package]] name = "embedded-graphics" @@ -983,25 +1142,14 @@ checksum = "5443807d6dff69373d433ab9ef5378ad8df50ca6298caf15de6e52e24aaf54d5" [[package]] name = "errno" -version = "0.3.2" +version = "0.3.8" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6b30f669a7961ef1631673d2766cc92f52d64f7ef354d4fe0ddfd30ed52f0f4f" +checksum = "a258e46cdc063eb8519c00b9fc845fc47bcfca4130e2f08e88665ceda8474245" dependencies = [ - "errno-dragonfly", "libc", "windows-sys", ] -[[package]] -name = "errno-dragonfly" -version = "0.1.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "aa68f1b12764fab894d2755d2518754e71b4fd80ecfb822714a1206c2aab39bf" -dependencies = [ - "cc", - "libc", -] - [[package]] name = "fatfs" version = "0.4.0" @@ -1027,15 +1175,55 @@ dependencies = [ "num-traits", ] +[[package]] +name = "fnv" +version = "1.0.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1" + +[[package]] +name = "futures-core" +version = "0.3.30" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dfc6580bb841c5a68e9ef15c77ccc837b40a7504914d52e47b8b0e9bbda25a1d" + +[[package]] +name = "futures-intrusive" +version = "0.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1d930c203dd0b6ff06e0201a4a2fe9149b43c684fd4420555b26d21b1a02956f" +dependencies = [ + "futures-core", + "lock_api", +] + +[[package]] +name = "futures-task" +version = "0.3.30" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "38d84fa142264698cdce1a9f9172cf383a0c82de1bddcf3092901442c4097004" + +[[package]] +name = "futures-util" +version = "0.3.30" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3d6401deb83407ab3da39eba7e33987a73c3df0c82b4bb5813ee871c19c41d48" +dependencies = [ + "futures-core", + "futures-task", + "pin-project-lite", + "pin-utils", +] + [[package]] name = "getrandom" -version = "0.2.10" +version = "0.2.14" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "be4136b2a15dd319360be1c07d9933517ccf0be8f16bf62a3bee4f0d618df427" +checksum = "94b22e06ecb0110981051723910cbf0b5f5e09a2062dd7663334ee79a9d1286c" dependencies = [ "cfg-if", "libc", - "wasi 0.11.0+wasi-snapshot-preview1", + "wasi", ] [[package]] @@ -1046,9 +1234,13 @@ checksum = "d2fabcfbdc87f4758337ca535fb41a6d701b65693ce38287d856d1674551ec9b" [[package]] name = "half" -version = "1.8.2" +version = "2.4.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "eabb4a44450da02c90444cf74558da904edde8fb4e9035a9a6a4e15445af0bd7" +checksum = "6dd08c532ae367adf81c312a4580bc67f1d0fe8bc9c460520283f4c0ff277888" +dependencies = [ + "cfg-if", + "crunchy", +] [[package]] name = "handler_table" @@ -1065,15 +1257,15 @@ dependencies = [ [[package]] name = "hashbrown" -version = "0.14.0" +version = "0.14.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2c6201b9ff9fd90a5a3bac2e56a830d0caa509576f0e503818ee82c181b3437a" +checksum = "e5274423e17b7c9fc20b6e7e208532f9b19825d82dfd615708b70edd83df41f1" [[package]] name = "heapless" -version = "0.7.16" +version = "0.7.17" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "db04bc24a18b9ea980628ecf00e6c0264f3c1426dac36c00cb49b6fbad8b0743" +checksum = "cdc6457c0eb62c71aac4bc17216026d8410337c4126773b9c5daba343f17964f" dependencies = [ "atomic-polyfill", "hash32", @@ -1084,22 +1276,31 @@ dependencies = [ [[package]] name = "hermit-abi" -version = "0.3.2" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d231dfb89cfffdbc30e7fc41579ed6066ad03abda9e567ccafae602b97ec5024" + +[[package]] +name = "home" +version = "0.5.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "443144c8cdadd93ebf52ddb4056d257f5b52c04d3c804e657d19eb73fc33668b" +checksum = "e3d1354bf6b7235cb4a0576c2619fd4ed18183f689b12b006a0ee7329eeff9a5" +dependencies = [ + "windows-sys", +] [[package]] name = "iana-time-zone" -version = "0.1.57" +version = "0.1.60" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2fad5b825842d2b38bd206f3e81d6957625fd7f0a361e345c30e01a0ae2dd613" +checksum = "e7ffbb5a1b541ea2561f8c41c087286cc091e21e556a4f09a8f6cbf17b69b141" dependencies = [ "android_system_properties", "core-foundation-sys", "iana-time-zone-haiku", "js-sys", "wasm-bindgen", - "windows", + "windows-core", ] [[package]] @@ -1111,11 +1312,17 @@ dependencies = [ "cc", ] +[[package]] +name = "ident_case" +version = "1.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39" + [[package]] name = "indexmap" -version = "2.0.0" +version = "2.2.6" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d5477fe2230a79769d8dc68e0eabf5437907c0457a5614a9e8dddb67f65eb65d" +checksum = "168fb715dda47215e360912c096649d23d58bf392ac62f73919e831745e40f26" dependencies = [ "equivalent", "hashbrown", @@ -1123,12 +1330,12 @@ dependencies = [ [[package]] name = "is-terminal" -version = "0.4.9" +version = "0.4.12" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "cb0889898416213fab133e1d33a0e5858a48177452750691bde3666d0fdbaf8b" +checksum = "f23ff5ef2b80d608d61efee834934d862cd92461afc0560dedf493e4c033738b" dependencies = [ "hermit-abi", - "rustix", + "libc", "windows-sys", ] @@ -1143,9 +1350,9 @@ dependencies = [ [[package]] name = "itoa" -version = "1.0.9" +version = "1.0.11" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "af150ab688ff2122fcef229be89cb50dd66af9e01a4ff320cc137eecc9bacc38" +checksum = "49f1f14873335454500d59611f1cf4a4b0f786f9ac11f4312a78e4cf2566695b" [[package]] name = "ixgbe-driver" @@ -1161,9 +1368,9 @@ dependencies = [ [[package]] name = "js-sys" -version = "0.3.64" +version = "0.3.69" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c5f195fe497f702db0f318b07fdd68edb16955aed830df8363d837542f8f935a" +checksum = "29c15563dc2726973df627357ce0c9ddddbea194836909d655df6a75d2cf296d" dependencies = [ "wasm-bindgen", ] @@ -1197,18 +1404,18 @@ checksum = "830d08ce1d1d941e6b30645f1a0eb5643013d835ce3779a5fc208261dbe10f55" [[package]] name = "libc" -version = "0.2.147" +version = "0.2.154" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b4668fb0ea861c1df094127ac5f1da3409a82116a4ba74fca2e58ef927159bb3" +checksum = "ae743338b92ff9146ce83992f766a31066a91a8c84a45e0e9f21e7cf6de6d346" [[package]] name = "libloading" -version = "0.7.4" +version = "0.8.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b67380fd3b2fbe7527a606e18729d21c6f3951633d0500574c4dc22d2d638b9f" +checksum = "0c2a198fb6b0eada2a8df47933734e6d35d350665a33a3593d7164fa52c75c19" dependencies = [ "cfg-if", - "winapi", + "windows-targets", ] [[package]] @@ -1217,15 +1424,15 @@ version = "0.1.0" [[package]] name = "linux-raw-sys" -version = "0.4.5" +version = "0.4.13" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "57bcfdad1b858c2db7c38303a6d2ad4dfaf5eb53dfeb0910128b2c26d6158503" +checksum = "01cda141df6706de531b6c46c3a33ecca755538219bd484262fa09410c13539c" [[package]] name = "lock_api" -version = "0.4.10" +version = "0.4.12" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c1cc9717a20b1bb222f333e6a92fd32f7d8a18ddc5a3191a11af45dcbf4dcd16" +checksum = "07af8b9cdd281b7915f413fa73f29ebd5d55d0d3f0155584dade1ff18cea1b17" dependencies = [ "autocfg", "scopeguard", @@ -1233,9 +1440,9 @@ dependencies = [ [[package]] name = "log" -version = "0.4.19" +version = "0.4.21" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b06a4cde4c0f271a446782e3eff8de789548ce57dbc8eca9292c27f4a42004b4" +checksum = "90ed8c1e510134f979dbc4f070f87d4313098b704861a105fe34231c70a3901c" [[package]] name = "managed" @@ -1245,18 +1452,9 @@ checksum = "0ca88d725a0a943b096803bd34e73a4437208b6077654cc4ecb2947a5f91618d" [[package]] name = "memchr" -version = "2.5.0" +version = "2.7.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2dffe52ecf27772e601905b7522cb4ef790d2cc203488bbd0e2fe85fcb74566d" - -[[package]] -name = "memoffset" -version = "0.9.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5a634b1c61a95585bd15607c6ab0c4e5b226e695ff2800ba0cdccddf208c406c" -dependencies = [ - "autocfg", -] +checksum = "6c8640c5d730cb13ebd907d8d04b52f55ac9a2eec55b440c8892f40d56c76c1d" [[package]] name = "memory_addr" @@ -1264,9 +1462,9 @@ version = "0.1.0" [[package]] name = "micromath" -version = "2.0.0" +version = "2.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "39617bc909d64b068dcffd0e3e31679195b5576d0c83fadc52690268cc2b2b55" +checksum = "c3c8dda44ff03a2f238717214da50f65d5a53b45cd213a7370424ffdb6fae815" [[package]] name = "minimal-lexical" @@ -1300,29 +1498,41 @@ dependencies = [ ] [[package]] -name = "num-traits" -version = "0.2.16" +name = "num-derive" +version = "0.3.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f30b0abd723be7e2ffca1272140fac1a2f084c77ec3e123c192b66af1ee9e6c2" +checksum = "876a53fff98e03a936a674b29568b0e605f06b29372c2489ff4de23f1949743d" dependencies = [ - "autocfg", + "proc-macro2", + "quote", + "syn 1.0.109", ] [[package]] -name = "num_cpus" -version = "1.16.0" +name = "num-derive" +version = "0.4.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4161fcb6d602d4d2081af7c3a45852d875a03dd337a6bfdd6e06407b61342a43" +checksum = "ed3955f1a9c7c0c15e092f9c887db08b1fc683305fdf6eb6684f22555355e202" dependencies = [ - "hermit-abi", - "libc", + "proc-macro2", + "quote", + "syn 2.0.60", +] + +[[package]] +name = "num-traits" +version = "0.2.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "da0df0e5185db44f69b44f26786fe401b6c293d1907744beaa7fa62b2e5a517a" +dependencies = [ + "autocfg", ] [[package]] name = "once_cell" -version = "1.18.0" +version = "1.19.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dd8b5dd2ae5ed71462c540258bedcb51965123ad7e7ccf4b9a8cafaa4a63576d" +checksum = "3fdb12b2476b595f9358c5161aa467c2438859caa136dec86c26fdd2efe17b92" [[package]] name = "oorandom" @@ -1330,6 +1540,15 @@ version = "11.1.3" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "0ab1bc2a289d34bd04a330323ac98a1b4bc82c9d9fcb1e66b63caa84da26b575" +[[package]] +name = "os_units" +version = "0.4.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "76f5d56adacad84b1031b481722ddd4ec261ba0b5c420d45855248918b21dff3" +dependencies = [ + "x86_64", +] + [[package]] name = "page_table" version = "0.1.0" @@ -1344,7 +1563,7 @@ name = "page_table_entry" version = "0.1.0" dependencies = [ "aarch64-cpu", - "bitflags 2.4.0", + "bitflags 2.5.0", "memory_addr", "x86_64", ] @@ -1355,6 +1574,16 @@ version = "1.0.14" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "de3145af08024dea9fa9914f381a17b8fc6034dfb00f3a84013f7ff43f29ed4c" +[[package]] +name = "pci_types" +version = "0.6.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ebac2b2ee11791f721a51184b632a916b3044f2ee7b2374e7fdcfdf3eaf29c79" +dependencies = [ + "bit_field", + "bitflags 2.5.0", +] + [[package]] name = "peeking_take_while" version = "0.1.2" @@ -1378,9 +1607,21 @@ version = "0.1.0" dependencies = [ "proc-macro2", "quote", - "syn 2.0.29", + "syn 2.0.60", ] +[[package]] +name = "pin-project-lite" +version = "0.2.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bda66fc9667c18cb2758a2ac84d1167245054bcf85d5d1aaa6923f45801bdd02" + +[[package]] +name = "pin-utils" +version = "0.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8b870d8c151b6f2fb93e84a13146138f05d02ed11c7e7c54f8826aaaf7c9f184" + [[package]] name = "plotters" version = "0.3.5" @@ -1417,12 +1658,12 @@ checksum = "5b40af805b3121feab8a3c29f04d8ad262fa8e0561883e7653e024ae4479e6de" [[package]] name = "prettyplease" -version = "0.2.12" +version = "0.2.19" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6c64d9ba0963cdcea2e1b2230fbae2bab30eb25a174be395c41e764bfb65dd62" +checksum = "5ac2cf0f2e4f42b49f5ffd07dae8d746508ef7526c13940e5f524012ae6c6550" dependencies = [ "proc-macro2", - "syn 2.0.29", + "syn 2.0.60", ] [[package]] @@ -1451,18 +1692,18 @@ dependencies = [ [[package]] name = "proc-macro2" -version = "1.0.66" +version = "1.0.81" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "18fb31db3f9bddb2ea821cde30a9f70117e3f119938b5ee630b7403aa6e2ead9" +checksum = "3d1597b0c024618f09a9c3b8655b7e430397a36d23fdafec26d6965e9eec3eba" dependencies = [ "unicode-ident", ] [[package]] name = "quote" -version = "1.0.33" +version = "1.0.36" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5267fca4496028628a95160fc423a33e8b2e6af8a5302579e322e4b520293cae" +checksum = "0fa76aaf39101c457836aec0ce2316dbdc3ab723cdda1c6bd4e6ad4208acaca7" dependencies = [ "proc-macro2", ] @@ -1512,18 +1753,18 @@ dependencies = [ [[package]] name = "raw-cpuid" -version = "11.0.1" +version = "11.0.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9d86a7c4638d42c44551f4791a20e687dbb4c3de1f33c43dd71e355cd429def1" +checksum = "e29830cbb1290e404f24c73af91c5d8d631ce7e128691e9477556b540cd01ecd" dependencies = [ - "bitflags 2.4.0", + "bitflags 2.5.0", ] [[package]] name = "rayon" -version = "1.7.0" +version = "1.10.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1d2df5196e37bcc87abebc0053e20787d73847bb33134a69841207dd0a47f03b" +checksum = "b418a60154510ca1a002a752ca9714984e21e4241e804d32555251faf8b78ffa" dependencies = [ "either", "rayon-core", @@ -1531,21 +1772,19 @@ dependencies = [ [[package]] name = "rayon-core" -version = "1.11.0" +version = "1.12.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4b8f95bd6966f5c87776639160a66bd8ab9895d9d4ab01ddba9fc60661aebe8d" +checksum = "1465873a3dfdaa8ae7cb14b4383657caab0b3e8a0aa9ae8e04b044854c8dfce2" dependencies = [ - "crossbeam-channel", "crossbeam-deque", "crossbeam-utils", - "num_cpus", ] [[package]] name = "regex" -version = "1.9.3" +version = "1.10.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "81bc1d4caf89fac26a70747fe603c130093b53c773888797a6329091246d651a" +checksum = "c117dbdfde9c8308975b6a18d71f3f385c89461f7b3fb054288ecf2a2058ba4c" dependencies = [ "aho-corasick", "memchr", @@ -1555,9 +1794,9 @@ dependencies = [ [[package]] name = "regex-automata" -version = "0.3.6" +version = "0.4.6" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fed1ceff11a1dddaee50c9dc8e4938bd106e9d89ae372f192311e7da498e3b69" +checksum = "86b83b8b9847f9bf95ef68afb0b8e6cdb80f498442f5179a29fad448fcc1eaea" dependencies = [ "aho-corasick", "memchr", @@ -1566,9 +1805,9 @@ dependencies = [ [[package]] name = "regex-syntax" -version = "0.7.4" +version = "0.8.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e5ea92a5b6195c6ef2a0295ea818b312502c6fc94dde986c5553242e18fd4ce2" +checksum = "adad44e29e4c806119491a7f06f03de4d1af22c3a680dd47f1e6e179439d1f56" [[package]] name = "riscv" @@ -1610,11 +1849,11 @@ dependencies = [ [[package]] name = "rustix" -version = "0.38.8" +version = "0.38.34" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "19ed4fa021d81c8392ce04db050a3da9a60299050b7ae1cf482d862b54a7218f" +checksum = "70dc5ec042f7a43c4a73241207cecc9873a06d45debb38b329f8541d85c2730f" dependencies = [ - "bitflags 2.4.0", + "bitflags 2.5.0", "errno", "libc", "linux-raw-sys", @@ -1623,15 +1862,15 @@ dependencies = [ [[package]] name = "rustversion" -version = "1.0.14" +version = "1.0.15" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7ffc183a10b4478d04cbbbfc96d0873219d962dd5accaff2ffbd4ceb7df837f4" +checksum = "80af6f9131f277a45a3fba6ce8e2258037bb0477a67e610d3c1fe046ab31de47" [[package]] name = "ryu" -version = "1.0.15" +version = "1.0.17" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1ad4cc8da4ef723ed60bced201181d83791ad433213d8c24efffda1eec85d741" +checksum = "e86697c916019a8588c99b5fac3cead74ec0b4b819707a682fd4d23fa0ce1ba1" [[package]] name = "same-file" @@ -1675,35 +1914,35 @@ checksum = "94143f37725109f92c262ed2cf5e59bce7498c01bcc1502d7b9afe439a4e9f49" [[package]] name = "semver" -version = "1.0.18" +version = "1.0.22" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b0293b4b29daaf487284529cc2f5675b8e57c61f70167ba415a463651fd6a918" +checksum = "92d43fe69e652f3df9bdc2b85b2854a0825b86e4fb76bc44d945137d053639ca" [[package]] name = "serde" -version = "1.0.185" +version = "1.0.200" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "be9b6f69f1dfd54c3b568ffa45c310d6973a5e5148fd40cf515acaf38cf5bc31" +checksum = "ddc6f9cc94d67c0e21aaf7eda3a010fd3af78ebf6e096aa6e2e13c79749cce4f" dependencies = [ "serde_derive", ] [[package]] name = "serde_derive" -version = "1.0.185" +version = "1.0.200" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dc59dfdcbad1437773485e0367fea4b090a2e0a16d9ffc46af47764536a298ec" +checksum = "856f046b9400cee3c8c94ed572ecdb752444c24528c035cd35882aad6f492bcb" dependencies = [ "proc-macro2", "quote", - "syn 2.0.29", + "syn 2.0.60", ] [[package]] name = "serde_json" -version = "1.0.105" +version = "1.0.116" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "693151e1ac27563d6dbcec9dee9fbd5da8539b20fa14ad3752b2e6d363ace360" +checksum = "3e17db7126d17feb94eb3fad46bf1a96b034e8aacbc2e775fe81505f8b0b2813" dependencies = [ "itoa", "ryu", @@ -1712,9 +1951,9 @@ dependencies = [ [[package]] name = "shlex" -version = "1.1.0" +version = "1.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "43b2853a4d09f215c24cc5489c992ce46052d359b5109343cbafbf26bc62f8a3" +checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64" [[package]] name = "slab_allocator" @@ -1760,6 +1999,28 @@ dependencies = [ "kernel_guard", ] +[[package]] +name = "spinning_top" +version = "0.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d96d2d1d716fb500937168cc09353ffdc7a012be8475ac7308e1bdf0e3923300" +dependencies = [ + "lock_api", +] + +[[package]] +name = "ssd1306" +version = "0.8.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b37918f6137f2b58427181c3e10a731bef1061a9756b13ffbade64f21892acc6" +dependencies = [ + "display-interface", + "display-interface-i2c", + "display-interface-spi", + "embedded-graphics-core", + "embedded-hal", +] + [[package]] name = "stable_deref_trait" version = "1.2.0" @@ -1772,6 +2033,12 @@ version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "a2eb9349b6444b326872e140eb1cf5e7c522154d69e7a0ffb0fb81c06b37543f" +[[package]] +name = "strsim" +version = "0.10.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "73473c0e59e6d5812c5dfe2a064a6444949f089e20eec9a2e5506596494e4623" + [[package]] name = "svgbobdoc" version = "0.3.0" @@ -1798,9 +2065,9 @@ dependencies = [ [[package]] name = "syn" -version = "2.0.29" +version = "2.0.60" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c324c494eba9d92503e6f1ef2e6df781e78f6a7705a0202d9801b198807d518a" +checksum = "909518bc7b1c9b779f1bbf07f2929d35af9f0f37e47c6e9ef7f9dddc1e1821f3" dependencies = [ "proc-macro2", "quote", @@ -1809,39 +2076,37 @@ dependencies = [ [[package]] name = "thiserror" -version = "1.0.47" +version = "1.0.59" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "97a802ec30afc17eee47b2855fc72e0c4cd62be9b4efe6591edde0ec5bd68d8f" +checksum = "f0126ad08bff79f29fc3ae6a55cc72352056dfff61e3ff8bb7129476d44b23aa" dependencies = [ "thiserror-impl", ] [[package]] name = "thiserror-impl" -version = "1.0.47" +version = "1.0.59" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6bb623b56e39ab7dcd4b1b98bb6c8f8d907ed255b18de254088016b27a8ee19b" +checksum = "d1cd413b5d558b4c5bf3680e324a6fa5014e7b7c067a51e69dbdf47eb7148b66" dependencies = [ "proc-macro2", "quote", - "syn 2.0.29", + "syn 2.0.60", ] [[package]] -name = "time" -version = "0.1.45" +name = "timer_list" +version = "0.1.0" + +[[package]] +name = "tinybmp" +version = "0.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1b797afad3f312d1c66a56d11d0316f916356d11bd158fbc6ca6389ff6bf805a" +checksum = "197cc000e382175ff15abd9c54c694ef80ef20cb07e7f956c71e3ea97fc8dc60" dependencies = [ - "libc", - "wasi 0.10.0+wasi-snapshot-preview1", - "winapi", + "embedded-graphics", ] -[[package]] -name = "timer_list" -version = "0.1.0" - [[package]] name = "tinytemplate" version = "1.2.1" @@ -1858,17 +2123,23 @@ version = "0.8.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "696941a0aee7e276a165a978b37918fd5d22c55c3d6bda197813070ca9c0f21c" +[[package]] +name = "tock-registers" +version = "0.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2b9e2fdb3a1e862c0661768b7ed25390811df1947a8acbfbefe09b47078d93c4" + [[package]] name = "toml_datetime" -version = "0.6.3" +version = "0.6.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7cda73e2f1397b1262d6dfdcef8aafae14d1de7748d66822d3bfeeb6d03e5e4b" +checksum = "3550f4e9685620ac18a50ed434eb3aec30db8ba93b0287467bca5826ea25baf1" [[package]] name = "toml_edit" -version = "0.19.14" +version = "0.19.15" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f8123f27e969974a3dfba720fdb560be359f57b44302d280ba72e76a74480e8a" +checksum = "1b5bb770da30e5cbfde35a2d7b9b8a2c4b8ef89548a7a6aeab5c9a576e3e7421" dependencies = [ "indexmap", "toml_datetime", @@ -1881,20 +2152,20 @@ version = "0.1.0" dependencies = [ "proc-macro2", "quote", - "syn 2.0.29", + "syn 2.0.60", ] [[package]] name = "unicode-ident" -version = "1.0.11" +version = "1.0.12" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "301abaae475aa91687eb82514b328ab47a211a533026cb25fc3e519b86adfc3c" +checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b" [[package]] name = "unicode-width" -version = "0.1.10" +version = "0.1.12" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c0edd1e5b14653f783770bce4a4dabb4a5108a5370a5f5d8cfe8710c361f6c8b" +checksum = "68f5e5f3158ecfd4b8ff6fe086db7c8467a2dfdac97fe420f2b7c4aa97af66d6" [[package]] name = "version_check" @@ -1904,10 +2175,10 @@ checksum = "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e483f" [[package]] name = "virtio-drivers" -version = "0.4.0" -source = "git+https://github.com/rcore-os/virtio-drivers.git?rev=409ee72#409ee723c92adf309e825a7b87f53049707ed306" +version = "0.7.1" +source = "git+https://github.com/rcore-os/virtio-drivers.git?rev=4b60f5d#4b60f5d341a7211dfec7382062f965c5433c51c2" dependencies = [ - "bitflags 1.3.2", + "bitflags 2.5.0", "log", "zerocopy", ] @@ -1938,20 +2209,14 @@ checksum = "442887c63f2c839b346c192d047a7c87e73d0689c9157b00b53dcc27dd5ea793" [[package]] name = "walkdir" -version = "2.3.3" +version = "2.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "36df944cda56c7d8d8b7496af378e6b16de9284591917d307c9b4d313c44e698" +checksum = "29790946404f91d9c5d06f9874efddea1dc06c5efe94541a7d6863108e3a5e4b" dependencies = [ "same-file", "winapi-util", ] -[[package]] -name = "wasi" -version = "0.10.0+wasi-snapshot-preview1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1a143597ca7c7793eff794def352d41792a93c481eb1042423ff7ff72ba2c31f" - [[package]] name = "wasi" version = "0.11.0+wasi-snapshot-preview1" @@ -1960,9 +2225,9 @@ checksum = "9c8d87e72b64a3b4db28d11ce29237c246188f4f51057d65a7eab63b7987e423" [[package]] name = "wasm-bindgen" -version = "0.2.87" +version = "0.2.92" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7706a72ab36d8cb1f80ffbf0e071533974a60d0a308d01a5d0375bf60499a342" +checksum = "4be2531df63900aeb2bca0daaaddec08491ee64ceecbee5076636a3b026795a8" dependencies = [ "cfg-if", "wasm-bindgen-macro", @@ -1970,24 +2235,24 @@ dependencies = [ [[package]] name = "wasm-bindgen-backend" -version = "0.2.87" +version = "0.2.92" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5ef2b6d3c510e9625e5fe6f509ab07d66a760f0885d858736483c32ed7809abd" +checksum = "614d787b966d3989fa7bb98a654e369c762374fd3213d212cfc0251257e747da" dependencies = [ "bumpalo", "log", "once_cell", "proc-macro2", "quote", - "syn 2.0.29", + "syn 2.0.60", "wasm-bindgen-shared", ] [[package]] name = "wasm-bindgen-macro" -version = "0.2.87" +version = "0.2.92" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dee495e55982a3bd48105a7b947fd2a9b4a8ae3010041b9e0faab3f9cd028f1d" +checksum = "a1f8823de937b71b9460c0c34e25f3da88250760bec0ebac694b49997550d726" dependencies = [ "quote", "wasm-bindgen-macro-support", @@ -1995,28 +2260,28 @@ dependencies = [ [[package]] name = "wasm-bindgen-macro-support" -version = "0.2.87" +version = "0.2.92" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "54681b18a46765f095758388f2d0cf16eb8d4169b639ab575a8f5693af210c7b" +checksum = "e94f17b526d0a461a191c78ea52bbce64071ed5c04c9ffe424dcb38f74171bb7" dependencies = [ "proc-macro2", "quote", - "syn 2.0.29", + "syn 2.0.60", "wasm-bindgen-backend", "wasm-bindgen-shared", ] [[package]] name = "wasm-bindgen-shared" -version = "0.2.87" +version = "0.2.92" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ca6ad05a4870b2bf5fe995117d3728437bd27d7cd5f06f13c17443ef369775a1" +checksum = "af190c94f2773fdb3729c55b007a722abb5384da03bc0986df4c289bf5567e96" [[package]] name = "web-sys" -version = "0.3.64" +version = "0.3.69" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9b85cbef8c220a6abc02aefd892dfc0fc23afb1c6a426316ec33253a3877249b" +checksum = "77afa9a11836342370f4817622a2f0f418b134426d91a82dfb48f532d2ec13ef" dependencies = [ "js-sys", "wasm-bindgen", @@ -2024,73 +2289,53 @@ dependencies = [ [[package]] name = "which" -version = "4.4.0" +version = "4.4.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2441c784c52b289a054b7201fc93253e288f094e2f4be9058343127c4226a269" +checksum = "87ba24419a2078cd2b0f2ede2691b6c66d8e47836da3b6db8265ebad47afbfc7" dependencies = [ "either", - "libc", + "home", "once_cell", + "rustix", ] -[[package]] -name = "winapi" -version = "0.3.9" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5c839a674fcd7a98952e593242ea400abe93992746761e38641405d28b00f419" -dependencies = [ - "winapi-i686-pc-windows-gnu", - "winapi-x86_64-pc-windows-gnu", -] - -[[package]] -name = "winapi-i686-pc-windows-gnu" -version = "0.4.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ac3b87c63620426dd9b991e5ce0329eff545bccbbb34f3be09ff6fb6ab51b7b6" - [[package]] name = "winapi-util" -version = "0.1.5" +version = "0.1.8" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "70ec6ce85bb158151cae5e5c87f95a8e97d2c0c4b001223f33a334e3ce5de178" +checksum = "4d4cc384e1e73b93bafa6fb4f1df8c41695c8a91cf9c4c64358067d15a7b6c6b" dependencies = [ - "winapi", + "windows-sys", ] [[package]] -name = "winapi-x86_64-pc-windows-gnu" -version = "0.4.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f" - -[[package]] -name = "windows" -version = "0.48.0" +name = "windows-core" +version = "0.52.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e686886bc078bc1b0b600cac0147aadb815089b6e4da64016cbd754b6342700f" +checksum = "33ab640c8d7e35bf8ba19b884ba838ceb4fba93a4e8c65a9059d08afcfc683d9" dependencies = [ "windows-targets", ] [[package]] name = "windows-sys" -version = "0.48.0" +version = "0.52.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "677d2418bec65e3338edb076e806bc1ec15693c5d0104683f2efe857f61056a9" +checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d" dependencies = [ "windows-targets", ] [[package]] name = "windows-targets" -version = "0.48.5" +version = "0.52.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9a2fa6e2155d7247be68c096456083145c183cbbbc2764150dda45a87197940c" +checksum = "6f0713a46559409d202e70e28227288446bf7841d3211583a4b53e3f6d96e7eb" dependencies = [ "windows_aarch64_gnullvm", "windows_aarch64_msvc", "windows_i686_gnu", + "windows_i686_gnullvm", "windows_i686_msvc", "windows_x86_64_gnu", "windows_x86_64_gnullvm", @@ -2099,60 +2344,66 @@ dependencies = [ [[package]] name = "windows_aarch64_gnullvm" -version = "0.48.5" +version = "0.52.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2b38e32f0abccf9987a4e3079dfb67dcd799fb61361e53e2882c3cbaf0d905d8" +checksum = "7088eed71e8b8dda258ecc8bac5fb1153c5cffaf2578fc8ff5d61e23578d3263" [[package]] name = "windows_aarch64_msvc" -version = "0.48.5" +version = "0.52.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dc35310971f3b2dbbf3f0690a219f40e2d9afcf64f9ab7cc1be722937c26b4bc" +checksum = "9985fd1504e250c615ca5f281c3f7a6da76213ebd5ccc9561496568a2752afb6" [[package]] name = "windows_i686_gnu" -version = "0.48.5" +version = "0.52.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "88ba073cf16d5372720ec942a8ccbf61626074c6d4dd2e745299726ce8b89670" + +[[package]] +name = "windows_i686_gnullvm" +version = "0.52.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a75915e7def60c94dcef72200b9a8e58e5091744960da64ec734a6c6e9b3743e" +checksum = "87f4261229030a858f36b459e748ae97545d6f1ec60e5e0d6a3d32e0dc232ee9" [[package]] name = "windows_i686_msvc" -version = "0.48.5" +version = "0.52.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8f55c233f70c4b27f66c523580f78f1004e8b5a8b659e05a4eb49d4166cca406" +checksum = "db3c2bf3d13d5b658be73463284eaf12830ac9a26a90c717b7f771dfe97487bf" [[package]] name = "windows_x86_64_gnu" -version = "0.48.5" +version = "0.52.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "53d40abd2583d23e4718fddf1ebec84dbff8381c07cae67ff7768bbf19c6718e" +checksum = "4e4246f76bdeff09eb48875a0fd3e2af6aada79d409d33011886d3e1581517d9" [[package]] name = "windows_x86_64_gnullvm" -version = "0.48.5" +version = "0.52.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0b7b52767868a23d5bab768e390dc5f5c55825b6d30b86c844ff2dc7414044cc" +checksum = "852298e482cd67c356ddd9570386e2862b5673c85bd5f88df9ab6802b334c596" [[package]] name = "windows_x86_64_msvc" -version = "0.48.5" +version = "0.52.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ed94fce61571a4006852b7389a063ab983c02eb1bb37b47f8272ce92d06d9538" +checksum = "bec47e5bfd1bff0eeaf6d8b485cc1074891a197ab4225d504cb7a1ab88b02bf0" [[package]] name = "winnow" -version = "0.5.14" +version = "0.5.40" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d09770118a7eb1ccaf4a594a221334119a44a814fcb0d31c5b85e83e97227a97" +checksum = "f593a95398737aeed53e489c785df13f3618e41dbcd6718c6addbf1395aa6876" dependencies = [ "memchr", ] [[package]] name = "x2apic" -version = "0.4.2" +version = "0.4.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "547152b57dd1ae0ce7a4ef1c6470f6039aa7ed22e2179d5bc4f3eda1304e0db3" +checksum = "cbcd582541cbb8ef1dfc24a3c849a64ff074b1b512af723ad90056558d424602" dependencies = [ "bit", "bitflags 1.3.2", @@ -2174,21 +2425,34 @@ dependencies = [ [[package]] name = "x86_64" -version = "0.14.10" +version = "0.14.12" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "100555a863c0092238c2e0e814c1096c1e5cf066a309c696a87e907b5f8c5d69" +checksum = "96cb6fd45bfeab6a5055c5bffdb08768bd0c069f1d946debe585bbb380a7c062" dependencies = [ "bit_field", - "bitflags 1.3.2", + "bitflags 2.5.0", "rustversion", "volatile 0.4.6", ] +[[package]] +name = "xhci" +version = "0.9.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "09f3f0483969259f2adb6524054400d94ac352e59fa37da6c6ca3b9b3d83ff83" +dependencies = [ + "accessor", + "bit_field", + "num-derive 0.3.3", + "num-traits", + "paste", +] + [[package]] name = "zerocopy" -version = "0.6.3" +version = "0.7.32" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f3b9c234616391070b0b173963ebc65a9195068e7ed3731c6edac2ec45ebe106" +checksum = "74d4d3961e53fa4c9a25a8637fc2bfaf2595b3d3ae34875568a5cf64787716be" dependencies = [ "byteorder", "zerocopy-derive", @@ -2196,11 +2460,11 @@ dependencies = [ [[package]] name = "zerocopy-derive" -version = "0.6.3" +version = "0.7.32" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8f7f3a471f98d0a61c34322fbbfd10c384b07687f680d4119813713f72308d91" +checksum = "9ce1b18ccd8e73a9321186f97e46f9f04b778851177567b1975109d26a08d2a6" dependencies = [ "proc-macro2", "quote", - "syn 2.0.29", + "syn 2.0.60", ] diff --git a/Cargo.toml b/Cargo.toml index 2d41b98b64..0dbf7262da 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -19,6 +19,7 @@ members = [ "crates/driver_net", "crates/driver_pci", "crates/driver_virtio", + "crates/driver_usb", "crates/flatten_objects", "crates/handler_table", "crates/kernel_guard", @@ -36,6 +37,7 @@ members = [ "crates/timer_list", "crates/tuple_for_each", + "modules/axalloc", "modules/axconfig", "modules/axdisplay", @@ -71,7 +73,6 @@ members = [ "apps/task/priority", "apps/task/tls", "apps/cli", - "apps/boards/raspi4", ] diff --git a/Makefile b/Makefile index b351596584..913968d283 100644 --- a/Makefile +++ b/Makefile @@ -19,7 +19,9 @@ # - `ACCEL`: Enable hardware acceleration (KVM on linux) # - `QEMU_LOG`: Enable QEMU logging (log file is "qemu.log") # - `NET_DUMP`: Enable network packet dump (log file is "netdump.pcap") -# - `NET_DEV`: QEMU netdev backend types: user, tap +# - `NET_DEV`: QEMU netdev backend types: user, tap, bridge +# - `VFIO_PCI`: PCI device address in the format "bus:dev.func" to passthrough +# - `VHOST`: Enable vhost-net for tap backend (only for `NET_DEV=tap`) # * Network options: # - `IP`: ArceOS IPv4 address (default is 10.0.2.15 for QEMU user netdev) # - `GW`: Gateway IPv4 address (default is 10.0.2.2 for QEMU user netdev) @@ -48,6 +50,8 @@ DISK_IMG ?= disk.img QEMU_LOG ?= n NET_DUMP ?= n NET_DEV ?= user +VFIO_PCI ?= +VHOST ?= n # Network options IP ?= 10.0.2.15 @@ -103,6 +107,10 @@ else ifeq ($(ARCH), aarch64) ACCEL ?= n PLATFORM_NAME ?= aarch64-qemu-virt TARGET := aarch64-unknown-none-softfloat +# else ifeq ($(ARCH), phytium-pi) +# ACCEL ?= n +# PLATFORM_NAME ?= aarch64-phytium-pi +# TARGET := aarch64-unknown-none-softfloat else $(error "ARCH" must be one of "x86_64", "riscv64", or "aarch64") endif @@ -141,8 +149,12 @@ include scripts/make/utils.mk include scripts/make/build.mk include scripts/make/qemu.mk include scripts/make/test.mk + + ifeq ($(PLATFORM_NAME), aarch64-raspi4) include scripts/make/raspi4.mk +else ifeq ($(PLATFORM_NAME), aarch64-phytium-pi) + include scripts/make/phytium-pi.mk else ifeq ($(PLATFORM_NAME), aarch64-bsta1000b) include scripts/make/bsta1000b-fada.mk endif diff --git a/api/arceos_posix_api/src/lib.rs b/api/arceos_posix_api/src/lib.rs index 1e0e126e9e..75eb9bd7ce 100644 --- a/api/arceos_posix_api/src/lib.rs +++ b/api/arceos_posix_api/src/lib.rs @@ -4,7 +4,6 @@ #![cfg_attr(all(not(test), not(doc)), no_std)] #![feature(ip_in_core)] -#![feature(result_option_inspect)] #![feature(doc_cfg)] #![feature(doc_auto_cfg)] #![allow(clippy::missing_safety_doc)] diff --git a/api/axfeat/Cargo.toml b/api/axfeat/Cargo.toml index 2947a7ea1d..df1198a19e 100644 --- a/api/axfeat/Cargo.toml +++ b/api/axfeat/Cargo.toml @@ -45,6 +45,13 @@ net = ["alloc", "paging", "axdriver/virtio-net", "dep:axnet", "axruntime/net"] # Display display = ["alloc", "paging", "axdriver/virtio-gpu", "dep:axdisplay", "axruntime/display"] +# USB Host +usb-host = ["alloc", "paging", "axdriver/usb_host", "axruntime/usb","multitask"] + +# Board support package +phytium-pi = ["axdriver?/phytium-xhci", "axdriver?/phytium-pci"] + + # Device drivers bus-mmio = ["axdriver?/bus-mmio"] bus-pci = ["axdriver?/bus-pci"] diff --git a/apps/boards/raspi4/Cargo.toml b/apps/boards/raspi4/Cargo.toml deleted file mode 100644 index 20ba2836e1..0000000000 --- a/apps/boards/raspi4/Cargo.toml +++ /dev/null @@ -1,12 +0,0 @@ -[package] -name = "arceos-raspi4" -version = "0.1.0" -edition = "2021" -authors = ["Yuekai Jia "] - -# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html - -[dependencies] -axstd = { path = "../../../ulib/axstd", optional = true } - -arm_pl011 = { version = "0.1.0", path = "../../../crates/arm_pl011" } \ No newline at end of file diff --git a/apps/boards/raspi4/README.md b/apps/boards/raspi4/README.md deleted file mode 100644 index 2382fa00b6..0000000000 --- a/apps/boards/raspi4/README.md +++ /dev/null @@ -1,149 +0,0 @@ - -### 编译生成 img 文件的命令 -``` -make A=apps/boards/raspi4 ARCH=aarch64 PLATFORM=aarch64-raspi4 LOG=debug SMP=4 run -cat ../rust-raspberrypi-OS-tutorials/06_uart_chainloader/kernel8.img apps/boards/raspi4/raspi4_aarch64-raspi4.bin > kernel8.img -``` - -### 编译过程记录 -``` -# make A=apps/boards/raspi4 ARCH=aarch64 PLATFORM=aarch64-raspi4 LOG=debug SMP=4 run - Building App: raspi4, Arch: aarch64, Platform: aarch64-raspi4, App type: rust -cargo build --target aarch64-unknown-none-softfloat --target-dir /root/Github/Chenlong/arceos/target --release --manifest-path apps/boards/raspi4/Cargo.toml --features "axstd/log-level-debug axstd/smp" - Compiling axconfig v0.1.0 (/root/Github/Chenlong/arceos/modules/axconfig) - Compiling spinlock v0.1.0 (/root/Github/Chenlong/arceos/crates/spinlock) - Compiling axhal v0.1.0 (/root/Github/Chenlong/arceos/modules/axhal) - Compiling axlog v0.1.0 (/root/Github/Chenlong/arceos/modules/axlog) - Compiling axruntime v0.1.0 (/root/Github/Chenlong/arceos/modules/axruntime) - Compiling axfeat v0.1.0 (/root/Github/Chenlong/arceos/api/axfeat) - Compiling arceos_api v0.1.0 (/root/Github/Chenlong/arceos/api/arceos_api) - Compiling axstd v0.1.0 (/root/Github/Chenlong/arceos/ulib/axstd) - Compiling arceos-raspi4 v0.1.0 (/root/Github/Chenlong/arceos/apps/boards/raspi4) - Finished release [optimized] target(s) in 1.59s -rust-objcopy --binary-architecture=aarch64 apps/boards/raspi4/raspi4_aarch64-raspi4.elf --strip-all -O binary apps/boards/raspi4/raspi4_aarch64-raspi4.bin - Running on qemu... -emu-system-aarch64 -m 2G -smp 4 -cpu cortex-a72 -machine raspi4b2g -kernel apps/boards/raspi4/raspi4_aarch64-raspi4.bin -nographic - - d8888 .d88888b. .d8888b. - d88888 d88P" "Y88b d88P Y88b - d88P888 888 888 Y88b. - d88P 888 888d888 .d8888b .d88b. 888 888 "Y888b. - d88P 888 888P" d88P" d8P Y8b 888 888 "Y88b. - d88P 888 888 888 88888888 888 888 "888 - d8888888888 888 Y88b. Y8b. Y88b. .d88P Y88b d88P -d88P 888 888 "Y8888P "Y8888 "Y88888P" "Y8888P" - -arch = aarch64 -platform = aarch64-raspi4 -target = aarch64-unknown-none-softfloat -smp = 4 -build_mode = release -log_level = debug - -[ 0.013401 axruntime:126] Logging is enabled. -[ 0.017938 axruntime:127] Primary CPU 0 started, dtb = 0x100. -[ 0.020174 axruntime:129] Found physcial memory regions: -[ 0.022343 axruntime:131] [PA:0x80000, PA:0x87000) .text (READ | EXECUTE | RESERVED) -[ 0.025306 axruntime:131] [PA:0x87000, PA:0x89000) .rodata (READ | RESERVED) -[ 0.027690 axruntime:131] [PA:0x89000, PA:0x8d000) .data .tdata .tbss .percpu (READ | WRITE | RESERVED) -[ 0.029109 axruntime:131] [PA:0x8d000, PA:0x18d000) boot stack (READ | WRITE | RESERVED) -[ 0.030433 axruntime:131] [PA:0x18d000, PA:0x18e000) .bss (READ | WRITE | RESERVED) -[ 0.031586 axruntime:131] [PA:0x0, PA:0x1000) spintable (READ | WRITE | RESERVED) -[ 0.032880 axruntime:131] [PA:0x18e000, PA:0xfc000000) free memory (READ | WRITE | FREE) -[ 0.034360 axruntime:131] [PA:0xfe201000, PA:0xfe202000) mmio (READ | WRITE | DEVICE | RESERVED) -[ 0.035648 axruntime:131] [PA:0xff841000, PA:0xff849000) mmio (READ | WRITE | DEVICE | RESERVED) -[ 0.036969 axruntime:149] Initialize platform devices... -[ 0.038219 axruntime::mp:18] starting CPU 1... -[ 0.040891 axruntime::mp:35] Secondary CPU 1 started. -[ 0.045548 axruntime::mp:18] starting CPU 2... -[ 0.046443 axruntime::mp:45] Secondary CPU 1 init OK. -[ 0.055724 axruntime::mp:35] Secondary CPU 2 started. -[ 0.056580 axruntime::mp:18] starting CPU 3... -[ 0.058083 axruntime::mp:45] Secondary CPU 2 init OK. -[ 0.063700 axruntime::mp:35] Secondary CPU 3 started. -[ 0.064109 axruntime::mp:45] Secondary CPU 3 init OK. -[ 0.068492 axruntime:185] Primary CPU 0 init OK. -Hello, world! -start -??`g1 -forward -??d~1 -2 -3 -4 -stop -??1 -turn left -??d?1 -forward -??d~1 -2 -3 -4 -stop -??1 -turn left -??d?1 -forward -??d~1 -2 -3 -4 -stop -??1 -turn left -??d?1 -forward -??d~1 -2 -3 -4 -stop -??1 -turn left -??d?1 -forward -??d~1 -2 -3 -4 -stop -??1 -turn left -??d?1 -forward -??d~1 -2 -3 -4 -stop -??1 -turn left -??d?1 -forward -??d~1 -2 -3 -4 -stop -??1 -turn left -??d?1 -forward -??d~1 -2 -3 -4 -stop -??1 -turn left -??d?1 -forward -??d~1 -2 -3 -4 -stop -??1 - -``` diff --git a/apps/boards/raspi4/src/main.rs b/apps/boards/raspi4/src/main.rs deleted file mode 100644 index c51ba6c389..0000000000 --- a/apps/boards/raspi4/src/main.rs +++ /dev/null @@ -1,159 +0,0 @@ -#![cfg_attr(feature = "axstd", no_std)] -#![cfg_attr(feature = "axstd", no_main)] - -#[cfg(feature = "axstd")] -use axstd::println; -use arm_pl011::pl011::Pl011Uart; - -#[cfg_attr(feature = "axstd", no_mangle)] -fn main() { - println!("Hello, world!"); - - fn delay(seconds: u64) { - for i in 1..seconds+1 { - println!("{} ", i); - - fn fibonacci_recursive(n: u64) -> u64 { - if n == 0 { - return 0; - } - if n == 1 { - return 1; - } - return fibonacci_recursive(n - 1) + fibonacci_recursive(n - 2); - } - - fibonacci_recursive(34 + (i % 2)); - } - } - - let uart_base = 0xffff_0000_fe20_1000 as *mut u8; - let mut uart = Pl011Uart::new(uart_base); - - println!("start"); - { - // 鸣笛：0xFF_FC_05_02_60_00_67 - uart.putchar(0xff); - uart.putchar(0xfc); - uart.putchar(0x05); - uart.putchar(0x02); - uart.putchar(0x60); - uart.putchar(0x00); - uart.putchar(0x67); - } - delay(1); - - loop { - println!("forward"); - { - // 前进：0xff_fc_07_11_01_01_64_00_7e - uart.putchar(0xff); - uart.putchar(0xfc); - uart.putchar(0x07); - uart.putchar(0x11); - uart.putchar(0x01); - uart.putchar(0x01); - uart.putchar(0x64); - uart.putchar(0x00); - uart.putchar(0x7e); - } - delay(6); - - println!("stop"); - { - // 停止：0xff_fc_07_11_01_00_00_00_19 - uart.putchar(0xff); - uart.putchar(0xfc); - uart.putchar(0x07); - uart.putchar(0x11); - uart.putchar(0x01); - uart.putchar(0x00); - uart.putchar(0x00); - uart.putchar(0x00); - uart.putchar(0x19); - } - delay(1); - - println!("turn right"); - { - // // 左转：0xff_fc_07_11_01_05_64_00_82 - // uart.putchar(0xff); - // uart.putchar(0xfc); - // uart.putchar(0x07); - // uart.putchar(0x11); - // uart.putchar(0x01); - // uart.putchar(0x05); - // uart.putchar(0x64); - // uart.putchar(0x00); - // uart.putchar(0x82); - - // 右转：0xff_fc_07_11_01_06_64_00_83 - uart.putchar(0xff); - uart.putchar(0xfc); - uart.putchar(0x07); - uart.putchar(0x11); - uart.putchar(0x01); - uart.putchar(0x06); - uart.putchar(0x64); - uart.putchar(0x00); - uart.putchar(0x83); - } - delay(1); - // println!("forward"); - // { - // // 前进：0xff_fc_07_11_01_01_64_00_7e - // uart.putchar(0xff); - // uart.putchar(0xfc); - // uart.putchar(0x07); - // uart.putchar(0x11); - // uart.putchar(0x01); - // uart.putchar(0x01); - // uart.putchar(0x64); - // uart.putchar(0x00); - // uart.putchar(0x7e); - // } - // delay(4); - - println!("stop"); - { - // 停止：0xff_fc_07_11_01_00_00_00_19 - uart.putchar(0xff); - uart.putchar(0xfc); - uart.putchar(0x07); - uart.putchar(0x11); - uart.putchar(0x01); - uart.putchar(0x00); - uart.putchar(0x00); - uart.putchar(0x00); - uart.putchar(0x19); - } - delay(1); - - println!("turn right"); - { - // // 左转：0xff_fc_07_11_01_05_64_00_82 - // uart.putchar(0xff); - // uart.putchar(0xfc); - // uart.putchar(0x07); - // uart.putchar(0x11); - // uart.putchar(0x01); - // uart.putchar(0x05); - // uart.putchar(0x64); - // uart.putchar(0x00); - // uart.putchar(0x82); - - // 右转：0xff_fc_07_11_01_06_64_00_83 - uart.putchar(0xff); - uart.putchar(0xfc); - uart.putchar(0x07); - uart.putchar(0x11); - uart.putchar(0x01); - uart.putchar(0x06); - uart.putchar(0x64); - uart.putchar(0x00); - uart.putchar(0x83); - } - delay(1); - } - -} diff --git a/apps/cli/Cargo.toml b/apps/cli/Cargo.toml index f5a776b9c0..fed46ec2b7 100644 --- a/apps/cli/Cargo.toml +++ b/apps/cli/Cargo.toml @@ -16,4 +16,9 @@ default = [] # crate_interface = { path = "../../../crates/crate_interface", optional = true } # axstd = { path = "../../../ulib/axstd", features = ["alloc", "fs"], optional = true } -axstd = { path = "../../ulib/axstd", optional = true } \ No newline at end of file +driver_i2c = { path = "../../crates/driver_i2c" } +axstd = { path = "../../ulib/axstd", optional = true } +axfeat = {path = "../../api/axfeat", features = ["phytium-pi","usb-host","multitask"]} +driver_usb ={ path = "../../crates/driver_usb",features = ["phytium-xhci"]} +xhci = "0.9" + diff --git a/apps/cli/src/cmd.rs b/apps/cli/src/cmd.rs index 9fed8c4cb5..821e6e1c15 100644 --- a/apps/cli/src/cmd.rs +++ b/apps/cli/src/cmd.rs @@ -1,5 +1,4 @@ use std::io::{self}; - #[cfg(all(not(feature = "axstd"), unix))] macro_rules! print_err { @@ -18,9 +17,28 @@ const CMD_TABLE: &[(&str, CmdHandler)] = &[ ("help", do_help), ("uname", do_uname), ("ldr", do_ldr), - ("str", do_str) + ("str", do_str), + ("test_xhci", test_xhci), + ("enum_port", enum_port), + ("iicoled", do_iicoled), ]; +fn do_iicoled(_args: &str) { + // if let Err(()) = driver_i2c::run_iicoled() { + // println!("Failed to start iicoled: {}", err); + // } + driver_i2c::run_iicoled(); +} + +fn test_xhci(_args: &str) { + driver_usb::try_init(0x31a08000 as usize) + // unsafe { xhci::Registers::new(0xffff_0000_31a0_8000 as usize, MemoryMapper {}) }; +} + +fn enum_port(_args: &str) { + driver_usb::enum_port() +} + fn do_uname(_args: &str) { let arch = option_env!("AX_ARCH").unwrap_or(""); let platform = option_env!("AX_PLATFORM").unwrap_or(""); @@ -53,37 +71,58 @@ fn do_exit(_args: &str) { fn do_ldr(args: &str) { println!("ldr"); if args.is_empty() { - println!("try: ldr ffff0000400fe000 / ldr ffff000040080000 ffff000040080008"); + println!("try: ldr ffff0000400fe000 4"); } - fn ldr_one(addr: &str) -> io::Result<()> { - println!("addr = {}", addr); - - if let Ok(parsed_addr) = u64::from_str_radix(addr, 16) { - let address: *const u64 = parsed_addr as *const u64; // 强制转换为合适的指针类型 - - let value: u64; - println!("Parsed address: {:p}", address); // 打印地址时使用 %p 格式化符号 - - unsafe { - value = *address; + fn ldr_one(addr: &str, offset: &str) -> io::Result<()> { + // println!("addr = {}", addr); + + if let (Ok(parsed_addr), Ok(parsed_offset)) = ( + u64::from_str_radix(addr, 16), + u64::from_str_radix(offset, 10), + ) { + for i in 0..parsed_offset { + let address: *const u64 = (parsed_addr + i * 8) as *const u64; // 强制转换为合适的指针类型 + if address.is_aligned() { + let value: u64; + // println!("Parsed address: {:p}", address); // 打印地址时使用 %p 格式化符号 + + unsafe { + value = *address; + } + + let le_bytes = value.to_le_bytes(); + + // println!("Value at address {}: 0x{:X}", addr, value); // 使用输入的地址打印值 + // println!("value at address{} = 0x{:X}: ", addr, value); + for chunk in le_bytes.chunks(4) { + let mut chunk_value: u32 = 0; + for (i, byte) in chunk.iter().enumerate() { + chunk_value |= (*byte as u32) << (i * 8); + } + println!("{:032b}", chunk_value); + } + } else { + println!("addr not aligned!"); + } } - - println!("Value at address {}: 0x{:X}", addr, value); // 使用输入的地址打印值 } else { println!("Failed to parse address."); } return Ok(()); } - for addr in args.split_whitespace() { - if let Err(e) = ldr_one(addr) { - println!("ldr {} {}", addr, e); - } - } + // for addr in args.split_whitespace() { + // if let Err(e) = ldr_one(addr) { + // println!("ldr {} {}", addr, e); + // } + // } + let mut split_ascii_whitespace = args.split_ascii_whitespace(); + let base_addr = split_ascii_whitespace.next(); + let byte_counts = split_ascii_whitespace.next().unwrap_or("1"); + ldr_one(base_addr.unwrap(), byte_counts); } - // use crate::mem::phys_to_virt; // use core::ptr::{read_volatile, write_volatile}; @@ -131,7 +170,6 @@ fn do_str(args: &str) { str_one(addr, val).unwrap(); // 调用 str_one 函数并传递 addr 和 val } } - } pub fn run_cmd(line: &[u8]) { @@ -153,3 +191,5 @@ fn split_whitespace(str: &str) -> (&str, &str) { str.find(char::is_whitespace) .map_or((str, ""), |n| (&str[..n], str[n + 1..].trim())) } + +fn test_net(str: &str) {} diff --git a/apps/cli/src/main.rs b/apps/cli/src/main.rs index e10360e87d..192a73cb26 100644 --- a/apps/cli/src/main.rs +++ b/apps/cli/src/main.rs @@ -1,5 +1,6 @@ #![cfg_attr(feature = "axstd", no_std)] #![cfg_attr(feature = "axstd", no_main)] +#![allow(warnings)] #[macro_use] #[cfg(feature = "axstd")] diff --git a/apps/fs/shell/src/cmd.rs b/apps/fs/shell/src/cmd.rs index dd652e892d..7bcc5d5ba0 100644 --- a/apps/fs/shell/src/cmd.rs +++ b/apps/fs/shell/src/cmd.rs @@ -28,7 +28,7 @@ const CMD_TABLE: &[(&str, CmdHandler)] = &[ ("rm", do_rm), ("uname", do_uname), ("ldr", do_ldr), - ("str", do_str) + ("str", do_str), ]; fn file_type_to_char(ty: FileType) -> char { @@ -348,7 +348,6 @@ fn do_str(args: &str) { str_one(addr, val).unwrap(); // 调用 str_one 函数并传递 addr 和 val } } - } pub fn run_cmd(line: &[u8]) { diff --git a/apps/helloworld/Cargo.toml b/apps/helloworld/Cargo.toml index 9b759ec55a..0d09b7715e 100644 --- a/apps/helloworld/Cargo.toml +++ b/apps/helloworld/Cargo.toml @@ -8,3 +8,4 @@ authors = ["Yuekai Jia "] [dependencies] axstd = { path = "../../ulib/axstd", optional = true } +# axfeat = {path = "../../api/axfeat/",features = ["phytium","bus-pci","usb-host"]} diff --git a/apps/helloworld/helloworld_aarch64-phytium-pi.elf.id0 b/apps/helloworld/helloworld_aarch64-phytium-pi.elf.id0 new file mode 100644 index 0000000000..f5dbc7c766 Binary files /dev/null and b/apps/helloworld/helloworld_aarch64-phytium-pi.elf.id0 differ diff --git a/apps/helloworld/helloworld_aarch64-phytium-pi.elf.id1 b/apps/helloworld/helloworld_aarch64-phytium-pi.elf.id1 new file mode 100644 index 0000000000..e69de29bb2 diff --git a/apps/helloworld/helloworld_aarch64-phytium-pi.elf.nam b/apps/helloworld/helloworld_aarch64-phytium-pi.elf.nam new file mode 100644 index 0000000000..e69de29bb2 diff --git a/arceos-fada.bin.gz b/arceos-fada.bin.gz new file mode 100644 index 0000000000..34f2cc2d3f Binary files /dev/null and b/arceos-fada.bin.gz differ diff --git a/arceos-fada.itb b/arceos-fada.itb new file mode 100644 index 0000000000..f3dd8003c1 Binary files /dev/null and b/arceos-fada.itb differ diff --git a/arceos-phytium-pi.bin.gz b/arceos-phytium-pi.bin.gz new file mode 100644 index 0000000000..b0b3ca43c3 Binary files /dev/null and b/arceos-phytium-pi.bin.gz differ diff --git a/arceos-phytiym-pi.itb b/arceos-phytiym-pi.itb new file mode 100644 index 0000000000..1b4700a7d2 Binary files /dev/null and b/arceos-phytiym-pi.itb differ diff --git a/crates/allocator/src/lib.rs b/crates/allocator/src/lib.rs index 5ced1b9921..7a79161d0e 100644 --- a/crates/allocator/src/lib.rs +++ b/crates/allocator/src/lib.rs @@ -9,7 +9,6 @@ //! - [`IdAllocator`]: Used to allocate unique IDs. #![no_std] -#![feature(result_option_inspect)] #![cfg_attr(feature = "allocator_api", feature(allocator_api))] #[cfg(feature = "bitmap")] diff --git a/crates/driver_common/src/lib.rs b/crates/driver_common/src/lib.rs index c249b98837..444add2d46 100644 --- a/crates/driver_common/src/lib.rs +++ b/crates/driver_common/src/lib.rs @@ -27,6 +27,8 @@ pub enum DeviceType { Net, /// Graphic display device (e.g., GPU) Display, + /// USB host controller + USBHost, } /// The error type for device operation failures. diff --git a/crates/driver_i2c/Cargo.toml b/crates/driver_i2c/Cargo.toml new file mode 100644 index 0000000000..cf09e46782 --- /dev/null +++ b/crates/driver_i2c/Cargo.toml @@ -0,0 +1,15 @@ +[package] +name = "driver_i2c" +version = "0.1.0" +edition = "2021" + +[dependencies.ssd1306] +version = "0.8.4" + +[dependencies.tinybmp] +version = "0.5.0" + +[dependencies.embedded-graphics] +version = "0.8.1" + + \ No newline at end of file diff --git a/crates/driver_i2c/src/lib.rs b/crates/driver_i2c/src/lib.rs new file mode 100644 index 0000000000..acb940b37d --- /dev/null +++ b/crates/driver_i2c/src/lib.rs @@ -0,0 +1,39 @@ +#![no_std] + +use core::fmt::Write; +use ssd1306::{ + prelude::*, + I2CDisplayInterface, + Ssd1306, + mode::BufferedGraphicsMode, + mode::BasicMode, +}; + +pub fn run_iicoled() { + let mut oled_sda = io.pins.gpio21.into_push_pull_output(); + let mut oled_scl = io.pins.gpio22.into_push_pull_output(); + let mut i2c = BlockingI2c::i2c1( + peripherals.I2C0, + oled_sda, + oled_scl, + 100u32.kHz(), + &clocks, + ); + let interface = I2CDisplayInterface::new(i2c); + + let mut display = + Ssd1306::new(interface, DisplaySize128x64, DisplayRotation::Rotate0).into_terminal_mode(); + display.init().unwrap(); + display.clear().unwrap(); + + // Spam some characters to the display + for c in 97..123 { + let _ = display.write_str(unsafe { core::str::from_utf8_unchecked(&[c]) }); + } + for c in 65..91 { + let _ = display.write_str(unsafe { core::str::from_utf8_unchecked(&[c]) }); + } + + // The `write!()` macro is also supported + write!(display, "Hello, {}", "world"); +} diff --git a/crates/driver_net/Cargo.toml b/crates/driver_net/Cargo.toml index 5018c4a7c8..dfa7fe59d7 100644 --- a/crates/driver_net/Cargo.toml +++ b/crates/driver_net/Cargo.toml @@ -12,9 +12,12 @@ documentation = "https://rcore-os.github.io/arceos/driver_net/index.html" [features] default = [] ixgbe = ["dep:ixgbe-driver"] +phytium=[] [dependencies] spin = "0.9" log = "0.4" driver_common = { path = "../driver_common" } ixgbe-driver = {git = "https://github.com/KuangjuX/ixgbe-driver.git", rev = "8e5eb74", optional = true} +tock-registers="0.8" +bit_field = "0.10" \ No newline at end of file diff --git a/crates/driver_net/src/lib.rs b/crates/driver_net/src/lib.rs index 0f9c9ed363..ec90750fab 100644 --- a/crates/driver_net/src/lib.rs +++ b/crates/driver_net/src/lib.rs @@ -8,7 +8,10 @@ #[cfg(feature = "ixgbe")] /// ixgbe NIC device driver. pub mod ixgbe; + mod net_buf; +#[cfg(feature = "phytium")] +mod phytiym_ethernet_controller; use core::ptr::NonNull; diff --git a/crates/driver_pci/Cargo.toml b/crates/driver_pci/Cargo.toml index 062cbd0a69..89105c55ee 100644 --- a/crates/driver_pci/Cargo.toml +++ b/crates/driver_pci/Cargo.toml @@ -9,5 +9,17 @@ homepage = "https://github.com/rcore-os/arceos" repository = "https://github.com/rcore-os/arceos/tree/main/crates/driver_pci" documentation = "https://rcore-os.github.io/arceos/driver_pci/index.html" +[features] +phytium-pci = [] +virtio = [] + [dependencies] -virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers.git", rev = "409ee72" } +virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers.git", rev = "4b60f5d" } +log="0.4" +ratio = { path = "../../crates/ratio" } +pci_types = "0.6" +tock-registers="0.8" +bit_field = "0.10" + +[target.'cfg(target_arch = "aarch64")'.dependencies] +aarch64-cpu = "9.4" \ No newline at end of file diff --git a/crates/driver_pci/src/bcm2711.rs b/crates/driver_pci/src/bcm2711.rs new file mode 100644 index 0000000000..fe4cd135a0 --- /dev/null +++ b/crates/driver_pci/src/bcm2711.rs @@ -0,0 +1,563 @@ +use crate::types::{ConfigCommand, ConifgPciPciBridge}; +use crate::{err::*, Access, PciAddress}; +use aarch64_cpu::registers::*; +use core::{marker::PhantomData, ops::Add, ptr::NonNull}; +use ratio::Ratio; +use tock_registers::{ + interfaces::{ReadWriteable, Readable, Writeable}, + register_bitfields, register_structs, + registers::{ReadOnly, ReadWrite}, +}; +use virtio_drivers::transport::mmio; + +register_bitfields![ + u32, + // /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ + // 0x00ac + // BRCM_PCIE_CAP_REGS []， + + // Broadcom STB PCIe Register Offsets + // 0x0188 + RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 [ + LITTLE_ENDIAN OFFSET(0) NUMBITS(1) [], + ENDIAN_MODE_BAR2 OFFSET(0xC) NUMBITS(1) [], + ], + + // 0x043c + RC_CFG_PRIV1_ID_VAL3 [ + CLASS_ID OFFSET(0) NUMBITS(24) [ + pcie_pcie_bridge = 0x060400 + ], + ], + // 0x04dc + // PCIE_RC_CFG_PRIV1_LINK_CAPABILITY [], + + + // 0x1100 + // RC_DL_MDIO_ADDR [], + + // 0x1104 + // RC_DL_MDIO_WR_DATA [], + // 0x1108 + // RC_DL_MDIO_RD_DATA + + // 0x4008 + MISC_MISC_CTRL [ + SCB_ACCESS_EN OFFSET(12) NUMBITS(1) [], + CFG_READ_UR_MODE OFFSET(13) NUMBITS(1) [], + MAX_BURST_SIZE OFFSET(20) NUMBITS(2) [], + SCB0_SIZE OFFSET(27) NUMBITS(5) [ + init_val = 0x17, + ], + SCB1_SIZE OFFSET(22) NUMBITS(5) [], + SCB2_SIZE OFFSET(0) NUMBITS(1) [], + ], + // 0x400c + MISC_CPU_2_PCIE_MEM_WIN0_LO [ + MEM_WIN0_LO OFFSET(0) NUMBITS(32) [ + // TODO + init_val = 0x0000_0000 + ], + ], + // 0x4010 + MISC_CPU_2_PCIE_MEM_WIN0_HI [ + MEM_WIN0_HI OFFSET(0) NUMBITS(32) [ + init_val = 0x0000_0006 + ], + ], + + // 0x4204 + + + // 0x402C + MISC_RC_BAR1_CONFIG_LO [ + MEM_WIN OFFSET(0) NUMBITS(5)[] + ], + + // 0x4034 + MISC_RC_BAR2_CONFIG_LO [ + VALUE_LO OFFSET(0) NUMBITS(32)[ + init_val = 0x11, + ] + ], + // 0x4038 + MISC_RC_BAR2_CONFIG_HI [ + VALUE_HI OFFSET(0) NUMBITS(32)[ + init_val = 0x4, + ] + ], + // 0x403C + MISC_RC_BAR3_CONFIG_LO [ + MEM_WIN OFFSET(0) NUMBITS(5)[] + ], + + // 0x4044 + // MISC_MSI_BAR_CONFIG_LO + // 0x4048 + // MISC_MSI_BAR_CONFIG_HI + // 0x404c + // MISC_MSI_DATA_CONFIG + // 0x4060 + // MISC_EOI_CTRL + // 0x4064 + // MISC_PCIE_CTRL + // 0x4068 + MISC_PCIE_STATUS [ + CHECK_BITS OFFSET(4) NUMBITS(2)[], + RC_MODE OFFSET(7) NUMBITS(1)[], + ], + // 0x406c + MISC_REVISION [ + MISC_REVISION OFFSET(0) NUMBITS(32)[] + ], + + // 0x4070 + MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT [ + MEM_WIN0_BASE_LIMIT OFFSET(0) NUMBITS(32)[ + // TODO + init_val = 0 + ] + ], + // 0x4080 + MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI [ + MEM_WIN0_BASE_HI OFFSET(0) NUMBITS(32)[ + init_val = 6 + ] + ], + // 0x4084 + MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI [ + MEM_WIN0_LIMIT_HI OFFSET(0) NUMBITS(32)[ + init_val = 6 + ] + ], + // 0x4204 + MISC_HARD_PCIE_HARD_DEBUG [ + CLKREQ_DEBUG_ENABLE OFFSET(0) NUMBITS(1) [], + CLKREQ_L1SS_ENABLE OFFSET(21) NUMBITS(1) [], + SERDES_IDDQ OFFSET(27) NUMBITS(1) [], + ], + + // 0x4300 INTR2_CPU_BASE + INTR2_CPU_STATUS [ + INTR_STATUS OFFSET(0) NUMBITS(32) [], + ], + // 0x4304 0x4300 + 0x4 + INTR2_CPU_SET [ + INTR_SET OFFSET(0) NUMBITS(32) [], + ], + // 0x4308 0x4300 + 0x8 + INTR2_CPU_CLR [ + INTR_CLR OFFSET(0) NUMBITS(32) [] + ], + // 0x430c 0x4300 + 0x0c + INTR2_CPU_MASK_STATUS [ + INTR_MASK_STATUS OFFSET(0) NUMBITS(32) [] + ], + // 0x4310 0x4300 + 0x10 + INTR2_CPU_MASK_SET [ + INTR_MASK_SET OFFSET(0) NUMBITS(32) [] + ], + // 0x4314 0x4500 + 0x14 + INTR2_CPU_MASK_CLR [ + INTR_MASK_CLR OFFSET(0) NUMBITS(32) [] + ], + // 0x4500 MSI_INTR2_BASE + MSI_INTR2_STATUS [ + INTR_STATUS OFFSET(0) NUMBITS(32) [], + ], + // 0x4504 0x4500 + 0x4 + MSI_INTR2_SET [ + INTR_SET OFFSET(0) NUMBITS(32) [], + ], + // 0x4508 0x4500 + 0x8 + MSI_INTR2_CLR [ + INTR_CLR OFFSET(0) NUMBITS(32) [] + ], + // 0x450c 0x4500 + 0x0c + MSI_INTR2_MASK_STATUS [ + INTR_MASK_STATUS OFFSET(0) NUMBITS(32) [] + ], + // 0x4510 0x4500 + 0x10 + MSI_INTR2_MASK_SET [ + INTR_MASK_SET OFFSET(0) NUMBITS(32) [] + ], + // 0x4514 0x4500 + 0x14 + MSI_INTR2_MASK_CLR [ + INTR_MASK_CLR OFFSET(0) NUMBITS(32) [] + ], + + + // 0x8000 + // EXT_CFG_DATA + // 0x9000 + // EXT_CFG_INDEX + + // 0x9210 + RGR1_SW_INIT_1 [ + RGR1_SW_INTI_1_PERST OFFSET(0) NUMBITS(1) [], + RGR1_SW_INTI_1_INIT OFFSET(1) NUMBITS(1) [], + ], + + RC_CFG_VENDOR_SPECIFIC_REG1 [ + ENDIAN_MODE OFFSET(2) NUMBITS(2) [ + LITTLE_ENDIAN = 0 + ], + ], + + RC_CFG_PRIV1_LINK_CAPABILITY [ + ASPM_SUPPORT OFFSET(10) NUMBITS(2)[ + + ] + ] + +]; + +register_structs! { + /// Pl011 registers. + BCM2711PCIeHostBridgeRegs { + (0x00 => _rsvd1), + (0x0188 => rc_cfg_vendor_vendor_specific_reg1: ReadWrite), + (0x018C => _rsvd222), + (0x043c => rc_cfg_priv1_id_val3: ReadWrite), + (0x0440 => _rsvdd2), + (0x04dc => rc_cfg_priv1_link_capability: ReadWrite), + (0x04e0 => _rsvdd3), + (0x1100 => rc_dl_mdio_addr), + (0x1104 => rc_dl_mdio_wr_data), + (0x1108 => rc_dl_mdio_rd_data), + (0x4008 => misc_misc_ctrl: ReadWrite), + (0x400C => misc_cpu_2_pcie_mem_win0_lo: ReadWrite), + (0x4010 => misc_cpu_2_pcie_mem_win0_hi: ReadWrite), + (0x4014 => _rsvd22), + (0x4028 => _rsvd2), + (0x402C => misc_rc_bar1_config_lo: ReadWrite), + (0x4030 => _rsvdd), + (0x4034 => misc_rc_bar2_config_lo: ReadWrite), + (0x4038 => misc_rc_bar2_config_hi: ReadWrite), + (0x403C => misc_rc_bar3_config_lo: ReadWrite), + (0x4040 => _rsvddd), + (0x4044 => misc_msi_bar_config_lo), + (0x4048 => misc_msi_bar_config_hi), + (0x404c => misc_msi_data_config ), + (0x4060 => misc_eoi_ctrl), + (0x4064 => misc_pcie_ctrl), + (0x4068 => misc_pcie_status: ReadOnly), + (0x406C => misc_revision: ReadWrite), + (0x4070 => misc_cpu_2_pcie_mem_win0_base_limit: ReadWrite), + (0x4074 => hole), + (0x4080 => misc_cpu_2_pcie_mem_win0_base_hi: ReadWrite), + (0x4084 => misc_cpu_2_pcie_mem_win0_limit_hi: ReadWrite), + (0x4088 => hole2), + (0x4204 => misc_hard_pcie_hard_debug: ReadWrite), + (0x4208 => _rsvd3), + /// cpu intr + (0x4300 => intr2_cpu_status: ReadWrite), + (0x4304 => intr2_cpu_set: ReadWrite), + (0x4308 => intr2_cpu_clr: ReadWrite), + (0x430C => intr2_cpu_mask_status: ReadWrite), + (0x4310 => intr2_cpu_mask_set: ReadWrite), + (0x4314 => intr2_cpu_mask_clr: ReadWrite), + (0x4318 => hole3), + /// msi intr + (0x4500 => msi_intr2_status: ReadWrite), + (0x4504 => msi_intr2_set: ReadWrite), + (0x4508 => msi_intr2_clr: ReadWrite), + (0x450C => msi_intr2_mask_status: ReadWrite), + (0x4510 => msi_intr2_mask_set: ReadWrite), + (0x4514 => msi_intr2_mask_clr: ReadWrite), + (0x4518 => hole4), + /// Interrupt Clear Register. + (0x9210 => rgr1_sw_init: ReadWrite), + (0x9214 => _rsvd4), + (0x9310 => @END), + } +} + +impl BCM2711PCIeHostBridgeRegs { + fn pcie_link_up(&self) -> bool { + self.misc_pcie_status.read(MISC_PCIE_STATUS::CHECK_BITS) == 0x3 + } + + fn set_gen(&self, gen: u32) { + const PCI_EXP_LNKCTL2: usize = 48; + const PCI_EXP_LNKCAP: usize = 12; + const PCI_EXP_LNKCAP_SLS: u32 = 0x0000000f; + + unsafe { + let cap_base = self as *const BCM2711PCIeHostBridgeRegs as *const u8 as usize + 0x00ac; + let mut lnkctl2 = ((cap_base + PCI_EXP_LNKCTL2) as *const u16).read_volatile(); + let mut lnkcap = ((cap_base + PCI_EXP_LNKCAP) as *const u32).read_volatile(); + lnkcap = (lnkcap & !PCI_EXP_LNKCAP_SLS) | gen; + + ((cap_base + PCI_EXP_LNKCAP) as *mut u32).write_volatile(lnkcap); + + lnkctl2 = (lnkctl2 & !0xf) | gen as u16; + + ((cap_base + PCI_EXP_LNKCTL2) as *mut u16).write_volatile(lnkctl2); + } + } +} + +use core::time::Duration; +use log::{debug, info}; + +const RGR1_SW_INIT_1: usize = 0x9210; +const EXT_CFG_INDEX: usize = 0x9000; +const EXT_CFG_DATA: usize = 0x8000; +// const EXT_CFG_DATA: usize = 0x9004; + +#[derive(Clone)] +pub struct BCM2711 {} + +fn cfg_index(addr: PciAddress) -> usize { + ((addr.device as u32) << 15 | (addr.function as u32) << 12 | (addr.bus as u32) << 20) as usize +} + +impl BCM2711 { + unsafe fn do_setup(mmio_base: usize) { + let regs = &mut *(mmio_base as *mut BCM2711PCIeHostBridgeRegs); + + debug!("PCIe link start @0x{:X}...", mmio_base); + /* + * Reset the bridge, assert the fundamental reset. Note for some SoCs, + * e.g. BCM7278, the fundamental reset should not be asserted here. + * This will need to be changed when support for other SoCs is added. + */ + regs.rgr1_sw_init.modify( + RGR1_SW_INIT_1::RGR1_SW_INTI_1_INIT::SET + RGR1_SW_INIT_1::RGR1_SW_INTI_1_PERST::SET, + ); + debug!("assert fundamental reset"); + /* + * The delay is a safety precaution to preclude the reset signal + * from looking like a glitch. + */ + busy_wait(Duration::from_micros(100)); + + /* Take the bridge out of reset */ + regs.rgr1_sw_init + .modify(RGR1_SW_INIT_1::RGR1_SW_INTI_1_INIT::CLEAR); + debug!("deassert bridge reset"); + + // enable serdes + regs.misc_hard_pcie_hard_debug + .modify(MISC_HARD_PCIE_HARD_DEBUG::SERDES_IDDQ::CLEAR); + debug!("enable serdes"); + /* Wait for SerDes to be stable */ + busy_wait(core::time::Duration::from_micros(100)); + + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ + regs.misc_misc_ctrl.write( + MISC_MISC_CTRL::MAX_BURST_SIZE::SET + + MISC_MISC_CTRL::SCB_ACCESS_EN::SET + + MISC_MISC_CTRL::CFG_READ_UR_MODE::SET + + MISC_MISC_CTRL::SCB2_SIZE::SET, + ); + + regs.misc_rc_bar2_config_lo + .write(MISC_RC_BAR2_CONFIG_LO::VALUE_LO::init_val); + regs.misc_rc_bar2_config_hi + .write(MISC_RC_BAR2_CONFIG_HI::VALUE_HI::init_val); + + regs.misc_misc_ctrl.set(0x88003000); + + /* Disable the PCIe->GISB memory window (RC_BAR1) */ + regs.misc_rc_bar1_config_lo + .modify(MISC_RC_BAR1_CONFIG_LO::MEM_WIN::CLEAR); + /* Disable the PCIe->SCB memory window (RC_BAR3) */ + regs.misc_rc_bar3_config_lo + .modify(MISC_RC_BAR3_CONFIG_LO::MEM_WIN::CLEAR); + + /* Mask all interrupts since we are not handling any yet */ + regs.msi_intr2_mask_set + .write(MSI_INTR2_MASK_SET::INTR_MASK_SET::SET); + + /* Clear any interrupts we find on boot */ + regs.msi_intr2_clr.write(MSI_INTR2_CLR::INTR_CLR::SET); + + /* Unassert the fundamental reset */ + regs.rgr1_sw_init + .modify(RGR1_SW_INIT_1::RGR1_SW_INTI_1_PERST::CLEAR); + + /* + * Wait for 100ms after PERST# deassertion; see PCIe CEM specification + * sections 2.2, PCIe r5.0, 6.6.1. + */ + busy_wait(core::time::Duration::from_millis(100)); + + debug!("PCIe wait for link up..."); + + /* Give the RC/EP time to wake up, before trying to configure RC. + * Intermittently check status for link-up, up to a total of 100ms. + */ + for _ in 0..100 { + if regs.pcie_link_up() { + break; + } + busy_wait(core::time::Duration::from_millis(1)); + } + + if !regs.pcie_link_up() { + panic!("pcie link down!"); + } + + // check if controller is running in root complex mode. if bit 7 is not set, and error + { + let val = regs.misc_pcie_status.read(MISC_PCIE_STATUS::RC_MODE); + if val != 0x1 { + panic!("PCIe controller is not running in root complex mode"); + } + } + + // outbound memory + // regs.misc_cpu_2_pcie_mem_win0_lo.set(0xC0000000); + // regs.misc_cpu_2_pcie_mem_win0_hi.set(0x0); + regs.misc_cpu_2_pcie_mem_win0_lo.set(0x0); + regs.misc_cpu_2_pcie_mem_win0_hi.set(0x6); + regs.misc_cpu_2_pcie_mem_win0_base_limit.set(0x3FF00000); + regs.misc_cpu_2_pcie_mem_win0_base_hi + .write(MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI::MEM_WIN0_BASE_HI::init_val); + regs.misc_cpu_2_pcie_mem_win0_limit_hi + .write(MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI::MEM_WIN0_LIMIT_HI::init_val); + /* + * For config space accesses on the RC, show the right class for + * a PCIe-PCIe bridge (the default setting is to be EP mode). + */ + regs.rc_cfg_priv1_id_val3 + .modify(RC_CFG_PRIV1_ID_VAL3::CLASS_ID::pcie_pcie_bridge); + + // ssc + //todo + + let lnksta = ((mmio_base + 0xac + 18) as *const u16).read_volatile(); + + let cls = lnksta & 0xf; + + let nlw = (lnksta & 0x03f0) >> 4; + + info!( + "PCIe BRCM: link up, {} Gbps x{:?}", + link_speed_to_str(cls), + nlw + ); + + regs.rc_cfg_vendor_vendor_specific_reg1 + .write(RC_CFG_VENDOR_SPECIFIC_REG1::ENDIAN_MODE::LITTLE_ENDIAN); + + /* + * We used to enable the CLKREQ# input here, but a few PCIe cards don't + * attach anything to the CLKREQ# line, so we shouldn't assume that + * it's connected and working. The controller does allow detecting + * whether the port on the other side of our link is/was driving this + * signal, so we could check before we assume. But because this signal + * is for power management, which doesn't make sense in a bootloader, + * let's instead just unadvertise ASPM support. + */ + regs.rc_cfg_priv1_link_capability + .modify(RC_CFG_PRIV1_LINK_CAPABILITY::ASPM_SUPPORT::CLEAR); + } +} + +fn link_speed_to_str(cls: u16) -> &'static str { + match cls { + 0x1 => "2.5", + 0x2 => "5.0", + 0x3 => "8.0", + _ => "??", + } +} + +impl Access for BCM2711 { + fn map_conf(mmio_base: usize, addr: PciAddress) -> Option { + // bus 0 bus 1 只有一个Device + if addr.bus <= 2 && addr.device > 0 { + return None; + } + + if addr.bus == 0 { + return Some(mmio_base); + } + + let idx = cfg_index(addr); + unsafe { + ((mmio_base + EXT_CFG_INDEX) as *mut u32).write_volatile(idx as u32); + } + return Some(mmio_base + EXT_CFG_DATA); + } + + fn probe_bridge(mmio_base: usize, bridge: &ConifgPciPciBridge) { + debug!("bridge bcm2711"); + + bridge.set_cache_line_size(64 / 4); + bridge.set_memory_base((0xF8000000u32 >> 16) as u16); + bridge.set_memory_limit((0xF8000000u32 >> 16) as u16); + bridge.set_control(0x01); + unsafe { + (bridge.cfg_addr as *mut u8) + .offset(0xac + 0x1c) + .write_volatile(0x10); + } + + bridge.to_header().set_command([ + ConfigCommand::MemorySpaceEnable, + ConfigCommand::BusMasterEnable, + ConfigCommand::ParityErrorResponse, + ConfigCommand::SERREnable, + ]) + } + + fn setup(mmio_base: usize) { + init_early(); + unsafe { + Self::do_setup(mmio_base); + } + } +} + +/// Number of nanoseconds in a second. +pub const NANOS_PER_SEC: u64 = 1_000_000_000; +static mut CNTPCT_TO_NANOS_RATIO: Ratio = Ratio::zero(); +static mut NANOS_TO_CNTPCT_RATIO: Ratio = Ratio::zero(); +/// Early stage initialization: stores the timer frequency. +fn init_early() { + let freq = CNTFRQ_EL0.get(); + unsafe { + CNTPCT_TO_NANOS_RATIO = Ratio::new(NANOS_PER_SEC as u32, freq as u32); + NANOS_TO_CNTPCT_RATIO = CNTPCT_TO_NANOS_RATIO.inverse(); + } +} + +pub fn current_ticks() -> u64 { + CNTPCT_EL0.get() +} +/// Converts hardware ticks to nanoseconds. +#[inline] +pub fn ticks_to_nanos(ticks: u64) -> u64 { + unsafe { CNTPCT_TO_NANOS_RATIO.mul_trunc(ticks) } +} + +/// Converts nanoseconds to hardware ticks. +#[inline] +pub fn nanos_to_ticks(nanos: u64) -> u64 { + unsafe { NANOS_TO_CNTPCT_RATIO.mul_trunc(nanos) } +} + +/// Returns the current clock time in nanoseconds. +pub fn current_time_nanos() -> u64 { + ticks_to_nanos(current_ticks()) +} + +pub fn current_time() -> Duration { + Duration::from_nanos(current_time_nanos()) +} + +/// Busy waiting for the given duration. +pub fn busy_wait(dur: Duration) { + busy_wait_until(current_time() + dur); +} + +/// Busy waiting until reaching the given deadline. +pub fn busy_wait_until(deadline: Duration) { + while current_time() < deadline { + core::hint::spin_loop(); + } +} diff --git a/crates/driver_pci/src/device_types.rs b/crates/driver_pci/src/device_types.rs new file mode 100644 index 0000000000..cdb9fe5622 --- /dev/null +++ b/crates/driver_pci/src/device_types.rs @@ -0,0 +1,2801 @@ +#![allow(non_upper_case_globals)] +//todo PLEASE ANYONE FIX THESE CONSTANTS INTO ENUM/ARRAY FOR DRIVER LOAD! +pub const PCI_CLASS_NOT_DEFINED: usize = 0x0000; +pub const PCI_CLASS_NOT_DEFINED_VGA: usize = 0x0001; +pub const PCI_BASE_CLASS_STORAGE: usize = 0x01; +pub const PCI_CLASS_STORAGE_SCSI: usize = 0x0100; +pub const PCI_CLASS_STORAGE_IDE: usize = 0x0101; +pub const PCI_CLASS_STORAGE_FLOPPY: usize = 0x0102; +pub const PCI_CLASS_STORAGE_IPI: usize = 0x0103; +pub const PCI_CLASS_STORAGE_RAID: usize = 0x0104; +pub const PCI_CLASS_STORAGE_SATA: usize = 0x0106; +pub const PCI_CLASS_STORAGE_SATA_AHCI: usize = 0x010601; +pub const PCI_CLASS_STORAGE_SAS: usize = 0x0107; +pub const PCI_CLASS_STORAGE_EXPRESS: usize = 0x010802; +pub const PCI_CLASS_STORAGE_OTHER: usize = 0x0180; +pub const PCI_BASE_CLASS_NETWORK: usize = 0x02; +pub const PCI_CLASS_NETWORK_ETHERNET: usize = 0x0200; +pub const PCI_CLASS_NETWORK_TOKEN_RING: usize = 0x0201; +pub const PCI_CLASS_NETWORK_FDDI: usize = 0x0202; +pub const PCI_CLASS_NETWORK_ATM: usize = 0x0203; +pub const PCI_CLASS_NETWORK_OTHER: usize = 0x0280; +pub const PCI_BASE_CLASS_DISPLAY: usize = 0x03; +pub const PCI_CLASS_DISPLAY_VGA: usize = 0x0300; +pub const PCI_CLASS_DISPLAY_XGA: usize = 0x0301; +pub const PCI_CLASS_DISPLAY_3D: usize = 0x0302; +pub const PCI_CLASS_DISPLAY_OTHER: usize = 0x0380; +pub const PCI_BASE_CLASS_MULTIMEDIA: usize = 0x04; +pub const PCI_CLASS_MULTIMEDIA_VIDEO: usize = 0x0400; +pub const PCI_CLASS_MULTIMEDIA_AUDIO: usize = 0x0401; +pub const PCI_CLASS_MULTIMEDIA_PHONE: usize = 0x0402; +pub const PCI_CLASS_MULTIMEDIA_HD_AUDIO: usize = 0x0403; +pub const PCI_CLASS_MULTIMEDIA_OTHER: usize = 0x0480; +pub const PCI_BASE_CLASS_MEMORY: usize = 0x05; +pub const PCI_CLASS_MEMORY_RAM: usize = 0x0500; +pub const PCI_CLASS_MEMORY_FLASH: usize = 0x0501; +pub const PCI_CLASS_MEMORY_OTHER: usize = 0x0580; +pub const PCI_BASE_CLASS_BRIDGE: usize = 0x06; +pub const PCI_CLASS_BRIDGE_HOST: usize = 0x0600; +pub const PCI_CLASS_BRIDGE_ISA: usize = 0x0601; +pub const PCI_CLASS_BRIDGE_EISA: usize = 0x0602; +pub const PCI_CLASS_BRIDGE_MC: usize = 0x0603; +pub const PCI_CLASS_BRIDGE_PCI: usize = 0x0604; +pub const PCI_CLASS_BRIDGE_PCI_NORMAL: usize = 0x060400; +pub const PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE: usize = 0x060401; +pub const PCI_CLASS_BRIDGE_PCMCIA: usize = 0x0605; +pub const PCI_CLASS_BRIDGE_NUBUS: usize = 0x0606; +pub const PCI_CLASS_BRIDGE_CARDBUS: usize = 0x0607; +pub const PCI_CLASS_BRIDGE_RACEWAY: usize = 0x0608; +pub const PCI_CLASS_BRIDGE_OTHER: usize = 0x0680; +pub const PCI_BASE_CLASS_COMMUNICATION: usize = 0x07; +pub const PCI_CLASS_COMMUNICATION_SERIAL: usize = 0x0700; +pub const PCI_CLASS_COMMUNICATION_PARALLEL: usize = 0x0701; +pub const PCI_CLASS_COMMUNICATION_MULTISERIAL: usize = 0x0702; +pub const PCI_CLASS_COMMUNICATION_MODEM: usize = 0x0703; +pub const PCI_CLASS_COMMUNICATION_OTHER: usize = 0x0780; +pub const PCI_BASE_CLASS_SYSTEM: usize = 0x08; +pub const PCI_CLASS_SYSTEM_PIC: usize = 0x0800; +pub const PCI_CLASS_SYSTEM_PIC_IOAPIC: usize = 0x080010; +pub const PCI_CLASS_SYSTEM_PIC_IOXAPIC: usize = 0x080020; +pub const PCI_CLASS_SYSTEM_DMA: usize = 0x0801; +pub const PCI_CLASS_SYSTEM_TIMER: usize = 0x0802; +pub const PCI_CLASS_SYSTEM_RTC: usize = 0x0803; +pub const PCI_CLASS_SYSTEM_PCI_HOTPLUG: usize = 0x0804; +pub const PCI_CLASS_SYSTEM_SDHCI: usize = 0x0805; +pub const PCI_CLASS_SYSTEM_RCEC: usize = 0x0807; +pub const PCI_CLASS_SYSTEM_OTHER: usize = 0x0880; +pub const PCI_BASE_CLASS_INPUT: usize = 0x09; +pub const PCI_CLASS_INPUT_KEYBOARD: usize = 0x0900; +pub const PCI_CLASS_INPUT_PEN: usize = 0x0901; +pub const PCI_CLASS_INPUT_MOUSE: usize = 0x0902; +pub const PCI_CLASS_INPUT_SCANNER: usize = 0x0903; +pub const PCI_CLASS_INPUT_GAMEPORT: usize = 0x0904; +pub const PCI_CLASS_INPUT_OTHER: usize = 0x0980; +pub const PCI_BASE_CLASS_DOCKING: usize = 0x0a; +pub const PCI_CLASS_DOCKING_GENERIC: usize = 0x0a00; +pub const PCI_CLASS_DOCKING_OTHER: usize = 0x0a80; +pub const PCI_BASE_CLASS_PROCESSOR: usize = 0x0b; +pub const PCI_CLASS_PROCESSOR_386: usize = 0x0b00; +pub const PCI_CLASS_PROCESSOR_486: usize = 0x0b01; +pub const PCI_CLASS_PROCESSOR_PENTIUM: usize = 0x0b02; +pub const PCI_CLASS_PROCESSOR_ALPHA: usize = 0x0b10; +pub const PCI_CLASS_PROCESSOR_POWERPC: usize = 0x0b20; +pub const PCI_CLASS_PROCESSOR_MIPS: usize = 0x0b30; +pub const PCI_CLASS_PROCESSOR_CO: usize = 0x0b40; +pub const PCI_BASE_CLASS_SERIAL: usize = 0x0c; +pub const PCI_CLASS_SERIAL_FIREWIRE: usize = 0x0c00; +pub const PCI_CLASS_SERIAL_FIREWIRE_OHCI: usize = 0x0c0010; +pub const PCI_CLASS_SERIAL_ACCESS: usize = 0x0c01; +pub const PCI_CLASS_SERIAL_SSA: usize = 0x0c02; +pub const PCI_CLASS_SERIAL_USB: usize = 0x0c03; +pub const PCI_CLASS_SERIAL_USB_UHCI: usize = 0x0c0300; +pub const PCI_CLASS_SERIAL_USB_OHCI: usize = 0x0c0310; +pub const PCI_CLASS_SERIAL_USB_EHCI: usize = 0x0c0320; +pub const PCI_CLASS_SERIAL_USB_XHCI: usize = 0x0c0330; +pub const PCI_CLASS_SERIAL_USB_DEVICE: usize = 0x0c03fe; +pub const PCI_CLASS_SERIAL_FIBER: usize = 0x0c04; +pub const PCI_CLASS_SERIAL_SMBUS: usize = 0x0c05; +pub const PCI_CLASS_SERIAL_IPMI: usize = 0x0c07; +pub const PCI_CLASS_SERIAL_IPMI_SMIC: usize = 0x0c0700; +pub const PCI_CLASS_SERIAL_IPMI_KCS: usize = 0x0c0701; +pub const PCI_CLASS_SERIAL_IPMI_BT: usize = 0x0c0702; +pub const PCI_BASE_CLASS_WIRELESS: usize = 0x0d; +pub const PCI_CLASS_WIRELESS_RF_CONTROLLER: usize = 0x0d10; +pub const PCI_CLASS_WIRELESS_WHCI: usize = 0x0d1010; +pub const PCI_BASE_CLASS_INTELLIGENT: usize = 0x0e; +pub const PCI_CLASS_INTELLIGENT_I2O: usize = 0x0e00; +pub const PCI_BASE_CLASS_SATELLITE: usize = 0x0f; +pub const PCI_CLASS_SATELLITE_TV: usize = 0x0f00; +pub const PCI_CLASS_SATELLITE_AUDIO: usize = 0x0f01; +pub const PCI_CLASS_SATELLITE_VOICE: usize = 0x0f03; +pub const PCI_CLASS_SATELLITE_DATA: usize = 0x0f04; +pub const PCI_BASE_CLASS_CRYPT: usize = 0x10; +pub const PCI_CLASS_CRYPT_NETWORK: usize = 0x1000; +pub const PCI_CLASS_CRYPT_ENTERTAINMENT: usize = 0x1001; +pub const PCI_CLASS_CRYPT_OTHER: usize = 0x1080; +pub const PCI_BASE_CLASS_SIGNAL_PROCESSING: usize = 0x11; +pub const PCI_CLASS_SP_DPIO: usize = 0x1100; +pub const PCI_CLASS_SP_OTHER: usize = 0x1180; +pub const PCI_CLASS_OTHERS: usize = 0xff; +pub const PCI_VENDOR_ID_LOONGSON: usize = 0x0014; +pub const PCI_VENDOR_ID_TTTECH: usize = 0x0357; +pub const PCI_DEVICE_ID_TTTECH_MC322: usize = 0x000a; +pub const PCI_VENDOR_ID_DYNALINK: usize = 0x0675; +pub const PCI_DEVICE_ID_DYNALINK_IS64PH: usize = 0x1702; +pub const PCI_VENDOR_ID_UBIQUITI: usize = 0x0777; +pub const PCI_VENDOR_ID_BERKOM: usize = 0x0871; +pub const PCI_DEVICE_ID_BERKOM_A1T: usize = 0xffa1; +pub const PCI_DEVICE_ID_BERKOM_T_CONCEPT: usize = 0xffa2; +pub const PCI_DEVICE_ID_BERKOM_A4T: usize = 0xffa4; +pub const PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO: usize = 0xffa8; +pub const PCI_VENDOR_ID_COMPAQ: usize = 0x0e11; +pub const PCI_DEVICE_ID_COMPAQ_TOKENRING: usize = 0x0508; +pub const PCI_DEVICE_ID_COMPAQ_TACHYON: usize = 0xa0fc; +pub const PCI_DEVICE_ID_COMPAQ_SMART2P: usize = 0xae10; +pub const PCI_DEVICE_ID_COMPAQ_NETEL100: usize = 0xae32; +pub const PCI_DEVICE_ID_COMPAQ_NETEL10: usize = 0xae34; +pub const PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE: usize = 0xae33; +pub const PCI_DEVICE_ID_COMPAQ_NETFLEX3I: usize = 0xae35; +pub const PCI_DEVICE_ID_COMPAQ_NETEL100D: usize = 0xae40; +pub const PCI_DEVICE_ID_COMPAQ_NETEL100PI: usize = 0xae43; +pub const PCI_DEVICE_ID_COMPAQ_NETEL100I: usize = 0xb011; +pub const PCI_DEVICE_ID_COMPAQ_CISS: usize = 0xb060; +pub const PCI_DEVICE_ID_COMPAQ_CISSB: usize = 0xb178; +pub const PCI_DEVICE_ID_COMPAQ_CISSC: usize = 0x46; +pub const PCI_DEVICE_ID_COMPAQ_THUNDER: usize = 0xf130; +pub const PCI_DEVICE_ID_COMPAQ_NETFLEX3B: usize = 0xf150; +pub const PCI_VENDOR_ID_NCR: usize = 0x1000; +pub const PCI_VENDOR_ID_LSI_LOGIC: usize = 0x1000; +pub const PCI_DEVICE_ID_NCR_53C810: usize = 0x0001; +pub const PCI_DEVICE_ID_NCR_53C820: usize = 0x0002; +pub const PCI_DEVICE_ID_NCR_53C825: usize = 0x0003; +pub const PCI_DEVICE_ID_NCR_53C815: usize = 0x0004; +pub const PCI_DEVICE_ID_LSI_53C810AP: usize = 0x0005; +pub const PCI_DEVICE_ID_NCR_53C860: usize = 0x0006; +pub const PCI_DEVICE_ID_LSI_53C1510: usize = 0x000a; +pub const PCI_DEVICE_ID_NCR_53C896: usize = 0x000b; +pub const PCI_DEVICE_ID_NCR_53C895: usize = 0x000c; +pub const PCI_DEVICE_ID_NCR_53C885: usize = 0x000d; +pub const PCI_DEVICE_ID_NCR_53C875: usize = 0x000f; +pub const PCI_DEVICE_ID_NCR_53C1510: usize = 0x0010; +pub const PCI_DEVICE_ID_LSI_53C895A: usize = 0x0012; +pub const PCI_DEVICE_ID_LSI_53C875A: usize = 0x0013; +pub const PCI_DEVICE_ID_LSI_53C1010_33: usize = 0x0020; +pub const PCI_DEVICE_ID_LSI_53C1010_66: usize = 0x0021; +pub const PCI_DEVICE_ID_LSI_53C1030: usize = 0x0030; +pub const PCI_DEVICE_ID_LSI_1030_53C1035: usize = 0x0032; +pub const PCI_DEVICE_ID_LSI_53C1035: usize = 0x0040; +pub const PCI_DEVICE_ID_NCR_53C875J: usize = 0x008f; +pub const PCI_DEVICE_ID_LSI_FC909: usize = 0x0621; +pub const PCI_DEVICE_ID_LSI_FC929: usize = 0x0622; +pub const PCI_DEVICE_ID_LSI_FC929_LAN: usize = 0x0623; +pub const PCI_DEVICE_ID_LSI_FC919: usize = 0x0624; +pub const PCI_DEVICE_ID_LSI_FC919_LAN: usize = 0x0625; +pub const PCI_DEVICE_ID_LSI_FC929X: usize = 0x0626; +pub const PCI_DEVICE_ID_LSI_FC939X: usize = 0x0642; +pub const PCI_DEVICE_ID_LSI_FC949X: usize = 0x0640; +pub const PCI_DEVICE_ID_LSI_FC949ES: usize = 0x0646; +pub const PCI_DEVICE_ID_LSI_FC919X: usize = 0x0628; +pub const PCI_DEVICE_ID_NCR_YELLOWFIN: usize = 0x0701; +pub const PCI_DEVICE_ID_LSI_61C102: usize = 0x0901; +pub const PCI_DEVICE_ID_LSI_63C815: usize = 0x1000; +pub const PCI_DEVICE_ID_LSI_SAS1064: usize = 0x0050; +pub const PCI_DEVICE_ID_LSI_SAS1064R: usize = 0x0411; +pub const PCI_DEVICE_ID_LSI_SAS1066: usize = 0x005E; +pub const PCI_DEVICE_ID_LSI_SAS1068: usize = 0x0054; +pub const PCI_DEVICE_ID_LSI_SAS1064A: usize = 0x005C; +pub const PCI_DEVICE_ID_LSI_SAS1064E: usize = 0x0056; +pub const PCI_DEVICE_ID_LSI_SAS1066E: usize = 0x005A; +pub const PCI_DEVICE_ID_LSI_SAS1068E: usize = 0x0058; +pub const PCI_DEVICE_ID_LSI_SAS1078: usize = 0x0060; +pub const PCI_VENDOR_ID_ATI: usize = 0x1002; +pub const PCI_DEVICE_ID_ATI_68800: usize = 0x4158; +pub const PCI_DEVICE_ID_ATI_215CT222: usize = 0x4354; +pub const PCI_DEVICE_ID_ATI_210888CX: usize = 0x4358; +pub const PCI_DEVICE_ID_ATI_215ET222: usize = 0x4554; +pub const PCI_DEVICE_ID_ATI_215GB: usize = 0x4742; +pub const PCI_DEVICE_ID_ATI_215GD: usize = 0x4744; +pub const PCI_DEVICE_ID_ATI_215GI: usize = 0x4749; +pub const PCI_DEVICE_ID_ATI_215GP: usize = 0x4750; +pub const PCI_DEVICE_ID_ATI_215GQ: usize = 0x4751; +pub const PCI_DEVICE_ID_ATI_215XL: usize = 0x4752; +pub const PCI_DEVICE_ID_ATI_215GT: usize = 0x4754; +pub const PCI_DEVICE_ID_ATI_215GTB: usize = 0x4755; +pub const PCI_DEVICE_ID_ATI_215_IV: usize = 0x4756; +pub const PCI_DEVICE_ID_ATI_215_IW: usize = 0x4757; +pub const PCI_DEVICE_ID_ATI_215_IZ: usize = 0x475A; +pub const PCI_DEVICE_ID_ATI_210888GX: usize = 0x4758; +pub const PCI_DEVICE_ID_ATI_215_LB: usize = 0x4c42; +pub const PCI_DEVICE_ID_ATI_215_LD: usize = 0x4c44; +pub const PCI_DEVICE_ID_ATI_215_LG: usize = 0x4c47; +pub const PCI_DEVICE_ID_ATI_215_LI: usize = 0x4c49; +pub const PCI_DEVICE_ID_ATI_215_LM: usize = 0x4c4D; +pub const PCI_DEVICE_ID_ATI_215_LN: usize = 0x4c4E; +pub const PCI_DEVICE_ID_ATI_215_LR: usize = 0x4c52; +pub const PCI_DEVICE_ID_ATI_215_LS: usize = 0x4c53; +pub const PCI_DEVICE_ID_ATI_264_LT: usize = 0x4c54; +pub const PCI_DEVICE_ID_ATI_264VT: usize = 0x5654; +pub const PCI_DEVICE_ID_ATI_264VU: usize = 0x5655; +pub const PCI_DEVICE_ID_ATI_264VV: usize = 0x5656; +pub const PCI_DEVICE_ID_ATI_RAGE128_RE: usize = 0x5245; +pub const PCI_DEVICE_ID_ATI_RAGE128_RF: usize = 0x5246; +pub const PCI_DEVICE_ID_ATI_RAGE128_RG: usize = 0x5247; +pub const PCI_DEVICE_ID_ATI_RAGE128_RK: usize = 0x524b; +pub const PCI_DEVICE_ID_ATI_RAGE128_RL: usize = 0x524c; +pub const PCI_DEVICE_ID_ATI_RAGE128_SE: usize = 0x5345; +pub const PCI_DEVICE_ID_ATI_RAGE128_SF: usize = 0x5346; +pub const PCI_DEVICE_ID_ATI_RAGE128_SG: usize = 0x5347; +pub const PCI_DEVICE_ID_ATI_RAGE128_SH: usize = 0x5348; +pub const PCI_DEVICE_ID_ATI_RAGE128_SK: usize = 0x534b; +pub const PCI_DEVICE_ID_ATI_RAGE128_SL: usize = 0x534c; +pub const PCI_DEVICE_ID_ATI_RAGE128_SM: usize = 0x534d; +pub const PCI_DEVICE_ID_ATI_RAGE128_SN: usize = 0x534e; +pub const PCI_DEVICE_ID_ATI_RAGE128_TF: usize = 0x5446; +pub const PCI_DEVICE_ID_ATI_RAGE128_TL: usize = 0x544c; +pub const PCI_DEVICE_ID_ATI_RAGE128_TR: usize = 0x5452; +pub const PCI_DEVICE_ID_ATI_RAGE128_TS: usize = 0x5453; +pub const PCI_DEVICE_ID_ATI_RAGE128_TT: usize = 0x5454; +pub const PCI_DEVICE_ID_ATI_RAGE128_TU: usize = 0x5455; +pub const PCI_DEVICE_ID_ATI_RAGE128_LE: usize = 0x4c45; +pub const PCI_DEVICE_ID_ATI_RAGE128_LF: usize = 0x4c46; +pub const PCI_DEVICE_ID_ATI_RAGE128_MF: usize = 0x4d46; +pub const PCI_DEVICE_ID_ATI_RAGE128_ML: usize = 0x4d4c; +pub const PCI_DEVICE_ID_ATI_RAGE128_PA: usize = 0x5041; +pub const PCI_DEVICE_ID_ATI_RAGE128_PB: usize = 0x5042; +pub const PCI_DEVICE_ID_ATI_RAGE128_PC: usize = 0x5043; +pub const PCI_DEVICE_ID_ATI_RAGE128_PD: usize = 0x5044; +pub const PCI_DEVICE_ID_ATI_RAGE128_PE: usize = 0x5045; +pub const PCI_DEVICE_ID_ATI_RAGE128_PF: usize = 0x5046; +pub const PCI_DEVICE_ID_ATI_RAGE128_PG: usize = 0x5047; +pub const PCI_DEVICE_ID_ATI_RAGE128_PH: usize = 0x5048; +pub const PCI_DEVICE_ID_ATI_RAGE128_PI: usize = 0x5049; +pub const PCI_DEVICE_ID_ATI_RAGE128_PJ: usize = 0x504A; +pub const PCI_DEVICE_ID_ATI_RAGE128_PK: usize = 0x504B; +pub const PCI_DEVICE_ID_ATI_RAGE128_PL: usize = 0x504C; +pub const PCI_DEVICE_ID_ATI_RAGE128_PM: usize = 0x504D; +pub const PCI_DEVICE_ID_ATI_RAGE128_PN: usize = 0x504E; +pub const PCI_DEVICE_ID_ATI_RAGE128_PO: usize = 0x504F; +pub const PCI_DEVICE_ID_ATI_RAGE128_PP: usize = 0x5050; +pub const PCI_DEVICE_ID_ATI_RAGE128_PQ: usize = 0x5051; +pub const PCI_DEVICE_ID_ATI_RAGE128_PR: usize = 0x5052; +pub const PCI_DEVICE_ID_ATI_RAGE128_PS: usize = 0x5053; +pub const PCI_DEVICE_ID_ATI_RAGE128_PT: usize = 0x5054; +pub const PCI_DEVICE_ID_ATI_RAGE128_PU: usize = 0x5055; +pub const PCI_DEVICE_ID_ATI_RAGE128_PV: usize = 0x5056; +pub const PCI_DEVICE_ID_ATI_RAGE128_PW: usize = 0x5057; +pub const PCI_DEVICE_ID_ATI_RAGE128_PX: usize = 0x5058; +pub const PCI_DEVICE_ID_ATI_RADEON_QD: usize = 0x5144; +pub const PCI_DEVICE_ID_ATI_RADEON_QE: usize = 0x5145; +pub const PCI_DEVICE_ID_ATI_RADEON_QF: usize = 0x5146; +pub const PCI_DEVICE_ID_ATI_RADEON_QG: usize = 0x5147; +pub const PCI_DEVICE_ID_ATI_RADEON_QY: usize = 0x5159; +pub const PCI_DEVICE_ID_ATI_RADEON_QZ: usize = 0x515a; +pub const PCI_DEVICE_ID_ATI_RADEON_QL: usize = 0x514c; +pub const PCI_DEVICE_ID_ATI_RADEON_QN: usize = 0x514e; +pub const PCI_DEVICE_ID_ATI_RADEON_QO: usize = 0x514f; +pub const PCI_DEVICE_ID_ATI_RADEON_Ql: usize = 0x516c; +pub const PCI_DEVICE_ID_ATI_RADEON_BB: usize = 0x4242; +pub const PCI_DEVICE_ID_ATI_RADEON_QM: usize = 0x514d; +pub const PCI_DEVICE_ID_ATI_RADEON_QW: usize = 0x5157; +pub const PCI_DEVICE_ID_ATI_RADEON_QX: usize = 0x5158; +pub const PCI_DEVICE_ID_ATI_RADEON_Id: usize = 0x4964; +pub const PCI_DEVICE_ID_ATI_RADEON_Ie: usize = 0x4965; +pub const PCI_DEVICE_ID_ATI_RADEON_If: usize = 0x4966; +pub const PCI_DEVICE_ID_ATI_RADEON_Ig: usize = 0x4967; +pub const PCI_DEVICE_ID_ATI_RADEON_Ya: usize = 0x5961; +pub const PCI_DEVICE_ID_ATI_RADEON_Yd: usize = 0x5964; +pub const PCI_DEVICE_ID_ATI_RADEON_ND: usize = 0x4e44; +pub const PCI_DEVICE_ID_ATI_RADEON_NE: usize = 0x4e45; +pub const PCI_DEVICE_ID_ATI_RADEON_NF: usize = 0x4e46; +pub const PCI_DEVICE_ID_ATI_RADEON_NG: usize = 0x4e47; +pub const PCI_DEVICE_ID_ATI_RADEON_LY: usize = 0x4c59; +pub const PCI_DEVICE_ID_ATI_RADEON_LZ: usize = 0x4c5a; +pub const PCI_DEVICE_ID_ATI_RADEON_LW: usize = 0x4c57; +pub const PCI_DEVICE_ID_ATI_RADEON_LX: usize = 0x4c58; +pub const PCI_DEVICE_ID_ATI_RADEON_Ld: usize = 0x4c64; +pub const PCI_DEVICE_ID_ATI_RADEON_Le: usize = 0x4c65; +pub const PCI_DEVICE_ID_ATI_RADEON_Lf: usize = 0x4c66; +pub const PCI_DEVICE_ID_ATI_RADEON_Lg: usize = 0x4c67; +pub const PCI_DEVICE_ID_ATI_RS100: usize = 0xcab0; +pub const PCI_DEVICE_ID_ATI_RS200: usize = 0xcab2; +pub const PCI_DEVICE_ID_ATI_RS200_B: usize = 0xcbb2; +pub const PCI_DEVICE_ID_ATI_RS250: usize = 0xcab3; +pub const PCI_DEVICE_ID_ATI_RS300_100: usize = 0x5830; +pub const PCI_DEVICE_ID_ATI_RS300_133: usize = 0x5831; +pub const PCI_DEVICE_ID_ATI_RS300_166: usize = 0x5832; +pub const PCI_DEVICE_ID_ATI_RS300_200: usize = 0x5833; +pub const PCI_DEVICE_ID_ATI_RS350_100: usize = 0x7830; +pub const PCI_DEVICE_ID_ATI_RS350_133: usize = 0x7831; +pub const PCI_DEVICE_ID_ATI_RS350_166: usize = 0x7832; +pub const PCI_DEVICE_ID_ATI_RS350_200: usize = 0x7833; +pub const PCI_DEVICE_ID_ATI_RS400_100: usize = 0x5a30; +pub const PCI_DEVICE_ID_ATI_RS400_133: usize = 0x5a31; +pub const PCI_DEVICE_ID_ATI_RS400_166: usize = 0x5a32; +pub const PCI_DEVICE_ID_ATI_RS400_200: usize = 0x5a33; +pub const PCI_DEVICE_ID_ATI_RS480: usize = 0x5950; +pub const PCI_DEVICE_ID_ATI_IXP200_IDE: usize = 0x4349; +pub const PCI_DEVICE_ID_ATI_IXP200_SMBUS: usize = 0x4353; +pub const PCI_DEVICE_ID_ATI_IXP300_SMBUS: usize = 0x4363; +pub const PCI_DEVICE_ID_ATI_IXP300_IDE: usize = 0x4369; +pub const PCI_DEVICE_ID_ATI_IXP300_SATA: usize = 0x436e; +pub const PCI_DEVICE_ID_ATI_IXP400_SMBUS: usize = 0x4372; +pub const PCI_DEVICE_ID_ATI_IXP400_IDE: usize = 0x4376; +pub const PCI_DEVICE_ID_ATI_IXP400_SATA: usize = 0x4379; +pub const PCI_DEVICE_ID_ATI_IXP400_SATA2: usize = 0x437a; +pub const PCI_DEVICE_ID_ATI_IXP600_SATA: usize = 0x4380; +pub const PCI_DEVICE_ID_ATI_SBX00_SMBUS: usize = 0x4385; +pub const PCI_DEVICE_ID_ATI_IXP600_IDE: usize = 0x438c; +pub const PCI_DEVICE_ID_ATI_IXP700_SATA: usize = 0x4390; +pub const PCI_DEVICE_ID_ATI_IXP700_IDE: usize = 0x439c; +pub const PCI_VENDOR_ID_VLSI: usize = 0x1004; +pub const PCI_DEVICE_ID_VLSI_82C592: usize = 0x0005; +pub const PCI_DEVICE_ID_VLSI_82C593: usize = 0x0006; +pub const PCI_DEVICE_ID_VLSI_82C594: usize = 0x0007; +pub const PCI_DEVICE_ID_VLSI_82C597: usize = 0x0009; +pub const PCI_DEVICE_ID_VLSI_82C541: usize = 0x000c; +pub const PCI_DEVICE_ID_VLSI_82C543: usize = 0x000d; +pub const PCI_DEVICE_ID_VLSI_82C532: usize = 0x0101; +pub const PCI_DEVICE_ID_VLSI_82C534: usize = 0x0102; +pub const PCI_DEVICE_ID_VLSI_82C535: usize = 0x0104; +pub const PCI_DEVICE_ID_VLSI_82C147: usize = 0x0105; +pub const PCI_DEVICE_ID_VLSI_VAS96011: usize = 0x0702; +pub const PCI_DEVICE_ID_RD890_IOMMU: usize = 0x5a23; +pub const PCI_VENDOR_ID_ADL: usize = 0x1005; +pub const PCI_DEVICE_ID_ADL_2301: usize = 0x2301; +pub const PCI_VENDOR_ID_NS: usize = 0x100b; +pub const PCI_DEVICE_ID_NS_87415: usize = 0x0002; +pub const PCI_DEVICE_ID_NS_87560_LIO: usize = 0x000e; +pub const PCI_DEVICE_ID_NS_87560_USB: usize = 0x0012; +pub const PCI_DEVICE_ID_NS_83815: usize = 0x0020; +pub const PCI_DEVICE_ID_NS_83820: usize = 0x0022; +pub const PCI_DEVICE_ID_NS_CS5535_ISA: usize = 0x002b; +pub const PCI_DEVICE_ID_NS_CS5535_IDE: usize = 0x002d; +pub const PCI_DEVICE_ID_NS_CS5535_AUDIO: usize = 0x002e; +pub const PCI_DEVICE_ID_NS_CS5535_USB: usize = 0x002f; +pub const PCI_DEVICE_ID_NS_GX_VIDEO: usize = 0x0030; +pub const PCI_DEVICE_ID_NS_SATURN: usize = 0x0035; +pub const PCI_DEVICE_ID_NS_SCx200_BRIDGE: usize = 0x0500; +pub const PCI_DEVICE_ID_NS_SCx200_SMI: usize = 0x0501; +pub const PCI_DEVICE_ID_NS_SCx200_IDE: usize = 0x0502; +pub const PCI_DEVICE_ID_NS_SCx200_AUDIO: usize = 0x0503; +pub const PCI_DEVICE_ID_NS_SCx200_VIDEO: usize = 0x0504; +pub const PCI_DEVICE_ID_NS_SCx200_XBUS: usize = 0x0505; +pub const PCI_DEVICE_ID_NS_SC1100_BRIDGE: usize = 0x0510; +pub const PCI_DEVICE_ID_NS_SC1100_SMI: usize = 0x0511; +pub const PCI_DEVICE_ID_NS_SC1100_XBUS: usize = 0x0515; +pub const PCI_DEVICE_ID_NS_87410: usize = 0xd001; +pub const PCI_DEVICE_ID_NS_GX_HOST_BRIDGE: usize = 0x0028; +pub const PCI_VENDOR_ID_TSENG: usize = 0x100c; +pub const PCI_DEVICE_ID_TSENG_W32P_2: usize = 0x3202; +pub const PCI_DEVICE_ID_TSENG_W32P_b: usize = 0x3205; +pub const PCI_DEVICE_ID_TSENG_W32P_c: usize = 0x3206; +pub const PCI_DEVICE_ID_TSENG_W32P_d: usize = 0x3207; +pub const PCI_DEVICE_ID_TSENG_ET6000: usize = 0x3208; +pub const PCI_VENDOR_ID_WEITEK: usize = 0x100e; +pub const PCI_DEVICE_ID_WEITEK_P9000: usize = 0x9001; +pub const PCI_DEVICE_ID_WEITEK_P9100: usize = 0x9100; +pub const PCI_VENDOR_ID_DEC: usize = 0x1011; +pub const PCI_DEVICE_ID_DEC_BRD: usize = 0x0001; +pub const PCI_DEVICE_ID_DEC_TULIP: usize = 0x0002; +pub const PCI_DEVICE_ID_DEC_TGA: usize = 0x0004; +pub const PCI_DEVICE_ID_DEC_TULIP_FAST: usize = 0x0009; +pub const PCI_DEVICE_ID_DEC_TGA2: usize = 0x000D; +pub const PCI_DEVICE_ID_DEC_FDDI: usize = 0x000F; +pub const PCI_DEVICE_ID_DEC_TULIP_PLUS: usize = 0x0014; +pub const PCI_DEVICE_ID_DEC_21142: usize = 0x0019; +pub const PCI_DEVICE_ID_DEC_21052: usize = 0x0021; +pub const PCI_DEVICE_ID_DEC_21150: usize = 0x0022; +pub const PCI_DEVICE_ID_DEC_21152: usize = 0x0024; +pub const PCI_DEVICE_ID_DEC_21153: usize = 0x0025; +pub const PCI_DEVICE_ID_DEC_21154: usize = 0x0026; +pub const PCI_DEVICE_ID_DEC_21285: usize = 0x1065; +pub const PCI_DEVICE_ID_COMPAQ_42XX: usize = 0x0046; +pub const PCI_VENDOR_ID_CIRRUS: usize = 0x1013; +pub const PCI_DEVICE_ID_CIRRUS_7548: usize = 0x0038; +pub const PCI_DEVICE_ID_CIRRUS_5430: usize = 0x00a0; +pub const PCI_DEVICE_ID_CIRRUS_5434_4: usize = 0x00a4; +pub const PCI_DEVICE_ID_CIRRUS_5434_8: usize = 0x00a8; +pub const PCI_DEVICE_ID_CIRRUS_5436: usize = 0x00ac; +pub const PCI_DEVICE_ID_CIRRUS_5446: usize = 0x00b8; +pub const PCI_DEVICE_ID_CIRRUS_5480: usize = 0x00bc; +pub const PCI_DEVICE_ID_CIRRUS_5462: usize = 0x00d0; +pub const PCI_DEVICE_ID_CIRRUS_5464: usize = 0x00d4; +pub const PCI_DEVICE_ID_CIRRUS_5465: usize = 0x00d6; +pub const PCI_DEVICE_ID_CIRRUS_6729: usize = 0x1100; +pub const PCI_DEVICE_ID_CIRRUS_6832: usize = 0x1110; +pub const PCI_DEVICE_ID_CIRRUS_7543: usize = 0x1202; +pub const PCI_DEVICE_ID_CIRRUS_4610: usize = 0x6001; +pub const PCI_DEVICE_ID_CIRRUS_4612: usize = 0x6003; +pub const PCI_DEVICE_ID_CIRRUS_4615: usize = 0x6004; +pub const PCI_VENDOR_ID_IBM: usize = 0x1014; +pub const PCI_DEVICE_ID_IBM_TR: usize = 0x0018; +pub const PCI_DEVICE_ID_IBM_TR_WAKE: usize = 0x003e; +pub const PCI_DEVICE_ID_IBM_CPC710_PCI64: usize = 0x00fc; +pub const PCI_DEVICE_ID_IBM_SNIPE: usize = 0x0180; +pub const PCI_DEVICE_ID_IBM_CITRINE: usize = 0x028C; +pub const PCI_DEVICE_ID_IBM_GEMSTONE: usize = 0xB166; +pub const PCI_DEVICE_ID_IBM_OBSIDIAN: usize = 0x02BD; +pub const PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1: usize = 0x0031; +pub const PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2: usize = 0x0219; +pub const PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX: usize = 0x021A; +pub const PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM: usize = 0x0251; +pub const PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE: usize = 0x0361; +pub const PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL: usize = 0x252; +pub const PCI_SUBVENDOR_ID_IBM: usize = 0x1014; +pub const PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT: usize = 0x03d4; +pub const PCI_VENDOR_ID_UNISYS: usize = 0x1018; +pub const PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR: usize = 0x001C; +pub const PCI_VENDOR_ID_COMPEX2: usize = 0x101a; +pub const PCI_DEVICE_ID_COMPEX2_100VG: usize = 0x0005; +pub const PCI_VENDOR_ID_WD: usize = 0x101c; +pub const PCI_DEVICE_ID_WD_90C: usize = 0xc24a; +pub const PCI_VENDOR_ID_AMI: usize = 0x101e; +pub const PCI_DEVICE_ID_AMI_MEGARAID3: usize = 0x1960; +pub const PCI_DEVICE_ID_AMI_MEGARAID: usize = 0x9010; +pub const PCI_DEVICE_ID_AMI_MEGARAID2: usize = 0x9060; +pub const PCI_VENDOR_ID_AMD: usize = 0x1022; +pub const PCI_DEVICE_ID_AMD_K8_NB: usize = 0x1100; +pub const PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP: usize = 0x1101; +pub const PCI_DEVICE_ID_AMD_K8_NB_MEMCTL: usize = 0x1102; +pub const PCI_DEVICE_ID_AMD_K8_NB_MISC: usize = 0x1103; +pub const PCI_DEVICE_ID_AMD_10H_NB_HT: usize = 0x1200; +pub const PCI_DEVICE_ID_AMD_10H_NB_MAP: usize = 0x1201; +pub const PCI_DEVICE_ID_AMD_10H_NB_DRAM: usize = 0x1202; +pub const PCI_DEVICE_ID_AMD_10H_NB_MISC: usize = 0x1203; +pub const PCI_DEVICE_ID_AMD_10H_NB_LINK: usize = 0x1204; +pub const PCI_DEVICE_ID_AMD_11H_NB_HT: usize = 0x1300; +pub const PCI_DEVICE_ID_AMD_11H_NB_MAP: usize = 0x1301; +pub const PCI_DEVICE_ID_AMD_11H_NB_DRAM: usize = 0x1302; +pub const PCI_DEVICE_ID_AMD_11H_NB_MISC: usize = 0x1303; +pub const PCI_DEVICE_ID_AMD_11H_NB_LINK: usize = 0x1304; +pub const PCI_DEVICE_ID_AMD_15H_M10H_F3: usize = 0x1403; +pub const PCI_DEVICE_ID_AMD_15H_M30H_NB_F3: usize = 0x141d; +pub const PCI_DEVICE_ID_AMD_15H_M30H_NB_F4: usize = 0x141e; +pub const PCI_DEVICE_ID_AMD_15H_M60H_NB_F3: usize = 0x1573; +pub const PCI_DEVICE_ID_AMD_15H_M60H_NB_F4: usize = 0x1574; +pub const PCI_DEVICE_ID_AMD_15H_NB_F0: usize = 0x1600; +pub const PCI_DEVICE_ID_AMD_15H_NB_F1: usize = 0x1601; +pub const PCI_DEVICE_ID_AMD_15H_NB_F2: usize = 0x1602; +pub const PCI_DEVICE_ID_AMD_15H_NB_F3: usize = 0x1603; +pub const PCI_DEVICE_ID_AMD_15H_NB_F4: usize = 0x1604; +pub const PCI_DEVICE_ID_AMD_15H_NB_F5: usize = 0x1605; +pub const PCI_DEVICE_ID_AMD_16H_NB_F3: usize = 0x1533; +pub const PCI_DEVICE_ID_AMD_16H_NB_F4: usize = 0x1534; +pub const PCI_DEVICE_ID_AMD_16H_M30H_NB_F3: usize = 0x1583; +pub const PCI_DEVICE_ID_AMD_16H_M30H_NB_F4: usize = 0x1584; +pub const PCI_DEVICE_ID_AMD_17H_DF_F3: usize = 0x1463; +pub const PCI_DEVICE_ID_AMD_17H_M10H_DF_F3: usize = 0x15eb; +pub const PCI_DEVICE_ID_AMD_17H_M30H_DF_F3: usize = 0x1493; +pub const PCI_DEVICE_ID_AMD_17H_M60H_DF_F3: usize = 0x144b; +pub const PCI_DEVICE_ID_AMD_17H_M70H_DF_F3: usize = 0x1443; +pub const PCI_DEVICE_ID_AMD_VANGOGH_USB: usize = 0x163a; +pub const PCI_DEVICE_ID_AMD_19H_DF_F3: usize = 0x1653; +pub const PCI_DEVICE_ID_AMD_CNB17H_F3: usize = 0x1703; +pub const PCI_DEVICE_ID_AMD_LANCE: usize = 0x2000; +pub const PCI_DEVICE_ID_AMD_LANCE_HOME: usize = 0x2001; +pub const PCI_DEVICE_ID_AMD_SCSI: usize = 0x2020; +pub const PCI_DEVICE_ID_AMD_SERENADE: usize = 0x36c0; +pub const PCI_DEVICE_ID_AMD_FE_GATE_7006: usize = 0x7006; +pub const PCI_DEVICE_ID_AMD_FE_GATE_7007: usize = 0x7007; +pub const PCI_DEVICE_ID_AMD_FE_GATE_700C: usize = 0x700C; +pub const PCI_DEVICE_ID_AMD_FE_GATE_700E: usize = 0x700E; +pub const PCI_DEVICE_ID_AMD_COBRA_7401: usize = 0x7401; +pub const PCI_DEVICE_ID_AMD_VIPER_7409: usize = 0x7409; +pub const PCI_DEVICE_ID_AMD_VIPER_740B: usize = 0x740B; +pub const PCI_DEVICE_ID_AMD_VIPER_7410: usize = 0x7410; +pub const PCI_DEVICE_ID_AMD_VIPER_7411: usize = 0x7411; +pub const PCI_DEVICE_ID_AMD_VIPER_7413: usize = 0x7413; +pub const PCI_DEVICE_ID_AMD_VIPER_7440: usize = 0x7440; +pub const PCI_DEVICE_ID_AMD_OPUS_7441: usize = 0x7441; +pub const PCI_DEVICE_ID_AMD_OPUS_7443: usize = 0x7443; +pub const PCI_DEVICE_ID_AMD_VIPER_7443: usize = 0x7443; +pub const PCI_DEVICE_ID_AMD_OPUS_7445: usize = 0x7445; +pub const PCI_DEVICE_ID_AMD_GOLAM_7450: usize = 0x7450; +pub const PCI_DEVICE_ID_AMD_8111_PCI: usize = 0x7460; +pub const PCI_DEVICE_ID_AMD_8111_LPC: usize = 0x7468; +pub const PCI_DEVICE_ID_AMD_8111_IDE: usize = 0x7469; +pub const PCI_DEVICE_ID_AMD_8111_SMBUS2: usize = 0x746a; +pub const PCI_DEVICE_ID_AMD_8111_SMBUS: usize = 0x746b; +pub const PCI_DEVICE_ID_AMD_8111_AUDIO: usize = 0x746d; +pub const PCI_DEVICE_ID_AMD_8151_0: usize = 0x7454; +pub const PCI_DEVICE_ID_AMD_8131_BRIDGE: usize = 0x7450; +pub const PCI_DEVICE_ID_AMD_8131_APIC: usize = 0x7451; +pub const PCI_DEVICE_ID_AMD_8132_BRIDGE: usize = 0x7458; +pub const PCI_DEVICE_ID_AMD_NL_USB: usize = 0x7912; +pub const PCI_DEVICE_ID_AMD_CS5535_IDE: usize = 0x208F; +pub const PCI_DEVICE_ID_AMD_CS5536_ISA: usize = 0x2090; +pub const PCI_DEVICE_ID_AMD_CS5536_FLASH: usize = 0x2091; +pub const PCI_DEVICE_ID_AMD_CS5536_AUDIO: usize = 0x2093; +pub const PCI_DEVICE_ID_AMD_CS5536_OHC: usize = 0x2094; +pub const PCI_DEVICE_ID_AMD_CS5536_EHC: usize = 0x2095; +pub const PCI_DEVICE_ID_AMD_CS5536_UDC: usize = 0x2096; +pub const PCI_DEVICE_ID_AMD_CS5536_UOC: usize = 0x2097; +pub const PCI_DEVICE_ID_AMD_CS5536_DEV_IDE: usize = 0x2092; +pub const PCI_DEVICE_ID_AMD_CS5536_IDE: usize = 0x209A; +pub const PCI_DEVICE_ID_AMD_LX_VIDEO: usize = 0x2081; +pub const PCI_DEVICE_ID_AMD_LX_AES: usize = 0x2082; +pub const PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE: usize = 0x7800; +pub const PCI_DEVICE_ID_AMD_HUDSON2_SMBUS: usize = 0x780b; +pub const PCI_DEVICE_ID_AMD_HUDSON2_IDE: usize = 0x780c; +pub const PCI_DEVICE_ID_AMD_KERNCZ_SMBUS: usize = 0x790b; +pub const PCI_VENDOR_ID_TRIDENT: usize = 0x1023; +pub const PCI_DEVICE_ID_TRIDENT_4DWAVE_DX: usize = 0x2000; +pub const PCI_DEVICE_ID_TRIDENT_4DWAVE_NX: usize = 0x2001; +pub const PCI_DEVICE_ID_TRIDENT_9320: usize = 0x9320; +pub const PCI_DEVICE_ID_TRIDENT_9388: usize = 0x9388; +pub const PCI_DEVICE_ID_TRIDENT_9397: usize = 0x9397; +pub const PCI_DEVICE_ID_TRIDENT_939A: usize = 0x939A; +pub const PCI_DEVICE_ID_TRIDENT_9520: usize = 0x9520; +pub const PCI_DEVICE_ID_TRIDENT_9525: usize = 0x9525; +pub const PCI_DEVICE_ID_TRIDENT_9420: usize = 0x9420; +pub const PCI_DEVICE_ID_TRIDENT_9440: usize = 0x9440; +pub const PCI_DEVICE_ID_TRIDENT_9660: usize = 0x9660; +pub const PCI_DEVICE_ID_TRIDENT_9750: usize = 0x9750; +pub const PCI_DEVICE_ID_TRIDENT_9850: usize = 0x9850; +pub const PCI_DEVICE_ID_TRIDENT_9880: usize = 0x9880; +pub const PCI_DEVICE_ID_TRIDENT_8400: usize = 0x8400; +pub const PCI_DEVICE_ID_TRIDENT_8420: usize = 0x8420; +pub const PCI_DEVICE_ID_TRIDENT_8500: usize = 0x8500; +pub const PCI_VENDOR_ID_AI: usize = 0x1025; +pub const PCI_DEVICE_ID_AI_M1435: usize = 0x1435; +pub const PCI_VENDOR_ID_DELL: usize = 0x1028; +pub const PCI_DEVICE_ID_DELL_RACIII: usize = 0x0008; +pub const PCI_DEVICE_ID_DELL_RAC4: usize = 0x0012; +pub const PCI_DEVICE_ID_DELL_PERC5: usize = 0x0015; +pub const PCI_VENDOR_ID_MATROX: usize = 0x102B; +pub const PCI_DEVICE_ID_MATROX_MGA_2: usize = 0x0518; +pub const PCI_DEVICE_ID_MATROX_MIL: usize = 0x0519; +pub const PCI_DEVICE_ID_MATROX_MYS: usize = 0x051A; +pub const PCI_DEVICE_ID_MATROX_MIL_2: usize = 0x051b; +pub const PCI_DEVICE_ID_MATROX_MYS_AGP: usize = 0x051e; +pub const PCI_DEVICE_ID_MATROX_MIL_2_AGP: usize = 0x051f; +pub const PCI_DEVICE_ID_MATROX_MGA_IMP: usize = 0x0d10; +pub const PCI_DEVICE_ID_MATROX_G100_MM: usize = 0x1000; +pub const PCI_DEVICE_ID_MATROX_G100_AGP: usize = 0x1001; +pub const PCI_DEVICE_ID_MATROX_G200_PCI: usize = 0x0520; +pub const PCI_DEVICE_ID_MATROX_G200_AGP: usize = 0x0521; +pub const PCI_DEVICE_ID_MATROX_G400: usize = 0x0525; +pub const PCI_DEVICE_ID_MATROX_G200EV_PCI: usize = 0x0530; +pub const PCI_DEVICE_ID_MATROX_G550: usize = 0x2527; +pub const PCI_DEVICE_ID_MATROX_VIA: usize = 0x4536; +pub const PCI_VENDOR_ID_MOBILITY_ELECTRONICS: usize = 0x14f2; +pub const PCI_VENDOR_ID_CT: usize = 0x102c; +pub const PCI_DEVICE_ID_CT_69000: usize = 0x00c0; +pub const PCI_DEVICE_ID_CT_65545: usize = 0x00d8; +pub const PCI_DEVICE_ID_CT_65548: usize = 0x00dc; +pub const PCI_DEVICE_ID_CT_65550: usize = 0x00e0; +pub const PCI_DEVICE_ID_CT_65554: usize = 0x00e4; +pub const PCI_DEVICE_ID_CT_65555: usize = 0x00e5; +pub const PCI_VENDOR_ID_MIRO: usize = 0x1031; +pub const PCI_DEVICE_ID_MIRO_36050: usize = 0x5601; +pub const PCI_DEVICE_ID_MIRO_DC10PLUS: usize = 0x7efe; +pub const PCI_DEVICE_ID_MIRO_DC30PLUS: usize = 0xd801; +pub const PCI_VENDOR_ID_NEC: usize = 0x1033; +pub const PCI_DEVICE_ID_NEC_CBUS_1: usize = 0x0001; +pub const PCI_DEVICE_ID_NEC_LOCAL: usize = 0x0002; +pub const PCI_DEVICE_ID_NEC_ATM: usize = 0x0003; +pub const PCI_DEVICE_ID_NEC_R4000: usize = 0x0004; +pub const PCI_DEVICE_ID_NEC_486: usize = 0x0005; +pub const PCI_DEVICE_ID_NEC_ACCEL_1: usize = 0x0006; +pub const PCI_DEVICE_ID_NEC_UXBUS: usize = 0x0007; +pub const PCI_DEVICE_ID_NEC_ACCEL_2: usize = 0x0008; +pub const PCI_DEVICE_ID_NEC_GRAPH: usize = 0x0009; +pub const PCI_DEVICE_ID_NEC_VL: usize = 0x0016; +pub const PCI_DEVICE_ID_NEC_STARALPHA2: usize = 0x002c; +pub const PCI_DEVICE_ID_NEC_CBUS_2: usize = 0x002d; +pub const PCI_DEVICE_ID_NEC_USB: usize = 0x0035; +pub const PCI_DEVICE_ID_NEC_CBUS_3: usize = 0x003b; +pub const PCI_DEVICE_ID_NEC_NAPCCARD: usize = 0x003e; +pub const PCI_DEVICE_ID_NEC_PCX2: usize = 0x0046; +pub const PCI_DEVICE_ID_NEC_VRC5476: usize = 0x009b; +pub const PCI_DEVICE_ID_NEC_VRC4173: usize = 0x00a5; +pub const PCI_DEVICE_ID_NEC_VRC5477_AC97: usize = 0x00a6; +pub const PCI_DEVICE_ID_NEC_PC9821CS01: usize = 0x800c; +pub const PCI_DEVICE_ID_NEC_PC9821NRB06: usize = 0x800d; +pub const PCI_VENDOR_ID_FD: usize = 0x1036; +pub const PCI_DEVICE_ID_FD_36C70: usize = 0x0000; +pub const PCI_VENDOR_ID_SI: usize = 0x1039; +pub const PCI_DEVICE_ID_SI_5591_AGP: usize = 0x0001; +pub const PCI_DEVICE_ID_SI_6202: usize = 0x0002; +pub const PCI_DEVICE_ID_SI_503: usize = 0x0008; +pub const PCI_DEVICE_ID_SI_ACPI: usize = 0x0009; +pub const PCI_DEVICE_ID_SI_SMBUS: usize = 0x0016; +pub const PCI_DEVICE_ID_SI_LPC: usize = 0x0018; +pub const PCI_DEVICE_ID_SI_5597_VGA: usize = 0x0200; +pub const PCI_DEVICE_ID_SI_6205: usize = 0x0205; +pub const PCI_DEVICE_ID_SI_501: usize = 0x0406; +pub const PCI_DEVICE_ID_SI_496: usize = 0x0496; +pub const PCI_DEVICE_ID_SI_300: usize = 0x0300; +pub const PCI_DEVICE_ID_SI_315H: usize = 0x0310; +pub const PCI_DEVICE_ID_SI_315: usize = 0x0315; +pub const PCI_DEVICE_ID_SI_315PRO: usize = 0x0325; +pub const PCI_DEVICE_ID_SI_530: usize = 0x0530; +pub const PCI_DEVICE_ID_SI_540: usize = 0x0540; +pub const PCI_DEVICE_ID_SI_550: usize = 0x0550; +pub const PCI_DEVICE_ID_SI_540_VGA: usize = 0x5300; +pub const PCI_DEVICE_ID_SI_550_VGA: usize = 0x5315; +pub const PCI_DEVICE_ID_SI_620: usize = 0x0620; +pub const PCI_DEVICE_ID_SI_630: usize = 0x0630; +pub const PCI_DEVICE_ID_SI_633: usize = 0x0633; +pub const PCI_DEVICE_ID_SI_635: usize = 0x0635; +pub const PCI_DEVICE_ID_SI_640: usize = 0x0640; +pub const PCI_DEVICE_ID_SI_645: usize = 0x0645; +pub const PCI_DEVICE_ID_SI_646: usize = 0x0646; +pub const PCI_DEVICE_ID_SI_648: usize = 0x0648; +pub const PCI_DEVICE_ID_SI_650: usize = 0x0650; +pub const PCI_DEVICE_ID_SI_651: usize = 0x0651; +pub const PCI_DEVICE_ID_SI_655: usize = 0x0655; +pub const PCI_DEVICE_ID_SI_661: usize = 0x0661; +pub const PCI_DEVICE_ID_SI_730: usize = 0x0730; +pub const PCI_DEVICE_ID_SI_733: usize = 0x0733; +pub const PCI_DEVICE_ID_SI_630_VGA: usize = 0x6300; +pub const PCI_DEVICE_ID_SI_735: usize = 0x0735; +pub const PCI_DEVICE_ID_SI_740: usize = 0x0740; +pub const PCI_DEVICE_ID_SI_741: usize = 0x0741; +pub const PCI_DEVICE_ID_SI_745: usize = 0x0745; +pub const PCI_DEVICE_ID_SI_746: usize = 0x0746; +pub const PCI_DEVICE_ID_SI_755: usize = 0x0755; +pub const PCI_DEVICE_ID_SI_760: usize = 0x0760; +pub const PCI_DEVICE_ID_SI_900: usize = 0x0900; +pub const PCI_DEVICE_ID_SI_961: usize = 0x0961; +pub const PCI_DEVICE_ID_SI_962: usize = 0x0962; +pub const PCI_DEVICE_ID_SI_963: usize = 0x0963; +pub const PCI_DEVICE_ID_SI_965: usize = 0x0965; +pub const PCI_DEVICE_ID_SI_966: usize = 0x0966; +pub const PCI_DEVICE_ID_SI_968: usize = 0x0968; +pub const PCI_DEVICE_ID_SI_1180: usize = 0x1180; +pub const PCI_DEVICE_ID_SI_5511: usize = 0x5511; +pub const PCI_DEVICE_ID_SI_5513: usize = 0x5513; +pub const PCI_DEVICE_ID_SI_5517: usize = 0x5517; +pub const PCI_DEVICE_ID_SI_5518: usize = 0x5518; +pub const PCI_DEVICE_ID_SI_5571: usize = 0x5571; +pub const PCI_DEVICE_ID_SI_5581: usize = 0x5581; +pub const PCI_DEVICE_ID_SI_5582: usize = 0x5582; +pub const PCI_DEVICE_ID_SI_5591: usize = 0x5591; +pub const PCI_DEVICE_ID_SI_5596: usize = 0x5596; +pub const PCI_DEVICE_ID_SI_5597: usize = 0x5597; +pub const PCI_DEVICE_ID_SI_5598: usize = 0x5598; +pub const PCI_DEVICE_ID_SI_5600: usize = 0x5600; +pub const PCI_DEVICE_ID_SI_7012: usize = 0x7012; +pub const PCI_DEVICE_ID_SI_7013: usize = 0x7013; +pub const PCI_DEVICE_ID_SI_7016: usize = 0x7016; +pub const PCI_DEVICE_ID_SI_7018: usize = 0x7018; +pub const PCI_VENDOR_ID_HP: usize = 0x103c; +pub const PCI_VENDOR_ID_HP_3PAR: usize = 0x1590; +pub const PCI_DEVICE_ID_HP_VISUALIZE_EG: usize = 0x1005; +pub const PCI_DEVICE_ID_HP_VISUALIZE_FX6: usize = 0x1006; +pub const PCI_DEVICE_ID_HP_VISUALIZE_FX4: usize = 0x1008; +pub const PCI_DEVICE_ID_HP_VISUALIZE_FX2: usize = 0x100a; +pub const PCI_DEVICE_ID_HP_TACHYON: usize = 0x1028; +pub const PCI_DEVICE_ID_HP_TACHLITE: usize = 0x1029; +pub const PCI_DEVICE_ID_HP_J2585A: usize = 0x1030; +pub const PCI_DEVICE_ID_HP_J2585B: usize = 0x1031; +pub const PCI_DEVICE_ID_HP_J2973A: usize = 0x1040; +pub const PCI_DEVICE_ID_HP_J2970A: usize = 0x1042; +pub const PCI_DEVICE_ID_HP_DIVA: usize = 0x1048; +pub const PCI_DEVICE_ID_HP_DIVA_TOSCA1: usize = 0x1049; +pub const PCI_DEVICE_ID_HP_DIVA_TOSCA2: usize = 0x104A; +pub const PCI_DEVICE_ID_HP_DIVA_MAESTRO: usize = 0x104B; +pub const PCI_DEVICE_ID_HP_REO_IOC: usize = 0x10f1; +pub const PCI_DEVICE_ID_HP_VISUALIZE_FXE: usize = 0x108b; +pub const PCI_DEVICE_ID_HP_DIVA_HALFDOME: usize = 0x1223; +pub const PCI_DEVICE_ID_HP_DIVA_KEYSTONE: usize = 0x1226; +pub const PCI_DEVICE_ID_HP_DIVA_POWERBAR: usize = 0x1227; +pub const PCI_DEVICE_ID_HP_ZX1_IOC: usize = 0x122a; +pub const PCI_DEVICE_ID_HP_PCIX_LBA: usize = 0x122e; +pub const PCI_DEVICE_ID_HP_SX1000_IOC: usize = 0x127c; +pub const PCI_DEVICE_ID_HP_DIVA_EVEREST: usize = 0x1282; +pub const PCI_DEVICE_ID_HP_DIVA_AUX: usize = 0x1290; +pub const PCI_DEVICE_ID_HP_DIVA_RMP3: usize = 0x1301; +pub const PCI_DEVICE_ID_HP_DIVA_HURRICANE: usize = 0x132a; +pub const PCI_DEVICE_ID_HP_CISSA: usize = 0x3220; +pub const PCI_DEVICE_ID_HP_CISSC: usize = 0x3230; +pub const PCI_DEVICE_ID_HP_CISSD: usize = 0x3238; +pub const PCI_DEVICE_ID_HP_CISSE: usize = 0x323a; +pub const PCI_DEVICE_ID_HP_CISSF: usize = 0x323b; +pub const PCI_DEVICE_ID_HP_CISSH: usize = 0x323c; +pub const PCI_DEVICE_ID_HP_CISSI: usize = 0x3239; +pub const PCI_DEVICE_ID_HP_ZX2_IOC: usize = 0x4031; +pub const PCI_VENDOR_ID_PCTECH: usize = 0x1042; +pub const PCI_DEVICE_ID_PCTECH_RZ1000: usize = 0x1000; +pub const PCI_DEVICE_ID_PCTECH_RZ1001: usize = 0x1001; +pub const PCI_DEVICE_ID_PCTECH_SAMURAI_IDE: usize = 0x3020; +pub const PCI_VENDOR_ID_ASUSTEK: usize = 0x1043; +pub const PCI_DEVICE_ID_ASUSTEK_0675: usize = 0x0675; +pub const PCI_VENDOR_ID_DPT: usize = 0x1044; +pub const PCI_DEVICE_ID_DPT: usize = 0xa400; +pub const PCI_VENDOR_ID_OPTI: usize = 0x1045; +pub const PCI_DEVICE_ID_OPTI_82C558: usize = 0xc558; +pub const PCI_DEVICE_ID_OPTI_82C621: usize = 0xc621; +pub const PCI_DEVICE_ID_OPTI_82C700: usize = 0xc700; +pub const PCI_DEVICE_ID_OPTI_82C825: usize = 0xd568; +pub const PCI_VENDOR_ID_ELSA: usize = 0x1048; +pub const PCI_DEVICE_ID_ELSA_MICROLINK: usize = 0x1000; +pub const PCI_DEVICE_ID_ELSA_QS3000: usize = 0x3000; +pub const PCI_VENDOR_ID_STMICRO: usize = 0x104A; +pub const PCI_DEVICE_ID_STMICRO_USB_HOST: usize = 0xCC00; +pub const PCI_DEVICE_ID_STMICRO_USB_OHCI: usize = 0xCC01; +pub const PCI_DEVICE_ID_STMICRO_USB_OTG: usize = 0xCC02; +pub const PCI_DEVICE_ID_STMICRO_UART_HWFC: usize = 0xCC03; +pub const PCI_DEVICE_ID_STMICRO_UART_NO_HWFC: usize = 0xCC04; +pub const PCI_DEVICE_ID_STMICRO_SOC_DMA: usize = 0xCC05; +pub const PCI_DEVICE_ID_STMICRO_SATA: usize = 0xCC06; +pub const PCI_DEVICE_ID_STMICRO_I2C: usize = 0xCC07; +pub const PCI_DEVICE_ID_STMICRO_SPI_HS: usize = 0xCC08; +pub const PCI_DEVICE_ID_STMICRO_MAC: usize = 0xCC09; +pub const PCI_DEVICE_ID_STMICRO_SDIO_EMMC: usize = 0xCC0A; +pub const PCI_DEVICE_ID_STMICRO_SDIO: usize = 0xCC0B; +pub const PCI_DEVICE_ID_STMICRO_GPIO: usize = 0xCC0C; +pub const PCI_DEVICE_ID_STMICRO_VIP: usize = 0xCC0D; +pub const PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA: usize = 0xCC0E; +pub const PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS: usize = 0xCC0F; +pub const PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS: usize = 0xCC10; +pub const PCI_DEVICE_ID_STMICRO_CAN: usize = 0xCC11; +pub const PCI_DEVICE_ID_STMICRO_MLB: usize = 0xCC12; +pub const PCI_DEVICE_ID_STMICRO_DBP: usize = 0xCC13; +pub const PCI_DEVICE_ID_STMICRO_SATA_PHY: usize = 0xCC14; +pub const PCI_DEVICE_ID_STMICRO_ESRAM: usize = 0xCC15; +pub const PCI_DEVICE_ID_STMICRO_VIC: usize = 0xCC16; +pub const PCI_VENDOR_ID_BUSLOGIC: usize = 0x104B; +pub const PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC: usize = 0x0140; +pub const PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER: usize = 0x1040; +pub const PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT: usize = 0x8130; +pub const PCI_VENDOR_ID_TI: usize = 0x104c; +pub const PCI_DEVICE_ID_TI_TVP4020: usize = 0x3d07; +pub const PCI_DEVICE_ID_TI_4450: usize = 0x8011; +pub const PCI_DEVICE_ID_TI_XX21_XX11: usize = 0x8031; +pub const PCI_DEVICE_ID_TI_XX21_XX11_FM: usize = 0x8033; +pub const PCI_DEVICE_ID_TI_XX21_XX11_SD: usize = 0x8034; +pub const PCI_DEVICE_ID_TI_X515: usize = 0x8036; +pub const PCI_DEVICE_ID_TI_XX12: usize = 0x8039; +pub const PCI_DEVICE_ID_TI_XX12_FM: usize = 0x803b; +pub const PCI_DEVICE_ID_TI_XIO2000A: usize = 0x8231; +pub const PCI_DEVICE_ID_TI_1130: usize = 0xac12; +pub const PCI_DEVICE_ID_TI_1031: usize = 0xac13; +pub const PCI_DEVICE_ID_TI_1131: usize = 0xac15; +pub const PCI_DEVICE_ID_TI_1250: usize = 0xac16; +pub const PCI_DEVICE_ID_TI_1220: usize = 0xac17; +pub const PCI_DEVICE_ID_TI_1221: usize = 0xac19; +pub const PCI_DEVICE_ID_TI_1210: usize = 0xac1a; +pub const PCI_DEVICE_ID_TI_1450: usize = 0xac1b; +pub const PCI_DEVICE_ID_TI_1225: usize = 0xac1c; +pub const PCI_DEVICE_ID_TI_1251A: usize = 0xac1d; +pub const PCI_DEVICE_ID_TI_1211: usize = 0xac1e; +pub const PCI_DEVICE_ID_TI_1251B: usize = 0xac1f; +pub const PCI_DEVICE_ID_TI_4410: usize = 0xac41; +pub const PCI_DEVICE_ID_TI_4451: usize = 0xac42; +pub const PCI_DEVICE_ID_TI_4510: usize = 0xac44; +pub const PCI_DEVICE_ID_TI_4520: usize = 0xac46; +pub const PCI_DEVICE_ID_TI_7510: usize = 0xac47; +pub const PCI_DEVICE_ID_TI_7610: usize = 0xac48; +pub const PCI_DEVICE_ID_TI_7410: usize = 0xac49; +pub const PCI_DEVICE_ID_TI_1410: usize = 0xac50; +pub const PCI_DEVICE_ID_TI_1420: usize = 0xac51; +pub const PCI_DEVICE_ID_TI_1451A: usize = 0xac52; +pub const PCI_DEVICE_ID_TI_1620: usize = 0xac54; +pub const PCI_DEVICE_ID_TI_1520: usize = 0xac55; +pub const PCI_DEVICE_ID_TI_1510: usize = 0xac56; +pub const PCI_DEVICE_ID_TI_X620: usize = 0xac8d; +pub const PCI_DEVICE_ID_TI_X420: usize = 0xac8e; +pub const PCI_DEVICE_ID_TI_XX20_FM: usize = 0xac8f; +pub const PCI_DEVICE_ID_TI_DRA74x: usize = 0xb500; +pub const PCI_DEVICE_ID_TI_DRA72x: usize = 0xb501; +pub const PCI_VENDOR_ID_SONY: usize = 0x104d; +pub const PCI_VENDOR_ID_WINBOND2: usize = 0x1050; +pub const PCI_DEVICE_ID_WINBOND2_89C940F: usize = 0x5a5a; +pub const PCI_DEVICE_ID_WINBOND2_6692: usize = 0x6692; +pub const PCI_VENDOR_ID_ANIGMA: usize = 0x1051; +pub const PCI_DEVICE_ID_ANIGMA_MC145575: usize = 0x0100; +pub const PCI_VENDOR_ID_EFAR: usize = 0x1055; +pub const PCI_DEVICE_ID_EFAR_SLC90E66_1: usize = 0x9130; +pub const PCI_DEVICE_ID_EFAR_SLC90E66_3: usize = 0x9463; +pub const PCI_VENDOR_ID_MOTOROLA: usize = 0x1057; +pub const PCI_DEVICE_ID_MOTOROLA_MPC105: usize = 0x0001; +pub const PCI_DEVICE_ID_MOTOROLA_MPC106: usize = 0x0002; +pub const PCI_DEVICE_ID_MOTOROLA_MPC107: usize = 0x0004; +pub const PCI_DEVICE_ID_MOTOROLA_RAVEN: usize = 0x4801; +pub const PCI_DEVICE_ID_MOTOROLA_FALCON: usize = 0x4802; +pub const PCI_DEVICE_ID_MOTOROLA_HAWK: usize = 0x4803; +pub const PCI_DEVICE_ID_MOTOROLA_HARRIER: usize = 0x480b; +pub const PCI_DEVICE_ID_MOTOROLA_MPC5200: usize = 0x5803; +pub const PCI_DEVICE_ID_MOTOROLA_MPC5200B: usize = 0x5809; +pub const PCI_VENDOR_ID_PROMISE: usize = 0x105a; +pub const PCI_DEVICE_ID_PROMISE_20265: usize = 0x0d30; +pub const PCI_DEVICE_ID_PROMISE_20267: usize = 0x4d30; +pub const PCI_DEVICE_ID_PROMISE_20246: usize = 0x4d33; +pub const PCI_DEVICE_ID_PROMISE_20262: usize = 0x4d38; +pub const PCI_DEVICE_ID_PROMISE_20263: usize = 0x0D38; +pub const PCI_DEVICE_ID_PROMISE_20268: usize = 0x4d68; +pub const PCI_DEVICE_ID_PROMISE_20269: usize = 0x4d69; +pub const PCI_DEVICE_ID_PROMISE_20270: usize = 0x6268; +pub const PCI_DEVICE_ID_PROMISE_20271: usize = 0x6269; +pub const PCI_DEVICE_ID_PROMISE_20275: usize = 0x1275; +pub const PCI_DEVICE_ID_PROMISE_20276: usize = 0x5275; +pub const PCI_DEVICE_ID_PROMISE_20277: usize = 0x7275; +pub const PCI_VENDOR_ID_FOXCONN: usize = 0x105b; +pub const PCI_VENDOR_ID_UMC: usize = 0x1060; +pub const PCI_DEVICE_ID_UMC_UM8673F: usize = 0x0101; +pub const PCI_DEVICE_ID_UMC_UM8886BF: usize = 0x673a; +pub const PCI_DEVICE_ID_UMC_UM8886A: usize = 0x886a; +pub const PCI_VENDOR_ID_PICOPOWER: usize = 0x1066; +pub const PCI_DEVICE_ID_PICOPOWER_PT86C523: usize = 0x0002; +pub const PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: usize = 0x8002; +pub const PCI_VENDOR_ID_MYLEX: usize = 0x1069; +pub const PCI_DEVICE_ID_MYLEX_DAC960_P: usize = 0x0001; +pub const PCI_DEVICE_ID_MYLEX_DAC960_PD: usize = 0x0002; +pub const PCI_DEVICE_ID_MYLEX_DAC960_PG: usize = 0x0010; +pub const PCI_DEVICE_ID_MYLEX_DAC960_LA: usize = 0x0020; +pub const PCI_DEVICE_ID_MYLEX_DAC960_LP: usize = 0x0050; +pub const PCI_DEVICE_ID_MYLEX_DAC960_BA: usize = 0xBA56; +pub const PCI_DEVICE_ID_MYLEX_DAC960_GEM: usize = 0xB166; +pub const PCI_VENDOR_ID_APPLE: usize = 0x106b; +pub const PCI_DEVICE_ID_APPLE_BANDIT: usize = 0x0001; +pub const PCI_DEVICE_ID_APPLE_HYDRA: usize = 0x000e; +pub const PCI_DEVICE_ID_APPLE_UNI_N_FW: usize = 0x0018; +pub const PCI_DEVICE_ID_APPLE_UNI_N_AGP: usize = 0x0020; +pub const PCI_DEVICE_ID_APPLE_UNI_N_GMAC: usize = 0x0021; +pub const PCI_DEVICE_ID_APPLE_UNI_N_GMACP: usize = 0x0024; +pub const PCI_DEVICE_ID_APPLE_UNI_N_AGP_P: usize = 0x0027; +pub const PCI_DEVICE_ID_APPLE_UNI_N_AGP15: usize = 0x002d; +pub const PCI_DEVICE_ID_APPLE_UNI_N_PCI15: usize = 0x002e; +pub const PCI_DEVICE_ID_APPLE_UNI_N_GMAC2: usize = 0x0032; +pub const PCI_DEVICE_ID_APPLE_UNI_N_ATA: usize = 0x0033; +pub const PCI_DEVICE_ID_APPLE_UNI_N_AGP2: usize = 0x0034; +pub const PCI_DEVICE_ID_APPLE_IPID_ATA100: usize = 0x003b; +pub const PCI_DEVICE_ID_APPLE_K2_ATA100: usize = 0x0043; +pub const PCI_DEVICE_ID_APPLE_U3_AGP: usize = 0x004b; +pub const PCI_DEVICE_ID_APPLE_K2_GMAC: usize = 0x004c; +pub const PCI_DEVICE_ID_APPLE_SH_ATA: usize = 0x0050; +pub const PCI_DEVICE_ID_APPLE_SH_SUNGEM: usize = 0x0051; +pub const PCI_DEVICE_ID_APPLE_U3L_AGP: usize = 0x0058; +pub const PCI_DEVICE_ID_APPLE_U3H_AGP: usize = 0x0059; +pub const PCI_DEVICE_ID_APPLE_U4_PCIE: usize = 0x005b; +pub const PCI_DEVICE_ID_APPLE_IPID2_AGP: usize = 0x0066; +pub const PCI_DEVICE_ID_APPLE_IPID2_ATA: usize = 0x0069; +pub const PCI_DEVICE_ID_APPLE_IPID2_FW: usize = 0x006a; +pub const PCI_DEVICE_ID_APPLE_IPID2_GMAC: usize = 0x006b; +pub const PCI_DEVICE_ID_APPLE_TIGON3: usize = 0x1645; +pub const PCI_VENDOR_ID_YAMAHA: usize = 0x1073; +pub const PCI_DEVICE_ID_YAMAHA_724: usize = 0x0004; +pub const PCI_DEVICE_ID_YAMAHA_724F: usize = 0x000d; +pub const PCI_DEVICE_ID_YAMAHA_740: usize = 0x000a; +pub const PCI_DEVICE_ID_YAMAHA_740C: usize = 0x000c; +pub const PCI_DEVICE_ID_YAMAHA_744: usize = 0x0010; +pub const PCI_DEVICE_ID_YAMAHA_754: usize = 0x0012; +pub const PCI_VENDOR_ID_QLOGIC: usize = 0x1077; +pub const PCI_DEVICE_ID_QLOGIC_ISP10160: usize = 0x1016; +pub const PCI_DEVICE_ID_QLOGIC_ISP1020: usize = 0x1020; +pub const PCI_DEVICE_ID_QLOGIC_ISP1080: usize = 0x1080; +pub const PCI_DEVICE_ID_QLOGIC_ISP12160: usize = 0x1216; +pub const PCI_DEVICE_ID_QLOGIC_ISP1240: usize = 0x1240; +pub const PCI_DEVICE_ID_QLOGIC_ISP1280: usize = 0x1280; +pub const PCI_DEVICE_ID_QLOGIC_ISP2100: usize = 0x2100; +pub const PCI_DEVICE_ID_QLOGIC_ISP2200: usize = 0x2200; +pub const PCI_DEVICE_ID_QLOGIC_ISP2300: usize = 0x2300; +pub const PCI_DEVICE_ID_QLOGIC_ISP2312: usize = 0x2312; +pub const PCI_DEVICE_ID_QLOGIC_ISP2322: usize = 0x2322; +pub const PCI_DEVICE_ID_QLOGIC_ISP6312: usize = 0x6312; +pub const PCI_DEVICE_ID_QLOGIC_ISP6322: usize = 0x6322; +pub const PCI_DEVICE_ID_QLOGIC_ISP2422: usize = 0x2422; +pub const PCI_DEVICE_ID_QLOGIC_ISP2432: usize = 0x2432; +pub const PCI_DEVICE_ID_QLOGIC_ISP2512: usize = 0x2512; +pub const PCI_DEVICE_ID_QLOGIC_ISP2522: usize = 0x2522; +pub const PCI_DEVICE_ID_QLOGIC_ISP5422: usize = 0x5422; +pub const PCI_DEVICE_ID_QLOGIC_ISP5432: usize = 0x5432; +pub const PCI_VENDOR_ID_CYRIX: usize = 0x1078; +pub const PCI_DEVICE_ID_CYRIX_5510: usize = 0x0000; +pub const PCI_DEVICE_ID_CYRIX_PCI_MASTER: usize = 0x0001; +pub const PCI_DEVICE_ID_CYRIX_5520: usize = 0x0002; +pub const PCI_DEVICE_ID_CYRIX_5530_LEGACY: usize = 0x0100; +pub const PCI_DEVICE_ID_CYRIX_5530_IDE: usize = 0x0102; +pub const PCI_DEVICE_ID_CYRIX_5530_AUDIO: usize = 0x0103; +pub const PCI_DEVICE_ID_CYRIX_5530_VIDEO: usize = 0x0104; +pub const PCI_VENDOR_ID_CONTAQ: usize = 0x1080; +pub const PCI_DEVICE_ID_CONTAQ_82C693: usize = 0xc693; +pub const PCI_VENDOR_ID_OLICOM: usize = 0x108d; +pub const PCI_DEVICE_ID_OLICOM_OC2325: usize = 0x0012; +pub const PCI_DEVICE_ID_OLICOM_OC2183: usize = 0x0013; +pub const PCI_DEVICE_ID_OLICOM_OC2326: usize = 0x0014; +pub const PCI_VENDOR_ID_SUN: usize = 0x108e; +pub const PCI_DEVICE_ID_SUN_EBUS: usize = 0x1000; +pub const PCI_DEVICE_ID_SUN_HAPPYMEAL: usize = 0x1001; +pub const PCI_DEVICE_ID_SUN_RIO_EBUS: usize = 0x1100; +pub const PCI_DEVICE_ID_SUN_RIO_GEM: usize = 0x1101; +pub const PCI_DEVICE_ID_SUN_RIO_1394: usize = 0x1102; +pub const PCI_DEVICE_ID_SUN_RIO_USB: usize = 0x1103; +pub const PCI_DEVICE_ID_SUN_GEM: usize = 0x2bad; +pub const PCI_DEVICE_ID_SUN_SIMBA: usize = 0x5000; +pub const PCI_DEVICE_ID_SUN_PBM: usize = 0x8000; +pub const PCI_DEVICE_ID_SUN_SCHIZO: usize = 0x8001; +pub const PCI_DEVICE_ID_SUN_SABRE: usize = 0xa000; +pub const PCI_DEVICE_ID_SUN_HUMMINGBIRD: usize = 0xa001; +pub const PCI_DEVICE_ID_SUN_TOMATILLO: usize = 0xa801; +pub const PCI_DEVICE_ID_SUN_CASSINI: usize = 0xabba; +pub const PCI_VENDOR_ID_NI: usize = 0x1093; +pub const PCI_DEVICE_ID_NI_PCI2322: usize = 0xd130; +pub const PCI_DEVICE_ID_NI_PCI2324: usize = 0xd140; +pub const PCI_DEVICE_ID_NI_PCI2328: usize = 0xd150; +pub const PCI_DEVICE_ID_NI_PXI8422_2322: usize = 0xd190; +pub const PCI_DEVICE_ID_NI_PXI8422_2324: usize = 0xd1a0; +pub const PCI_DEVICE_ID_NI_PXI8420_2322: usize = 0xd1d0; +pub const PCI_DEVICE_ID_NI_PXI8420_2324: usize = 0xd1e0; +pub const PCI_DEVICE_ID_NI_PXI8420_2328: usize = 0xd1f0; +pub const PCI_DEVICE_ID_NI_PXI8420_23216: usize = 0xd1f1; +pub const PCI_DEVICE_ID_NI_PCI2322I: usize = 0xd250; +pub const PCI_DEVICE_ID_NI_PCI2324I: usize = 0xd270; +pub const PCI_DEVICE_ID_NI_PCI23216: usize = 0xd2b0; +pub const PCI_DEVICE_ID_NI_PXI8430_2322: usize = 0x7080; +pub const PCI_DEVICE_ID_NI_PCI8430_2322: usize = 0x70db; +pub const PCI_DEVICE_ID_NI_PXI8430_2324: usize = 0x70dd; +pub const PCI_DEVICE_ID_NI_PCI8430_2324: usize = 0x70df; +pub const PCI_DEVICE_ID_NI_PXI8430_2328: usize = 0x70e2; +pub const PCI_DEVICE_ID_NI_PCI8430_2328: usize = 0x70e4; +pub const PCI_DEVICE_ID_NI_PXI8430_23216: usize = 0x70e6; +pub const PCI_DEVICE_ID_NI_PCI8430_23216: usize = 0x70e7; +pub const PCI_DEVICE_ID_NI_PXI8432_2322: usize = 0x70e8; +pub const PCI_DEVICE_ID_NI_PCI8432_2322: usize = 0x70ea; +pub const PCI_DEVICE_ID_NI_PXI8432_2324: usize = 0x70ec; +pub const PCI_DEVICE_ID_NI_PCI8432_2324: usize = 0x70ee; +pub const PCI_VENDOR_ID_CMD: usize = 0x1095; +pub const PCI_DEVICE_ID_CMD_643: usize = 0x0643; +pub const PCI_DEVICE_ID_CMD_646: usize = 0x0646; +pub const PCI_DEVICE_ID_CMD_648: usize = 0x0648; +pub const PCI_DEVICE_ID_CMD_649: usize = 0x0649; +pub const PCI_DEVICE_ID_SII_680: usize = 0x0680; +pub const PCI_DEVICE_ID_SII_3112: usize = 0x3112; +pub const PCI_DEVICE_ID_SII_1210SA: usize = 0x0240; +pub const PCI_VENDOR_ID_BROOKTREE: usize = 0x109e; +pub const PCI_DEVICE_ID_BROOKTREE_878: usize = 0x0878; +pub const PCI_DEVICE_ID_BROOKTREE_879: usize = 0x0879; +pub const PCI_VENDOR_ID_SGI: usize = 0x10a9; +pub const PCI_DEVICE_ID_SGI_IOC3: usize = 0x0003; +pub const PCI_DEVICE_ID_SGI_LITHIUM: usize = 0x1002; +pub const PCI_VENDOR_ID_WINBOND: usize = 0x10ad; +pub const PCI_DEVICE_ID_WINBOND_82C105: usize = 0x0105; +pub const PCI_DEVICE_ID_WINBOND_83C553: usize = 0x0565; +pub const PCI_VENDOR_ID_PLX: usize = 0x10b5; +pub const PCI_DEVICE_ID_PLX_R685: usize = 0x1030; +pub const PCI_DEVICE_ID_PLX_ROMULUS: usize = 0x106a; +pub const PCI_DEVICE_ID_PLX_SPCOM800: usize = 0x1076; +pub const PCI_DEVICE_ID_PLX_1077: usize = 0x1077; +pub const PCI_DEVICE_ID_PLX_SPCOM200: usize = 0x1103; +pub const PCI_DEVICE_ID_PLX_DJINN_ITOO: usize = 0x1151; +pub const PCI_DEVICE_ID_PLX_R753: usize = 0x1152; +pub const PCI_DEVICE_ID_PLX_OLITEC: usize = 0x1187; +pub const PCI_DEVICE_ID_PLX_PCI200SYN: usize = 0x3196; +pub const PCI_DEVICE_ID_PLX_9030: usize = 0x9030; +pub const PCI_DEVICE_ID_PLX_9050: usize = 0x9050; +pub const PCI_DEVICE_ID_PLX_9056: usize = 0x9056; +pub const PCI_DEVICE_ID_PLX_9080: usize = 0x9080; +pub const PCI_DEVICE_ID_PLX_GTEK_SERIAL2: usize = 0xa001; +pub const PCI_VENDOR_ID_MADGE: usize = 0x10b6; +pub const PCI_DEVICE_ID_MADGE_MK2: usize = 0x0002; +pub const PCI_VENDOR_ID_3COM: usize = 0x10b7; +pub const PCI_DEVICE_ID_3COM_3C985: usize = 0x0001; +pub const PCI_DEVICE_ID_3COM_3C940: usize = 0x1700; +pub const PCI_DEVICE_ID_3COM_3C339: usize = 0x3390; +pub const PCI_DEVICE_ID_3COM_3C359: usize = 0x3590; +pub const PCI_DEVICE_ID_3COM_3C940B: usize = 0x80eb; +pub const PCI_DEVICE_ID_3COM_3CR990: usize = 0x9900; +pub const PCI_DEVICE_ID_3COM_3CR990_TX_95: usize = 0x9902; +pub const PCI_DEVICE_ID_3COM_3CR990_TX_97: usize = 0x9903; +pub const PCI_DEVICE_ID_3COM_3CR990B: usize = 0x9904; +pub const PCI_DEVICE_ID_3COM_3CR990_FX: usize = 0x9905; +pub const PCI_DEVICE_ID_3COM_3CR990SVR95: usize = 0x9908; +pub const PCI_DEVICE_ID_3COM_3CR990SVR97: usize = 0x9909; +pub const PCI_DEVICE_ID_3COM_3CR990SVR: usize = 0x990a; +pub const PCI_VENDOR_ID_AL: usize = 0x10b9; +pub const PCI_DEVICE_ID_AL_M1533: usize = 0x1533; +pub const PCI_DEVICE_ID_AL_M1535: usize = 0x1535; +pub const PCI_DEVICE_ID_AL_M1541: usize = 0x1541; +pub const PCI_DEVICE_ID_AL_M1563: usize = 0x1563; +pub const PCI_DEVICE_ID_AL_M1621: usize = 0x1621; +pub const PCI_DEVICE_ID_AL_M1631: usize = 0x1631; +pub const PCI_DEVICE_ID_AL_M1632: usize = 0x1632; +pub const PCI_DEVICE_ID_AL_M1641: usize = 0x1641; +pub const PCI_DEVICE_ID_AL_M1644: usize = 0x1644; +pub const PCI_DEVICE_ID_AL_M1647: usize = 0x1647; +pub const PCI_DEVICE_ID_AL_M1651: usize = 0x1651; +pub const PCI_DEVICE_ID_AL_M1671: usize = 0x1671; +pub const PCI_DEVICE_ID_AL_M1681: usize = 0x1681; +pub const PCI_DEVICE_ID_AL_M1683: usize = 0x1683; +pub const PCI_DEVICE_ID_AL_M1689: usize = 0x1689; +pub const PCI_DEVICE_ID_AL_M5219: usize = 0x5219; +pub const PCI_DEVICE_ID_AL_M5228: usize = 0x5228; +pub const PCI_DEVICE_ID_AL_M5229: usize = 0x5229; +pub const PCI_DEVICE_ID_AL_M5451: usize = 0x5451; +pub const PCI_DEVICE_ID_AL_M7101: usize = 0x7101; +pub const PCI_VENDOR_ID_NEOMAGIC: usize = 0x10c8; +pub const PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO: usize = 0x8005; +pub const PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO: usize = 0x8006; +pub const PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO: usize = 0x8016; +pub const PCI_VENDOR_ID_TCONRAD: usize = 0x10da; +pub const PCI_DEVICE_ID_TCONRAD_TOKENRING: usize = 0x0508; +pub const PCI_VENDOR_ID_ROHM: usize = 0x10db; +pub const PCI_VENDOR_ID_NVIDIA: usize = 0x10de; +pub const PCI_DEVICE_ID_NVIDIA_TNT: usize = 0x0020; +pub const PCI_DEVICE_ID_NVIDIA_TNT2: usize = 0x0028; +pub const PCI_DEVICE_ID_NVIDIA_UTNT2: usize = 0x0029; +pub const PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN: usize = 0x002a; +pub const PCI_DEVICE_ID_NVIDIA_VTNT2: usize = 0x002C; +pub const PCI_DEVICE_ID_NVIDIA_UVTNT2: usize = 0x002D; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS: usize = 0x0034; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE: usize = 0x0035; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA: usize = 0x0036; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2: usize = 0x003e; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA: usize = 0x0040; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6800: usize = 0x0041; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE: usize = 0x0042; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT: usize = 0x0045; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000: usize = 0x004E; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS: usize = 0x0052; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE: usize = 0x0053; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA: usize = 0x0054; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2: usize = 0x0055; +pub const PCI_DEVICE_ID_NVIDIA_CK804_AUDIO: usize = 0x0059; +pub const PCI_DEVICE_ID_NVIDIA_CK804_PCIE: usize = 0x005d; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS: usize = 0x0064; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE: usize = 0x0065; +pub const PCI_DEVICE_ID_NVIDIA_MCP2_MODEM: usize = 0x0069; +pub const PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO: usize = 0x006a; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS: usize = 0x0084; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE: usize = 0x0085; +pub const PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM: usize = 0x0089; +pub const PCI_DEVICE_ID_NVIDIA_CK8_AUDIO: usize = 0x008a; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA: usize = 0x008e; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT: usize = 0x0090; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX: usize = 0x0091; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800: usize = 0x0098; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX: usize = 0x0099; +pub const PCI_DEVICE_ID_NVIDIA_ITNT2: usize = 0x00A0; +pub const PCI_DEVICE_ID_GEFORCE_6800A: usize = 0x00c1; +pub const PCI_DEVICE_ID_GEFORCE_6800A_LE: usize = 0x00c2; +pub const PCI_DEVICE_ID_GEFORCE_GO_6800: usize = 0x00c8; +pub const PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA: usize = 0x00c9; +pub const PCI_DEVICE_ID_QUADRO_FX_GO1400: usize = 0x00cc; +pub const PCI_DEVICE_ID_QUADRO_FX_1400: usize = 0x00ce; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE3: usize = 0x00d1; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS: usize = 0x00d4; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE: usize = 0x00d5; +pub const PCI_DEVICE_ID_NVIDIA_MCP3_MODEM: usize = 0x00d9; +pub const PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO: usize = 0x00da; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE3S: usize = 0x00e1; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA: usize = 0x00e3; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS: usize = 0x00e4; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE: usize = 0x00e5; +pub const PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO: usize = 0x00ea; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2: usize = 0x00ee; +pub const PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1: usize = 0x00f0; +pub const PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1: usize = 0x00f1; +pub const PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2: usize = 0x00f2; +pub const PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1: usize = 0x00f3; +pub const PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT: usize = 0x00f9; +pub const PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280: usize = 0x00fd; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR: usize = 0x0100; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR: usize = 0x0101; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO: usize = 0x0103; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX: usize = 0x0110; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2: usize = 0x0111; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO: usize = 0x0112; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR: usize = 0x0113; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT: usize = 0x0140; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6600: usize = 0x0141; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL: usize = 0x0145; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540: usize = 0x014E; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6200: usize = 0x014F; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS: usize = 0x0150; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2: usize = 0x0151; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA: usize = 0x0152; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO: usize = 0x0153; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE: usize = 0x0161; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200: usize = 0x0164; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250: usize = 0x0166; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1: usize = 0x0167; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1: usize = 0x0168; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460: usize = 0x0170; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440: usize = 0x0171; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420: usize = 0x0172; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE: usize = 0x0173; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO: usize = 0x0174; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO: usize = 0x0175; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32: usize = 0x0176; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO: usize = 0x0177; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL: usize = 0x0178; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64: usize = 0x0179; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_200: usize = 0x017A; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL: usize = 0x017B; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL: usize = 0x017C; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16: usize = 0x017D; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X: usize = 0x0181; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X: usize = 0x0182; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X: usize = 0x0183; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000: usize = 0x0185; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO: usize = 0x0186; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO: usize = 0x0187; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL: usize = 0x0188; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC: usize = 0x0189; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS: usize = 0x018A; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL: usize = 0x018B; +pub const PCI_DEVICE_ID_NVIDIA_IGEFORCE2: usize = 0x01a0; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE: usize = 0x01a4; +pub const PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO: usize = 0x01b1; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS: usize = 0x01b4; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_IDE: usize = 0x01bc; +pub const PCI_DEVICE_ID_NVIDIA_MCP1_MODEM: usize = 0x01c1; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE2: usize = 0x01e0; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE3: usize = 0x0200; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE3_1: usize = 0x0201; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE3_2: usize = 0x0202; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_DDC: usize = 0x0203; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B: usize = 0x0211; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE: usize = 0x0212; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT: usize = 0x0215; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600: usize = 0x0250; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400: usize = 0x0251; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200: usize = 0x0253; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL: usize = 0x0258; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL: usize = 0x0259; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL: usize = 0x025B; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS: usize = 0x0264; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE: usize = 0x0265; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA: usize = 0x0266; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2: usize = 0x0267; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS: usize = 0x0368; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE: usize = 0x036E; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA: usize = 0x037E; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2: usize = 0x037F; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800: usize = 0x0280; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X: usize = 0x0281; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE: usize = 0x0282; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO: usize = 0x0286; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL: usize = 0x0288; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL: usize = 0x0289; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL: usize = 0x028C; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA: usize = 0x0301; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800: usize = 0x0302; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000: usize = 0x0308; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000: usize = 0x0309; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA: usize = 0x0311; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600: usize = 0x0312; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE: usize = 0x0314; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600: usize = 0x031A; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650: usize = 0x031B; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700: usize = 0x031C; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200: usize = 0x0320; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA: usize = 0x0321; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1: usize = 0x0322; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE: usize = 0x0323; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200: usize = 0x0324; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250: usize = 0x0325; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500: usize = 0x0326; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100: usize = 0x0327; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32: usize = 0x0328; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200: usize = 0x0329; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI: usize = 0x032A; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500: usize = 0x032B; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300: usize = 0x032C; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100: usize = 0x032D; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA: usize = 0x0330; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900: usize = 0x0331; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT: usize = 0x0332; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA: usize = 0x0333; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT: usize = 0x0334; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000: usize = 0x0338; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700: usize = 0x033F; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA: usize = 0x0341; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700: usize = 0x0342; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE: usize = 0x0343; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE: usize = 0x0344; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1: usize = 0x0347; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2: usize = 0x0348; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000: usize = 0x034C; +pub const PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100: usize = 0x034E; +pub const PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0: usize = 0x0360; +pub const PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4: usize = 0x0364; +pub const PCI_DEVICE_ID_NVIDIA_NVENET_15: usize = 0x0373; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA: usize = 0x03E7; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS: usize = 0x03EB; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE: usize = 0x03EC; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2: usize = 0x03F6; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3: usize = 0x03F7; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS: usize = 0x0446; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE: usize = 0x0448; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS: usize = 0x0542; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE: usize = 0x0560; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE: usize = 0x056C; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS: usize = 0x0752; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE: usize = 0x0759; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS: usize = 0x07D8; +pub const PCI_DEVICE_ID_NVIDIA_GEFORCE_320M: usize = 0x08A0; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS: usize = 0x0AA2; +pub const PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA: usize = 0x0D85; +pub const PCI_VENDOR_ID_IMS: usize = 0x10e0; +pub const PCI_DEVICE_ID_IMS_TT128: usize = 0x9128; +pub const PCI_DEVICE_ID_IMS_TT3D: usize = 0x9135; +pub const PCI_VENDOR_ID_AMCC: usize = 0x10e8; +pub const PCI_VENDOR_ID_AMPERE: usize = 0x1def; +pub const PCI_VENDOR_ID_INTERG: usize = 0x10ea; +pub const PCI_DEVICE_ID_INTERG_1682: usize = 0x1682; +pub const PCI_DEVICE_ID_INTERG_2000: usize = 0x2000; +pub const PCI_DEVICE_ID_INTERG_2010: usize = 0x2010; +pub const PCI_DEVICE_ID_INTERG_5000: usize = 0x5000; +pub const PCI_DEVICE_ID_INTERG_5050: usize = 0x5050; +pub const PCI_VENDOR_ID_REALTEK: usize = 0x10ec; +pub const PCI_DEVICE_ID_REALTEK_8139: usize = 0x8139; +pub const PCI_VENDOR_ID_XILINX: usize = 0x10ee; +pub const PCI_DEVICE_ID_RME_DIGI96: usize = 0x3fc0; +pub const PCI_DEVICE_ID_RME_DIGI96_8: usize = 0x3fc1; +pub const PCI_DEVICE_ID_RME_DIGI96_8_PRO: usize = 0x3fc2; +pub const PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: usize = 0x3fc3; +pub const PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP: usize = 0x3fc5; +pub const PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI: usize = 0x3fc6; +pub const PCI_VENDOR_ID_INIT: usize = 0x1101; +pub const PCI_VENDOR_ID_CREATIVE: usize = 0x1102; +pub const PCI_DEVICE_ID_CREATIVE_EMU10K1: usize = 0x0002; +pub const PCI_DEVICE_ID_CREATIVE_20K1: usize = 0x0005; +pub const PCI_DEVICE_ID_CREATIVE_20K2: usize = 0x000b; +pub const PCI_SUBDEVICE_ID_CREATIVE_SB0760: usize = 0x0024; +pub const PCI_SUBDEVICE_ID_CREATIVE_SB08801: usize = 0x0041; +pub const PCI_SUBDEVICE_ID_CREATIVE_SB08802: usize = 0x0042; +pub const PCI_SUBDEVICE_ID_CREATIVE_SB08803: usize = 0x0043; +pub const PCI_SUBDEVICE_ID_CREATIVE_SB1270: usize = 0x0062; +pub const PCI_SUBDEVICE_ID_CREATIVE_HENDRIX: usize = 0x6000; +pub const PCI_VENDOR_ID_ECTIVA: usize = 0x1102; +pub const PCI_DEVICE_ID_ECTIVA_EV1938: usize = 0x8938; +pub const PCI_VENDOR_ID_TTI: usize = 0x1103; +pub const PCI_DEVICE_ID_TTI_HPT343: usize = 0x0003; +pub const PCI_DEVICE_ID_TTI_HPT366: usize = 0x0004; +pub const PCI_DEVICE_ID_TTI_HPT372: usize = 0x0005; +pub const PCI_DEVICE_ID_TTI_HPT302: usize = 0x0006; +pub const PCI_DEVICE_ID_TTI_HPT371: usize = 0x0007; +pub const PCI_DEVICE_ID_TTI_HPT374: usize = 0x0008; +pub const PCI_DEVICE_ID_TTI_HPT372N: usize = 0x0009; +pub const PCI_VENDOR_ID_SIGMA: usize = 0x1105; +pub const PCI_VENDOR_ID_VIA: usize = 0x1106; +pub const PCI_DEVICE_ID_VIA_8763_0: usize = 0x0198; +pub const PCI_DEVICE_ID_VIA_8380_0: usize = 0x0204; +pub const PCI_DEVICE_ID_VIA_3238_0: usize = 0x0238; +pub const PCI_DEVICE_ID_VIA_PT880: usize = 0x0258; +pub const PCI_DEVICE_ID_VIA_PT880ULTRA: usize = 0x0308; +pub const PCI_DEVICE_ID_VIA_PX8X0_0: usize = 0x0259; +pub const PCI_DEVICE_ID_VIA_3269_0: usize = 0x0269; +pub const PCI_DEVICE_ID_VIA_K8T800PRO_0: usize = 0x0282; +pub const PCI_DEVICE_ID_VIA_3296_0: usize = 0x0296; +pub const PCI_DEVICE_ID_VIA_8363_0: usize = 0x0305; +pub const PCI_DEVICE_ID_VIA_P4M800CE: usize = 0x0314; +pub const PCI_DEVICE_ID_VIA_P4M890: usize = 0x0327; +pub const PCI_DEVICE_ID_VIA_VT3324: usize = 0x0324; +pub const PCI_DEVICE_ID_VIA_VT3336: usize = 0x0336; +pub const PCI_DEVICE_ID_VIA_VT3351: usize = 0x0351; +pub const PCI_DEVICE_ID_VIA_VT3364: usize = 0x0364; +pub const PCI_DEVICE_ID_VIA_8371_0: usize = 0x0391; +pub const PCI_DEVICE_ID_VIA_6415: usize = 0x0415; +pub const PCI_DEVICE_ID_VIA_8501_0: usize = 0x0501; +pub const PCI_DEVICE_ID_VIA_82C561: usize = 0x0561; +pub const PCI_DEVICE_ID_VIA_82C586_1: usize = 0x0571; +pub const PCI_DEVICE_ID_VIA_82C576: usize = 0x0576; +pub const PCI_DEVICE_ID_VIA_82C586_0: usize = 0x0586; +pub const PCI_DEVICE_ID_VIA_82C596: usize = 0x0596; +pub const PCI_DEVICE_ID_VIA_82C597_0: usize = 0x0597; +pub const PCI_DEVICE_ID_VIA_82C598_0: usize = 0x0598; +pub const PCI_DEVICE_ID_VIA_8601_0: usize = 0x0601; +pub const PCI_DEVICE_ID_VIA_8605_0: usize = 0x0605; +pub const PCI_DEVICE_ID_VIA_82C686: usize = 0x0686; +pub const PCI_DEVICE_ID_VIA_82C691_0: usize = 0x0691; +pub const PCI_DEVICE_ID_VIA_82C576_1: usize = 0x1571; +pub const PCI_DEVICE_ID_VIA_82C586_2: usize = 0x3038; +pub const PCI_DEVICE_ID_VIA_82C586_3: usize = 0x3040; +pub const PCI_DEVICE_ID_VIA_82C596_3: usize = 0x3050; +pub const PCI_DEVICE_ID_VIA_82C596B_3: usize = 0x3051; +pub const PCI_DEVICE_ID_VIA_82C686_4: usize = 0x3057; +pub const PCI_DEVICE_ID_VIA_82C686_5: usize = 0x3058; +pub const PCI_DEVICE_ID_VIA_8233_5: usize = 0x3059; +pub const PCI_DEVICE_ID_VIA_8233_0: usize = 0x3074; +pub const PCI_DEVICE_ID_VIA_8633_0: usize = 0x3091; +pub const PCI_DEVICE_ID_VIA_8367_0: usize = 0x3099; +pub const PCI_DEVICE_ID_VIA_8653_0: usize = 0x3101; +pub const PCI_DEVICE_ID_VIA_8622: usize = 0x3102; +pub const PCI_DEVICE_ID_VIA_8235_USB_2: usize = 0x3104; +pub const PCI_DEVICE_ID_VIA_8233C_0: usize = 0x3109; +pub const PCI_DEVICE_ID_VIA_8361: usize = 0x3112; +pub const PCI_DEVICE_ID_VIA_XM266: usize = 0x3116; +pub const PCI_DEVICE_ID_VIA_612X: usize = 0x3119; +pub const PCI_DEVICE_ID_VIA_862X_0: usize = 0x3123; +pub const PCI_DEVICE_ID_VIA_8753_0: usize = 0x3128; +pub const PCI_DEVICE_ID_VIA_8233A: usize = 0x3147; +pub const PCI_DEVICE_ID_VIA_8703_51_0: usize = 0x3148; +pub const PCI_DEVICE_ID_VIA_8237_SATA: usize = 0x3149; +pub const PCI_DEVICE_ID_VIA_XN266: usize = 0x3156; +pub const PCI_DEVICE_ID_VIA_6410: usize = 0x3164; +pub const PCI_DEVICE_ID_VIA_8754C_0: usize = 0x3168; +pub const PCI_DEVICE_ID_VIA_8235: usize = 0x3177; +pub const PCI_DEVICE_ID_VIA_8385_0: usize = 0x3188; +pub const PCI_DEVICE_ID_VIA_8377_0: usize = 0x3189; +pub const PCI_DEVICE_ID_VIA_8378_0: usize = 0x3205; +pub const PCI_DEVICE_ID_VIA_8783_0: usize = 0x3208; +pub const PCI_DEVICE_ID_VIA_8237: usize = 0x3227; +pub const PCI_DEVICE_ID_VIA_8251: usize = 0x3287; +pub const PCI_DEVICE_ID_VIA_8261: usize = 0x3402; +pub const PCI_DEVICE_ID_VIA_8237A: usize = 0x3337; +pub const PCI_DEVICE_ID_VIA_8237S: usize = 0x3372; +pub const PCI_DEVICE_ID_VIA_SATA_EIDE: usize = 0x5324; +pub const PCI_DEVICE_ID_VIA_8231: usize = 0x8231; +pub const PCI_DEVICE_ID_VIA_8231_4: usize = 0x8235; +pub const PCI_DEVICE_ID_VIA_8365_1: usize = 0x8305; +pub const PCI_DEVICE_ID_VIA_CX700: usize = 0x8324; +pub const PCI_DEVICE_ID_VIA_CX700_IDE: usize = 0x0581; +pub const PCI_DEVICE_ID_VIA_VX800: usize = 0x8353; +pub const PCI_DEVICE_ID_VIA_VX855: usize = 0x8409; +pub const PCI_DEVICE_ID_VIA_VX900: usize = 0x8410; +pub const PCI_DEVICE_ID_VIA_8371_1: usize = 0x8391; +pub const PCI_DEVICE_ID_VIA_82C598_1: usize = 0x8598; +pub const PCI_DEVICE_ID_VIA_838X_1: usize = 0xB188; +pub const PCI_DEVICE_ID_VIA_83_87XX_1: usize = 0xB198; +pub const PCI_DEVICE_ID_VIA_VX855_IDE: usize = 0xC409; +pub const PCI_DEVICE_ID_VIA_ANON: usize = 0xFFFF; +pub const PCI_VENDOR_ID_SIEMENS: usize = 0x110A; +pub const PCI_DEVICE_ID_SIEMENS_DSCC4: usize = 0x2102; +pub const PCI_VENDOR_ID_VORTEX: usize = 0x1119; +pub const PCI_DEVICE_ID_VORTEX_GDT60x0: usize = 0x0000; +pub const PCI_DEVICE_ID_VORTEX_GDT6000B: usize = 0x0001; +pub const PCI_DEVICE_ID_VORTEX_GDT6x10: usize = 0x0002; +pub const PCI_DEVICE_ID_VORTEX_GDT6x20: usize = 0x0003; +pub const PCI_DEVICE_ID_VORTEX_GDT6530: usize = 0x0004; +pub const PCI_DEVICE_ID_VORTEX_GDT6550: usize = 0x0005; +pub const PCI_DEVICE_ID_VORTEX_GDT6x17: usize = 0x0006; +pub const PCI_DEVICE_ID_VORTEX_GDT6x27: usize = 0x0007; +pub const PCI_DEVICE_ID_VORTEX_GDT6537: usize = 0x0008; +pub const PCI_DEVICE_ID_VORTEX_GDT6557: usize = 0x0009; +pub const PCI_DEVICE_ID_VORTEX_GDT6x15: usize = 0x000a; +pub const PCI_DEVICE_ID_VORTEX_GDT6x25: usize = 0x000b; +pub const PCI_DEVICE_ID_VORTEX_GDT6535: usize = 0x000c; +pub const PCI_DEVICE_ID_VORTEX_GDT6555: usize = 0x000d; +pub const PCI_DEVICE_ID_VORTEX_GDT6x17RP: usize = 0x0100; +pub const PCI_DEVICE_ID_VORTEX_GDT6x27RP: usize = 0x0101; +pub const PCI_DEVICE_ID_VORTEX_GDT6537RP: usize = 0x0102; +pub const PCI_DEVICE_ID_VORTEX_GDT6557RP: usize = 0x0103; +pub const PCI_DEVICE_ID_VORTEX_GDT6x11RP: usize = 0x0104; +pub const PCI_DEVICE_ID_VORTEX_GDT6x21RP: usize = 0x0105; +pub const PCI_VENDOR_ID_EF: usize = 0x111a; +pub const PCI_DEVICE_ID_EF_ATM_FPGA: usize = 0x0000; +pub const PCI_DEVICE_ID_EF_ATM_ASIC: usize = 0x0002; +pub const PCI_DEVICE_ID_EF_ATM_LANAI2: usize = 0x0003; +pub const PCI_DEVICE_ID_EF_ATM_LANAIHB: usize = 0x0005; +pub const PCI_VENDOR_ID_IDT: usize = 0x111d; +pub const PCI_DEVICE_ID_IDT_IDT77201: usize = 0x0001; +pub const PCI_VENDOR_ID_FORE: usize = 0x1127; +pub const PCI_DEVICE_ID_FORE_PCA200E: usize = 0x0300; +pub const PCI_VENDOR_ID_PHILIPS: usize = 0x1131; +pub const PCI_DEVICE_ID_PHILIPS_SAA7146: usize = 0x7146; +pub const PCI_DEVICE_ID_PHILIPS_SAA9730: usize = 0x9730; +pub const PCI_VENDOR_ID_EICON: usize = 0x1133; +pub const PCI_DEVICE_ID_EICON_DIVA20: usize = 0xe002; +pub const PCI_DEVICE_ID_EICON_DIVA20_U: usize = 0xe004; +pub const PCI_DEVICE_ID_EICON_DIVA201: usize = 0xe005; +pub const PCI_DEVICE_ID_EICON_DIVA202: usize = 0xe00b; +pub const PCI_DEVICE_ID_EICON_MAESTRA: usize = 0xe010; +pub const PCI_DEVICE_ID_EICON_MAESTRAQ: usize = 0xe012; +pub const PCI_DEVICE_ID_EICON_MAESTRAQ_U: usize = 0xe013; +pub const PCI_DEVICE_ID_EICON_MAESTRAP: usize = 0xe014; +pub const PCI_VENDOR_ID_CISCO: usize = 0x1137; +pub const PCI_VENDOR_ID_ZIATECH: usize = 0x1138; +pub const PCI_DEVICE_ID_ZIATECH_5550_HC: usize = 0x5550; +pub const PCI_VENDOR_ID_SYSKONNECT: usize = 0x1148; +pub const PCI_DEVICE_ID_SYSKONNECT_TR: usize = 0x4200; +pub const PCI_DEVICE_ID_SYSKONNECT_GE: usize = 0x4300; +pub const PCI_DEVICE_ID_SYSKONNECT_YU: usize = 0x4320; +pub const PCI_DEVICE_ID_SYSKONNECT_9DXX: usize = 0x4400; +pub const PCI_DEVICE_ID_SYSKONNECT_9MXX: usize = 0x4500; +pub const PCI_VENDOR_ID_DIGI: usize = 0x114f; +pub const PCI_DEVICE_ID_DIGI_DF_M_IOM2_E: usize = 0x0070; +pub const PCI_DEVICE_ID_DIGI_DF_M_E: usize = 0x0071; +pub const PCI_DEVICE_ID_DIGI_DF_M_IOM2_A: usize = 0x0072; +pub const PCI_DEVICE_ID_DIGI_DF_M_A: usize = 0x0073; +pub const PCI_DEVICE_ID_DIGI_NEO_8: usize = 0x00B1; +pub const PCI_DEVICE_ID_NEO_2DB9: usize = 0x00C8; +pub const PCI_DEVICE_ID_NEO_2DB9PRI: usize = 0x00C9; +pub const PCI_DEVICE_ID_NEO_2RJ45: usize = 0x00CA; +pub const PCI_DEVICE_ID_NEO_2RJ45PRI: usize = 0x00CB; +pub const PCIE_DEVICE_ID_NEO_4_IBM: usize = 0x00F4; +pub const PCI_VENDOR_ID_XIRCOM: usize = 0x115d; +pub const PCI_DEVICE_ID_XIRCOM_RBM56G: usize = 0x0101; +pub const PCI_DEVICE_ID_XIRCOM_X3201_MDM: usize = 0x0103; +pub const PCI_VENDOR_ID_SERVERWORKS: usize = 0x1166; +pub const PCI_DEVICE_ID_SERVERWORKS_HE: usize = 0x0008; +pub const PCI_DEVICE_ID_SERVERWORKS_LE: usize = 0x0009; +pub const PCI_DEVICE_ID_SERVERWORKS_GCNB_LE: usize = 0x0017; +pub const PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB: usize = 0x0036; +pub const PCI_DEVICE_ID_SERVERWORKS_EPB: usize = 0x0103; +pub const PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE: usize = 0x0132; +pub const PCI_DEVICE_ID_SERVERWORKS_OSB4: usize = 0x0200; +pub const PCI_DEVICE_ID_SERVERWORKS_CSB5: usize = 0x0201; +pub const PCI_DEVICE_ID_SERVERWORKS_CSB6: usize = 0x0203; +pub const PCI_DEVICE_ID_SERVERWORKS_HT1000SB: usize = 0x0205; +pub const PCI_DEVICE_ID_SERVERWORKS_OSB4IDE: usize = 0x0211; +pub const PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: usize = 0x0212; +pub const PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: usize = 0x0213; +pub const PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: usize = 0x0214; +pub const PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: usize = 0x0217; +pub const PCI_DEVICE_ID_SERVERWORKS_CSB6LPC: usize = 0x0227; +pub const PCI_DEVICE_ID_SERVERWORKS_HT1100LD: usize = 0x0408; +pub const PCI_VENDOR_ID_ALTERA: usize = 0x1172; +pub const PCI_VENDOR_ID_SBE: usize = 0x1176; +pub const PCI_DEVICE_ID_SBE_WANXL100: usize = 0x0301; +pub const PCI_DEVICE_ID_SBE_WANXL200: usize = 0x0302; +pub const PCI_DEVICE_ID_SBE_WANXL400: usize = 0x0104; +pub const PCI_SUBDEVICE_ID_SBE_T3E3: usize = 0x0009; +pub const PCI_SUBDEVICE_ID_SBE_2T3E3_P0: usize = 0x0901; +pub const PCI_SUBDEVICE_ID_SBE_2T3E3_P1: usize = 0x0902; +pub const PCI_VENDOR_ID_TOSHIBA: usize = 0x1179; +pub const PCI_DEVICE_ID_TOSHIBA_PICCOLO_1: usize = 0x0101; +pub const PCI_DEVICE_ID_TOSHIBA_PICCOLO_2: usize = 0x0102; +pub const PCI_DEVICE_ID_TOSHIBA_PICCOLO_3: usize = 0x0103; +pub const PCI_DEVICE_ID_TOSHIBA_PICCOLO_5: usize = 0x0105; +pub const PCI_DEVICE_ID_TOSHIBA_TOPIC95: usize = 0x060a; +pub const PCI_DEVICE_ID_TOSHIBA_TOPIC97: usize = 0x060f; +pub const PCI_DEVICE_ID_TOSHIBA_TOPIC100: usize = 0x0617; +pub const PCI_VENDOR_ID_TOSHIBA_2: usize = 0x102f; +pub const PCI_DEVICE_ID_TOSHIBA_TC35815CF: usize = 0x0030; +pub const PCI_DEVICE_ID_TOSHIBA_TC35815_NWU: usize = 0x0031; +pub const PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939: usize = 0x0032; +pub const PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE: usize = 0x0105; +pub const PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC: usize = 0x0108; +pub const PCI_DEVICE_ID_TOSHIBA_SPIDER_NET: usize = 0x01b3; +pub const PCI_VENDOR_ID_ATTO: usize = 0x117c; +pub const PCI_VENDOR_ID_RICOH: usize = 0x1180; +pub const PCI_DEVICE_ID_RICOH_RL5C465: usize = 0x0465; +pub const PCI_DEVICE_ID_RICOH_RL5C466: usize = 0x0466; +pub const PCI_DEVICE_ID_RICOH_RL5C475: usize = 0x0475; +pub const PCI_DEVICE_ID_RICOH_RL5C476: usize = 0x0476; +pub const PCI_DEVICE_ID_RICOH_RL5C478: usize = 0x0478; +pub const PCI_DEVICE_ID_RICOH_R5C822: usize = 0x0822; +pub const PCI_DEVICE_ID_RICOH_R5CE822: usize = 0xe822; +pub const PCI_DEVICE_ID_RICOH_R5CE823: usize = 0xe823; +pub const PCI_DEVICE_ID_RICOH_R5C832: usize = 0x0832; +pub const PCI_DEVICE_ID_RICOH_R5C843: usize = 0x0843; +pub const PCI_VENDOR_ID_DLINK: usize = 0x1186; +pub const PCI_DEVICE_ID_DLINK_DGE510T: usize = 0x4c00; +pub const PCI_VENDOR_ID_ARTOP: usize = 0x1191; +pub const PCI_DEVICE_ID_ARTOP_ATP850UF: usize = 0x0005; +pub const PCI_DEVICE_ID_ARTOP_ATP860: usize = 0x0006; +pub const PCI_DEVICE_ID_ARTOP_ATP860R: usize = 0x0007; +pub const PCI_DEVICE_ID_ARTOP_ATP865: usize = 0x0008; +pub const PCI_DEVICE_ID_ARTOP_ATP865R: usize = 0x0009; +pub const PCI_DEVICE_ID_ARTOP_ATP867A: usize = 0x000A; +pub const PCI_DEVICE_ID_ARTOP_ATP867B: usize = 0x000B; +pub const PCI_DEVICE_ID_ARTOP_AEC7610: usize = 0x8002; +pub const PCI_DEVICE_ID_ARTOP_AEC7612UW: usize = 0x8010; +pub const PCI_DEVICE_ID_ARTOP_AEC7612U: usize = 0x8020; +pub const PCI_DEVICE_ID_ARTOP_AEC7612S: usize = 0x8030; +pub const PCI_DEVICE_ID_ARTOP_AEC7612D: usize = 0x8040; +pub const PCI_DEVICE_ID_ARTOP_AEC7612SUW: usize = 0x8050; +pub const PCI_DEVICE_ID_ARTOP_8060: usize = 0x8060; +pub const PCI_VENDOR_ID_ZEITNET: usize = 0x1193; +pub const PCI_DEVICE_ID_ZEITNET_1221: usize = 0x0001; +pub const PCI_DEVICE_ID_ZEITNET_1225: usize = 0x0002; +pub const PCI_VENDOR_ID_FUJITSU_ME: usize = 0x119e; +pub const PCI_DEVICE_ID_FUJITSU_FS155: usize = 0x0001; +pub const PCI_DEVICE_ID_FUJITSU_FS50: usize = 0x0003; +pub const PCI_SUBVENDOR_ID_KEYSPAN: usize = 0x11a9; +pub const PCI_SUBDEVICE_ID_KEYSPAN_SX2: usize = 0x5334; +pub const PCI_VENDOR_ID_MARVELL: usize = 0x11ab; +pub const PCI_VENDOR_ID_MARVELL_EXT: usize = 0x1b4b; +pub const PCI_DEVICE_ID_MARVELL_GT64111: usize = 0x4146; +pub const PCI_DEVICE_ID_MARVELL_GT64260: usize = 0x6430; +pub const PCI_DEVICE_ID_MARVELL_MV64360: usize = 0x6460; +pub const PCI_DEVICE_ID_MARVELL_MV64460: usize = 0x6480; +pub const PCI_DEVICE_ID_MARVELL_88ALP01_NAND: usize = 0x4100; +pub const PCI_DEVICE_ID_MARVELL_88ALP01_SD: usize = 0x4101; +pub const PCI_DEVICE_ID_MARVELL_88ALP01_CCIC: usize = 0x4102; +pub const PCI_VENDOR_ID_V3: usize = 0x11b0; +pub const PCI_DEVICE_ID_V3_V960: usize = 0x0001; +pub const PCI_DEVICE_ID_V3_V351: usize = 0x0002; +pub const PCI_VENDOR_ID_ATT: usize = 0x11c1; +pub const PCI_DEVICE_ID_ATT_VENUS_MODEM: usize = 0x480; +pub const PCI_VENDOR_ID_SPECIALIX: usize = 0x11cb; +pub const PCI_SUBDEVICE_ID_SPECIALIX_SPEED4: usize = 0xa004; +pub const PCI_VENDOR_ID_ANALOG_DEVICES: usize = 0x11d4; +pub const PCI_DEVICE_ID_AD1889JS: usize = 0x1889; +pub const PCI_DEVICE_ID_SEGA_BBA: usize = 0x1234; +pub const PCI_VENDOR_ID_ZORAN: usize = 0x11de; +pub const PCI_DEVICE_ID_ZORAN_36057: usize = 0x6057; +pub const PCI_DEVICE_ID_ZORAN_36120: usize = 0x6120; +pub const PCI_VENDOR_ID_COMPEX: usize = 0x11f6; +pub const PCI_DEVICE_ID_COMPEX_ENET100VG4: usize = 0x0112; +pub const PCI_VENDOR_ID_PMC_Sierra: usize = 0x11f8; +pub const PCI_VENDOR_ID_MICROSEMI: usize = 0x11f8; +pub const PCI_VENDOR_ID_RP: usize = 0x11fe; +pub const PCI_DEVICE_ID_RP32INTF: usize = 0x0001; +pub const PCI_DEVICE_ID_RP8INTF: usize = 0x0002; +pub const PCI_DEVICE_ID_RP16INTF: usize = 0x0003; +pub const PCI_DEVICE_ID_RP4QUAD: usize = 0x0004; +pub const PCI_DEVICE_ID_RP8OCTA: usize = 0x0005; +pub const PCI_DEVICE_ID_RP8J: usize = 0x0006; +pub const PCI_DEVICE_ID_RP4J: usize = 0x0007; +pub const PCI_DEVICE_ID_RP8SNI: usize = 0x0008; +pub const PCI_DEVICE_ID_RP16SNI: usize = 0x0009; +pub const PCI_DEVICE_ID_RPP4: usize = 0x000A; +pub const PCI_DEVICE_ID_RPP8: usize = 0x000B; +pub const PCI_DEVICE_ID_RP4M: usize = 0x000D; +pub const PCI_DEVICE_ID_RP2_232: usize = 0x000E; +pub const PCI_DEVICE_ID_RP2_422: usize = 0x000F; +pub const PCI_DEVICE_ID_URP32INTF: usize = 0x0801; +pub const PCI_DEVICE_ID_URP8INTF: usize = 0x0802; +pub const PCI_DEVICE_ID_URP16INTF: usize = 0x0803; +pub const PCI_DEVICE_ID_URP8OCTA: usize = 0x0805; +pub const PCI_DEVICE_ID_UPCI_RM3_8PORT: usize = 0x080C; +pub const PCI_DEVICE_ID_UPCI_RM3_4PORT: usize = 0x080D; +pub const PCI_DEVICE_ID_CRP16INTF: usize = 0x0903; +pub const PCI_VENDOR_ID_CYCLADES: usize = 0x120e; +pub const PCI_DEVICE_ID_CYCLOM_Y_Lo: usize = 0x0100; +pub const PCI_DEVICE_ID_CYCLOM_Y_Hi: usize = 0x0101; +pub const PCI_DEVICE_ID_CYCLOM_4Y_Lo: usize = 0x0102; +pub const PCI_DEVICE_ID_CYCLOM_4Y_Hi: usize = 0x0103; +pub const PCI_DEVICE_ID_CYCLOM_8Y_Lo: usize = 0x0104; +pub const PCI_DEVICE_ID_CYCLOM_8Y_Hi: usize = 0x0105; +pub const PCI_DEVICE_ID_CYCLOM_Z_Lo: usize = 0x0200; +pub const PCI_DEVICE_ID_CYCLOM_Z_Hi: usize = 0x0201; +pub const PCI_DEVICE_ID_PC300_RX_2: usize = 0x0300; +pub const PCI_DEVICE_ID_PC300_RX_1: usize = 0x0301; +pub const PCI_DEVICE_ID_PC300_TE_2: usize = 0x0310; +pub const PCI_DEVICE_ID_PC300_TE_1: usize = 0x0311; +pub const PCI_DEVICE_ID_PC300_TE_M_2: usize = 0x0320; +pub const PCI_DEVICE_ID_PC300_TE_M_1: usize = 0x0321; +pub const PCI_VENDOR_ID_ESSENTIAL: usize = 0x120f; +pub const PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER: usize = 0x0001; +pub const PCI_VENDOR_ID_O2: usize = 0x1217; +pub const PCI_DEVICE_ID_O2_6729: usize = 0x6729; +pub const PCI_DEVICE_ID_O2_6730: usize = 0x673a; +pub const PCI_DEVICE_ID_O2_6832: usize = 0x6832; +pub const PCI_DEVICE_ID_O2_6836: usize = 0x6836; +pub const PCI_DEVICE_ID_O2_6812: usize = 0x6872; +pub const PCI_DEVICE_ID_O2_6933: usize = 0x6933; +pub const PCI_DEVICE_ID_O2_8120: usize = 0x8120; +pub const PCI_DEVICE_ID_O2_8220: usize = 0x8220; +pub const PCI_DEVICE_ID_O2_8221: usize = 0x8221; +pub const PCI_DEVICE_ID_O2_8320: usize = 0x8320; +pub const PCI_DEVICE_ID_O2_8321: usize = 0x8321; +pub const PCI_VENDOR_ID_3DFX: usize = 0x121a; +pub const PCI_DEVICE_ID_3DFX_VOODOO: usize = 0x0001; +pub const PCI_DEVICE_ID_3DFX_VOODOO2: usize = 0x0002; +pub const PCI_DEVICE_ID_3DFX_BANSHEE: usize = 0x0003; +pub const PCI_DEVICE_ID_3DFX_VOODOO3: usize = 0x0005; +pub const PCI_DEVICE_ID_3DFX_VOODOO5: usize = 0x0009; +pub const PCI_VENDOR_ID_AVM: usize = 0x1244; +pub const PCI_DEVICE_ID_AVM_B1: usize = 0x0700; +pub const PCI_DEVICE_ID_AVM_C4: usize = 0x0800; +pub const PCI_DEVICE_ID_AVM_A1: usize = 0x0a00; +pub const PCI_DEVICE_ID_AVM_A1_V2: usize = 0x0e00; +pub const PCI_DEVICE_ID_AVM_C2: usize = 0x1100; +pub const PCI_DEVICE_ID_AVM_T1: usize = 0x1200; +pub const PCI_VENDOR_ID_STALLION: usize = 0x124d; +pub const PCI_VENDOR_ID_AT: usize = 0x1259; +pub const PCI_SUBDEVICE_ID_AT_2700FX: usize = 0x2701; +pub const PCI_SUBDEVICE_ID_AT_2701FX: usize = 0x2703; +pub const PCI_VENDOR_ID_ESS: usize = 0x125d; +pub const PCI_DEVICE_ID_ESS_ESS1968: usize = 0x1968; +pub const PCI_DEVICE_ID_ESS_ESS1978: usize = 0x1978; +pub const PCI_DEVICE_ID_ESS_ALLEGRO_1: usize = 0x1988; +pub const PCI_DEVICE_ID_ESS_ALLEGRO: usize = 0x1989; +pub const PCI_DEVICE_ID_ESS_CANYON3D_2LE: usize = 0x1990; +pub const PCI_DEVICE_ID_ESS_CANYON3D_2: usize = 0x1992; +pub const PCI_DEVICE_ID_ESS_MAESTRO3: usize = 0x1998; +pub const PCI_DEVICE_ID_ESS_MAESTRO3_1: usize = 0x1999; +pub const PCI_DEVICE_ID_ESS_MAESTRO3_HW: usize = 0x199a; +pub const PCI_DEVICE_ID_ESS_MAESTRO3_2: usize = 0x199b; +pub const PCI_VENDOR_ID_SATSAGEM: usize = 0x1267; +pub const PCI_DEVICE_ID_SATSAGEM_NICCY: usize = 0x1016; +pub const PCI_VENDOR_ID_ENSONIQ: usize = 0x1274; +pub const PCI_DEVICE_ID_ENSONIQ_CT5880: usize = 0x5880; +pub const PCI_DEVICE_ID_ENSONIQ_ES1370: usize = 0x5000; +pub const PCI_DEVICE_ID_ENSONIQ_ES1371: usize = 0x1371; +pub const PCI_VENDOR_ID_TRANSMETA: usize = 0x1279; +pub const PCI_DEVICE_ID_EFFICEON: usize = 0x0060; +pub const PCI_VENDOR_ID_ROCKWELL: usize = 0x127A; +pub const PCI_VENDOR_ID_ITE: usize = 0x1283; +pub const PCI_DEVICE_ID_ITE_8172: usize = 0x8172; +pub const PCI_DEVICE_ID_ITE_8211: usize = 0x8211; +pub const PCI_DEVICE_ID_ITE_8212: usize = 0x8212; +pub const PCI_DEVICE_ID_ITE_8213: usize = 0x8213; +pub const PCI_DEVICE_ID_ITE_8152: usize = 0x8152; +pub const PCI_DEVICE_ID_ITE_8872: usize = 0x8872; +pub const PCI_DEVICE_ID_ITE_IT8330G_0: usize = 0xe886; +pub const PCI_DEVICE_ID_ESS_ESS0100: usize = 0x0100; +pub const PCI_VENDOR_ID_ALTEON: usize = 0x12ae; +pub const PCI_SUBVENDOR_ID_CONNECT_TECH: usize = 0x12c4; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232: usize = 0x0001; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232: usize = 0x0002; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232: usize = 0x0003; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485: usize = 0x0004; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4: usize = 0x0005; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485: usize = 0x0006; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2: usize = 0x0007; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485: usize = 0x0008; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6: usize = 0x0009; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1: usize = 0x000A; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1: usize = 0x000B; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ: usize = 0x000C; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM: usize = 0x000D; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI: usize = 0x0100; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2: usize = 0x0201; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4: usize = 0x0202; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232: usize = 0x0300; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232: usize = 0x0301; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232: usize = 0x0302; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1: usize = 0x0310; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2: usize = 0x0311; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4: usize = 0x0312; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2: usize = 0x0320; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4: usize = 0x0321; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8: usize = 0x0322; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485: usize = 0x0330; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485: usize = 0x0331; +pub const PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485: usize = 0x0332; +pub const PCI_VENDOR_ID_NVIDIA_SGS: usize = 0x12d2; +pub const PCI_DEVICE_ID_NVIDIA_SGS_RIVA128: usize = 0x0018; +pub const PCI_VENDOR_ID_PERICOM: usize = 0x12D8; +pub const PCI_DEVICE_ID_PERICOM_PI7C9X7951: usize = 0x7951; +pub const PCI_DEVICE_ID_PERICOM_PI7C9X7952: usize = 0x7952; +pub const PCI_DEVICE_ID_PERICOM_PI7C9X7954: usize = 0x7954; +pub const PCI_DEVICE_ID_PERICOM_PI7C9X7958: usize = 0x7958; +pub const PCI_SUBVENDOR_ID_CHASE_PCIFAST: usize = 0x12E0; +pub const PCI_SUBDEVICE_ID_CHASE_PCIFAST4: usize = 0x0031; +pub const PCI_SUBDEVICE_ID_CHASE_PCIFAST8: usize = 0x0021; +pub const PCI_SUBDEVICE_ID_CHASE_PCIFAST16: usize = 0x0011; +pub const PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC: usize = 0x0041; +pub const PCI_SUBVENDOR_ID_CHASE_PCIRAS: usize = 0x124D; +pub const PCI_SUBDEVICE_ID_CHASE_PCIRAS4: usize = 0xF001; +pub const PCI_SUBDEVICE_ID_CHASE_PCIRAS8: usize = 0xF010; +pub const PCI_VENDOR_ID_AUREAL: usize = 0x12eb; +pub const PCI_DEVICE_ID_AUREAL_VORTEX_1: usize = 0x0001; +pub const PCI_DEVICE_ID_AUREAL_VORTEX_2: usize = 0x0002; +pub const PCI_DEVICE_ID_AUREAL_ADVANTAGE: usize = 0x0003; +pub const PCI_VENDOR_ID_ELECTRONICDESIGNGMBH: usize = 0x12f8; +pub const PCI_DEVICE_ID_LML_33R10: usize = 0x8a02; +pub const PCI_VENDOR_ID_ESDGMBH: usize = 0x12fe; +pub const PCI_DEVICE_ID_ESDGMBH_CPCIASIO4: usize = 0x0111; +pub const PCI_VENDOR_ID_CB: usize = 0x1307; +pub const PCI_VENDOR_ID_SIIG: usize = 0x131f; +pub const PCI_SUBVENDOR_ID_SIIG: usize = 0x131f; +pub const PCI_DEVICE_ID_SIIG_1S_10x_550: usize = 0x1000; +pub const PCI_DEVICE_ID_SIIG_1S_10x_650: usize = 0x1001; +pub const PCI_DEVICE_ID_SIIG_1S_10x_850: usize = 0x1002; +pub const PCI_DEVICE_ID_SIIG_1S1P_10x_550: usize = 0x1010; +pub const PCI_DEVICE_ID_SIIG_1S1P_10x_650: usize = 0x1011; +pub const PCI_DEVICE_ID_SIIG_1S1P_10x_850: usize = 0x1012; +pub const PCI_DEVICE_ID_SIIG_1P_10x: usize = 0x1020; +pub const PCI_DEVICE_ID_SIIG_2P_10x: usize = 0x1021; +pub const PCI_DEVICE_ID_SIIG_2S_10x_550: usize = 0x1030; +pub const PCI_DEVICE_ID_SIIG_2S_10x_650: usize = 0x1031; +pub const PCI_DEVICE_ID_SIIG_2S_10x_850: usize = 0x1032; +pub const PCI_DEVICE_ID_SIIG_2S1P_10x_550: usize = 0x1034; +pub const PCI_DEVICE_ID_SIIG_2S1P_10x_650: usize = 0x1035; +pub const PCI_DEVICE_ID_SIIG_2S1P_10x_850: usize = 0x1036; +pub const PCI_DEVICE_ID_SIIG_4S_10x_550: usize = 0x1050; +pub const PCI_DEVICE_ID_SIIG_4S_10x_650: usize = 0x1051; +pub const PCI_DEVICE_ID_SIIG_4S_10x_850: usize = 0x1052; +pub const PCI_DEVICE_ID_SIIG_1S_20x_550: usize = 0x2000; +pub const PCI_DEVICE_ID_SIIG_1S_20x_650: usize = 0x2001; +pub const PCI_DEVICE_ID_SIIG_1S_20x_850: usize = 0x2002; +pub const PCI_DEVICE_ID_SIIG_1P_20x: usize = 0x2020; +pub const PCI_DEVICE_ID_SIIG_2P_20x: usize = 0x2021; +pub const PCI_DEVICE_ID_SIIG_2S_20x_550: usize = 0x2030; +pub const PCI_DEVICE_ID_SIIG_2S_20x_650: usize = 0x2031; +pub const PCI_DEVICE_ID_SIIG_2S_20x_850: usize = 0x2032; +pub const PCI_DEVICE_ID_SIIG_2P1S_20x_550: usize = 0x2040; +pub const PCI_DEVICE_ID_SIIG_2P1S_20x_650: usize = 0x2041; +pub const PCI_DEVICE_ID_SIIG_2P1S_20x_850: usize = 0x2042; +pub const PCI_DEVICE_ID_SIIG_1S1P_20x_550: usize = 0x2010; +pub const PCI_DEVICE_ID_SIIG_1S1P_20x_650: usize = 0x2011; +pub const PCI_DEVICE_ID_SIIG_1S1P_20x_850: usize = 0x2012; +pub const PCI_DEVICE_ID_SIIG_4S_20x_550: usize = 0x2050; +pub const PCI_DEVICE_ID_SIIG_4S_20x_650: usize = 0x2051; +pub const PCI_DEVICE_ID_SIIG_4S_20x_850: usize = 0x2052; +pub const PCI_DEVICE_ID_SIIG_2S1P_20x_550: usize = 0x2060; +pub const PCI_DEVICE_ID_SIIG_2S1P_20x_650: usize = 0x2061; +pub const PCI_DEVICE_ID_SIIG_2S1P_20x_850: usize = 0x2062; +pub const PCI_DEVICE_ID_SIIG_8S_20x_550: usize = 0x2080; +pub const PCI_DEVICE_ID_SIIG_8S_20x_650: usize = 0x2081; +pub const PCI_DEVICE_ID_SIIG_8S_20x_850: usize = 0x2082; +pub const PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL: usize = 0x2050; +pub const PCI_VENDOR_ID_RADISYS: usize = 0x1331; +pub const PCI_VENDOR_ID_MICRO_MEMORY: usize = 0x1332; +pub const PCI_DEVICE_ID_MICRO_MEMORY_5415CN: usize = 0x5415; +pub const PCI_DEVICE_ID_MICRO_MEMORY_5425CN: usize = 0x5425; +pub const PCI_DEVICE_ID_MICRO_MEMORY_6155: usize = 0x6155; +pub const PCI_VENDOR_ID_DOMEX: usize = 0x134a; +pub const PCI_DEVICE_ID_DOMEX_DMX3191D: usize = 0x0001; +pub const PCI_VENDOR_ID_INTASHIELD: usize = 0x135a; +pub const PCI_DEVICE_ID_INTASHIELD_IS200: usize = 0x0d80; +pub const PCI_DEVICE_ID_INTASHIELD_IS400: usize = 0x0dc0; +pub const PCI_VENDOR_ID_QUATECH: usize = 0x135C; +pub const PCI_DEVICE_ID_QUATECH_QSC100: usize = 0x0010; +pub const PCI_DEVICE_ID_QUATECH_DSC100: usize = 0x0020; +pub const PCI_DEVICE_ID_QUATECH_DSC200: usize = 0x0030; +pub const PCI_DEVICE_ID_QUATECH_QSC200: usize = 0x0040; +pub const PCI_DEVICE_ID_QUATECH_ESC100D: usize = 0x0050; +pub const PCI_DEVICE_ID_QUATECH_ESC100M: usize = 0x0060; +pub const PCI_DEVICE_ID_QUATECH_QSCP100: usize = 0x0120; +pub const PCI_DEVICE_ID_QUATECH_DSCP100: usize = 0x0130; +pub const PCI_DEVICE_ID_QUATECH_QSCP200: usize = 0x0140; +pub const PCI_DEVICE_ID_QUATECH_DSCP200: usize = 0x0150; +pub const PCI_DEVICE_ID_QUATECH_QSCLP100: usize = 0x0170; +pub const PCI_DEVICE_ID_QUATECH_DSCLP100: usize = 0x0180; +pub const PCI_DEVICE_ID_QUATECH_DSC100E: usize = 0x0181; +pub const PCI_DEVICE_ID_QUATECH_SSCLP100: usize = 0x0190; +pub const PCI_DEVICE_ID_QUATECH_QSCLP200: usize = 0x01A0; +pub const PCI_DEVICE_ID_QUATECH_DSCLP200: usize = 0x01B0; +pub const PCI_DEVICE_ID_QUATECH_DSC200E: usize = 0x01B1; +pub const PCI_DEVICE_ID_QUATECH_SSCLP200: usize = 0x01C0; +pub const PCI_DEVICE_ID_QUATECH_ESCLP100: usize = 0x01E0; +pub const PCI_DEVICE_ID_QUATECH_SPPXP_100: usize = 0x0278; +pub const PCI_VENDOR_ID_SEALEVEL: usize = 0x135e; +pub const PCI_DEVICE_ID_SEALEVEL_U530: usize = 0x7101; +pub const PCI_DEVICE_ID_SEALEVEL_UCOMM2: usize = 0x7201; +pub const PCI_DEVICE_ID_SEALEVEL_UCOMM422: usize = 0x7402; +pub const PCI_DEVICE_ID_SEALEVEL_UCOMM232: usize = 0x7202; +pub const PCI_DEVICE_ID_SEALEVEL_COMM4: usize = 0x7401; +pub const PCI_DEVICE_ID_SEALEVEL_COMM8: usize = 0x7801; +pub const PCI_DEVICE_ID_SEALEVEL_7803: usize = 0x7803; +pub const PCI_DEVICE_ID_SEALEVEL_UCOMM8: usize = 0x7804; +pub const PCI_VENDOR_ID_HYPERCOPE: usize = 0x1365; +pub const PCI_DEVICE_ID_HYPERCOPE_PLX: usize = 0x9050; +pub const PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO: usize = 0x0104; +pub const PCI_SUBDEVICE_ID_HYPERCOPE_ERGO: usize = 0x0106; +pub const PCI_SUBDEVICE_ID_HYPERCOPE_METRO: usize = 0x0107; +pub const PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2: usize = 0x0108; +pub const PCI_VENDOR_ID_DIGIGRAM: usize = 0x1369; +pub const PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM: usize = 0xc001; +pub const PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM: usize = 0xc002; +pub const PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_SERIAL_SUBSYSTEM: usize = 0xc021; +pub const PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_CAE_SERIAL_SUBSYSTEM: usize = 0xc022; +pub const PCI_VENDOR_ID_KAWASAKI: usize = 0x136b; +pub const PCI_DEVICE_ID_MCHIP_KL5A72002: usize = 0xff01; +pub const PCI_VENDOR_ID_CNET: usize = 0x1371; +pub const PCI_DEVICE_ID_CNET_GIGACARD: usize = 0x434e; +pub const PCI_VENDOR_ID_LMC: usize = 0x1376; +pub const PCI_DEVICE_ID_LMC_HSSI: usize = 0x0003; +pub const PCI_DEVICE_ID_LMC_DS3: usize = 0x0004; +pub const PCI_DEVICE_ID_LMC_SSI: usize = 0x0005; +pub const PCI_DEVICE_ID_LMC_T1: usize = 0x0006; +pub const PCI_VENDOR_ID_NETGEAR: usize = 0x1385; +pub const PCI_DEVICE_ID_NETGEAR_GA620: usize = 0x620a; +pub const PCI_VENDOR_ID_APPLICOM: usize = 0x1389; +pub const PCI_DEVICE_ID_APPLICOM_PCIGENERIC: usize = 0x0001; +pub const PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN: usize = 0x0002; +pub const PCI_DEVICE_ID_APPLICOM_PCI2000PFB: usize = 0x0003; +pub const PCI_VENDOR_ID_MOXA: usize = 0x1393; +pub const PCI_DEVICE_ID_MOXA_RC7000: usize = 0x0001; +pub const PCI_DEVICE_ID_MOXA_CP102: usize = 0x1020; +pub const PCI_DEVICE_ID_MOXA_CP102UL: usize = 0x1021; +pub const PCI_DEVICE_ID_MOXA_CP102U: usize = 0x1022; +pub const PCI_DEVICE_ID_MOXA_C104: usize = 0x1040; +pub const PCI_DEVICE_ID_MOXA_CP104U: usize = 0x1041; +pub const PCI_DEVICE_ID_MOXA_CP104JU: usize = 0x1042; +pub const PCI_DEVICE_ID_MOXA_CP104EL: usize = 0x1043; +pub const PCI_DEVICE_ID_MOXA_CT114: usize = 0x1140; +pub const PCI_DEVICE_ID_MOXA_CP114: usize = 0x1141; +pub const PCI_DEVICE_ID_MOXA_CP118U: usize = 0x1180; +pub const PCI_DEVICE_ID_MOXA_CP118EL: usize = 0x1181; +pub const PCI_DEVICE_ID_MOXA_CP132: usize = 0x1320; +pub const PCI_DEVICE_ID_MOXA_CP132U: usize = 0x1321; +pub const PCI_DEVICE_ID_MOXA_CP134U: usize = 0x1340; +pub const PCI_DEVICE_ID_MOXA_C168: usize = 0x1680; +pub const PCI_DEVICE_ID_MOXA_CP168U: usize = 0x1681; +pub const PCI_DEVICE_ID_MOXA_CP168EL: usize = 0x1682; +pub const PCI_DEVICE_ID_MOXA_CP204J: usize = 0x2040; +pub const PCI_DEVICE_ID_MOXA_C218: usize = 0x2180; +pub const PCI_DEVICE_ID_MOXA_C320: usize = 0x3200; +pub const PCI_VENDOR_ID_CCD: usize = 0x1397; +pub const PCI_DEVICE_ID_CCD_HFC4S: usize = 0x08B4; +pub const PCI_SUBDEVICE_ID_CCD_PMX2S: usize = 0x1234; +pub const PCI_DEVICE_ID_CCD_HFC8S: usize = 0x16B8; +pub const PCI_DEVICE_ID_CCD_2BD0: usize = 0x2bd0; +pub const PCI_DEVICE_ID_CCD_HFCE1: usize = 0x30B1; +pub const PCI_SUBDEVICE_ID_CCD_SPD4S: usize = 0x3136; +pub const PCI_SUBDEVICE_ID_CCD_SPDE1: usize = 0x3137; +pub const PCI_DEVICE_ID_CCD_B000: usize = 0xb000; +pub const PCI_DEVICE_ID_CCD_B006: usize = 0xb006; +pub const PCI_DEVICE_ID_CCD_B007: usize = 0xb007; +pub const PCI_DEVICE_ID_CCD_B008: usize = 0xb008; +pub const PCI_DEVICE_ID_CCD_B009: usize = 0xb009; +pub const PCI_DEVICE_ID_CCD_B00A: usize = 0xb00a; +pub const PCI_DEVICE_ID_CCD_B00B: usize = 0xb00b; +pub const PCI_DEVICE_ID_CCD_B00C: usize = 0xb00c; +pub const PCI_DEVICE_ID_CCD_B100: usize = 0xb100; +pub const PCI_SUBDEVICE_ID_CCD_IOB4ST: usize = 0xB520; +pub const PCI_SUBDEVICE_ID_CCD_IOB8STR: usize = 0xB521; +pub const PCI_SUBDEVICE_ID_CCD_IOB8ST: usize = 0xB522; +pub const PCI_SUBDEVICE_ID_CCD_IOB1E1: usize = 0xB523; +pub const PCI_SUBDEVICE_ID_CCD_SWYX4S: usize = 0xB540; +pub const PCI_SUBDEVICE_ID_CCD_JH4S20: usize = 0xB550; +pub const PCI_SUBDEVICE_ID_CCD_IOB8ST_1: usize = 0xB552; +pub const PCI_SUBDEVICE_ID_CCD_JHSE1: usize = 0xB553; +pub const PCI_SUBDEVICE_ID_CCD_JH8S: usize = 0xB55B; +pub const PCI_SUBDEVICE_ID_CCD_BN4S: usize = 0xB560; +pub const PCI_SUBDEVICE_ID_CCD_BN8S: usize = 0xB562; +pub const PCI_SUBDEVICE_ID_CCD_BNE1: usize = 0xB563; +pub const PCI_SUBDEVICE_ID_CCD_BNE1D: usize = 0xB564; +pub const PCI_SUBDEVICE_ID_CCD_BNE1DP: usize = 0xB565; +pub const PCI_SUBDEVICE_ID_CCD_BN2S: usize = 0xB566; +pub const PCI_SUBDEVICE_ID_CCD_BN1SM: usize = 0xB567; +pub const PCI_SUBDEVICE_ID_CCD_BN4SM: usize = 0xB568; +pub const PCI_SUBDEVICE_ID_CCD_BN2SM: usize = 0xB569; +pub const PCI_SUBDEVICE_ID_CCD_BNE1M: usize = 0xB56A; +pub const PCI_SUBDEVICE_ID_CCD_BN8SP: usize = 0xB56B; +pub const PCI_SUBDEVICE_ID_CCD_HFC4S: usize = 0xB620; +pub const PCI_SUBDEVICE_ID_CCD_HFC8S: usize = 0xB622; +pub const PCI_DEVICE_ID_CCD_B700: usize = 0xb700; +pub const PCI_DEVICE_ID_CCD_B701: usize = 0xb701; +pub const PCI_SUBDEVICE_ID_CCD_HFCE1: usize = 0xC523; +pub const PCI_SUBDEVICE_ID_CCD_OV2S: usize = 0xE884; +pub const PCI_SUBDEVICE_ID_CCD_OV4S: usize = 0xE888; +pub const PCI_SUBDEVICE_ID_CCD_OV8S: usize = 0xE998; +pub const PCI_VENDOR_ID_EXAR: usize = 0x13a8; +pub const PCI_DEVICE_ID_EXAR_XR17C152: usize = 0x0152; +pub const PCI_DEVICE_ID_EXAR_XR17C154: usize = 0x0154; +pub const PCI_DEVICE_ID_EXAR_XR17C158: usize = 0x0158; +pub const PCI_DEVICE_ID_EXAR_XR17V352: usize = 0x0352; +pub const PCI_DEVICE_ID_EXAR_XR17V354: usize = 0x0354; +pub const PCI_DEVICE_ID_EXAR_XR17V358: usize = 0x0358; +pub const PCI_VENDOR_ID_MICROGATE: usize = 0x13c0; +pub const PCI_DEVICE_ID_MICROGATE_USC: usize = 0x0010; +pub const PCI_DEVICE_ID_MICROGATE_SCA: usize = 0x0030; +pub const PCI_VENDOR_ID_3WARE: usize = 0x13C1; +pub const PCI_DEVICE_ID_3WARE_1000: usize = 0x1000; +pub const PCI_DEVICE_ID_3WARE_7000: usize = 0x1001; +pub const PCI_DEVICE_ID_3WARE_9000: usize = 0x1002; +pub const PCI_VENDOR_ID_IOMEGA: usize = 0x13ca; +pub const PCI_DEVICE_ID_IOMEGA_BUZ: usize = 0x4231; +pub const PCI_VENDOR_ID_ABOCOM: usize = 0x13D1; +pub const PCI_DEVICE_ID_ABOCOM_2BD1: usize = 0x2BD1; +pub const PCI_VENDOR_ID_SUNDANCE: usize = 0x13f0; +pub const PCI_VENDOR_ID_CMEDIA: usize = 0x13f6; +pub const PCI_DEVICE_ID_CMEDIA_CM8338A: usize = 0x0100; +pub const PCI_DEVICE_ID_CMEDIA_CM8338B: usize = 0x0101; +pub const PCI_DEVICE_ID_CMEDIA_CM8738: usize = 0x0111; +pub const PCI_DEVICE_ID_CMEDIA_CM8738B: usize = 0x0112; +pub const PCI_VENDOR_ID_ADVANTECH: usize = 0x13fe; +pub const PCI_VENDOR_ID_MEILHAUS: usize = 0x1402; +pub const PCI_VENDOR_ID_LAVA: usize = 0x1407; +pub const PCI_DEVICE_ID_LAVA_DSERIAL: usize = 0x0100; +pub const PCI_DEVICE_ID_LAVA_QUATRO_A: usize = 0x0101; +pub const PCI_DEVICE_ID_LAVA_QUATRO_B: usize = 0x0102; +pub const PCI_DEVICE_ID_LAVA_QUATTRO_A: usize = 0x0120; +pub const PCI_DEVICE_ID_LAVA_QUATTRO_B: usize = 0x0121; +pub const PCI_DEVICE_ID_LAVA_OCTO_A: usize = 0x0180; +pub const PCI_DEVICE_ID_LAVA_OCTO_B: usize = 0x0181; +pub const PCI_DEVICE_ID_LAVA_PORT_PLUS: usize = 0x0200; +pub const PCI_DEVICE_ID_LAVA_QUAD_A: usize = 0x0201; +pub const PCI_DEVICE_ID_LAVA_QUAD_B: usize = 0x0202; +pub const PCI_DEVICE_ID_LAVA_SSERIAL: usize = 0x0500; +pub const PCI_DEVICE_ID_LAVA_PORT_650: usize = 0x0600; +pub const PCI_DEVICE_ID_LAVA_PARALLEL: usize = 0x8000; +pub const PCI_DEVICE_ID_LAVA_DUAL_PAR_A: usize = 0x8002; +pub const PCI_DEVICE_ID_LAVA_DUAL_PAR_B: usize = 0x8003; +pub const PCI_DEVICE_ID_LAVA_BOCA_IOPPAR: usize = 0x8800; +pub const PCI_VENDOR_ID_TIMEDIA: usize = 0x1409; +pub const PCI_DEVICE_ID_TIMEDIA_1889: usize = 0x7168; +pub const PCI_VENDOR_ID_ICE: usize = 0x1412; +pub const PCI_DEVICE_ID_ICE_1712: usize = 0x1712; +pub const PCI_DEVICE_ID_VT1724: usize = 0x1724; +pub const PCI_VENDOR_ID_OXSEMI: usize = 0x1415; +pub const PCI_DEVICE_ID_OXSEMI_12PCI840: usize = 0x8403; +pub const PCI_DEVICE_ID_OXSEMI_PCIe840: usize = 0xC000; +pub const PCI_DEVICE_ID_OXSEMI_PCIe840_G: usize = 0xC004; +pub const PCI_DEVICE_ID_OXSEMI_PCIe952_0: usize = 0xC100; +pub const PCI_DEVICE_ID_OXSEMI_PCIe952_0_G: usize = 0xC104; +pub const PCI_DEVICE_ID_OXSEMI_PCIe952_1: usize = 0xC110; +pub const PCI_DEVICE_ID_OXSEMI_PCIe952_1_G: usize = 0xC114; +pub const PCI_DEVICE_ID_OXSEMI_PCIe952_1_U: usize = 0xC118; +pub const PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU: usize = 0xC11C; +pub const PCI_DEVICE_ID_OXSEMI_16PCI954: usize = 0x9501; +pub const PCI_DEVICE_ID_OXSEMI_C950: usize = 0x950B; +pub const PCI_DEVICE_ID_OXSEMI_16PCI95N: usize = 0x9511; +pub const PCI_DEVICE_ID_OXSEMI_16PCI954PP: usize = 0x9513; +pub const PCI_DEVICE_ID_OXSEMI_16PCI952: usize = 0x9521; +pub const PCI_DEVICE_ID_OXSEMI_16PCI952PP: usize = 0x9523; +pub const PCI_SUBDEVICE_ID_OXSEMI_C950: usize = 0x0001; +pub const PCI_VENDOR_ID_CHELSIO: usize = 0x1425; +pub const PCI_VENDOR_ID_ADLINK: usize = 0x144a; +pub const PCI_VENDOR_ID_SAMSUNG: usize = 0x144d; +pub const PCI_VENDOR_ID_GIGABYTE: usize = 0x1458; +pub const PCI_VENDOR_ID_AMBIT: usize = 0x1468; +pub const PCI_VENDOR_ID_MYRICOM: usize = 0x14c1; +pub const PCI_VENDOR_ID_MEDIATEK: usize = 0x14c3; +pub const PCI_DEVICE_ID_MEDIATEK_7629: usize = 0x7629; +pub const PCI_VENDOR_ID_TITAN: usize = 0x14D2; +pub const PCI_DEVICE_ID_TITAN_010L: usize = 0x8001; +pub const PCI_DEVICE_ID_TITAN_100L: usize = 0x8010; +pub const PCI_DEVICE_ID_TITAN_110L: usize = 0x8011; +pub const PCI_DEVICE_ID_TITAN_200L: usize = 0x8020; +pub const PCI_DEVICE_ID_TITAN_210L: usize = 0x8021; +pub const PCI_DEVICE_ID_TITAN_400L: usize = 0x8040; +pub const PCI_DEVICE_ID_TITAN_800L: usize = 0x8080; +pub const PCI_DEVICE_ID_TITAN_100: usize = 0xA001; +pub const PCI_DEVICE_ID_TITAN_200: usize = 0xA005; +pub const PCI_DEVICE_ID_TITAN_400: usize = 0xA003; +pub const PCI_DEVICE_ID_TITAN_800B: usize = 0xA004; +pub const PCI_VENDOR_ID_PANACOM: usize = 0x14d4; +pub const PCI_DEVICE_ID_PANACOM_QUADMODEM: usize = 0x0400; +pub const PCI_DEVICE_ID_PANACOM_DUALMODEM: usize = 0x0402; +pub const PCI_VENDOR_ID_SIPACKETS: usize = 0x14d9; +pub const PCI_DEVICE_ID_SP1011: usize = 0x0010; +pub const PCI_VENDOR_ID_AFAVLAB: usize = 0x14db; +pub const PCI_DEVICE_ID_AFAVLAB_P028: usize = 0x2180; +pub const PCI_DEVICE_ID_AFAVLAB_P030: usize = 0x2182; +pub const PCI_SUBDEVICE_ID_AFAVLAB_P061: usize = 0x2150; +pub const PCI_VENDOR_ID_AMPLICON: usize = 0x14dc; +pub const PCI_VENDOR_ID_BCM_GVC: usize = 0x14a4; +pub const PCI_VENDOR_ID_BROADCOM: usize = 0x14e4; +pub const PCI_DEVICE_ID_TIGON3_5752: usize = 0x1600; +pub const PCI_DEVICE_ID_TIGON3_5752M: usize = 0x1601; +pub const PCI_DEVICE_ID_NX2_5709: usize = 0x1639; +pub const PCI_DEVICE_ID_NX2_5709S: usize = 0x163a; +pub const PCI_DEVICE_ID_TIGON3_5700: usize = 0x1644; +pub const PCI_DEVICE_ID_TIGON3_5701: usize = 0x1645; +pub const PCI_DEVICE_ID_TIGON3_5702: usize = 0x1646; +pub const PCI_DEVICE_ID_TIGON3_5703: usize = 0x1647; +pub const PCI_DEVICE_ID_TIGON3_5704: usize = 0x1648; +pub const PCI_DEVICE_ID_TIGON3_5704S_2: usize = 0x1649; +pub const PCI_DEVICE_ID_NX2_5706: usize = 0x164a; +pub const PCI_DEVICE_ID_NX2_5708: usize = 0x164c; +pub const PCI_DEVICE_ID_TIGON3_5702FE: usize = 0x164d; +pub const PCI_DEVICE_ID_NX2_57710: usize = 0x164e; +pub const PCI_DEVICE_ID_NX2_57711: usize = 0x164f; +pub const PCI_DEVICE_ID_NX2_57711E: usize = 0x1650; +pub const PCI_DEVICE_ID_TIGON3_5705: usize = 0x1653; +pub const PCI_DEVICE_ID_TIGON3_5705_2: usize = 0x1654; +pub const PCI_DEVICE_ID_TIGON3_5719: usize = 0x1657; +pub const PCI_DEVICE_ID_TIGON3_5721: usize = 0x1659; +pub const PCI_DEVICE_ID_TIGON3_5722: usize = 0x165a; +pub const PCI_DEVICE_ID_TIGON3_5723: usize = 0x165b; +pub const PCI_DEVICE_ID_TIGON3_5705M: usize = 0x165d; +pub const PCI_DEVICE_ID_TIGON3_5705M_2: usize = 0x165e; +pub const PCI_DEVICE_ID_NX2_57712: usize = 0x1662; +pub const PCI_DEVICE_ID_NX2_57712E: usize = 0x1663; +pub const PCI_DEVICE_ID_NX2_57712_MF: usize = 0x1663; +pub const PCI_DEVICE_ID_TIGON3_5714: usize = 0x1668; +pub const PCI_DEVICE_ID_TIGON3_5714S: usize = 0x1669; +pub const PCI_DEVICE_ID_TIGON3_5780: usize = 0x166a; +pub const PCI_DEVICE_ID_TIGON3_5780S: usize = 0x166b; +pub const PCI_DEVICE_ID_TIGON3_5705F: usize = 0x166e; +pub const PCI_DEVICE_ID_NX2_57712_VF: usize = 0x166f; +pub const PCI_DEVICE_ID_TIGON3_5754M: usize = 0x1672; +pub const PCI_DEVICE_ID_TIGON3_5755M: usize = 0x1673; +pub const PCI_DEVICE_ID_TIGON3_5756: usize = 0x1674; +pub const PCI_DEVICE_ID_TIGON3_5750: usize = 0x1676; +pub const PCI_DEVICE_ID_TIGON3_5751: usize = 0x1677; +pub const PCI_DEVICE_ID_TIGON3_5715: usize = 0x1678; +pub const PCI_DEVICE_ID_TIGON3_5715S: usize = 0x1679; +pub const PCI_DEVICE_ID_TIGON3_5754: usize = 0x167a; +pub const PCI_DEVICE_ID_TIGON3_5755: usize = 0x167b; +pub const PCI_DEVICE_ID_TIGON3_5751M: usize = 0x167d; +pub const PCI_DEVICE_ID_TIGON3_5751F: usize = 0x167e; +pub const PCI_DEVICE_ID_TIGON3_5787F: usize = 0x167f; +pub const PCI_DEVICE_ID_TIGON3_5761E: usize = 0x1680; +pub const PCI_DEVICE_ID_TIGON3_5761: usize = 0x1681; +pub const PCI_DEVICE_ID_TIGON3_5764: usize = 0x1684; +pub const PCI_DEVICE_ID_NX2_57800: usize = 0x168a; +pub const PCI_DEVICE_ID_NX2_57840: usize = 0x168d; +pub const PCI_DEVICE_ID_NX2_57810: usize = 0x168e; +pub const PCI_DEVICE_ID_TIGON3_5787M: usize = 0x1693; +pub const PCI_DEVICE_ID_TIGON3_5782: usize = 0x1696; +pub const PCI_DEVICE_ID_TIGON3_5784: usize = 0x1698; +pub const PCI_DEVICE_ID_TIGON3_5786: usize = 0x169a; +pub const PCI_DEVICE_ID_TIGON3_5787: usize = 0x169b; +pub const PCI_DEVICE_ID_TIGON3_5788: usize = 0x169c; +pub const PCI_DEVICE_ID_TIGON3_5789: usize = 0x169d; +pub const PCI_DEVICE_ID_NX2_57840_4_10: usize = 0x16a1; +pub const PCI_DEVICE_ID_NX2_57840_2_20: usize = 0x16a2; +pub const PCI_DEVICE_ID_NX2_57840_MF: usize = 0x16a4; +pub const PCI_DEVICE_ID_NX2_57800_MF: usize = 0x16a5; +pub const PCI_DEVICE_ID_TIGON3_5702X: usize = 0x16a6; +pub const PCI_DEVICE_ID_TIGON3_5703X: usize = 0x16a7; +pub const PCI_DEVICE_ID_TIGON3_5704S: usize = 0x16a8; +pub const PCI_DEVICE_ID_NX2_57800_VF: usize = 0x16a9; +pub const PCI_DEVICE_ID_NX2_5706S: usize = 0x16aa; +pub const PCI_DEVICE_ID_NX2_5708S: usize = 0x16ac; +pub const PCI_DEVICE_ID_NX2_57840_VF: usize = 0x16ad; +pub const PCI_DEVICE_ID_NX2_57810_MF: usize = 0x16ae; +pub const PCI_DEVICE_ID_NX2_57810_VF: usize = 0x16af; +pub const PCI_DEVICE_ID_TIGON3_5702A3: usize = 0x16c6; +pub const PCI_DEVICE_ID_TIGON3_5703A3: usize = 0x16c7; +pub const PCI_DEVICE_ID_TIGON3_5781: usize = 0x16dd; +pub const PCI_DEVICE_ID_TIGON3_5753: usize = 0x16f7; +pub const PCI_DEVICE_ID_TIGON3_5753M: usize = 0x16fd; +pub const PCI_DEVICE_ID_TIGON3_5753F: usize = 0x16fe; +pub const PCI_DEVICE_ID_TIGON3_5901: usize = 0x170d; +pub const PCI_DEVICE_ID_BCM4401B1: usize = 0x170c; +pub const PCI_DEVICE_ID_TIGON3_5901_2: usize = 0x170e; +pub const PCI_DEVICE_ID_TIGON3_5906: usize = 0x1712; +pub const PCI_DEVICE_ID_TIGON3_5906M: usize = 0x1713; +pub const PCI_DEVICE_ID_BCM4401: usize = 0x4401; +pub const PCI_DEVICE_ID_BCM4401B0: usize = 0x4402; +pub const PCI_VENDOR_ID_TOPIC: usize = 0x151f; +pub const PCI_DEVICE_ID_TOPIC_TP560: usize = 0x0000; +pub const PCI_VENDOR_ID_MAINPINE: usize = 0x1522; +pub const PCI_DEVICE_ID_MAINPINE_PBRIDGE: usize = 0x0100; +pub const PCI_VENDOR_ID_ENE: usize = 0x1524; +pub const PCI_DEVICE_ID_ENE_CB710_FLASH: usize = 0x0510; +pub const PCI_DEVICE_ID_ENE_CB712_SD: usize = 0x0550; +pub const PCI_DEVICE_ID_ENE_CB712_SD_2: usize = 0x0551; +pub const PCI_DEVICE_ID_ENE_CB714_SD: usize = 0x0750; +pub const PCI_DEVICE_ID_ENE_CB714_SD_2: usize = 0x0751; +pub const PCI_DEVICE_ID_ENE_1211: usize = 0x1211; +pub const PCI_DEVICE_ID_ENE_1225: usize = 0x1225; +pub const PCI_DEVICE_ID_ENE_1410: usize = 0x1410; +pub const PCI_DEVICE_ID_ENE_710: usize = 0x1411; +pub const PCI_DEVICE_ID_ENE_712: usize = 0x1412; +pub const PCI_DEVICE_ID_ENE_1420: usize = 0x1420; +pub const PCI_DEVICE_ID_ENE_720: usize = 0x1421; +pub const PCI_DEVICE_ID_ENE_722: usize = 0x1422; +pub const PCI_SUBVENDOR_ID_PERLE: usize = 0x155f; +pub const PCI_SUBDEVICE_ID_PCI_RAS4: usize = 0xf001; +pub const PCI_SUBDEVICE_ID_PCI_RAS8: usize = 0xf010; +pub const PCI_VENDOR_ID_SYBA: usize = 0x1592; +pub const PCI_DEVICE_ID_SYBA_2P_EPP: usize = 0x0782; +pub const PCI_DEVICE_ID_SYBA_1P_ECP: usize = 0x0783; +pub const PCI_VENDOR_ID_MORETON: usize = 0x15aa; +pub const PCI_DEVICE_ID_RASTEL_2PORT: usize = 0x2000; +pub const PCI_VENDOR_ID_VMWARE: usize = 0x15ad; +pub const PCI_DEVICE_ID_VMWARE_VMXNET3: usize = 0x07b0; +pub const PCI_VENDOR_ID_ZOLTRIX: usize = 0x15b0; +pub const PCI_DEVICE_ID_ZOLTRIX_2BD0: usize = 0x2bd0; +pub const PCI_VENDOR_ID_MELLANOX: usize = 0x15b3; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTX3: usize = 0x1003; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO: usize = 0x1007; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTIB: usize = 0x1011; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTX4: usize = 0x1013; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX: usize = 0x1015; +pub const PCI_DEVICE_ID_MELLANOX_TAVOR: usize = 0x5a44; +pub const PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE: usize = 0x5a46; +pub const PCI_DEVICE_ID_MELLANOX_SINAI_OLD: usize = 0x5e8c; +pub const PCI_DEVICE_ID_MELLANOX_SINAI: usize = 0x6274; +pub const PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT: usize = 0x6278; +pub const PCI_DEVICE_ID_MELLANOX_ARBEL: usize = 0x6282; +pub const PCI_DEVICE_ID_MELLANOX_HERMON_SDR: usize = 0x6340; +pub const PCI_DEVICE_ID_MELLANOX_HERMON_DDR: usize = 0x634a; +pub const PCI_DEVICE_ID_MELLANOX_HERMON_QDR: usize = 0x6354; +pub const PCI_DEVICE_ID_MELLANOX_HERMON_EN: usize = 0x6368; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTX_EN: usize = 0x6372; +pub const PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2: usize = 0x6732; +pub const PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2: usize = 0x673c; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2: usize = 0x6746; +pub const PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2: usize = 0x6750; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2: usize = 0x675a; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2: usize = 0x6764; +pub const PCI_DEVICE_ID_MELLANOX_CONNECTX2: usize = 0x676e; +pub const PCI_VENDOR_ID_DFI: usize = 0x15bd; +pub const PCI_VENDOR_ID_QUICKNET: usize = 0x15e2; +pub const PCI_DEVICE_ID_QUICKNET_XJ: usize = 0x0500; +pub const PCI_VENDOR_ID_ADDIDATA: usize = 0x15B8; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7500: usize = 0x7000; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7420: usize = 0x7001; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7300: usize = 0x7002; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7500_2: usize = 0x7009; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7420_2: usize = 0x700A; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7300_2: usize = 0x700B; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7500_3: usize = 0x700C; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7420_3: usize = 0x700D; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7300_3: usize = 0x700E; +pub const PCI_DEVICE_ID_ADDIDATA_APCI7800_3: usize = 0x700F; +pub const PCI_DEVICE_ID_ADDIDATA_APCIe7300: usize = 0x7010; +pub const PCI_DEVICE_ID_ADDIDATA_APCIe7420: usize = 0x7011; +pub const PCI_DEVICE_ID_ADDIDATA_APCIe7500: usize = 0x7012; +pub const PCI_DEVICE_ID_ADDIDATA_APCIe7800: usize = 0x7013; +pub const PCI_VENDOR_ID_PDC: usize = 0x15e9; +pub const PCI_VENDOR_ID_FARSITE: usize = 0x1619; +pub const PCI_DEVICE_ID_FARSITE_T2P: usize = 0x0400; +pub const PCI_DEVICE_ID_FARSITE_T4P: usize = 0x0440; +pub const PCI_DEVICE_ID_FARSITE_T1U: usize = 0x0610; +pub const PCI_DEVICE_ID_FARSITE_T2U: usize = 0x0620; +pub const PCI_DEVICE_ID_FARSITE_T4U: usize = 0x0640; +pub const PCI_DEVICE_ID_FARSITE_TE1: usize = 0x1610; +pub const PCI_DEVICE_ID_FARSITE_TE1C: usize = 0x1612; +pub const PCI_VENDOR_ID_ARIMA: usize = 0x161f; +pub const PCI_VENDOR_ID_BROCADE: usize = 0x1657; +pub const PCI_DEVICE_ID_BROCADE_CT: usize = 0x0014; +pub const PCI_DEVICE_ID_BROCADE_FC_8G1P: usize = 0x0017; +pub const PCI_DEVICE_ID_BROCADE_CT_FC: usize = 0x0021; +pub const PCI_VENDOR_ID_SIBYTE: usize = 0x166d; +pub const PCI_DEVICE_ID_BCM1250_PCI: usize = 0x0001; +pub const PCI_DEVICE_ID_BCM1250_HT: usize = 0x0002; +pub const PCI_VENDOR_ID_ATHEROS: usize = 0x168c; +pub const PCI_VENDOR_ID_NETCELL: usize = 0x169c; +pub const PCI_DEVICE_ID_REVOLUTION: usize = 0x0044; +pub const PCI_VENDOR_ID_CENATEK: usize = 0x16CA; +pub const PCI_DEVICE_ID_CENATEK_IDE: usize = 0x0001; +pub const PCI_VENDOR_ID_SYNOPSYS: usize = 0x16c3; +pub const PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: usize = 0xabcd; +pub const PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: usize = 0xabce; +pub const PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: usize = 0xabcf; +pub const PCI_DEVICE_ID_SYNOPSYS_EDDA: usize = 0xedda; +pub const PCI_VENDOR_ID_USR: usize = 0x16ec; +pub const PCI_VENDOR_ID_VITESSE: usize = 0x1725; +pub const PCI_DEVICE_ID_VITESSE_VSC7174: usize = 0x7174; +pub const PCI_VENDOR_ID_LINKSYS: usize = 0x1737; +pub const PCI_DEVICE_ID_LINKSYS_EG1064: usize = 0x1064; +pub const PCI_VENDOR_ID_ALTIMA: usize = 0x173b; +pub const PCI_DEVICE_ID_ALTIMA_AC1000: usize = 0x03e8; +pub const PCI_DEVICE_ID_ALTIMA_AC1001: usize = 0x03e9; +pub const PCI_DEVICE_ID_ALTIMA_AC9100: usize = 0x03ea; +pub const PCI_DEVICE_ID_ALTIMA_AC1003: usize = 0x03eb; +pub const PCI_VENDOR_ID_CAVIUM: usize = 0x177d; +pub const PCI_VENDOR_ID_TECHWELL: usize = 0x1797; +pub const PCI_DEVICE_ID_TECHWELL_6800: usize = 0x6800; +pub const PCI_DEVICE_ID_TECHWELL_6801: usize = 0x6801; +pub const PCI_DEVICE_ID_TECHWELL_6804: usize = 0x6804; +pub const PCI_DEVICE_ID_TECHWELL_6816_1: usize = 0x6810; +pub const PCI_DEVICE_ID_TECHWELL_6816_2: usize = 0x6811; +pub const PCI_DEVICE_ID_TECHWELL_6816_3: usize = 0x6812; +pub const PCI_DEVICE_ID_TECHWELL_6816_4: usize = 0x6813; +pub const PCI_VENDOR_ID_BELKIN: usize = 0x1799; +pub const PCI_DEVICE_ID_BELKIN_F5D7010V7: usize = 0x701f; +pub const PCI_VENDOR_ID_RDC: usize = 0x17f3; +pub const PCI_DEVICE_ID_RDC_R6020: usize = 0x6020; +pub const PCI_DEVICE_ID_RDC_R6030: usize = 0x6030; +pub const PCI_DEVICE_ID_RDC_R6040: usize = 0x6040; +pub const PCI_DEVICE_ID_RDC_R6060: usize = 0x6060; +pub const PCI_DEVICE_ID_RDC_R6061: usize = 0x6061; +pub const PCI_DEVICE_ID_RDC_D1010: usize = 0x1010; +pub const PCI_VENDOR_ID_GLI: usize = 0x17a0; +pub const PCI_VENDOR_ID_LENOVO: usize = 0x17aa; +pub const PCI_VENDOR_ID_QCOM: usize = 0x17cb; +pub const PCI_VENDOR_ID_CDNS: usize = 0x17cd; +pub const PCI_VENDOR_ID_ARECA: usize = 0x17d3; +pub const PCI_DEVICE_ID_ARECA_1110: usize = 0x1110; +pub const PCI_DEVICE_ID_ARECA_1120: usize = 0x1120; +pub const PCI_DEVICE_ID_ARECA_1130: usize = 0x1130; +pub const PCI_DEVICE_ID_ARECA_1160: usize = 0x1160; +pub const PCI_DEVICE_ID_ARECA_1170: usize = 0x1170; +pub const PCI_DEVICE_ID_ARECA_1200: usize = 0x1200; +pub const PCI_DEVICE_ID_ARECA_1201: usize = 0x1201; +pub const PCI_DEVICE_ID_ARECA_1202: usize = 0x1202; +pub const PCI_DEVICE_ID_ARECA_1210: usize = 0x1210; +pub const PCI_DEVICE_ID_ARECA_1220: usize = 0x1220; +pub const PCI_DEVICE_ID_ARECA_1230: usize = 0x1230; +pub const PCI_DEVICE_ID_ARECA_1260: usize = 0x1260; +pub const PCI_DEVICE_ID_ARECA_1270: usize = 0x1270; +pub const PCI_DEVICE_ID_ARECA_1280: usize = 0x1280; +pub const PCI_DEVICE_ID_ARECA_1380: usize = 0x1380; +pub const PCI_DEVICE_ID_ARECA_1381: usize = 0x1381; +pub const PCI_DEVICE_ID_ARECA_1680: usize = 0x1680; +pub const PCI_DEVICE_ID_ARECA_1681: usize = 0x1681; +pub const PCI_VENDOR_ID_S2IO: usize = 0x17d5; +pub const PCI_DEVICE_ID_S2IO_WIN: usize = 0x5731; +pub const PCI_DEVICE_ID_S2IO_UNI: usize = 0x5831; +pub const PCI_DEVICE_ID_HERC_WIN: usize = 0x5732; +pub const PCI_DEVICE_ID_HERC_UNI: usize = 0x5832; +pub const PCI_VENDOR_ID_SITECOM: usize = 0x182d; +pub const PCI_DEVICE_ID_SITECOM_DC105V2: usize = 0x3069; +pub const PCI_VENDOR_ID_TOPSPIN: usize = 0x1867; +pub const PCI_VENDOR_ID_COMMTECH: usize = 0x18f7; +pub const PCI_VENDOR_ID_SILAN: usize = 0x1904; +pub const PCI_VENDOR_ID_RENESAS: usize = 0x1912; +pub const PCI_DEVICE_ID_RENESAS_SH7781: usize = 0x0001; +pub const PCI_DEVICE_ID_RENESAS_SH7780: usize = 0x0002; +pub const PCI_DEVICE_ID_RENESAS_SH7763: usize = 0x0004; +pub const PCI_DEVICE_ID_RENESAS_SH7785: usize = 0x0007; +pub const PCI_DEVICE_ID_RENESAS_SH7786: usize = 0x0010; +pub const PCI_VENDOR_ID_SOLARFLARE: usize = 0x1924; +pub const PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0: usize = 0x0703; +pub const PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1: usize = 0x6703; +pub const PCI_DEVICE_ID_SOLARFLARE_SFC4000B: usize = 0x0710; +pub const PCI_VENDOR_ID_TDI: usize = 0x192E; +pub const PCI_DEVICE_ID_TDI_EHCI: usize = 0x0101; +pub const PCI_VENDOR_ID_FREESCALE: usize = 0x1957; +pub const PCI_VENDOR_ID_NXP: usize = 0x1957; +pub const PCI_DEVICE_ID_MPC8308: usize = 0xc006; +pub const PCI_DEVICE_ID_MPC8315E: usize = 0x00b4; +pub const PCI_DEVICE_ID_MPC8315: usize = 0x00b5; +pub const PCI_DEVICE_ID_MPC8314E: usize = 0x00b6; +pub const PCI_DEVICE_ID_MPC8314: usize = 0x00b7; +pub const PCI_DEVICE_ID_MPC8378E: usize = 0x00c4; +pub const PCI_DEVICE_ID_MPC8378: usize = 0x00c5; +pub const PCI_DEVICE_ID_MPC8377E: usize = 0x00c6; +pub const PCI_DEVICE_ID_MPC8377: usize = 0x00c7; +pub const PCI_DEVICE_ID_MPC8548E: usize = 0x0012; +pub const PCI_DEVICE_ID_MPC8548: usize = 0x0013; +pub const PCI_DEVICE_ID_MPC8543E: usize = 0x0014; +pub const PCI_DEVICE_ID_MPC8543: usize = 0x0015; +pub const PCI_DEVICE_ID_MPC8547E: usize = 0x0018; +pub const PCI_DEVICE_ID_MPC8545E: usize = 0x0019; +pub const PCI_DEVICE_ID_MPC8545: usize = 0x001a; +pub const PCI_DEVICE_ID_MPC8569E: usize = 0x0061; +pub const PCI_DEVICE_ID_MPC8569: usize = 0x0060; +pub const PCI_DEVICE_ID_MPC8568E: usize = 0x0020; +pub const PCI_DEVICE_ID_MPC8568: usize = 0x0021; +pub const PCI_DEVICE_ID_MPC8567E: usize = 0x0022; +pub const PCI_DEVICE_ID_MPC8567: usize = 0x0023; +pub const PCI_DEVICE_ID_MPC8533E: usize = 0x0030; +pub const PCI_DEVICE_ID_MPC8533: usize = 0x0031; +pub const PCI_DEVICE_ID_MPC8544E: usize = 0x0032; +pub const PCI_DEVICE_ID_MPC8544: usize = 0x0033; +pub const PCI_DEVICE_ID_MPC8572E: usize = 0x0040; +pub const PCI_DEVICE_ID_MPC8572: usize = 0x0041; +pub const PCI_DEVICE_ID_MPC8536E: usize = 0x0050; +pub const PCI_DEVICE_ID_MPC8536: usize = 0x0051; +pub const PCI_DEVICE_ID_P2020E: usize = 0x0070; +pub const PCI_DEVICE_ID_P2020: usize = 0x0071; +pub const PCI_DEVICE_ID_P2010E: usize = 0x0078; +pub const PCI_DEVICE_ID_P2010: usize = 0x0079; +pub const PCI_DEVICE_ID_P1020E: usize = 0x0100; +pub const PCI_DEVICE_ID_P1020: usize = 0x0101; +pub const PCI_DEVICE_ID_P1021E: usize = 0x0102; +pub const PCI_DEVICE_ID_P1021: usize = 0x0103; +pub const PCI_DEVICE_ID_P1011E: usize = 0x0108; +pub const PCI_DEVICE_ID_P1011: usize = 0x0109; +pub const PCI_DEVICE_ID_P1022E: usize = 0x0110; +pub const PCI_DEVICE_ID_P1022: usize = 0x0111; +pub const PCI_DEVICE_ID_P1013E: usize = 0x0118; +pub const PCI_DEVICE_ID_P1013: usize = 0x0119; +pub const PCI_DEVICE_ID_P4080E: usize = 0x0400; +pub const PCI_DEVICE_ID_P4080: usize = 0x0401; +pub const PCI_DEVICE_ID_P4040E: usize = 0x0408; +pub const PCI_DEVICE_ID_P4040: usize = 0x0409; +pub const PCI_DEVICE_ID_P2040E: usize = 0x0410; +pub const PCI_DEVICE_ID_P2040: usize = 0x0411; +pub const PCI_DEVICE_ID_P3041E: usize = 0x041E; +pub const PCI_DEVICE_ID_P3041: usize = 0x041F; +pub const PCI_DEVICE_ID_P5020E: usize = 0x0420; +pub const PCI_DEVICE_ID_P5020: usize = 0x0421; +pub const PCI_DEVICE_ID_P5010E: usize = 0x0428; +pub const PCI_DEVICE_ID_P5010: usize = 0x0429; +pub const PCI_DEVICE_ID_MPC8641: usize = 0x7010; +pub const PCI_DEVICE_ID_MPC8641D: usize = 0x7011; +pub const PCI_DEVICE_ID_MPC8610: usize = 0x7018; +pub const PCI_VENDOR_ID_PASEMI: usize = 0x1959; +pub const PCI_VENDOR_ID_ATTANSIC: usize = 0x1969; +pub const PCI_DEVICE_ID_ATTANSIC_L1: usize = 0x1048; +pub const PCI_DEVICE_ID_ATTANSIC_L2: usize = 0x2048; +pub const PCI_VENDOR_ID_JMICRON: usize = 0x197B; +pub const PCI_DEVICE_ID_JMICRON_JMB360: usize = 0x2360; +pub const PCI_DEVICE_ID_JMICRON_JMB361: usize = 0x2361; +pub const PCI_DEVICE_ID_JMICRON_JMB362: usize = 0x2362; +pub const PCI_DEVICE_ID_JMICRON_JMB363: usize = 0x2363; +pub const PCI_DEVICE_ID_JMICRON_JMB364: usize = 0x2364; +pub const PCI_DEVICE_ID_JMICRON_JMB365: usize = 0x2365; +pub const PCI_DEVICE_ID_JMICRON_JMB366: usize = 0x2366; +pub const PCI_DEVICE_ID_JMICRON_JMB368: usize = 0x2368; +pub const PCI_DEVICE_ID_JMICRON_JMB369: usize = 0x2369; +pub const PCI_DEVICE_ID_JMICRON_JMB38X_SD: usize = 0x2381; +pub const PCI_DEVICE_ID_JMICRON_JMB38X_MMC: usize = 0x2382; +pub const PCI_DEVICE_ID_JMICRON_JMB38X_MS: usize = 0x2383; +pub const PCI_DEVICE_ID_JMICRON_JMB385_MS: usize = 0x2388; +pub const PCI_DEVICE_ID_JMICRON_JMB388_SD: usize = 0x2391; +pub const PCI_DEVICE_ID_JMICRON_JMB388_ESD: usize = 0x2392; +pub const PCI_DEVICE_ID_JMICRON_JMB390_MS: usize = 0x2393; +pub const PCI_VENDOR_ID_KORENIX: usize = 0x1982; +pub const PCI_DEVICE_ID_KORENIX_JETCARDF0: usize = 0x1600; +pub const PCI_DEVICE_ID_KORENIX_JETCARDF1: usize = 0x16ff; +pub const PCI_DEVICE_ID_KORENIX_JETCARDF2: usize = 0x1700; +pub const PCI_DEVICE_ID_KORENIX_JETCARDF3: usize = 0x17ff; +pub const PCI_VENDOR_ID_HUAWEI: usize = 0x19e5; +pub const PCI_VENDOR_ID_NETRONOME: usize = 0x19ee; +pub const PCI_DEVICE_ID_NETRONOME_NFP4000: usize = 0x4000; +pub const PCI_DEVICE_ID_NETRONOME_NFP5000: usize = 0x5000; +pub const PCI_DEVICE_ID_NETRONOME_NFP6000: usize = 0x6000; +pub const PCI_DEVICE_ID_NETRONOME_NFP6000_VF: usize = 0x6003; +pub const PCI_VENDOR_ID_QMI: usize = 0x1a32; +pub const PCI_VENDOR_ID_AZWAVE: usize = 0x1a3b; +pub const PCI_VENDOR_ID_REDHAT_QUMRANET: usize = 0x1af4; +pub const PCI_SUBVENDOR_ID_REDHAT_QUMRANET: usize = 0x1af4; +pub const PCI_SUBDEVICE_ID_QEMU: usize = 0x1100; +pub const PCI_VENDOR_ID_ASMEDIA: usize = 0x1b21; +pub const PCI_VENDOR_ID_REDHAT: usize = 0x1b36; +pub const PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS: usize = 0x1c36; +pub const PCI_VENDOR_ID_CIRCUITCO: usize = 0x1cc8; +pub const PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD: usize = 0x0001; +pub const PCI_VENDOR_ID_AMAZON: usize = 0x1d0f; +pub const PCI_VENDOR_ID_ZHAOXIN: usize = 0x1d17; +pub const PCI_VENDOR_ID_HYGON: usize = 0x1d94; +pub const PCI_VENDOR_ID_HXT: usize = 0x1dbf; +pub const PCI_VENDOR_ID_TEKRAM: usize = 0x1de1; +pub const PCI_DEVICE_ID_TEKRAM_DC290: usize = 0xdc29; +pub const PCI_VENDOR_ID_TEHUTI: usize = 0x1fc9; +pub const PCI_DEVICE_ID_TEHUTI_3009: usize = 0x3009; +pub const PCI_DEVICE_ID_TEHUTI_3010: usize = 0x3010; +pub const PCI_DEVICE_ID_TEHUTI_3014: usize = 0x3014; +pub const PCI_VENDOR_ID_SUNIX: usize = 0x1fd4; +pub const PCI_DEVICE_ID_SUNIX_1999: usize = 0x1999; +pub const PCI_VENDOR_ID_HINT: usize = 0x3388; +pub const PCI_DEVICE_ID_HINT_VXPROII_IDE: usize = 0x8013; +pub const PCI_VENDOR_ID_3DLABS: usize = 0x3d3d; +pub const PCI_DEVICE_ID_3DLABS_PERMEDIA2: usize = 0x0007; +pub const PCI_DEVICE_ID_3DLABS_PERMEDIA2V: usize = 0x0009; +pub const PCI_VENDOR_ID_NETXEN: usize = 0x4040; +pub const PCI_DEVICE_ID_NX2031_10GXSR: usize = 0x0001; +pub const PCI_DEVICE_ID_NX2031_10GCX4: usize = 0x0002; +pub const PCI_DEVICE_ID_NX2031_4GCU: usize = 0x0003; +pub const PCI_DEVICE_ID_NX2031_IMEZ: usize = 0x0004; +pub const PCI_DEVICE_ID_NX2031_HMEZ: usize = 0x0005; +pub const PCI_DEVICE_ID_NX2031_XG_MGMT: usize = 0x0024; +pub const PCI_DEVICE_ID_NX2031_XG_MGMT2: usize = 0x0025; +pub const PCI_DEVICE_ID_NX3031: usize = 0x0100; +pub const PCI_VENDOR_ID_AKS: usize = 0x416c; +pub const PCI_DEVICE_ID_AKS_ALADDINCARD: usize = 0x0100; +pub const PCI_VENDOR_ID_ACCESSIO: usize = 0x494f; +pub const PCI_DEVICE_ID_ACCESSIO_WDG_CSM: usize = 0x22c0; +pub const PCI_VENDOR_ID_S3: usize = 0x5333; +pub const PCI_DEVICE_ID_S3_TRIO: usize = 0x8811; +pub const PCI_DEVICE_ID_S3_868: usize = 0x8880; +pub const PCI_DEVICE_ID_S3_968: usize = 0x88f0; +pub const PCI_DEVICE_ID_S3_SAVAGE4: usize = 0x8a25; +pub const PCI_DEVICE_ID_S3_PROSAVAGE8: usize = 0x8d04; +pub const PCI_DEVICE_ID_S3_SONICVIBES: usize = 0xca00; +pub const PCI_VENDOR_ID_DUNORD: usize = 0x5544; +pub const PCI_DEVICE_ID_DUNORD_I3000: usize = 0x0001; +pub const PCI_VENDOR_ID_DCI: usize = 0x6666; +pub const PCI_DEVICE_ID_DCI_PCCOM4: usize = 0x0001; +pub const PCI_DEVICE_ID_DCI_PCCOM8: usize = 0x0002; +pub const PCI_DEVICE_ID_DCI_PCCOM2: usize = 0x0004; +pub const PCI_VENDOR_ID_INTEL: usize = 0x8086; +pub const PCI_DEVICE_ID_INTEL_EESSC: usize = 0x0008; +pub const PCI_DEVICE_ID_INTEL_PXHD_0: usize = 0x0320; +pub const PCI_DEVICE_ID_INTEL_PXHD_1: usize = 0x0321; +pub const PCI_DEVICE_ID_INTEL_PXH_0: usize = 0x0329; +pub const PCI_DEVICE_ID_INTEL_PXH_1: usize = 0x032A; +pub const PCI_DEVICE_ID_INTEL_PXHV: usize = 0x032C; +pub const PCI_DEVICE_ID_INTEL_80332_0: usize = 0x0330; +pub const PCI_DEVICE_ID_INTEL_80332_1: usize = 0x0332; +pub const PCI_DEVICE_ID_INTEL_80333_0: usize = 0x0370; +pub const PCI_DEVICE_ID_INTEL_80333_1: usize = 0x0372; +pub const PCI_DEVICE_ID_INTEL_QAT_DH895XCC: usize = 0x0435; +pub const PCI_DEVICE_ID_INTEL_QAT_DH895XCC_VF: usize = 0x0443; +pub const PCI_DEVICE_ID_INTEL_82375: usize = 0x0482; +pub const PCI_DEVICE_ID_INTEL_82424: usize = 0x0483; +pub const PCI_DEVICE_ID_INTEL_82378: usize = 0x0484; +pub const PCI_DEVICE_ID_INTEL_MRST_SD0: usize = 0x0807; +pub const PCI_DEVICE_ID_INTEL_MRST_SD1: usize = 0x0808; +pub const PCI_DEVICE_ID_INTEL_MFD_SD: usize = 0x0820; +pub const PCI_DEVICE_ID_INTEL_MFD_SDIO1: usize = 0x0821; +pub const PCI_DEVICE_ID_INTEL_MFD_SDIO2: usize = 0x0822; +pub const PCI_DEVICE_ID_INTEL_MFD_EMMC0: usize = 0x0823; +pub const PCI_DEVICE_ID_INTEL_MFD_EMMC1: usize = 0x0824; +pub const PCI_DEVICE_ID_INTEL_MRST_SD2: usize = 0x084F; +pub const PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB: usize = 0x095E; +pub const PCI_DEVICE_ID_INTEL_I960: usize = 0x0960; +pub const PCI_DEVICE_ID_INTEL_I960RM: usize = 0x0962; +pub const PCI_DEVICE_ID_INTEL_CENTERTON_ILB: usize = 0x0c60; +pub const PCI_DEVICE_ID_INTEL_8257X_SOL: usize = 0x1062; +pub const PCI_DEVICE_ID_INTEL_82573E_SOL: usize = 0x1085; +pub const PCI_DEVICE_ID_INTEL_82573L_SOL: usize = 0x108F; +pub const PCI_DEVICE_ID_INTEL_82815_MC: usize = 0x1130; +pub const PCI_DEVICE_ID_INTEL_82815_CGC: usize = 0x1132; +pub const PCI_DEVICE_ID_INTEL_82092AA_0: usize = 0x1221; +pub const PCI_DEVICE_ID_INTEL_7505_0: usize = 0x2550; +pub const PCI_DEVICE_ID_INTEL_7205_0: usize = 0x255d; +pub const PCI_DEVICE_ID_INTEL_82437: usize = 0x122d; +pub const PCI_DEVICE_ID_INTEL_82371FB_0: usize = 0x122e; +pub const PCI_DEVICE_ID_INTEL_82371FB_1: usize = 0x1230; +pub const PCI_DEVICE_ID_INTEL_82371MX: usize = 0x1234; +pub const PCI_DEVICE_ID_INTEL_82441: usize = 0x1237; +pub const PCI_DEVICE_ID_INTEL_82380FB: usize = 0x124b; +pub const PCI_DEVICE_ID_INTEL_82439: usize = 0x1250; +pub const PCI_DEVICE_ID_INTEL_LIGHT_RIDGE: usize = 0x1513; +pub const PCI_DEVICE_ID_INTEL_EAGLE_RIDGE: usize = 0x151a; +pub const PCI_DEVICE_ID_INTEL_LIGHT_PEAK: usize = 0x151b; +pub const PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C: usize = 0x1547; +pub const PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C: usize = 0x1548; +pub const PCI_DEVICE_ID_INTEL_PORT_RIDGE: usize = 0x1549; +pub const PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_NHI: usize = 0x1566; +pub const PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_BRIDGE: usize = 0x1567; +pub const PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_NHI: usize = 0x1568; +pub const PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_BRIDGE: usize = 0x1569; +pub const PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI: usize = 0x156a; +pub const PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE: usize = 0x156b; +pub const PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI: usize = 0x156c; +pub const PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE: usize = 0x156d; +pub const PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI: usize = 0x1575; +pub const PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE: usize = 0x1576; +pub const PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI: usize = 0x1577; +pub const PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE: usize = 0x1578; +pub const PCI_DEVICE_ID_INTEL_80960_RP: usize = 0x1960; +pub const PCI_DEVICE_ID_INTEL_QAT_C3XXX: usize = 0x19e2; +pub const PCI_DEVICE_ID_INTEL_QAT_C3XXX_VF: usize = 0x19e3; +pub const PCI_DEVICE_ID_INTEL_82840_HB: usize = 0x1a21; +pub const PCI_DEVICE_ID_INTEL_82845_HB: usize = 0x1a30; +pub const PCI_DEVICE_ID_INTEL_IOAT: usize = 0x1a38; +pub const PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN: usize = 0x1c41; +pub const PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX: usize = 0x1c5f; +pub const PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0: usize = 0x1d40; +pub const PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1: usize = 0x1d41; +pub const PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI: usize = 0x1e31; +pub const PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN: usize = 0x1e40; +pub const PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX: usize = 0x1e5f; +pub const PCI_DEVICE_ID_INTEL_VMD_201D: usize = 0x201d; +pub const PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN: usize = 0x2310; +pub const PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX: usize = 0x231f; +pub const PCI_DEVICE_ID_INTEL_82801AA_0: usize = 0x2410; +pub const PCI_DEVICE_ID_INTEL_82801AA_1: usize = 0x2411; +pub const PCI_DEVICE_ID_INTEL_82801AA_3: usize = 0x2413; +pub const PCI_DEVICE_ID_INTEL_82801AA_5: usize = 0x2415; +pub const PCI_DEVICE_ID_INTEL_82801AA_6: usize = 0x2416; +pub const PCI_DEVICE_ID_INTEL_82801AA_8: usize = 0x2418; +pub const PCI_DEVICE_ID_INTEL_82801AB_0: usize = 0x2420; +pub const PCI_DEVICE_ID_INTEL_82801AB_1: usize = 0x2421; +pub const PCI_DEVICE_ID_INTEL_82801AB_3: usize = 0x2423; +pub const PCI_DEVICE_ID_INTEL_82801AB_5: usize = 0x2425; +pub const PCI_DEVICE_ID_INTEL_82801AB_6: usize = 0x2426; +pub const PCI_DEVICE_ID_INTEL_82801AB_8: usize = 0x2428; +pub const PCI_DEVICE_ID_INTEL_82801BA_0: usize = 0x2440; +pub const PCI_DEVICE_ID_INTEL_82801BA_2: usize = 0x2443; +pub const PCI_DEVICE_ID_INTEL_82801BA_4: usize = 0x2445; +pub const PCI_DEVICE_ID_INTEL_82801BA_6: usize = 0x2448; +pub const PCI_DEVICE_ID_INTEL_82801BA_8: usize = 0x244a; +pub const PCI_DEVICE_ID_INTEL_82801BA_9: usize = 0x244b; +pub const PCI_DEVICE_ID_INTEL_82801BA_10: usize = 0x244c; +pub const PCI_DEVICE_ID_INTEL_82801BA_11: usize = 0x244e; +pub const PCI_DEVICE_ID_INTEL_82801E_0: usize = 0x2450; +pub const PCI_DEVICE_ID_INTEL_82801E_11: usize = 0x245b; +pub const PCI_DEVICE_ID_INTEL_82801CA_0: usize = 0x2480; +pub const PCI_DEVICE_ID_INTEL_82801CA_3: usize = 0x2483; +pub const PCI_DEVICE_ID_INTEL_82801CA_5: usize = 0x2485; +pub const PCI_DEVICE_ID_INTEL_82801CA_6: usize = 0x2486; +pub const PCI_DEVICE_ID_INTEL_82801CA_10: usize = 0x248a; +pub const PCI_DEVICE_ID_INTEL_82801CA_11: usize = 0x248b; +pub const PCI_DEVICE_ID_INTEL_82801CA_12: usize = 0x248c; +pub const PCI_DEVICE_ID_INTEL_82801DB_0: usize = 0x24c0; +pub const PCI_DEVICE_ID_INTEL_82801DB_1: usize = 0x24c1; +pub const PCI_DEVICE_ID_INTEL_82801DB_2: usize = 0x24c2; +pub const PCI_DEVICE_ID_INTEL_82801DB_3: usize = 0x24c3; +pub const PCI_DEVICE_ID_INTEL_82801DB_5: usize = 0x24c5; +pub const PCI_DEVICE_ID_INTEL_82801DB_6: usize = 0x24c6; +pub const PCI_DEVICE_ID_INTEL_82801DB_9: usize = 0x24c9; +pub const PCI_DEVICE_ID_INTEL_82801DB_10: usize = 0x24ca; +pub const PCI_DEVICE_ID_INTEL_82801DB_11: usize = 0x24cb; +pub const PCI_DEVICE_ID_INTEL_82801DB_12: usize = 0x24cc; +pub const PCI_DEVICE_ID_INTEL_82801EB_0: usize = 0x24d0; +pub const PCI_DEVICE_ID_INTEL_82801EB_1: usize = 0x24d1; +pub const PCI_DEVICE_ID_INTEL_82801EB_3: usize = 0x24d3; +pub const PCI_DEVICE_ID_INTEL_82801EB_5: usize = 0x24d5; +pub const PCI_DEVICE_ID_INTEL_82801EB_6: usize = 0x24d6; +pub const PCI_DEVICE_ID_INTEL_82801EB_11: usize = 0x24db; +pub const PCI_DEVICE_ID_INTEL_82801EB_12: usize = 0x24dc; +pub const PCI_DEVICE_ID_INTEL_82801EB_13: usize = 0x24dd; +pub const PCI_DEVICE_ID_INTEL_ESB_1: usize = 0x25a1; +pub const PCI_DEVICE_ID_INTEL_ESB_2: usize = 0x25a2; +pub const PCI_DEVICE_ID_INTEL_ESB_4: usize = 0x25a4; +pub const PCI_DEVICE_ID_INTEL_ESB_5: usize = 0x25a6; +pub const PCI_DEVICE_ID_INTEL_ESB_9: usize = 0x25ab; +pub const PCI_DEVICE_ID_INTEL_ESB_10: usize = 0x25ac; +pub const PCI_DEVICE_ID_INTEL_82820_HB: usize = 0x2500; +pub const PCI_DEVICE_ID_INTEL_82820_UP_HB: usize = 0x2501; +pub const PCI_DEVICE_ID_INTEL_82850_HB: usize = 0x2530; +pub const PCI_DEVICE_ID_INTEL_82860_HB: usize = 0x2531; +pub const PCI_DEVICE_ID_INTEL_E7501_MCH: usize = 0x254c; +pub const PCI_DEVICE_ID_INTEL_82845G_HB: usize = 0x2560; +pub const PCI_DEVICE_ID_INTEL_82845G_IG: usize = 0x2562; +pub const PCI_DEVICE_ID_INTEL_82865_HB: usize = 0x2570; +pub const PCI_DEVICE_ID_INTEL_82865_IG: usize = 0x2572; +pub const PCI_DEVICE_ID_INTEL_82875_HB: usize = 0x2578; +pub const PCI_DEVICE_ID_INTEL_82915G_HB: usize = 0x2580; +pub const PCI_DEVICE_ID_INTEL_82915G_IG: usize = 0x2582; +pub const PCI_DEVICE_ID_INTEL_82915GM_HB: usize = 0x2590; +pub const PCI_DEVICE_ID_INTEL_82915GM_IG: usize = 0x2592; +pub const PCI_DEVICE_ID_INTEL_5000_ERR: usize = 0x25F0; +pub const PCI_DEVICE_ID_INTEL_5000_FBD0: usize = 0x25F5; +pub const PCI_DEVICE_ID_INTEL_5000_FBD1: usize = 0x25F6; +pub const PCI_DEVICE_ID_INTEL_82945G_HB: usize = 0x2770; +pub const PCI_DEVICE_ID_INTEL_82945G_IG: usize = 0x2772; +pub const PCI_DEVICE_ID_INTEL_3000_HB: usize = 0x2778; +pub const PCI_DEVICE_ID_INTEL_82945GM_HB: usize = 0x27A0; +pub const PCI_DEVICE_ID_INTEL_82945GM_IG: usize = 0x27A2; +pub const PCI_DEVICE_ID_INTEL_ICH6_0: usize = 0x2640; +pub const PCI_DEVICE_ID_INTEL_ICH6_1: usize = 0x2641; +pub const PCI_DEVICE_ID_INTEL_ICH6_2: usize = 0x2642; +pub const PCI_DEVICE_ID_INTEL_ICH6_16: usize = 0x266a; +pub const PCI_DEVICE_ID_INTEL_ICH6_17: usize = 0x266d; +pub const PCI_DEVICE_ID_INTEL_ICH6_18: usize = 0x266e; +pub const PCI_DEVICE_ID_INTEL_ICH6_19: usize = 0x266f; +pub const PCI_DEVICE_ID_INTEL_ESB2_0: usize = 0x2670; +pub const PCI_DEVICE_ID_INTEL_ESB2_14: usize = 0x2698; +pub const PCI_DEVICE_ID_INTEL_ESB2_17: usize = 0x269b; +pub const PCI_DEVICE_ID_INTEL_ESB2_18: usize = 0x269e; +pub const PCI_DEVICE_ID_INTEL_ICH7_0: usize = 0x27b8; +pub const PCI_DEVICE_ID_INTEL_ICH7_1: usize = 0x27b9; +pub const PCI_DEVICE_ID_INTEL_ICH7_30: usize = 0x27b0; +pub const PCI_DEVICE_ID_INTEL_TGP_LPC: usize = 0x27bc; +pub const PCI_DEVICE_ID_INTEL_ICH7_31: usize = 0x27bd; +pub const PCI_DEVICE_ID_INTEL_ICH7_17: usize = 0x27da; +pub const PCI_DEVICE_ID_INTEL_ICH7_19: usize = 0x27dd; +pub const PCI_DEVICE_ID_INTEL_ICH7_20: usize = 0x27de; +pub const PCI_DEVICE_ID_INTEL_ICH7_21: usize = 0x27df; +pub const PCI_DEVICE_ID_INTEL_ICH8_0: usize = 0x2810; +pub const PCI_DEVICE_ID_INTEL_ICH8_1: usize = 0x2811; +pub const PCI_DEVICE_ID_INTEL_ICH8_2: usize = 0x2812; +pub const PCI_DEVICE_ID_INTEL_ICH8_3: usize = 0x2814; +pub const PCI_DEVICE_ID_INTEL_ICH8_4: usize = 0x2815; +pub const PCI_DEVICE_ID_INTEL_ICH8_5: usize = 0x283e; +pub const PCI_DEVICE_ID_INTEL_ICH8_6: usize = 0x2850; +pub const PCI_DEVICE_ID_INTEL_VMD_28C0: usize = 0x28c0; +pub const PCI_DEVICE_ID_INTEL_ICH9_0: usize = 0x2910; +pub const PCI_DEVICE_ID_INTEL_ICH9_1: usize = 0x2917; +pub const PCI_DEVICE_ID_INTEL_ICH9_2: usize = 0x2912; +pub const PCI_DEVICE_ID_INTEL_ICH9_3: usize = 0x2913; +pub const PCI_DEVICE_ID_INTEL_ICH9_4: usize = 0x2914; +pub const PCI_DEVICE_ID_INTEL_ICH9_5: usize = 0x2919; +pub const PCI_DEVICE_ID_INTEL_ICH9_6: usize = 0x2930; +pub const PCI_DEVICE_ID_INTEL_ICH9_7: usize = 0x2916; +pub const PCI_DEVICE_ID_INTEL_ICH9_8: usize = 0x2918; +pub const PCI_DEVICE_ID_INTEL_I7_MCR: usize = 0x2c18; +pub const PCI_DEVICE_ID_INTEL_I7_MC_TAD: usize = 0x2c19; +pub const PCI_DEVICE_ID_INTEL_I7_MC_RAS: usize = 0x2c1a; +pub const PCI_DEVICE_ID_INTEL_I7_MC_TEST: usize = 0x2c1c; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL: usize = 0x2c20; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR: usize = 0x2c21; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK: usize = 0x2c22; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC: usize = 0x2c23; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL: usize = 0x2c28; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR: usize = 0x2c29; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK: usize = 0x2c2a; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC: usize = 0x2c2b; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL: usize = 0x2c30; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR: usize = 0x2c31; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK: usize = 0x2c32; +pub const PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC: usize = 0x2c33; +pub const PCI_DEVICE_ID_INTEL_I7_NONCORE: usize = 0x2c41; +pub const PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT: usize = 0x2c40; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE: usize = 0x2c50; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT: usize = 0x2c51; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2: usize = 0x2c70; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_SAD: usize = 0x2c81; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0: usize = 0x2c90; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_PHY0: usize = 0x2c91; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR: usize = 0x2c98; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD: usize = 0x2c99; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST: usize = 0x2c9C; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL: usize = 0x2ca0; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR: usize = 0x2ca1; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK: usize = 0x2ca2; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC: usize = 0x2ca3; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL: usize = 0x2ca8; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR: usize = 0x2ca9; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK: usize = 0x2caa; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC: usize = 0x2cab; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2: usize = 0x2d98; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2: usize = 0x2d99; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2: usize = 0x2d9a; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2: usize = 0x2d9c; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2: usize = 0x2da0; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2: usize = 0x2da1; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2: usize = 0x2da2; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2: usize = 0x2da3; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2: usize = 0x2da8; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2: usize = 0x2da9; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2: usize = 0x2daa; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2: usize = 0x2dab; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2: usize = 0x2db0; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2: usize = 0x2db1; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2: usize = 0x2db2; +pub const PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2: usize = 0x2db3; +pub const PCI_DEVICE_ID_INTEL_82855PM_HB: usize = 0x3340; +pub const PCI_DEVICE_ID_INTEL_IOAT_TBG4: usize = 0x3429; +pub const PCI_DEVICE_ID_INTEL_IOAT_TBG5: usize = 0x342a; +pub const PCI_DEVICE_ID_INTEL_IOAT_TBG6: usize = 0x342b; +pub const PCI_DEVICE_ID_INTEL_IOAT_TBG7: usize = 0x342c; +pub const PCI_DEVICE_ID_INTEL_X58_HUB_MGMT: usize = 0x342e; +pub const PCI_DEVICE_ID_INTEL_IOAT_TBG0: usize = 0x3430; +pub const PCI_DEVICE_ID_INTEL_IOAT_TBG1: usize = 0x3431; +pub const PCI_DEVICE_ID_INTEL_IOAT_TBG2: usize = 0x3432; +pub const PCI_DEVICE_ID_INTEL_IOAT_TBG3: usize = 0x3433; +pub const PCI_DEVICE_ID_INTEL_82830_HB: usize = 0x3575; +pub const PCI_DEVICE_ID_INTEL_82830_CGC: usize = 0x3577; +pub const PCI_DEVICE_ID_INTEL_82854_HB: usize = 0x358c; +pub const PCI_DEVICE_ID_INTEL_82854_IG: usize = 0x358e; +pub const PCI_DEVICE_ID_INTEL_82855GM_HB: usize = 0x3580; +pub const PCI_DEVICE_ID_INTEL_82855GM_IG: usize = 0x3582; +pub const PCI_DEVICE_ID_INTEL_E7520_MCH: usize = 0x3590; +pub const PCI_DEVICE_ID_INTEL_E7320_MCH: usize = 0x3592; +pub const PCI_DEVICE_ID_INTEL_MCH_PA: usize = 0x3595; +pub const PCI_DEVICE_ID_INTEL_MCH_PA1: usize = 0x3596; +pub const PCI_DEVICE_ID_INTEL_MCH_PB: usize = 0x3597; +pub const PCI_DEVICE_ID_INTEL_MCH_PB1: usize = 0x3598; +pub const PCI_DEVICE_ID_INTEL_MCH_PC: usize = 0x3599; +pub const PCI_DEVICE_ID_INTEL_MCH_PC1: usize = 0x359a; +pub const PCI_DEVICE_ID_INTEL_E7525_MCH: usize = 0x359e; +pub const PCI_DEVICE_ID_INTEL_I7300_MCH_ERR: usize = 0x360c; +pub const PCI_DEVICE_ID_INTEL_I7300_MCH_FB0: usize = 0x360f; +pub const PCI_DEVICE_ID_INTEL_I7300_MCH_FB1: usize = 0x3610; +pub const PCI_DEVICE_ID_INTEL_IOAT_CNB: usize = 0x360b; +pub const PCI_DEVICE_ID_INTEL_FBD_CNB: usize = 0x360c; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF0: usize = 0x3710; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF1: usize = 0x3711; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF2: usize = 0x3712; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF3: usize = 0x3713; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF4: usize = 0x3714; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF5: usize = 0x3715; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF6: usize = 0x3716; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF7: usize = 0x3717; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF8: usize = 0x3718; +pub const PCI_DEVICE_ID_INTEL_IOAT_JSF9: usize = 0x3719; +pub const PCI_DEVICE_ID_INTEL_QAT_C62X: usize = 0x37c8; +pub const PCI_DEVICE_ID_INTEL_QAT_C62X_VF: usize = 0x37c9; +pub const PCI_DEVICE_ID_INTEL_ICH10_0: usize = 0x3a14; +pub const PCI_DEVICE_ID_INTEL_ICH10_1: usize = 0x3a16; +pub const PCI_DEVICE_ID_INTEL_ICH10_2: usize = 0x3a18; +pub const PCI_DEVICE_ID_INTEL_ICH10_3: usize = 0x3a1a; +pub const PCI_DEVICE_ID_INTEL_ICH10_4: usize = 0x3a30; +pub const PCI_DEVICE_ID_INTEL_ICH10_5: usize = 0x3a60; +pub const PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN: usize = 0x3b00; +pub const PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX: usize = 0x3b1f; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB0: usize = 0x3c20; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB1: usize = 0x3c21; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB2: usize = 0x3c22; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB3: usize = 0x3c23; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB4: usize = 0x3c24; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB5: usize = 0x3c25; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB6: usize = 0x3c26; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB7: usize = 0x3c27; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB8: usize = 0x3c2e; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB9: usize = 0x3c2f; +pub const PCI_DEVICE_ID_INTEL_UNC_HA: usize = 0x3c46; +pub const PCI_DEVICE_ID_INTEL_UNC_IMC0: usize = 0x3cb0; +pub const PCI_DEVICE_ID_INTEL_UNC_IMC1: usize = 0x3cb1; +pub const PCI_DEVICE_ID_INTEL_UNC_IMC2: usize = 0x3cb4; +pub const PCI_DEVICE_ID_INTEL_UNC_IMC3: usize = 0x3cb5; +pub const PCI_DEVICE_ID_INTEL_UNC_QPI0: usize = 0x3c41; +pub const PCI_DEVICE_ID_INTEL_UNC_QPI1: usize = 0x3c42; +pub const PCI_DEVICE_ID_INTEL_UNC_R2PCIE: usize = 0x3c43; +pub const PCI_DEVICE_ID_INTEL_UNC_R3QPI0: usize = 0x3c44; +pub const PCI_DEVICE_ID_INTEL_UNC_R3QPI1: usize = 0x3c45; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: usize = 0x3c71; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0: usize = 0x3c72; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1: usize = 0x3c73; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2: usize = 0x3c76; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3: usize = 0x3c77; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: usize = 0x3ca0; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: usize = 0x3ca8; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: usize = 0x3caa; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: usize = 0x3cab; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: usize = 0x3cac; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: usize = 0x3cad; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: usize = 0x3cb8; +pub const PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX: usize = 0x3ce0; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: usize = 0x3cf4; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_BR: usize = 0x3cf5; +pub const PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: usize = 0x3cf6; +pub const PCI_DEVICE_ID_INTEL_IOAT_SNB: usize = 0x402f; +pub const PCI_DEVICE_ID_INTEL_5100_16: usize = 0x65f0; +pub const PCI_DEVICE_ID_INTEL_5100_19: usize = 0x65f3; +pub const PCI_DEVICE_ID_INTEL_5100_21: usize = 0x65f5; +pub const PCI_DEVICE_ID_INTEL_5100_22: usize = 0x65f6; +pub const PCI_DEVICE_ID_INTEL_5400_ERR: usize = 0x4030; +pub const PCI_DEVICE_ID_INTEL_5400_FBD0: usize = 0x4035; +pub const PCI_DEVICE_ID_INTEL_5400_FBD1: usize = 0x4036; +pub const PCI_DEVICE_ID_INTEL_IOAT_SCNB: usize = 0x65ff; +pub const PCI_DEVICE_ID_INTEL_EP80579_0: usize = 0x5031; +pub const PCI_DEVICE_ID_INTEL_EP80579_1: usize = 0x5032; +pub const PCI_DEVICE_ID_INTEL_82371SB_0: usize = 0x7000; +pub const PCI_DEVICE_ID_INTEL_82371SB_1: usize = 0x7010; +pub const PCI_DEVICE_ID_INTEL_82371SB_2: usize = 0x7020; +pub const PCI_DEVICE_ID_INTEL_82437VX: usize = 0x7030; +pub const PCI_DEVICE_ID_INTEL_82439TX: usize = 0x7100; +pub const PCI_DEVICE_ID_INTEL_82371AB_0: usize = 0x7110; +pub const PCI_DEVICE_ID_INTEL_82371AB: usize = 0x7111; +pub const PCI_DEVICE_ID_INTEL_82371AB_2: usize = 0x7112; +pub const PCI_DEVICE_ID_INTEL_82371AB_3: usize = 0x7113; +pub const PCI_DEVICE_ID_INTEL_82810_MC1: usize = 0x7120; +pub const PCI_DEVICE_ID_INTEL_82810_IG1: usize = 0x7121; +pub const PCI_DEVICE_ID_INTEL_82810_MC3: usize = 0x7122; +pub const PCI_DEVICE_ID_INTEL_82810_IG3: usize = 0x7123; +pub const PCI_DEVICE_ID_INTEL_82810E_MC: usize = 0x7124; +pub const PCI_DEVICE_ID_INTEL_82810E_IG: usize = 0x7125; +pub const PCI_DEVICE_ID_INTEL_82443LX_0: usize = 0x7180; +pub const PCI_DEVICE_ID_INTEL_82443LX_1: usize = 0x7181; +pub const PCI_DEVICE_ID_INTEL_82443BX_0: usize = 0x7190; +pub const PCI_DEVICE_ID_INTEL_82443BX_1: usize = 0x7191; +pub const PCI_DEVICE_ID_INTEL_82443BX_2: usize = 0x7192; +pub const PCI_DEVICE_ID_INTEL_440MX: usize = 0x7195; +pub const PCI_DEVICE_ID_INTEL_440MX_6: usize = 0x7196; +pub const PCI_DEVICE_ID_INTEL_82443MX_0: usize = 0x7198; +pub const PCI_DEVICE_ID_INTEL_82443MX_1: usize = 0x7199; +pub const PCI_DEVICE_ID_INTEL_82443MX_3: usize = 0x719b; +pub const PCI_DEVICE_ID_INTEL_82443GX_0: usize = 0x71a0; +pub const PCI_DEVICE_ID_INTEL_82443GX_2: usize = 0x71a2; +pub const PCI_DEVICE_ID_INTEL_82372FB_1: usize = 0x7601; +pub const PCI_DEVICE_ID_INTEL_SCH_LPC: usize = 0x8119; +pub const PCI_DEVICE_ID_INTEL_SCH_IDE: usize = 0x811a; +pub const PCI_DEVICE_ID_INTEL_E6XX_CU: usize = 0x8183; +pub const PCI_DEVICE_ID_INTEL_ITC_LPC: usize = 0x8186; +pub const PCI_DEVICE_ID_INTEL_82454GX: usize = 0x84c4; +pub const PCI_DEVICE_ID_INTEL_82450GX: usize = 0x84c5; +pub const PCI_DEVICE_ID_INTEL_82451NX: usize = 0x84ca; +pub const PCI_DEVICE_ID_INTEL_82454NX: usize = 0x84cb; +pub const PCI_DEVICE_ID_INTEL_84460GX: usize = 0x84ea; +pub const PCI_DEVICE_ID_INTEL_IXP4XX: usize = 0x8500; +pub const PCI_DEVICE_ID_INTEL_IXP2800: usize = 0x9004; +pub const PCI_DEVICE_ID_INTEL_VMD_9A0B: usize = 0x9a0b; +pub const PCI_DEVICE_ID_INTEL_S21152BB: usize = 0xb152; +pub const PCI_VENDOR_ID_WANGXUN: usize = 0x8088; +pub const PCI_VENDOR_ID_SCALEMP: usize = 0x8686; +pub const PCI_DEVICE_ID_SCALEMP_VSMP_CTL: usize = 0x1010; +pub const PCI_VENDOR_ID_COMPUTONE: usize = 0x8e0e; +pub const PCI_DEVICE_ID_COMPUTONE_PG: usize = 0x0302; +pub const PCI_SUBVENDOR_ID_COMPUTONE: usize = 0x8e0e; +pub const PCI_SUBDEVICE_ID_COMPUTONE_PG4: usize = 0x0001; +pub const PCI_SUBDEVICE_ID_COMPUTONE_PG8: usize = 0x0002; +pub const PCI_SUBDEVICE_ID_COMPUTONE_PG6: usize = 0x0003; +pub const PCI_VENDOR_ID_KTI: usize = 0x8e2e; +pub const PCI_VENDOR_ID_ADAPTEC: usize = 0x9004; +pub const PCI_DEVICE_ID_ADAPTEC_7810: usize = 0x1078; +pub const PCI_DEVICE_ID_ADAPTEC_7821: usize = 0x2178; +pub const PCI_DEVICE_ID_ADAPTEC_38602: usize = 0x3860; +pub const PCI_DEVICE_ID_ADAPTEC_7850: usize = 0x5078; +pub const PCI_DEVICE_ID_ADAPTEC_7855: usize = 0x5578; +pub const PCI_DEVICE_ID_ADAPTEC_3860: usize = 0x6038; +pub const PCI_DEVICE_ID_ADAPTEC_1480A: usize = 0x6075; +pub const PCI_DEVICE_ID_ADAPTEC_7860: usize = 0x6078; +pub const PCI_DEVICE_ID_ADAPTEC_7861: usize = 0x6178; +pub const PCI_DEVICE_ID_ADAPTEC_7870: usize = 0x7078; +pub const PCI_DEVICE_ID_ADAPTEC_7871: usize = 0x7178; +pub const PCI_DEVICE_ID_ADAPTEC_7872: usize = 0x7278; +pub const PCI_DEVICE_ID_ADAPTEC_7873: usize = 0x7378; +pub const PCI_DEVICE_ID_ADAPTEC_7874: usize = 0x7478; +pub const PCI_DEVICE_ID_ADAPTEC_7895: usize = 0x7895; +pub const PCI_DEVICE_ID_ADAPTEC_7880: usize = 0x8078; +pub const PCI_DEVICE_ID_ADAPTEC_7881: usize = 0x8178; +pub const PCI_DEVICE_ID_ADAPTEC_7882: usize = 0x8278; +pub const PCI_DEVICE_ID_ADAPTEC_7883: usize = 0x8378; +pub const PCI_DEVICE_ID_ADAPTEC_7884: usize = 0x8478; +pub const PCI_DEVICE_ID_ADAPTEC_7885: usize = 0x8578; +pub const PCI_DEVICE_ID_ADAPTEC_7886: usize = 0x8678; +pub const PCI_DEVICE_ID_ADAPTEC_7887: usize = 0x8778; +pub const PCI_DEVICE_ID_ADAPTEC_7888: usize = 0x8878; +pub const PCI_VENDOR_ID_ADAPTEC2: usize = 0x9005; +pub const PCI_DEVICE_ID_ADAPTEC2_2940U2: usize = 0x0010; +pub const PCI_DEVICE_ID_ADAPTEC2_2930U2: usize = 0x0011; +pub const PCI_DEVICE_ID_ADAPTEC2_7890B: usize = 0x0013; +pub const PCI_DEVICE_ID_ADAPTEC2_7890: usize = 0x001f; +pub const PCI_DEVICE_ID_ADAPTEC2_3940U2: usize = 0x0050; +pub const PCI_DEVICE_ID_ADAPTEC2_3950U2D: usize = 0x0051; +pub const PCI_DEVICE_ID_ADAPTEC2_7896: usize = 0x005f; +pub const PCI_DEVICE_ID_ADAPTEC2_7892A: usize = 0x0080; +pub const PCI_DEVICE_ID_ADAPTEC2_7892B: usize = 0x0081; +pub const PCI_DEVICE_ID_ADAPTEC2_7892D: usize = 0x0083; +pub const PCI_DEVICE_ID_ADAPTEC2_7892P: usize = 0x008f; +pub const PCI_DEVICE_ID_ADAPTEC2_7899A: usize = 0x00c0; +pub const PCI_DEVICE_ID_ADAPTEC2_7899B: usize = 0x00c1; +pub const PCI_DEVICE_ID_ADAPTEC2_7899D: usize = 0x00c3; +pub const PCI_DEVICE_ID_ADAPTEC2_7899P: usize = 0x00cf; +pub const PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN: usize = 0x0500; +pub const PCI_DEVICE_ID_ADAPTEC2_SCAMP: usize = 0x0503; +pub const PCI_VENDOR_ID_HOLTEK: usize = 0x9412; +pub const PCI_DEVICE_ID_HOLTEK_6565: usize = 0x6565; +pub const PCI_VENDOR_ID_NETMOS: usize = 0x9710; +pub const PCI_DEVICE_ID_NETMOS_9705: usize = 0x9705; +pub const PCI_DEVICE_ID_NETMOS_9715: usize = 0x9715; +pub const PCI_DEVICE_ID_NETMOS_9735: usize = 0x9735; +pub const PCI_DEVICE_ID_NETMOS_9745: usize = 0x9745; +pub const PCI_DEVICE_ID_NETMOS_9755: usize = 0x9755; +pub const PCI_DEVICE_ID_NETMOS_9805: usize = 0x9805; +pub const PCI_DEVICE_ID_NETMOS_9815: usize = 0x9815; +pub const PCI_DEVICE_ID_NETMOS_9835: usize = 0x9835; +pub const PCI_DEVICE_ID_NETMOS_9845: usize = 0x9845; +pub const PCI_DEVICE_ID_NETMOS_9855: usize = 0x9855; +pub const PCI_DEVICE_ID_NETMOS_9865: usize = 0x9865; +pub const PCI_DEVICE_ID_NETMOS_9900: usize = 0x9900; +pub const PCI_DEVICE_ID_NETMOS_9901: usize = 0x9901; +pub const PCI_DEVICE_ID_NETMOS_9904: usize = 0x9904; +pub const PCI_DEVICE_ID_NETMOS_9912: usize = 0x9912; +pub const PCI_DEVICE_ID_NETMOS_9922: usize = 0x9922; +pub const PCI_VENDOR_ID_3COM_2: usize = 0xa727; +pub const PCI_VENDOR_ID_SOLIDRUN: usize = 0xd063; +pub const PCI_VENDOR_ID_DIGIUM: usize = 0xd161; +pub const PCI_DEVICE_ID_DIGIUM_HFC4S: usize = 0xb410; +pub const PCI_SUBVENDOR_ID_EXSYS: usize = 0xd84d; +pub const PCI_SUBDEVICE_ID_EXSYS_4014: usize = 0x4014; +pub const PCI_SUBDEVICE_ID_EXSYS_4055: usize = 0x4055; +pub const PCI_VENDOR_ID_TIGERJET: usize = 0xe159; +pub const PCI_DEVICE_ID_TIGERJET_300: usize = 0x0001; +pub const PCI_DEVICE_ID_TIGERJET_100: usize = 0x0002; +pub const PCI_VENDOR_ID_XILINX_RME: usize = 0xea60; +pub const PCI_DEVICE_ID_RME_DIGI32: usize = 0x9896; +pub const PCI_DEVICE_ID_RME_DIGI32_PRO: usize = 0x9897; +pub const PCI_DEVICE_ID_RME_DIGI32_8: usize = 0x9898; +pub const PCI_VENDOR_ID_XEN: usize = 0x5853; +pub const PCI_DEVICE_ID_XEN_PLATFORM: usize = 0x0001; +pub const PCI_VENDOR_ID_OCZ: usize = 0x1b85; +pub const PCI_VENDOR_ID_NCUBE: usize = 0x10ff; +pub const PCI_VENDOR_ID_PHYTIUM: usize = 0x1db7; diff --git a/crates/driver_pci/src/err.rs b/crates/driver_pci/src/err.rs new file mode 100644 index 0000000000..a0e1d49b6e --- /dev/null +++ b/crates/driver_pci/src/err.rs @@ -0,0 +1,18 @@ +use core::fmt::{Display, Formatter}; + +/// Errors accessing a PCI device. +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum PciError { + /// The device reported an invalid BAR type. + InvalidBarType, +} + +impl Display for PciError { + fn fmt(&self, f: &mut Formatter) -> core::fmt::Result { + match self { + Self::InvalidBarType => write!(f, "Invalid PCI BAR type."), + } + } +} + +pub type Result = core::result::Result; diff --git a/crates/driver_pci/src/lib.rs b/crates/driver_pci/src/lib.rs index 4ae0b9b978..34f5fa7607 100644 --- a/crates/driver_pci/src/lib.rs +++ b/crates/driver_pci/src/lib.rs @@ -7,47 +7,52 @@ //! [2]: https://docs.rs/virtio-drivers/latest/virtio_drivers/transport/pci/bus/index.html #![no_std] +#![allow(warnings)] -pub use virtio_drivers::transport::pci::bus::{BarInfo, Cam, HeaderType, MemoryBarType, PciError}; -pub use virtio_drivers::transport::pci::bus::{ - CapabilityInfo, Command, DeviceFunction, DeviceFunctionInfo, PciRoot, Status, -}; +extern crate alloc; +pub mod device_types; +pub mod err; +mod root_complex; +pub mod types; +use core::ops::Range; -/// Used to allocate MMIO regions for PCI BARs. -pub struct PciRangeAllocator { - _start: u64, - end: u64, - current: u64, -} +pub use root_complex::*; +use types::ConifgPciPciBridge; +// #[cfg(feature = "phytiym_pci")] +// mod bcm2711; +mod phytium; -impl PciRangeAllocator { - /// Creates a new allocator from a memory range. - pub const fn new(base: u64, size: u64) -> Self { - Self { - _start: base, - end: base + size, - current: base, - } - } +// pub use virtio_drivers::transport::pci::bus::{BarInfo}; - /// Allocates a memory region with the given size. - /// - /// The `size` should be a power of 2, and the returned value is also a - /// multiple of `size`. - pub fn alloc(&mut self, size: u64) -> Option { - if !size.is_power_of_two() { - return None; - } - let ret = align_up(self.current, size); - if ret + size > self.end { - return None; - } - - self.current = ret + size; - Some(ret) +#[derive(Clone, Copy)] +pub struct PciAddress { + pub bus: usize, + pub device: usize, + pub function: usize, +} +impl core::fmt::Display for PciAddress { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "{:02x}:{:02x}.{}", self.bus, self.device, self.function) } } -const fn align_up(addr: u64, align: u64) -> u64 { - (addr + align - 1) & !(align - 1) +// #[cfg(platform = "aarch64-raspi4")] +// #[cfg(feature = "bcm2711")] +#[cfg(feature = "phytium-pci")] +pub type RootComplex = PciRootComplex; + +// pub type RootComplex = PciRootComplex; + +pub type PciRoot = RootComplex; +pub type DeviceFunction = PciAddress; +pub type BarInfo = types::Bar; + +pub fn new_root_complex(mmio_base: usize, bar_range: Range) -> RootComplex { + PciRootComplex::new(mmio_base, bar_range) +} + +pub trait Access { + fn setup(mmio_base: usize); + fn probe_bridge(mmio_base: usize, bridge_header: &ConifgPciPciBridge); + fn map_conf(mmio_base: usize, addr: PciAddress) -> Option; } diff --git a/crates/driver_pci/src/phytium/mod.rs b/crates/driver_pci/src/phytium/mod.rs new file mode 100644 index 0000000000..7f8cb003a2 --- /dev/null +++ b/crates/driver_pci/src/phytium/mod.rs @@ -0,0 +1,61 @@ +use log::debug; + +use crate::{types::ConfigCommand, Access, PciAddress}; + +#[derive(Clone)] +pub struct PhytiumPCIeDummy {} + +const RGR1_SW_INIT_1: usize = 0x9210; +const EXT_CFG_INDEX: usize = 0x9000; +const EXT_CFG_DATA: usize = 0x8000; + +fn cfg_index(addr: PciAddress) -> usize { + ((addr.device as u32) << 15 | (addr.function as u32) << 12 | (addr.bus as u32) << 20) as usize +} + +impl Access for PhytiumPCIeDummy { + fn setup(mmio_base: usize) { + debug!("PCIe link start @0x{:X}...", mmio_base); + debug!( + "theroticly, since uboot had already initialized it, we need't to operate it any more!" + ) + } + + fn probe_bridge(mmio_base: usize, bridge_header: &crate::types::ConifgPciPciBridge) { + debug!("bridge phytium weird pcie chip"); + + bridge_header.set_cache_line_size(64 / 4); + bridge_header.set_memory_base((0xF8000000u32 >> 16) as u16); + bridge_header.set_memory_limit((0xF8000000u32 >> 16) as u16); + bridge_header.set_control(0x01); + unsafe { + (bridge_header.cfg_addr as *mut u8) + .offset(0xac + 0x1c) + .write_volatile(0x10); + } + + bridge_header.to_header().set_command([ + ConfigCommand::MemorySpaceEnable, + ConfigCommand::BusMasterEnable, + ConfigCommand::ParityErrorResponse, + ConfigCommand::SERREnable, + ]) + } + + fn map_conf(mmio_base: usize, addr: crate::PciAddress) -> Option { + // // bus 0 bus 1 只有一个Device + // if addr.bus <= 2 && addr.device > 0 { + // return None; + // } + + if addr.bus == 0 { + return Some(mmio_base); + } + + let idx = cfg_index(addr); + unsafe { + ((mmio_base + EXT_CFG_INDEX) as *mut u32).write_volatile(idx as u32); + } + return Some(mmio_base + EXT_CFG_DATA); + } +} diff --git a/crates/driver_pci/src/root_complex.rs b/crates/driver_pci/src/root_complex.rs new file mode 100644 index 0000000000..cd714ff6eb --- /dev/null +++ b/crates/driver_pci/src/root_complex.rs @@ -0,0 +1,356 @@ +use crate::err::*; +use crate::types::*; +use crate::Access; +use crate::PciAddress; +use alloc::vec::Vec; +use core::fmt; +use core::fmt::{Display, Formatter}; +use core::marker::PhantomData; +use core::ops::Range; +use log::*; +use tock_registers::interfaces::{ReadWriteable, Readable}; +use tock_registers::{ + register_bitfields, register_structs, + registers::{ReadOnly, ReadWrite}, +}; +const MAX_BUS: usize = 256; +const MAX_DEVICES: usize = 32; +const MAX_FUNCTIONS: usize = 8; + +/// The root complex of a PCI bus. +#[derive(Clone)] +pub struct PciRootComplex { + mmio_base: usize, + allocator: PciRangeAllocator, + _marker: PhantomData, +} + +impl PciRootComplex { + pub fn new(mmio_base: usize, bar_range: Range) -> Self { + A::setup(mmio_base); + Self { + mmio_base, + allocator: PciRangeAllocator::new(bar_range), + _marker: PhantomData::default(), + } + } +} + +impl PciRootComplex { + /// Enumerates PCI devices on the given bus. + pub fn enumerate_bus(&self) -> BusDeviceIterator { + // Safe because the BusDeviceIterator only reads read-only fields. + let root = Self { + mmio_base: self.mmio_base, + allocator: self.allocator.clone(), + _marker: PhantomData::default(), + }; + BusDeviceIterator { + root, + next: PciAddress { + bus: 0, + device: 0, + function: 0, + }, + stack: Vec::new(), + } + } + + pub fn bar_info(&self, bdf: PciAddress, slot: u8) -> Option { + let cfg_addr = A::map_conf(self.mmio_base, bdf).unwrap(); + let mut ep = ConifgEndpoint::new(cfg_addr); + ep.bar(slot) + } + + fn read(&self, bdf: PciAddress, offset: usize) -> T { + let cfg_addr = A::map_conf(self.mmio_base, bdf).unwrap(); + unsafe { + let addr = cfg_addr + offset; + (addr as *const T).read_volatile() + } + } + + fn write(&self, bdf: PciAddress, offset: usize, value: T) { + let cfg_addr = A::map_conf(self.mmio_base, bdf).unwrap(); + unsafe { + let addr = cfg_addr + offset; + (addr as *mut T).write_volatile(value) + } + } +} +/// An iterator which enumerates PCI devices and functions on a given bus. +pub struct BusDeviceIterator { + /// This must only be used to read read-only fields, and must not be exposed outside this + /// module, because it uses the same CAM as the main `PciRoot` instance. + root: PciRootComplex, + next: PciAddress, + stack: Vec, +} + +impl BusDeviceIterator {} + +impl Iterator for BusDeviceIterator { + type Item = (PciAddress, DeviceFunctionInfo, ConfigSpace); + + fn next(&mut self) -> Option { + debug!("into next!"); + loop { + debug!("looped"); + if self.next.function >= MAX_FUNCTIONS { + debug!("added"); + self.next.function = 0; + self.next.device += 1; + } + + if self.next.device >= MAX_DEVICES { + if let Some(parent) = self.stack.pop() { + let sub = self.next.bus; + self.next.bus = parent.bus; + self.next.device = parent.device + 1; + self.next.function = 0; + let cfg_addr = A::map_conf(self.root.mmio_base, parent.clone()).unwrap(); + let bridge = ConifgPciPciBridge::new(cfg_addr); + trace!("Bridge {} set subordinate: {:X}", parent, sub); + bridge.set_subordinate_bus_number(sub as _); + } else { + debug!("none!"); + return None; + } + } + + let current = self.next.clone(); + + let cfg_addr = match A::map_conf(self.root.mmio_base, current.clone()) { + Some(c) => c, + None => { + debug!("no conf"); + if current.function == 0 { + self.next.device += 1; + } else { + self.next.function += 1; + } + continue; + } + }; + + // debug!("begin: {} @ 0x{:X}", current, cfg_addr); + let header = PciHeader::new(cfg_addr); + let (vid, did) = header.vendor_id_and_device_id(); + // debug!("vid {:X}, did {:X}", vid, did); + + if vid == 0xffff { + if current.function == 0 { + self.next.device += 1; + } else { + self.next.function += 1; + } + continue; + } + let multi = header.has_multiple_functions(); + + let header_type = header.header_type(); + let (dv, bc, sc, interface) = header.revision_and_class(); + let mut info = DeviceFunctionInfo::default(); + info.vendor_id = vid; + info.device_id = did; + info.revision = dv; + info.class = bc; + info.subclass = sc; + info.header_type = header_type; + info.prog_if = interface; + let config_space; + debug!("header_type:{:?}", header_type); + match header_type { + HeaderType::PciPciBridge => { + let bridge = ConifgPciPciBridge::new(cfg_addr); + self.stack.push(current.clone()); + self.next.bus += 1; + self.next.device = 0; + self.next.function = 0; + bridge.set_secondary_bus_number(self.next.bus as _); + bridge.set_subordinate_bus_number(0xff); + A::probe_bridge(self.root.mmio_base, &bridge); + config_space = ConfigSpace { + address: current.clone(), + cfg_addr, + header, + kind: ConfigKind::PciPciBridge { inner: bridge }, + } + } + HeaderType::Endpoint => { + if current.function == 0 && !multi { + self.next.device += 1; + } else { + self.next.function += 1; + } + let ep = config_ep(cfg_addr, &mut self.root.allocator); + config_space = ConfigSpace { + address: current.clone(), + cfg_addr, + header, + kind: ConfigKind::Endpoint { inner: ep }, + } + } + _ => { + debug!("no_header"); + if current.function == 0 && !multi { + self.next.device += 1; + } else { + self.next.function += 1; + } + continue; + } + } + + let out = (current.clone(), info, config_space); + return Some(out); + } + + debug!("isnone..."); + None + } +} + +fn config_ep(cfg_addr: usize, allocator: &mut PciRangeAllocator) -> ConifgEndpoint { + let mut ep = ConifgEndpoint::new(cfg_addr); + let mut slot = 0; + while slot < ConifgEndpoint::MAX_BARS { + let bar = ep.bar(slot); + match bar { + Some(bar) => match bar { + Bar::Io { port } => { + debug!(" BAR {}: IO port: {:X}", slot, port); + } + Bar::Memory64 { + address, + size, + prefetchable, + } => { + let addr = allocator.alloc(size).unwrap(); + unsafe { + ep.write_bar64(slot, addr); + } + debug!( + " BAR {}: MEM [{:#x}, {:#x}){}{}", + slot, + addr, + addr + size, + " 64bit", + if prefetchable { " pref" } else { "" }, + ); + + slot += 1; + } + Bar::Memory32 { + address, + size, + prefetchable, + } => { + let addr = allocator.alloc(size as u64).unwrap() as u32; + unsafe { + ep.write_bar32(slot, addr); + } + debug!( + " BAR {}: MEM [{:#x}, {:#x}){}{}", + slot, + addr, + addr + size, + " 32bit", + if prefetchable { " pref" } else { "" }, + ); + } + }, + None => {} + } + + slot += 1; + } + + ep +} + +/// Information about a PCI device function. +#[derive(Clone, Debug, Eq, PartialEq)] +pub struct DeviceFunctionInfo { + /// The PCI vendor ID. + pub vendor_id: u16, + /// The PCI device ID. + pub device_id: u16, + /// The PCI class. + pub class: u8, + /// The PCI subclass. + pub subclass: u8, + /// The PCI programming interface byte. + pub prog_if: u8, + /// The PCI revision ID. + pub revision: u8, + /// The type of PCI device. + pub header_type: HeaderType, +} + +impl Default for DeviceFunctionInfo { + fn default() -> Self { + Self { + header_type: HeaderType::PciPciBridge, + vendor_id: 0, + device_id: 0, + class: 0, + subclass: 0, + prog_if: 0, + revision: 0, + } + } +} + +impl Display for DeviceFunctionInfo { + fn fmt(&self, f: &mut Formatter) -> fmt::Result { + write!( + f, + "{:04X}:{:04X} (class {:02x}.{:02x}, rev {:02x}) {:?}", + self.vendor_id, + self.device_id, + self.class, + self.subclass, + self.revision, + self.header_type, + ) + } +} + +/// Used to allocate MMIO regions for PCI BARs. +#[derive(Clone)] +struct PciRangeAllocator { + range: Range, + current: u64, +} + +impl PciRangeAllocator { + /// Creates a new allocator from a memory range. + pub fn new(range: Range) -> Self { + Self { + range: range.clone(), + current: range.start, + } + } + + /// Allocates a memory region with the given size. + /// + /// The `size` should be a power of 2, and the returned value is also a + /// multiple of `size`. + pub fn alloc(&mut self, size: u64) -> Option { + if !size.is_power_of_two() { + return None; + } + let ret = align_up(self.current, size); + if ret + size > self.range.end { + return None; + } + + self.current = ret + size; + Some(ret) + } +} + +const fn align_up(addr: u64, align: u64) -> u64 { + (addr + align - 1) & !(align - 1) +} diff --git a/crates/driver_pci/src/types.rs b/crates/driver_pci/src/types.rs new file mode 100644 index 0000000000..fbf7ee1d98 --- /dev/null +++ b/crates/driver_pci/src/types.rs @@ -0,0 +1,413 @@ +use crate::PciAddress; +use bit_field::BitField; +use tock_registers::interfaces::ReadWriteable; +use tock_registers::interfaces::Readable; +use tock_registers::interfaces::Writeable; +use tock_registers::registers::ReadOnly; +use tock_registers::{register_bitfields, register_structs, registers::ReadWrite}; + +register_bitfields![ + u32, + + RC_CFG_REGS1 [ + VENDOR_ID OFFSET(0) NUMBITS(16) [], + DEVICE_ID OFFSET(16) NUMBITS(16) [], + ], + + RC_CFG_REGS3 [ + REVISION OFFSET(0) NUMBITS(8)[], + INTERFACE OFFSET(8) NUMBITS(8)[], + SUB_CLASS OFFSET(16) NUMBITS(8)[], + BASE_CLASS OFFSET(24) NUMBITS(8)[], + ], + RC_CFG_REGS4 [ + HEADER_TYPE OFFSET(16) NUMBITS(7)[ + Endpoint = 0, + PciPciBridge = 1, + CardBusBridge = 3, + ], + HAS_MULTIPLE_FUNCTIONS OFFSET(23) NUMBITS(1)[ + False = 0, + True = 1, + ] + ], + + RC_CFG_BUS_NUMS_REG1 [ + PRIMARY_BUS_NUMBER OFFSET(0) NUMBITS(8) [], + SECONDARY_BUS_NUMBER OFFSET(8) NUMBITS(8) [], + SUBORDINATE_BUS_NUMBER OFFSET(16) NUMBITS(8) [], + ], +]; + +register_bitfields! { + u16, + RC_CFG_COMMAND[ + IO_SPACE_ENABLE OFFSET(0) NUMBITS(1) [], + MEMORY_SPACE_ENABLE OFFSET(1) NUMBITS(1) [], + BUS_MASTER_ENABLE OFFSET(2) NUMBITS(1) [], + SPECIAL_CYCLE_ENABLE OFFSET(3) NUMBITS(1) [], + MEMORY_WRITE_AND_INVALIDATE OFFSET(4) NUMBITS(1) [], + VGA_PALETTE_SNOOP OFFSET(5) NUMBITS(1) [], + PARITY_ERROR_RESPONSE OFFSET(6) NUMBITS(1) [], + IDSEL_STEP_WAIT_CYCLE_CONTROL OFFSET(7) NUMBITS(1) [], + SERR_ENABLE OFFSET(8) NUMBITS(1) [], + FAST_BACK_TO_BACK_ENABLE OFFSET(9) NUMBITS(1) [], + INTERRUPT_DISABLE OFFSET(10) NUMBITS(1) [], + ], + + RC_CFG_STATUS[ + IMMEDIATE_READINESS OFFSET(0) NUMBITS(3) [], + INTERRUPT_STATUS OFFSET(3) NUMBITS(1) [], + CAPABILITIES_LIST OFFSET(4) NUMBITS(1) [], + CAPABLE_66MHZ OFFSET(5) NUMBITS(1) [], + ], +} + +register_structs! { + HeaderRegs { + (0x00 => reg1: ReadOnly), + (0x04 => command: ReadWrite), + (0x06 => status: ReadOnly), + (0x08 => reg3: ReadOnly), + (0x0c => reg4: ReadOnly), + (0x10 => @END), + } +} + +register_structs! { + PCIBridgeRegs { + (0x00 => _rsvd1), + (0x0C => cache_line_size: ReadWrite), + (0x0D => _rsvd2), + (0x18 => primary_bus_number: ReadWrite), + (0x19 => secondary_bus_number: ReadWrite), + (0x1a => subordinate_bus_number: ReadWrite), + (0x1b => secondary_latency_timer: ReadWrite), + (0x1c => _io), + (0x20 => memory_base: ReadWrite), + (0x22 => memory_limit: ReadWrite), + (0x24 => _rsvd3), + (0x3C => _interrupt_line), + (0x3D => interrupt_pin), + (0x3E => control: ReadWrite), + (0x3F => _rsvd4), + (0x40 => @END), + } +} +register_structs! { + EndpointRegs { + (0x00 => _rsvd1), + (0x10 => bar0: ReadWrite), + (0x14 => bar1: ReadWrite), + (0x18 => bar2: ReadWrite), + (0x1C => bar3: ReadWrite), + (0x20 => bar4: ReadWrite), + (0x24 => bar5: ReadWrite), + (0x28 => _card_bus_cis), + (0x40 => @END), + } +} + +#[derive(Clone, Copy, PartialEq, Eq, Debug)] +pub enum HeaderType { + Endpoint, + PciPciBridge, + CardBusBridge, + Unknown(u8), +} + +#[derive(Clone)] +pub struct PciHeader { + cfg_base: usize, +} + +impl PciHeader { + pub fn new(cfg_base: usize) -> PciHeader { + PciHeader { cfg_base } + } + + fn regs(&self) -> &'static HeaderRegs { + unsafe { &*(self.cfg_base as *const HeaderRegs) } + } + + pub fn vendor_id_and_device_id(&self) -> (u16, u16) { + let regs = self.regs(); + ( + regs.reg1.read(RC_CFG_REGS1::VENDOR_ID) as u16, + regs.reg1.read(RC_CFG_REGS1::DEVICE_ID) as u16, + ) + } + + pub fn has_multiple_functions(&self) -> bool { + match self + .regs() + .reg4 + .read_as_enum(RC_CFG_REGS4::HAS_MULTIPLE_FUNCTIONS) + { + Some(RC_CFG_REGS4::HAS_MULTIPLE_FUNCTIONS::Value::True) => true, + _ => false, + } + } + + pub fn header_type(&self) -> HeaderType { + match self.regs().reg4.read_as_enum(RC_CFG_REGS4::HEADER_TYPE) { + Some(RC_CFG_REGS4::HEADER_TYPE::Value::Endpoint) => HeaderType::Endpoint, + Some(RC_CFG_REGS4::HEADER_TYPE::Value::PciPciBridge) => HeaderType::PciPciBridge, + Some(RC_CFG_REGS4::HEADER_TYPE::Value::CardBusBridge) => HeaderType::CardBusBridge, + None => HeaderType::Unknown(0), + } + } + pub fn revision_and_class(&self) -> (Revision, BaseClass, SubClass, Interface) { + let reg3 = &self.regs().reg3; + return ( + reg3.read(RC_CFG_REGS3::REVISION) as u8, + reg3.read(RC_CFG_REGS3::BASE_CLASS) as u8, + reg3.read(RC_CFG_REGS3::SUB_CLASS) as u8, + reg3.read(RC_CFG_REGS3::INTERFACE) as u8, + ); + } + pub fn set_command(&self, command: impl IntoIterator) { + let cmd = command + .into_iter() + .fold(0u16, |acc, a| acc + a.clone() as u16); + self.regs().command.set(cmd) + } +} + +pub type Revision = u8; +pub type BaseClass = u8; +pub type SubClass = u8; +pub type Interface = u8; + +#[derive(Clone, Copy, Debug)] +#[repr(u16)] +pub enum ConfigCommand { + IoSpaceEnable = 1 << 0, + MemorySpaceEnable = 1 << 1, + BusMasterEnable = 1 << 2, + SpecialCycleEnable = 1 << 3, + MemoryWriteAndInvalidate = 1 << 4, + VGAPaletteSnoop = 1 << 5, + ParityErrorResponse = 1 << 6, + IDSELStepWaitCycleControl = 1 << 7, + SERREnable = 1 << 8, + FastBackToBackEnable = 1 << 9, + InterruptDisable = 1 << 10, +} + +pub struct ConifgPciPciBridge { + pub(crate) cfg_addr: usize, +} + +impl ConifgPciPciBridge { + pub fn new(cfg_addr: usize) -> ConifgPciPciBridge { + ConifgPciPciBridge { cfg_addr } + } + + fn regs(&self) -> &'static PCIBridgeRegs { + unsafe { &*(self.cfg_addr as *const PCIBridgeRegs) } + } + pub fn to_header(&self) -> PciHeader { + PciHeader::new(self.cfg_addr) + } + + pub fn set_primary_bus_number(&self, bus: u8) { + self.regs().primary_bus_number.set(bus); + } + + pub fn set_secondary_bus_number(&self, bus: u8) { + self.regs().secondary_bus_number.set(bus); + } + + pub fn set_subordinate_bus_number(&self, bus: u8) { + self.regs().subordinate_bus_number.set(bus); + } + + pub fn set_memory_base(&self, base: u16) { + self.regs().memory_base.set(base); + } + + pub fn set_memory_limit(&self, limit: u16) { + self.regs().memory_limit.set(limit); + } + + pub fn set_cache_line_size(&self, size: u8) { + self.regs().cache_line_size.set(size); + } + + pub fn set_control(&self, ctl: u8) { + self.regs().control.set(ctl); + } +} + +pub struct ConifgEndpoint { + cfg_addr: usize, +} +impl ConifgEndpoint { + pub const MAX_BARS: u8 = 6; + + pub fn new(cfg_addr: usize) -> Self { + Self { cfg_addr } + } + + fn regs(&self) -> &'static EndpointRegs { + unsafe { &*(self.cfg_addr as *const EndpointRegs) } + } + pub fn to_header(&self) -> PciHeader { + PciHeader::new(self.cfg_addr) + } + + fn read(offset: usize) -> u32 { + unsafe { (offset as *const u32).read_volatile() } + } + fn write(offset: usize, value: u32) { + unsafe { (offset as *mut u32).write_volatile(value) } + } + + /// Get the contents of a BAR in a given slot. Empty bars will return `None`. + /// + /// ### Note + /// 64-bit memory BARs use two slots, so if one is decoded in e.g. slot #0, this method should not be called + /// for slot #1 + pub fn bar(&self, slot: u8) -> Option { + if slot >= Self::MAX_BARS { + return None; + } + + let offset = self.cfg_addr + 0x10 + (slot as usize) * 4; + let bar = Self::read(offset); + + /* + * If bit 0 is `0`, the BAR is in memory. If it's `1`, it's in I/O. + */ + if bar.get_bit(0) == false { + let prefetchable = bar.get_bit(3); + let address = bar.get_bits(4..32) << 4; + + match bar.get_bits(1..3) { + 0b00 => { + let size = unsafe { + Self::write(offset, 0xfffffff0); + let mut readback = unsafe { (offset as *const u32).read_volatile() }; + Self::write(offset, address); + + /* + * If the entire readback value is zero, the BAR is not implemented, so we return `None`. + */ + if readback == 0x0 { + return None; + } + + readback.set_bits(0..4, 0); + 1 << readback.trailing_zeros() + }; + Some(Bar::Memory32 { + address, + size, + prefetchable, + }) + } + + 0b10 => { + /* + * If the BAR is 64 bit-wide and this slot is the last, there is no second slot to read. + */ + if slot >= 5 { + return None; + } + + let address_upper = Self::read(offset + 4); + + let mut size = unsafe { + Self::write(offset, 0xfffffff0); + Self::write(offset + 4, 0xffffffff); + let mut readback_low = Self::read(offset); + let readback_high = Self::read(offset + 4); + Self::write(offset, address); + Self::write(offset + 4, address_upper); + + /* + * If the readback from the first slot is not 0, the size of the BAR is less than 4GiB. + */ + readback_low.set_bits(0..4, 0); + if readback_low != 0 { + (1 << readback_low.trailing_zeros()) as u64 + } else { + 1u64 << ((readback_high.trailing_zeros() + 32) as u64) + } + }; + + let address64 = { + let mut address = address as u64; + // TODO: do we need to mask off the lower bits on this? + address.set_bits(32..64, address_upper as u64); + address + }; + Some(Bar::Memory64 { + address: address64, + size, + prefetchable, + }) + } + // TODO: should we bother to return an error here? + _ => panic!("BAR Memory type is reserved!"), + } + } else { + Some(Bar::Io { + port: bar.get_bits(2..32) << 2, + }) + } + } + + pub fn write_bar64(&mut self, slot: u8, value: u64) { + unsafe { + let offset = self.cfg_addr + 0x10 + (slot as usize) * 4; + Self::write(offset, value.get_bits(0..32) as u32); + Self::write(offset + 4, value.get_bits(32..64) as u32); + } + } + + pub fn write_bar32(&mut self, slot: u8, value: u32) { + let offset = self.cfg_addr + 0x10 + (slot as usize) * 4; + unsafe { + Self::write(offset, value as u32); + } + } +} + +pub const MAX_BARS: usize = 6; + +#[derive(Clone, Copy, Debug)] +pub enum Bar { + Memory32 { + address: u32, + size: u32, + prefetchable: bool, + }, + Memory64 { + address: u64, + size: u64, + prefetchable: bool, + }, + Io { + port: u32, + }, +} + +#[derive(Clone, Copy, PartialEq, Eq, Debug)] +pub enum BarWriteError { + NoSuchBar, + InvalidValue, +} + +pub struct ConfigSpace { + pub address: PciAddress, + pub cfg_addr: usize, + pub header: PciHeader, + pub kind: ConfigKind, +} + +pub enum ConfigKind { + Endpoint { inner: ConifgEndpoint }, + PciPciBridge { inner: ConifgPciPciBridge }, +} diff --git a/crates/driver_usb/Cargo.lock b/crates/driver_usb/Cargo.lock new file mode 100644 index 0000000000..5d9cc838a5 --- /dev/null +++ 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a/crates/driver_usb/Cargo.toml b/crates/driver_usb/Cargo.toml new file mode 100644 index 0000000000..6b33891194 --- /dev/null +++ b/crates/driver_usb/Cargo.toml @@ -0,0 +1,60 @@ +[package] +name = "driver_usb" +version = "0.1.0" +edition = "2021" +description = "Common traits and types for usb device drivers" +license = "GPL-3.0-or-later OR Apache-2.0" +homepage = "https://github.com/rcore-os/arceos" +repository = "https://github.com/rcore-os/arceos/tree/main/crates/driver_usb" +documentation = "https://rcore-os.github.io/arceos/driver_usb/index.html" + + +# include=[ +# "libusb-for-arceos/libusb", +# ] + +[features] +default = [] +phytium-xhci = [] + + +[dependencies] +driver_common = { path = "../driver_common" } +driver_pci = { path = "../driver_pci" } +xhci = "0.9" +log = "0.4" +axhal = { path = "../../modules/axhal" } +axtask = { path = "../../modules/axtask", features = [ + "multitask", + "sched_fifo", +] } +axsync = { path = "../../modules/axsync", features = ["multitask"] } +axconfig = { path = "../../modules/axconfig" } +os_units = "0.4.0" +page_table = { path = "../page_table" } +page_table_entry = { path = "../page_table_entry" } +spinlock = { path = "../../crates/spinlock" } +tock-registers = "0.9.0" +bit_field = "0.10" +axalloc = { path = "../../modules/axalloc" } +futures-util = { version = "0.3.28", features = [ + "alloc", +], default-features = false } +futures-intrusive = { version = "0.5.0", features = [ + "alloc", +], default-features = false } +spinning_top = { version = "0.3.0" } +conquer-once = { version = "0.4.0", default-features = false } +derive_builder = { version = "0.20.0", features = [ + "alloc", +], default-features = false } +crossbeam-queue = { version = "0.3.8", features = [ + "alloc", +], default-features = false } +num-derive = "0.4.0" +num-traits = { version = "0.2.16", default-features = false } +byteorder = { version = "1.4.3", default-features = false } + + +[target.'cfg(target_arch = "aarch64")'.dependencies] +aarch64-cpu = "9.3" diff --git a/crates/driver_usb/src/.build.rs b/crates/driver_usb/src/.build.rs new file mode 100644 index 0000000000..a2e2a1c83b --- /dev/null +++ b/crates/driver_usb/src/.build.rs @@ -0,0 +1,295 @@ +// use regex::Regex; +// use std::io::{Read, Write}; +// use std::path::PathBuf; +// use std::{env, fs}; + +// // TODO: MODIFY IT TO ARCEOS ENV VARS +// fn main() { +// let mut c = cc::Build::new(); +// let root = PathBuf::from(env::var_os("CARGO_MANIFEST_DIR").unwrap()); +// let config_dir = PathBuf::from(env::var_os("OUT_DIR").unwrap()).join("include"); +// let libusb_src = root.join("libusb").join("libusb"); +// fs::create_dir_all(&config_dir).unwrap(); +// let libusb_src_os = libusb_src.join("os"); + +// c.include(&config_dir); +// c.include(&libusb_src); +// c.include(&libusb_src_os); + +// c.warnings(false); + +// let src_files = vec![ +// "core.c", +// "descriptor.c", +// "hotplug.c", +// "io.c", +// "strerror.c", +// "sync.c", +// ]; + +// for file in src_files.iter() { +// c.file(libusb_src.join(file)); +// } +// let mut src_os_files: Vec<&str> = vec![]; + +// if env::var("CARGO_CFG_TARGET_FAMILY") == Ok("unix".into()) { +// src_os_files = vec!["events_posix.c", "threads_posix.c"]; + +// if env::var("CARGO_CFG_TARGET_OS") == Ok("linux".into()) +// || env::var("CARGO_CFG_TARGET_OS") == Ok("android".into()) +// { +// c.define("OS_LINUX", Some("1")); +// // c.define("HAVE_ASM_TYPES_H", Some("1")); +// c.define("_GNU_SOURCE", Some("1")); +// c.define("HAVE_TIMERFD", Some("1")); +// c.define("HAVE_EVENTFD", Some("1")); +// src_os_files.push("linux_netlink.c"); +// src_os_files.push("linux_usbfs.c"); +// } + +// if env::var("CARGO_CFG_TARGET_OS") == Ok("macos".into()) { +// c.define("OS_DARWIN", Some("1")); +// c.define("TARGET_OS_OSX", Some("1")); +// c.file(libusb_src_os.join("darwin_usb.c")); +// println!("cargo:rustc-link-lib=framework=CoreFoundation"); +// println!("cargo:rustc-link-lib=framework=IOKit"); +// println!("cargo:rustc-link-lib=framework=Security"); +// println!("cargo:rustc-link-lib=objc"); +// } +// } +// if env::var("CARGO_CFG_TARGET_OS") == Ok("windows".into()) { +// #[cfg(target_env = "msvc")] +// c.flag("/source-charset:utf-8"); + +// c.warnings(false); +// c.define("OS_WINDOWS", Some("1")); +// src_os_files = vec![ +// "events_windows.c", +// "threads_windows.c", +// "windows_common.c", +// "windows_usbdk.c", +// "windows_winusb.c", +// ]; + +// if env::var("CARGO_CFG_TARGET_ENV") != Ok("msvc".into()) { +// c.define("DEFAULT_VISIBILITY", Some("")); +// c.define("PLATFORM_WINDOWS", Some("1")); +// } +// println!("cargo:rustc-link-lib=dylib={}", "user32"); +// } else { +// c.define( +// "DEFAULT_VISIBILITY", +// Some("__attribute__((visibility(\"default\")))"), +// ); +// } + +// for file in src_os_files.iter() { +// c.file(libusb_src_os.join(file)); +// } + +// let mut params = Params { +// c: &mut c, +// root: &root, +// config_dir: &config_dir, +// libusb_src_dir: &libusb_src, +// libusb_src_os_dir: &libusb_src_os, +// }; +// gen_config_h(&mut params); + +// let version = get_libusb_version(&libusb_src); + +// println!("cargo:warning=version: {}", version); +// c.compile("usb"); +// } + +// fn get_libusb_version_one(src: &str, e: &str) -> i32 { +// let res = format!(r"#define LIBUSB_{} (\d+)(\s+)#endif", e); +// let re = Regex::new(&res).unwrap(); +// let caps = re.captures(&src).unwrap(); +// let version = caps.get(1).unwrap().as_str(); +// version.parse::().unwrap() +// } +// fn get_libusb_version(libusb_src: &PathBuf) -> String { +// let mut f = fs::File::open(libusb_src.join("version.h")).unwrap(); +// let mut h_str = String::new(); +// let _ = f.read_to_string(&mut h_str).unwrap(); + +// let v1 = get_libusb_version_one(&h_str, "MAJOR"); +// let v2 = get_libusb_version_one(&h_str, "MINOR"); +// let v3 = get_libusb_version_one(&h_str, "MICRO"); + +// format!("{}.{}.{}", v1, v2, v3) +// } + +// #[allow(unused)] +// struct Params<'a> { +// c: &'a mut cc::Build, +// root: &'a PathBuf, +// config_dir: &'a PathBuf, +// libusb_src_dir: &'a PathBuf, +// libusb_src_os_dir: &'a PathBuf, +// } + +// fn gen_config_h(params: &mut Params) { +// if env::var("CARGO_CFG_TARGET_ENV") == Ok("msvc".into()) { +// fs::copy( +// params.root.join("libusb").join("msvc").join("config.h"), +// params.config_dir.join("config.h"), +// ) +// .unwrap(); +// } else if env::var("CARGO_CFG_TARGET_OS") == Ok("android".into()) { +// fs::copy( +// params.root.join("libusb").join("android").join("config.h"), +// params.config_dir.join("config.h"), +// ) +// .unwrap(); +// } else if env::var("CARGO_CFG_TARGET_OS") == Ok("macos".into()) { +// fs::copy( +// params.root.join("libusb").join("Xcode").join("config.h"), +// params.config_dir.join("config.h"), +// ) +// .unwrap(); +// } else if env::var("CARGO_CFG_TARGET_FAMILY") == Ok("unix".into()) { +// let mut config_h = fs::File::create(params.config_dir.join("config.h")).unwrap(); +// write!(config_h, "{}", CONFIG_H_UNIX_CONTENT).unwrap(); +// let version = get_libusb_version(¶ms.libusb_src_dir); +// let package_string = format!("libusb-1.0 {}", &version); + +// params.c.define("PACKAGE_VERSION", Some(version.as_str())); +// params +// .c +// .define("PACKAGE_STRING", Some(package_string.as_str())); +// params.c.define("VERSION", Some(version.as_str())); +// } +// } + +// const CONFIG_H_UNIX_CONTENT: &str = r#" + +// // #define DEFAULT_VISIBILITY __attribute__ ((visibility ("default"))) + +// /* Define to 1 to enable message logging. */ +// #define ENABLE_LOGGING 1 + +// /* Define to 1 if you have the header file. */ +// /* #undef HAVE_ASM_TYPES_H */ +// /* Define to 1 if you have the `clock_gettime' function. */ +// #define HAVE_CLOCK_GETTIME 1 + +// /* Define to 1 if you have the declaration of `EFD_CLOEXEC', and to 0 if you +// don't. */ +// #define HAVE_DECL_EFD_CLOEXEC 1 + +// /* Define to 1 if you have the declaration of `EFD_NONBLOCK', and to 0 if you +// don't. */ +// #define HAVE_DECL_EFD_NONBLOCK 1 + +// /* Define to 1 if you have the declaration of `TFD_CLOEXEC', and to 0 if you +// don't. */ +// #define HAVE_DECL_TFD_CLOEXEC 1 + +// /* Define to 1 if you have the declaration of `TFD_NONBLOCK', and to 0 if you +// don't. */ +// #define HAVE_DECL_TFD_NONBLOCK 1 + +// /* Define to 1 if you have the header file. */ +// #define HAVE_DLFCN_H 1 + +// /* Define to 1 if you have the header file. */ +// #define HAVE_INTTYPES_H 1 + +// /* Define to 1 if you have the header +// file. */ +// /* #undef HAVE_IOKIT_USB_IOUSBHOSTFAMILYDEFINITIONS_H */ +// /* Define to 1 if you have the `udev' library (-ludev). */ +// // #define HAVE_LIBUDEV 1 + +// /* Define to 1 if the system has the type `nfds_t'. */ +// #define HAVE_NFDS_T 1 + +// /* Define to 1 if you have the `pipe2' function. */ +// #define HAVE_PIPE2 1 + +// /* Define to 1 if you have the `pthread_condattr_setclock' function. */ +// #define HAVE_PTHREAD_CONDATTR_SETCLOCK 1 + +// /* Define to 1 if you have the `pthread_setname_np' function. */ +// #define HAVE_PTHREAD_SETNAME_NP 1 + +// /* Define to 1 if you have the `pthread_threadid_np' function. */ +// /* #undef HAVE_PTHREAD_THREADID_NP */ +// /* Define to 1 if you have the header file. */ +// #define HAVE_STDINT_H 1 + +// /* Define to 1 if you have the header file. */ +// #define HAVE_STDIO_H 1 + +// /* Define to 1 if you have the header file. */ +// #define HAVE_STDLIB_H 1 + +// /* Define to 1 if you have the header file. */ +// #define HAVE_STRINGS_H 1 + +// /* Define to 1 if you have the header file. */ +// #define HAVE_STRING_H 1 + +// /* Define to 1 if the system has the type `struct timespec'. */ +// /* #undef HAVE_STRUCT_TIMESPEC */ +// /* Define to 1 if you have the `syslog' function. */ +// /* #undef HAVE_SYSLOG */ +// /* Define to 1 if you have the header file. */ +// #define HAVE_SYS_STAT_H 1 + +// /* Define to 1 if you have the header file. */ +// #define HAVE_SYS_TIME_H 1 + +// /* Define to 1 if you have the header file. */ +// #define HAVE_SYS_TYPES_H 1 + +// /* Define to 1 if you have the header file. */ +// #define HAVE_UNISTD_H 1 + +// /* Define to the sub-directory where libtool stores uninstalled libraries. */ +// #define LT_OBJDIR ".libs/" + +// /* Name of package */ +// #define PACKAGE "libusb-1.0" + +// /* Define to the address where bug reports for this package should be sent. */ +// #define PACKAGE_BUGREPORT "libusb-devel@lists.sourceforge.net" + +// /* Define to the full name of this package. */ +// #define PACKAGE_NAME "libusb-1.0" + +// /* Define to the one symbol short name of this package. */ +// #define PACKAGE_TARNAME "libusb-1.0" + +// /* Define to the home page for this package. */ +// #define PACKAGE_URL "http://libusb.info" + +// /* Define to 1 if compiling for a POSIX platform. */ +// #define PLATFORM_POSIX 1 + +// /* Define to 1 if compiling for a Windows platform. */ +// /* #undef PLATFORM_WINDOWS */ +// /* Define to the attribute for enabling parameter checks on printf-like +// functions. */ +// #define PRINTF_FORMAT(a, b) __attribute__ ((__format__ (__printf__, a, b))) + +// /* Define to 1 if all of the C90 standard headers exist (not just the ones +// required in a freestanding environment). This macro is provided for +// backward compatibility; new code need not use it. */ +// #define STDC_HEADERS 1 + +// /* UMockdev hotplug code is not racy */ +// /* #undef UMOCKDEV_HOTPLUG */ +// /* Define to 1 to output logging messages to the systemwide log. */ +// /* #undef USE_SYSTEM_LOGGING_FACILITY */ +// /* Define to the oldest supported Windows version. */ +// /* #undef _WIN32_WINNT */ +// /* Define to `__inline__' or `__inline' if that's what the C compiler +// calls it, or to nothing if 'inline' is not supported under any name. */ +// #ifndef __cplusplus +// /* #undef inline */ +// #endif + +// "#; diff --git a/crates/driver_usb/src/device_types.rs b/crates/driver_usb/src/device_types.rs new file mode 100644 index 0000000000..4b8cdf5711 --- /dev/null +++ b/crates/driver_usb/src/device_types.rs @@ -0,0 +1,41 @@ +pub(crate) const PCI_VENDOR_ID_FRESCO_LOGIC: u16 = 0x1b73; +pub(crate) const PCI_DEVICE_ID_FRESCO_LOGIC_PDK: u16 = 0x1000; +pub(crate) const PCI_DEVICE_ID_FRESCO_LOGIC_FL1009: u16 = 0x1009; +pub(crate) const PCI_DEVICE_ID_FRESCO_LOGIC_FL1100: u16 = 0x1100; +pub(crate) const PCI_DEVICE_ID_FRESCO_LOGIC_FL1400: u16 = 0x1400; +pub(crate) const PCI_VENDOR_ID_ETRON: u16 = 0x1b6f; +pub(crate) const PCI_DEVICE_ID_EJ168: u16 = 0x7023; +pub(crate) const PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI: u16 = 0x8c31; +pub(crate) const PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI: u16 = 0x9c31; +pub(crate) const PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI: u16 = 0x9cb1; +pub(crate) const PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI: u16 = 0x22b5; +pub(crate) const PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI: u16 = 0xa12f; +pub(crate) const PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI: u16 = 0x9d2f; +pub(crate) const PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI: u16 = 0x0aa8; +pub(crate) const PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI: u16 = 0x1aa8; +pub(crate) const PCI_DEVICE_ID_INTEL_APL_XHCI: u16 = 0x5aa8; +pub(crate) const PCI_DEVICE_ID_INTEL_DNV_XHCI: u16 = 0x19d0; +pub(crate) const PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI: u16 = 0x15b5; +pub(crate) const PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI: u16 = 0x15b6; +pub(crate) const PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI: u16 = 0x15c1; +pub(crate) const PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI: u16 = 0x15db; +pub(crate) const PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI: u16 = 0x15d4; +pub(crate) const PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI: u16 = 0x15e9; +pub(crate) const PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI: u16 = 0x15ec; +pub(crate) const PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI: u16 = 0x15f0; +pub(crate) const PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI: u16 = 0x8a13; +pub(crate) const PCI_DEVICE_ID_INTEL_CML_XHCI: u16 = 0xa3af; +pub(crate) const PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI: u16 = 0x9a13; +pub(crate) const PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI: u16 = 0x1138; +pub(crate) const PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI: u16 = 0x51ed; +pub(crate) const PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI: u16 = 0x54ed; +pub(crate) const PCI_DEVICE_ID_AMD_PROMONTORYA_4: u16 = 0x43b9; +pub(crate) const PCI_DEVICE_ID_AMD_PROMONTORYA_3: u16 = 0x43ba; +pub(crate) const PCI_DEVICE_ID_AMD_PROMONTORYA_2: u16 = 0x43bb; +pub(crate) const PCI_DEVICE_ID_AMD_PROMONTORYA_1: u16 = 0x43bc; +pub(crate) const PCI_DEVICE_ID_ASMEDIA_1042_XHCI: u16 = 0x1042; +pub(crate) const PCI_DEVICE_ID_ASMEDIA_1042A_XHCI: u16 = 0x1142; +pub(crate) const PCI_DEVICE_ID_ASMEDIA_1142_XHCI: u16 = 0x1242; +pub(crate) const PCI_DEVICE_ID_ASMEDIA_2142_XHCI: u16 = 0x2142; +pub(crate) const PCI_DEVICE_ID_ASMEDIA_3242_XHCI: u16 = 0x3242; +pub(crate) const PCI_DEVICE_ID_PHYTIUM_XHCI: u16 = 0xdc27; diff --git a/crates/driver_usb/src/dma.rs b/crates/driver_usb/src/dma.rs new file mode 100644 index 0000000000..b666121b6a --- /dev/null +++ b/crates/driver_usb/src/dma.rs @@ -0,0 +1,67 @@ +use core::{ + alloc::{Allocator, Layout}, + mem::size_of, + ops::{Deref, DerefMut}, + ptr::{slice_from_raw_parts, NonNull}, +}; + +use log::debug; + +pub struct DMAVec { + layout: Layout, + ptr: NonNull<[T]>, + allocator: A, +} + +impl DMAVec { + /// DMAVec的新建方法。 + ///
size: 数组期望的元素数量。 + ///
align: 内存对齐的字节大小。 + ///
allocator: 用于数组内存分配和释放的分配器实例。 + ///
返回一个初始化好的DMAVec实例。 + pub fn new(size: usize, align: usize, allocator: A) -> Self { + //计算所需内存大小 + let buff_size = size * size_of::(); + // 根据元素数量和对其要求创建内存布局 + let layout = Layout::from_size_align(buff_size, align).unwrap(); + // 使用分配器分配内存 + let buff = allocator.allocate(layout).unwrap(); + let ptr; + unsafe { + // 将分配的原始指针转换为T类型的切片指针，并确保其非空。 + let s = &*slice_from_raw_parts(buff.as_ptr() as *const T, size); + ptr = NonNull::from(s); + } + Self { + layout, + ptr, + allocator, + } + } +} + +// 实现Deref trait，使得DMAVec可以像切片一样被使用。 +impl Deref for DMAVec { + type Target = [T]; + + fn deref(&self) -> &Self::Target { + unsafe { self.ptr.as_ref() } + } +} + +// 实现DerefMut trait，使得DMAVec可以像切片一样被变相修改。 +impl DerefMut for DMAVec { + fn deref_mut(&mut self) -> &mut Self::Target { + unsafe { self.ptr.as_mut() } + } +} + +// 实现Drop trait，用于在DMAVec实例被销毁时释放其占用的内存。 +impl Drop for DMAVec { + fn drop(&mut self) { + unsafe { + let ptr = self.ptr.cast::(); + self.allocator.deallocate(ptr, self.layout); + } + } +} diff --git a/crates/driver_usb/src/host/exchanger/command.rs b/crates/driver_usb/src/host/exchanger/command.rs new file mode 100644 index 0000000000..777f8e7489 --- /dev/null +++ b/crates/driver_usb/src/host/exchanger/command.rs @@ -0,0 +1,136 @@ +use super::{ + super::structures::ring::command, + receiver::{self, ReceiveFuture}, +}; +use crate::{Futurelock, FuturelockGuard}; +use alloc::sync::Arc; +use axhal::mem::VirtAddr; +use command_trb::{AddressDevice, ConfigureEndpoint, EnableSlot, EvaluateContext}; +use conquer_once::spin::OnceCell; +use event::CompletionCode; +use futures_util::task::AtomicWaker; +use log::debug; +use spinning_top::Spinlock; + +use xhci::ring::trb::{command as command_trb, event}; + +static SENDER: OnceCell> = OnceCell::uninit(); + +pub(crate) fn init() { + let ring = Arc::new(Spinlock::new(command::Ring::new())); + + ring.lock().init(); + + SENDER + .try_init_once(|| Spinlock::new(Sender::new(ring))) + .expect("`Sender` is initialized more than once.") +} + +pub(crate) fn enable_device_slot() -> u8 { + lock().enable_device_slot() +} + +pub(crate) fn address_device(input_cx: VirtAddr, slot: u8) { + lock().address_device(input_cx, slot); +} + +pub(crate) fn configure_endpoint(cx: VirtAddr, slot: u8) { + lock().configure_endpoint(cx, slot); +} + +pub(crate) fn evaluate_context(cx: VirtAddr, slot: u8) { + lock().evaluate_context(cx, slot); +} + +fn lock() -> spinning_top::lock_api::MutexGuard<'static, spinning_top::RawSpinlock, Sender> { + let s = SENDER.try_get().expect("`SENDER` is not initialized."); + s.lock() +} + +struct Sender { + channel: Channel, +} +impl Sender { + fn new(ring: Arc>) -> Self { + Self { + channel: Channel::new(ring), + } + } + + fn enable_device_slot(&mut self) -> u8 { + let t = EnableSlot::default(); + let completion = self.send_and_receive(t.into()); + panic_on_error("Enable Device Slot", completion); + if let event::Allowed::CommandCompletion(c) = completion { + c.slot_id() + } else { + unreachable!() + } + } + + fn address_device(&mut self, input_context_addr: VirtAddr, slot_id: u8) { + let t = *AddressDevice::default() + .set_input_context_pointer(input_context_addr.as_usize() as u64) + .set_slot_id(slot_id); + let c = self.send_and_receive(t.into()); + panic_on_error("Address Device", c); + } + + fn configure_endpoint(&mut self, context_addr: VirtAddr, slot_id: u8) { + let t = *ConfigureEndpoint::default() + .set_input_context_pointer(context_addr.as_usize() as u64) + .set_slot_id(slot_id); + let c = self.send_and_receive(t.into()); + panic_on_error("Configure Endpoint", c); + } + + fn evaluate_context(&mut self, cx: VirtAddr, slot: u8) { + let t = *EvaluateContext::default() + .set_input_context_pointer(cx.as_usize() as u64) + .set_slot_id(slot); + let c = self.send_and_receive(t.into()); + panic_on_error("Evaluate Context", c); + } + + fn send_and_receive(&mut self, t: command_trb::Allowed) -> event::Allowed { + self.channel.send_and_receive(t) + } +} + +struct Channel { + ring: Arc>, + waker: Arc>, +} +impl Channel { + fn new(ring: Arc>) -> Self { + Self { + ring, + waker: Arc::new(Spinlock::new(AtomicWaker::new())), + } + } + + fn send_and_receive(&mut self, t: command_trb::Allowed) -> event::Allowed { + debug!("send and receive: {:?}", t); + let a = self.ring.lock().enqueue(t); + self.register_with_receiver(a); + self.get_trb(a) + } + + fn register_with_receiver(&mut self, trb_a: VirtAddr) { + receiver::add_entry(trb_a, self.waker.clone()).expect("Sender is already registered."); + } + + fn get_trb(&mut self, trb_a: VirtAddr) -> event::Allowed { + ReceiveFuture::new(trb_a).poll() + } +} + +fn panic_on_error(n: &str, c: event::Allowed) { + if let event::Allowed::CommandCompletion(c) = c { + if c.completion_code() != Ok(CompletionCode::Success) { + panic!("{} command failed: {:?}", n, c.completion_code()); + } + } else { + unreachable!("The Command Completion TRB is the only TRB to receive in response to the Command TRBs.") + } +} diff --git a/crates/driver_usb/src/host/exchanger/mod.rs b/crates/driver_usb/src/host/exchanger/mod.rs new file mode 100644 index 0000000000..db6d4e1674 --- /dev/null +++ b/crates/driver_usb/src/host/exchanger/mod.rs @@ -0,0 +1,3 @@ +pub(crate) mod command; +pub(crate) mod receiver; +pub(crate) mod transfer; diff --git a/crates/driver_usb/src/host/exchanger/receiver.rs b/crates/driver_usb/src/host/exchanger/receiver.rs new file mode 100644 index 0000000000..11f4f2ec12 --- /dev/null +++ b/crates/driver_usb/src/host/exchanger/receiver.rs @@ -0,0 +1,128 @@ +use alloc::{collections::BTreeMap, sync::Arc}; +use axhal::mem::VirtAddr; +use conquer_once::spin::Lazy; +use core::{ + future::Future, + pin::Pin, + task::{Context, Poll}, +}; +use futures_util::task::AtomicWaker; +use log::debug; +use spinning_top::{guard::SpinlockGuard, Spinlock}; + +use xhci::ring::trb::event; + +static RECEIVER: Lazy> = Lazy::new(|| Spinlock::new(Receiver::new())); + +pub(crate) fn add_entry(trb_a: VirtAddr, waker: Arc>) -> Result<(), Error> { + lock().add_entry(trb_a, waker) +} + +pub(crate) fn receive(t: event::Allowed) { + lock().receive(t) +} + +fn lock() -> SpinlockGuard<'static, Receiver> { + RECEIVER + .try_lock() + .expect("Failed to acquire the lock of `RECEIVER`.") +} + +struct Receiver { + trbs: BTreeMap>, + wakers: BTreeMap>>, +} +impl Receiver { + fn new() -> Self { + Self { + trbs: BTreeMap::new(), + wakers: BTreeMap::new(), + } + } + + fn add_entry( + &mut self, + addr_to_trb: VirtAddr, + waker: Arc>, + ) -> Result<(), Error> { + if self.trbs.insert(addr_to_trb, None).is_some() { + return Err(Error::AddrAlreadyRegistered); + } + + if self.wakers.insert(addr_to_trb, waker).is_some() { + return Err(Error::AddrAlreadyRegistered); + } + Ok(()) + } + + fn receive(&mut self, trb: event::Allowed) { + if let Err(e) = self.insert_trb(trb) { + panic!("Failed to receive a command completion trb: {:?}", e); + } + } + + fn insert_trb(&mut self, trb: event::Allowed) -> Result<(), Error> { + let addr_to_trb = Self::trb_addr(trb); + { + let addr_to_trb = Self::trb_addr(trb); + *self + .trbs + .get_mut(&addr_to_trb) + .ok_or(Error::NoSuchAddress)? = Some(trb); + Ok(()) + }?; + Ok(()) + } + + fn trb_arrives(&self, addr_to_trb: VirtAddr) -> bool { + match self.trbs.get(&addr_to_trb) { + Some(trb) => trb.is_some(), + None => panic!("No such TRB with the address {:?}", addr_to_trb), + } + } + + fn remove_entry(&mut self, addr_to_trb: VirtAddr) -> Option { + match self.trbs.remove(&addr_to_trb) { + Some(trb) => trb, + None => panic!("No such receiver with TRB address: {:?}", addr_to_trb), + } + } + + fn trb_addr(t: event::Allowed) -> VirtAddr { + VirtAddr::from(match t { + event::Allowed::TransferEvent(e) => e.trb_pointer() as usize, + event::Allowed::CommandCompletion(c) => c.command_trb_pointer() as usize, + _ => todo!(), + }) + } +} + +#[derive(Debug)] +pub(crate) enum Error { + AddrAlreadyRegistered, + NoSuchAddress, +} + +pub(crate) struct ReceiveFuture { + addr_to_trb: VirtAddr, +} +impl ReceiveFuture { + pub(crate) fn new(addr_to_trb: VirtAddr) -> Self { + Self { addr_to_trb } + } + + pub fn poll(&mut self) -> event::Allowed { + crate::host::structures::ring::event::poll(); + let addr = self.addr_to_trb; + debug!("lock...?"); + let mut r = lock(); + debug!("LOCK!"); + + loop { + debug!("waiting for trb!"); + if r.trb_arrives(addr) { + return r.remove_entry(addr).unwrap(); + } + } + } +} diff --git a/crates/driver_usb/src/host/exchanger/transfer.rs b/crates/driver_usb/src/host/exchanger/transfer.rs new file mode 100644 index 0000000000..78d70684d1 --- /dev/null +++ b/crates/driver_usb/src/host/exchanger/transfer.rs @@ -0,0 +1,252 @@ +use crate::host::{ + page_box::PageBox, + structures::{descriptor, registers, ring::transfer}, +}; + +use super::receiver::{self, receive, ReceiveFuture}; +use alloc::{sync::Arc, vec::Vec}; +use axhal::mem::VirtAddr; +use core::convert::TryInto; +use futures_util::task::AtomicWaker; +use log::debug; +use spinning_top::Spinlock; + +use xhci::ring::trb::{ + event, transfer as transfer_trb, + transfer::{Direction, Noop, Normal, TransferType}, +}; + +pub(crate) struct Sender { + channel: Channel, +} +impl Sender { + pub(crate) fn new(doorbell_writer: DoorbellWriter) -> Self { + Self { + channel: Channel::new(doorbell_writer), + } + } + + pub(crate) fn ring_addr(&self) -> VirtAddr { + self.channel.ring_addr() + } + + pub(crate) fn get_max_packet_size_from_device_descriptor(&mut self) -> u16 { + let b = PageBox::from(descriptor::Device::default()); + + let setup = *transfer_trb::SetupStage::default() + .set_transfer_type(TransferType::In) + .clear_interrupt_on_completion() + .set_request_type(0x80) + .set_request(6) + .set_value(0x0100) + .set_length(8); + + let data = *transfer_trb::DataStage::default() + .set_direction(Direction::In) + .set_trb_transfer_length(8) + .clear_interrupt_on_completion() + .set_data_buffer_pointer(b.virt_addr().as_usize() as u64); + + let status = *transfer_trb::StatusStage::default().set_interrupt_on_completion(); + + self.issue_trbs(&[setup.into(), data.into(), status.into()]); + + b.max_packet_size() + } + + pub(crate) fn set_configure(&mut self, config_val: u8) { + let setup = *transfer_trb::SetupStage::default() + .set_transfer_type(TransferType::No) + .clear_interrupt_on_completion() + .set_request_type(0) + .set_request(9) + .set_value(config_val.into()) + .set_length(0); + + let status = *transfer_trb::StatusStage::default().set_interrupt_on_completion(); + + self.issue_trbs(&[setup.into(), status.into()]); + } + + pub(crate) fn set_idle(&mut self) { + let setup = *transfer_trb::SetupStage::default() + .set_transfer_type(TransferType::No) + .clear_interrupt_on_completion() + .set_request_type(0x21) + .set_request(0x0a) + .set_value(0) + .set_length(0); + + let status = *transfer_trb::StatusStage::default().set_interrupt_on_completion(); + + self.issue_trbs(&[setup.into(), status.into()]); + } + + pub(crate) fn set_boot_protocol(&mut self) { + let setup = *transfer_trb::SetupStage::default() + .set_transfer_type(TransferType::No) + .clear_interrupt_on_completion() + .set_request_type(0b0010_0001) + .set_request(0x0b) + .set_value(0) + .set_length(0); + + let status = *transfer_trb::StatusStage::default().set_interrupt_on_completion(); + + self.issue_trbs(&[setup.into(), status.into()]); + } + + pub(crate) fn get_configuration_descriptor(&mut self) -> PageBox<[u8]> { + let b = PageBox::new_slice(0, 4096); + + let (setup, data, status) = Self::trbs_for_getting_descriptors( + &b, + DescTyIdx::new(descriptor::Ty::Configuration, 0), + ); + + self.issue_trbs(&[setup, data, status]); + debug!("Got TRBs"); + b + } + + pub(crate) fn issue_normal_trb(&mut self, b: &PageBox) { + let t = *Normal::default() + .set_data_buffer_pointer(b.virt_addr().as_usize() as u64) + .set_trb_transfer_length(b.bytes().as_usize().try_into().unwrap()) + .set_interrupt_on_completion(); + debug!("Normal TRB: {:X?}", t); + self.issue_trbs(&[t.into()]); + } + + pub(crate) fn issue_nop_trb(&mut self) { + let t = Noop::default(); + + self.issue_trbs(&[t.into()]); + } + + fn trbs_for_getting_descriptors( + b: &PageBox, + t: DescTyIdx, + ) -> ( + transfer_trb::Allowed, + transfer_trb::Allowed, + transfer_trb::Allowed, + ) { + let setup = *transfer_trb::SetupStage::default() + .set_request_type(0b1000_0000) + .set_request(Request::GetDescriptor as u8) + .set_value(t.bits()) + .set_length(b.bytes().as_usize().try_into().unwrap()) + .set_transfer_type(TransferType::In); + + let data = *transfer_trb::DataStage::default() + .set_data_buffer_pointer(b.virt_addr().as_usize() as u64) + .set_trb_transfer_length(b.bytes().as_usize().try_into().unwrap()) + .set_direction(Direction::In); + + let status = *transfer_trb::StatusStage::default().set_interrupt_on_completion(); + + (setup.into(), data.into(), status.into()) + } + + fn issue_trbs(&mut self, ts: &[transfer_trb::Allowed]) -> Vec> { + self.channel.send_and_receive(ts) + } +} + +struct Channel { + ring: transfer::Ring, + doorbell_writer: DoorbellWriter, + waker: Arc>, +} +impl Channel { + fn new(doorbell_writer: DoorbellWriter) -> Self { + Self { + ring: transfer::Ring::new(), + doorbell_writer, + waker: Arc::new(Spinlock::new(AtomicWaker::new())), + } + } + + fn ring_addr(&self) -> VirtAddr { + self.ring.virt_addr() + } + + fn send_and_receive(&mut self, trbs: &[transfer_trb::Allowed]) -> Vec> { + let addrs = self.ring.enqueue(trbs); + // self.register_with_receiver(trbs, &addrs); + self.write_to_doorbell(); + self.get_trbs(trbs, &addrs) + } + + fn register_with_receiver(&mut self, ts: &[transfer_trb::Allowed], addrs: &[VirtAddr]) { + for (t, addr) in ts.iter().zip(addrs) { + self.register_trb(t, *addr); + } + } + + fn register_trb(&mut self, t: &transfer_trb::Allowed, a: VirtAddr) { + if t.interrupt_on_completion() { + receiver::add_entry(a, self.waker.clone()).expect("Sender is already registered."); + } + } + + fn write_to_doorbell(&mut self) { + self.doorbell_writer.write(); + } + + fn get_trbs( + &mut self, + ts: &[transfer_trb::Allowed], + addrs: &[VirtAddr], + ) -> Vec> { + let mut v = Vec::new(); + for (t, a) in ts.iter().zip(addrs) { + v.push(self.get_single_trb(t, *a)); + } + v + } + + fn get_single_trb( + &mut self, + t: &transfer_trb::Allowed, + addr: VirtAddr, + ) -> Option { + Some(ReceiveFuture::new(addr).poll()) + } +} + +pub(crate) struct DoorbellWriter { + slot_id: u8, + val: u32, +} +impl DoorbellWriter { + pub(crate) fn new(slot_id: u8, val: u32) -> Self { + Self { slot_id, val } + } + + pub(crate) fn write(&mut self) { + registers::handle(|r| { + r.doorbell.update_volatile_at(self.slot_id.into(), |d| { + d.set_doorbell_target(self.val.try_into().unwrap()); + }) + }); + } +} + +pub(crate) struct DescTyIdx { + ty: descriptor::Ty, + i: u8, +} +impl DescTyIdx { + pub(crate) fn new(ty: descriptor::Ty, i: u8) -> Self { + Self { ty, i } + } + pub(crate) fn bits(self) -> u16 { + (self.ty as u16) << 8 | u16::from(self.i) + } +} + +enum Request { + GetDescriptor = 6, +} diff --git a/crates/driver_usb/src/host/mapper.rs b/crates/driver_usb/src/host/mapper.rs new file mode 100644 index 0000000000..9d0776d071 --- /dev/null +++ b/crates/driver_usb/src/host/mapper.rs @@ -0,0 +1,11 @@ +use core::num::NonZeroUsize; + +#[derive(Clone, Copy, Debug)] +pub struct Mapper; +impl xhci::accessor::Mapper for Mapper { + unsafe fn map(&mut self, physical_address: usize, _: usize) -> NonZeroUsize { + NonZeroUsize::new(physical_address).expect("physical_address is zero") + } + + fn unmap(&mut self, _: usize, _: usize) {} +} diff --git a/crates/driver_usb/src/host/mod.rs b/crates/driver_usb/src/host/mod.rs new file mode 100644 index 0000000000..06dd3f03b0 --- /dev/null +++ b/crates/driver_usb/src/host/mod.rs @@ -0,0 +1,50 @@ +// A workaround for the `derive_builder` crate. +#![allow(clippy::default_trait_access)] + +use core::alloc::Allocator; + +use driver_common::{BaseDriverOps, DeviceType}; + +use self::structures::{extended_capabilities, registers}; + +pub(crate) mod exchanger; +mod mapper; +mod page_box; +mod port; +mod structures; +mod xhc; + +pub struct VL805 { + alloc: A, + // regs: Registers, + // extended_capabilities: Option>, + base_addr: usize, +} + +impl BaseDriverOps for VL805 { + fn device_name(&self) -> &str { + "VL805 4-Port USB 3.0 Host Controller" + } + + fn device_type(&self) -> DeviceType { + DeviceType::USBHost + } +} + +pub fn init_statics(base_addr: usize) { + // SAFETY: BAR 0 address is passed. + unsafe { + registers::init(base_addr.into()); + extended_capabilities::init(base_addr.into()); + } +} + +pub fn init_xhci() { + xhc::init(); +} + +pub fn enum_port() { + port::enum_all_connected_port(); + + // multitask::add(Task::new_poll(event::task())); +} diff --git a/crates/driver_usb/src/host/page_box.rs b/crates/driver_usb/src/host/page_box.rs new file mode 100644 index 0000000000..a1ca277912 --- /dev/null +++ b/crates/driver_usb/src/host/page_box.rs @@ -0,0 +1,180 @@ +use axalloc::global_no_cache_allocator; +use axhal::mem::VirtAddr; +use core::alloc::Allocator; +use core::alloc::Layout; +use core::fmt; +use core::fmt::Debug; +use core::fmt::Formatter; +use core::marker::PhantomData; +use core::ops::Deref; +use core::ops::DerefMut; +use core::ptr::NonNull; +use core::slice; +use os_units::Bytes; + +/// A `Box`-like type that locates the inner value at a 4K bytes page boundary. +/// +/// xHCI specification prohibits some structures from crossing the page +/// boundary. Here, the size of a page is determined by Page Size Register (See +/// 5.4.3 of the spec). However, the minimum size of a page is 4K bytes, meaning +/// that keeping a structure within a 4K bytes page is always safe. It is very +/// costly, but at least it works. +pub struct PageBox { + addr: VirtAddr, + layout: Layout, + _marker: PhantomData, +} +impl PageBox { + pub fn from_layout_zeroed(layout: Layout) -> Self { + assert!( + layout.size() > 0, + "The size of the layout must be greater than 0." + ); + + let addr = unsafe { + global_no_cache_allocator() + .allocate(layout) + .unwrap() + .as_ptr() + }; + + // SAFETY: Safe as the address is well-aligned. + unsafe { core::ptr::write_bytes(addr as *mut u8, 0, layout.size()) }; + + Self { + addr: VirtAddr::from(addr.addr() as usize), + layout, + _marker: PhantomData, + } + } + + pub fn virt_addr(&self) -> VirtAddr { + // We assume the identity mapping set up by UEFI firmware. + VirtAddr::from(self.addr.as_usize()) + } + + pub fn bytes(&self) -> Bytes { + Bytes::from(self.layout.size()) + } +} +impl PageBox<[T]> { + pub fn new_slice(init: T, len: usize) -> Self { + let bytes = Bytes::from(len * core::mem::size_of::()); + let align = 4096.max(core::mem::align_of::()); + + let layout = Layout::from_size_align(bytes.as_usize(), align); + let layout = layout.unwrap_or_else(|_| { + panic!( + "Failed to create a layout for {} bytes with {} bytes alignment", + bytes.as_usize(), + align + ) + }); + + // SAFETY: `Layout::from_size_align` guarantees that the layout is valid. + let addr = unsafe { + global_no_cache_allocator() + .allocate_zeroed(layout) + .unwrap() + .as_ptr() + .addr() + }; + + // SAFETY: Safe as the address is well-aligned. + unsafe { + let mut slice = slice::from_raw_parts_mut(addr as *mut T, len); + for i in 0..len { + slice[i] = init.clone(); + } + }; + + Self { + addr: VirtAddr::from(addr as usize), + layout, + _marker: PhantomData, + } + } +} +impl Deref for PageBox { + type Target = T; + fn deref(&self) -> &Self::Target { + // SAFETY: Safe as the address is well-aligned. + unsafe { &*(self.addr.as_ptr() as *const T) } + } +} +impl Deref for PageBox<[T]> { + type Target = [T]; + fn deref(&self) -> &Self::Target { + let len = self.bytes().as_usize() / core::mem::size_of::(); + + // SAFETY: Safe as the address is well-aligned and the memory is allocated. + unsafe { slice::from_raw_parts(self.addr.as_ptr() as *const T, len) } + } +} +impl DerefMut for PageBox { + fn deref_mut(&mut self) -> &mut Self::Target { + // SAFETY: Safe as the address is well-aligned. + unsafe { &mut *(self.addr.as_mut_ptr() as *mut T) } + } +} +impl DerefMut for PageBox<[T]> { + fn deref_mut(&mut self) -> &mut Self::Target { + let len = self.bytes().as_usize() / core::mem::size_of::(); + + // SAFETY: Safe as the address is well-aligned and the memory is allocated. + unsafe { slice::from_raw_parts_mut(self.addr.as_mut_ptr() as *mut T, len) } + } +} +impl From for PageBox { + fn from(inner: T) -> Self { + let bytes = Bytes::from(core::mem::size_of::()); + let align = 4096.max(core::mem::align_of::()); + + let layout = Layout::from_size_align(bytes.as_usize(), align); + let layout = layout.unwrap_or_else(|_| { + panic!( + "Failed to create a layout for {} bytes with {} bytes alignment", + bytes.as_usize(), + align + ) + }); + + // SAFETY: `Layout::from_size_align` guarantees that the layout is valid. + let addr = unsafe { + global_no_cache_allocator() + .allocate(layout) + .unwrap() + .as_ptr() + }; + + // SAFETY: Safe as the address is well-aligned. + unsafe { core::ptr::write(addr as *mut T, inner) }; + + Self { + addr: VirtAddr::from(addr.addr() as usize), + layout, + _marker: PhantomData, + } + } +} +impl Default for PageBox { + fn default() -> Self { + let x: T = Default::default(); + + Self::from(x) + } +} +impl Debug for PageBox { + fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { + self.deref().fmt(f) + } +} +impl Drop for PageBox { + fn drop(&mut self) { + // SAFETY: `Layout::from_size_align` guarantees that the layout is valid. + unsafe { + global_no_cache_allocator() + .deallocate(NonNull::new(self.addr.as_mut_ptr()).unwrap(), self.layout) + } + } +} diff --git a/crates/driver_usb/src/host/port/endpoint.rs b/crates/driver_usb/src/host/port/endpoint.rs new file mode 100644 index 0000000000..d9bfe1fdb9 --- /dev/null +++ b/crates/driver_usb/src/host/port/endpoint.rs @@ -0,0 +1,72 @@ +use axhal::mem::VirtAddr; +use xhci::context::EndpointType; + +use crate::host::{exchanger::transfer, page_box::PageBox, structures::descriptor}; + +pub(super) struct Default { + sender: transfer::Sender, +} +impl Default { + pub(super) fn new(sender: transfer::Sender) -> Self { + Self { sender } + } + + pub(super) fn ring_addr(&self) -> VirtAddr { + self.sender.ring_addr() + } + + pub(super) fn get_max_packet_size(&mut self) -> u16 { + self.sender.get_max_packet_size_from_device_descriptor() + } + + pub(super) fn get_raw_configuration_descriptors(&mut self) -> PageBox<[u8]> { + self.sender.get_configuration_descriptor() + } + + pub(super) fn set_configuration(&mut self, config_val: u8) { + self.sender.set_configure(config_val); + } + + pub(super) fn set_idle(&mut self) { + self.sender.set_idle(); + } + + pub(super) fn set_boot_protocol(&mut self) { + self.sender.set_boot_protocol(); + } + + pub(super) fn issue_nop_trb(&mut self) { + self.sender.issue_nop_trb(); + } +} + +pub struct NonDefault { + desc: descriptor::Endpoint, + sender: transfer::Sender, +} +impl NonDefault { + pub(super) fn new(desc: descriptor::Endpoint, sender: transfer::Sender) -> Self { + Self { desc, sender } + } + + pub(super) fn descriptor(&self) -> descriptor::Endpoint { + self.desc + } + + pub(super) fn transfer_ring_addr(&self) -> VirtAddr { + self.sender.ring_addr() + } + + pub(super) fn ty(&self) -> EndpointType { + self.desc.ty() + } + + pub(super) fn issue_normal_trb(&mut self, b: &PageBox) { + self.sender.issue_normal_trb(b) + } +} + +#[derive(Debug)] +pub(crate) enum Error { + NoSuchEndpoint(EndpointType), +} diff --git a/crates/driver_usb/src/host/port/init/descriptor_fetcher.rs b/crates/driver_usb/src/host/port/init/descriptor_fetcher.rs new file mode 100644 index 0000000000..557a44dc9b --- /dev/null +++ b/crates/driver_usb/src/host/port/init/descriptor_fetcher.rs @@ -0,0 +1,106 @@ +use crate::host::{ + page_box::PageBox, + port::endpoint, + structures::{ + context::Context, + descriptor::{self, Descriptor}, + }, +}; + +use super::{ + endpoints_initializer::EndpointsInitializer, max_packet_size_setter::MaxPacketSizeSetter, +}; +use alloc::{sync::Arc, vec::Vec}; +use log::debug; +use spinning_top::Spinlock; + +pub(super) struct DescriptorFetcher { + port_number: u8, + slot_number: u8, + cx: Arc>, + ep0: endpoint::Default, +} +impl DescriptorFetcher { + pub(super) fn new(s: MaxPacketSizeSetter) -> Self { + let port_number = s.port_number(); + let slot_number = s.slot_number(); + let cx = s.context(); + let ep0 = s.ep0(); + + Self { + port_number, + slot_number, + cx, + ep0, + } + } + + pub(super) fn fetch(mut self) -> EndpointsInitializer { + let r = self.get_raw_descriptors(); + let ds = RawDescriptorParser::new(r).parse(); + EndpointsInitializer::new(self, ds) + } + + pub(super) fn context(&self) -> Arc> { + self.cx.clone() + } + + pub(super) fn port_number(&self) -> u8 { + self.port_number + } + + pub(super) fn slot_number(&self) -> u8 { + self.slot_number + } + + pub(super) fn ep0(self) -> endpoint::Default { + self.ep0 + } + + fn get_raw_descriptors(&mut self) -> PageBox<[u8]> { + self.ep0.get_raw_configuration_descriptors() + } +} + +struct RawDescriptorParser { + raw: PageBox<[u8]>, + current: usize, + len: usize, +} +impl RawDescriptorParser { + fn new(raw: PageBox<[u8]>) -> Self { + let len = raw.len(); + + Self { + raw, + current: 0, + len, + } + } + + fn parse(&mut self) -> Vec { + let mut v = Vec::new(); + while self.current < self.len && self.raw[self.current] > 0 { + match self.parse_first_descriptor() { + Ok(t) => { + debug!("desc : {:?}", t); + v.push(t); + } + Err(e) => debug!("Unrecognized USB descriptor: {:?}", e), + } + } + v + } + + fn parse_first_descriptor(&mut self) -> Result { + let raw = self.cut_raw_descriptor(); + Descriptor::from_slice(&raw) + } + + fn cut_raw_descriptor(&mut self) -> Vec { + let len: usize = self.raw[self.current].into(); + let v = self.raw[self.current..(self.current + len)].to_vec(); + self.current += len; + v + } +} diff --git a/crates/driver_usb/src/host/port/init/endpoints_initializer.rs b/crates/driver_usb/src/host/port/init/endpoints_initializer.rs new file mode 100644 index 0000000000..a87966dcec --- /dev/null +++ b/crates/driver_usb/src/host/port/init/endpoints_initializer.rs @@ -0,0 +1,284 @@ +use crate::host::{ + exchanger::{self, transfer}, + port::endpoint, + structures::{ + context::Context, + descriptor::{self, Descriptor}, + registers, + }, +}; + +use super::{descriptor_fetcher::DescriptorFetcher, fully_operational::FullyOperational}; +use alloc::{sync::Arc, vec::Vec}; +use axhal::mem::VirtAddr; +use bit_field::BitField; +use core::convert::TryInto; +use num_derive::FromPrimitive; +use num_traits::FromPrimitive; +use spinning_top::Spinlock; +use transfer::DoorbellWriter; + +use xhci::context::{EndpointHandler, EndpointType}; + +pub(super) struct EndpointsInitializer { + cx: Arc>, + descriptors: Vec, + endpoints: Vec, + ep0: endpoint::Default, + port_number: u8, + slot_number: u8, +} +impl EndpointsInitializer { + pub(super) fn new(f: DescriptorFetcher, descriptors: Vec) -> Self { + let cx = f.context(); + let endpoints = descriptors_to_endpoints(&f, &descriptors); + let port_number = f.port_number(); + let slot_number = f.slot_number(); + let ep0 = f.ep0(); + + Self { + cx, + descriptors, + endpoints, + ep0, + port_number, + slot_number, + } + } + + pub(super) fn init(mut self) -> FullyOperational { + self.init_contexts(); + self.set_context_entries(); + self.configure_endpoint(); + FullyOperational::new(self) + } + + pub(super) fn descriptors(&self) -> Vec { + self.descriptors.clone() + } + + pub(super) fn endpoints(self) -> (endpoint::Default, Vec) { + (self.ep0, self.endpoints) + } + + fn init_contexts(&mut self) { + for e in &mut self.endpoints { + ContextInitializer::new( + &mut self.cx.lock(), + &e.descriptor(), + e.transfer_ring_addr(), + self.port_number, + ) + .init() + } + } + + fn set_context_entries(&mut self) { + let mut cx = self.cx.lock(); + cx.input.device_mut().slot_mut().set_context_entries(31); + } + + fn configure_endpoint(&mut self) { + let a = self.cx.lock().input.virt_addr(); + exchanger::command::configure_endpoint(a, self.slot_number); + } +} + +struct ContextInitializer<'a> { + cx: &'a mut Context, + ep: &'a descriptor::Endpoint, + transfer_ring_addr: VirtAddr, + port_number: u8, +} +impl<'a> ContextInitializer<'a> { + #[allow(clippy::too_many_arguments)] // TODO + fn new( + cx: &'a mut Context, + ep: &'a descriptor::Endpoint, + transfer_ring_addr: VirtAddr, + port_number: u8, + ) -> Self { + Self { + cx, + ep, + transfer_ring_addr, + port_number, + } + } + + fn init(mut self) { + self.set_aflag(); + self.init_ep_context(); + } + + fn set_aflag(&mut self) { + let dci: usize = self.calculate_dci().into(); + let c = self.cx.input.control_mut(); + + c.set_add_context_flag(0); + c.clear_add_context_flag(1); // See xHCI dev manual 4.6.6. + c.set_add_context_flag(dci); + } + + fn calculate_dci(&self) -> u8 { + let a = self.ep.endpoint_address; + 2 * a.get_bits(0..=3) + a.get_bit(7) as u8 + } + + fn init_ep_context(&mut self) { + self.set_interval(); + + let ep_ty = self.ep.ty(); + self.ep_cx().set_endpoint_type(ep_ty); + + // TODO: This initializes the context only for USB2. Branch if the version of a device is + // USB3. + match ep_ty { + EndpointType::Control => self.init_for_control(), + EndpointType::BulkOut | EndpointType::BulkIn => self.init_for_bulk(), + EndpointType::IsochOut + | EndpointType::IsochIn + | EndpointType::InterruptOut + | EndpointType::InterruptIn => self.init_for_isoch_or_interrupt(), + EndpointType::NotValid => unreachable!("Not Valid Endpoint should not exist."), + } + } + + fn init_for_control(&mut self) { + assert_eq!( + self.ep.ty(), + EndpointType::Control, + "Not the Control Endpoint." + ); + + let sz = self.ep.max_packet_size; + let a = self.transfer_ring_addr; + let c = self.ep_cx(); + + c.set_max_packet_size(sz); + c.set_error_count(3); + c.set_tr_dequeue_pointer(a.as_usize() as u64); + c.set_dequeue_cycle_state(); + } + + fn init_for_bulk(&mut self) { + assert!(self.is_bulk(), "Not the Bulk Endpoint."); + + let sz = self.ep.max_packet_size; + let a = self.transfer_ring_addr; + let c = self.ep_cx(); + + c.set_max_packet_size(sz); + c.set_max_burst_size(0); + c.set_error_count(3); + c.set_max_primary_streams(0); + c.set_tr_dequeue_pointer(a.as_usize() as u64); + c.set_dequeue_cycle_state(); + } + + fn is_bulk(&self) -> bool { + let t = self.ep.ty(); + + [EndpointType::BulkOut, EndpointType::BulkIn].contains(&t) + } + + fn init_for_isoch_or_interrupt(&mut self) { + let t = self.ep.ty(); + assert!( + self.is_isoch_or_interrupt(), + "Not the Isochronous or the Interrupt Endpoint." + ); + + let sz = self.ep.max_packet_size; + let a = self.transfer_ring_addr; + let c = self.ep_cx(); + + c.set_max_packet_size(sz & 0x7ff); + c.set_max_burst_size(((sz & 0x1800) >> 11).try_into().unwrap()); + c.set_mult(0); + + if let EndpointType::IsochOut | EndpointType::IsochIn = t { + c.set_error_count(0); + } else { + c.set_error_count(3); + } + c.set_tr_dequeue_pointer(a.as_usize() as u64); + c.set_dequeue_cycle_state(); + } + + fn is_isoch_or_interrupt(&self) -> bool { + let t = self.ep.ty(); + [ + EndpointType::IsochOut, + EndpointType::IsochIn, + EndpointType::InterruptOut, + EndpointType::InterruptIn, + ] + .contains(&t) + } + + // TODO: Is this calculation correct? + fn set_interval(&mut self) { + let s = self.port_speed(); + let t = self.ep.ty(); + let i = self.ep.interval; + + let i = if let PortSpeed::FullSpeed | PortSpeed::LowSpeed = s { + if let EndpointType::IsochOut | EndpointType::IsochIn = t { + i + 2 + } else { + i + 3 + } + } else { + i - 1 + }; + + self.ep_cx().set_interval(i); + } + + fn port_speed(&self) -> PortSpeed { + FromPrimitive::from_u8(registers::handle(|r| { + r.port_register_set + .read_volatile_at((self.port_number - 1).into()) + .portsc + .port_speed() + })) + .expect("Failed to get the Port Speed.") + } + + fn ep_cx(&mut self) -> &mut dyn EndpointHandler { + let ep_i: usize = self.ep.endpoint_address.get_bits(0..=3).into(); + let is_input: usize = self.ep.endpoint_address.get_bit(7) as _; + let dpi = 2 * ep_i + is_input; + + self.cx.input.device_mut().endpoint_mut(dpi) + } +} + +#[derive(Copy, Clone, FromPrimitive)] +enum PortSpeed { + FullSpeed = 1, + LowSpeed = 2, + HighSpeed = 3, + SuperSpeed = 4, + SuperSpeedPlus = 5, +} + +fn descriptors_to_endpoints( + f: &DescriptorFetcher, + descriptors: &[Descriptor], +) -> Vec { + descriptors + .iter() + .filter_map(|desc| { + let _ = &f; + if let Descriptor::Endpoint(e) = desc { + let d = DoorbellWriter::new(f.slot_number(), e.doorbell_value()); + let s = transfer::Sender::new(d); + Some(endpoint::NonDefault::new(*e, s)) + } else { + None + } + }) + .collect() +} diff --git a/crates/driver_usb/src/host/port/init/fully_operational.rs b/crates/driver_usb/src/host/port/init/fully_operational.rs new file mode 100644 index 0000000000..6a75bf3240 --- /dev/null +++ b/crates/driver_usb/src/host/port/init/fully_operational.rs @@ -0,0 +1,84 @@ +use crate::host::{ + page_box::PageBox, + port::endpoint::{self, Error, NonDefault}, + structures::descriptor::Descriptor, +}; + +use super::endpoints_initializer::EndpointsInitializer; +use alloc::vec::Vec; +use core::slice; +use log::debug; +use xhci::context::EndpointType; + +pub struct FullyOperational { + descriptors: Vec, + def_ep: endpoint::Default, + eps: Vec, +} +impl FullyOperational { + pub(super) fn new(i: EndpointsInitializer) -> Self { + let descriptors = i.descriptors(); + let (def_ep, eps) = i.endpoints(); + + debug!("Endpoints collected"); + + Self { + descriptors, + def_ep, + eps, + } + } + + pub(in super::super) fn ty(&self) -> (u8, u8, u8) { + for d in &self.descriptors { + if let Descriptor::Interface(i) = d { + return i.ty(); + } + } + + unreachable!("HID class must have at least one interface descriptor"); + } + + pub(in super::super) fn issue_normal_trb( + &mut self, + b: &PageBox, + ty: EndpointType, + ) -> Result<(), Error> { + for ep in &mut self.eps { + if ep.ty() == ty { + ep.issue_normal_trb(b); + return Ok(()); + } + } + + Err(Error::NoSuchEndpoint(ty)) + } + + pub(in super::super) fn issue_nop_trb(&mut self) { + self.def_ep.issue_nop_trb(); + } + + pub(in super::super) fn set_configure(&mut self, config_val: u8) { + self.def_ep.set_configuration(config_val); + } + + pub(in super::super) fn set_idle(&mut self) { + self.def_ep.set_idle(); + } + + pub(in super::super) fn set_boot_protocol(&mut self) { + self.def_ep.set_boot_protocol(); + } + + pub(in super::super) fn descriptors(&self) -> &[Descriptor] { + &self.descriptors + } +} +impl<'a> IntoIterator for &'a mut FullyOperational { + type Item = &'a mut NonDefault; + type IntoIter = slice::IterMut<'a, NonDefault>; + + fn into_iter(self) -> Self::IntoIter { + self.eps.iter_mut() + } +} diff --git a/crates/driver_usb/src/host/port/init/max_packet_size_setter.rs b/crates/driver_usb/src/host/port/init/max_packet_size_setter.rs new file mode 100644 index 0000000000..bbeaf3da71 --- /dev/null +++ b/crates/driver_usb/src/host/port/init/max_packet_size_setter.rs @@ -0,0 +1,73 @@ +use crate::host::{exchanger, port::endpoint, structures::context::Context}; + +use super::{ + descriptor_fetcher::DescriptorFetcher, slot_structures_initializer::SlotStructuresInitializer, +}; +use alloc::sync::Arc; +use spinning_top::Spinlock; + +pub(super) struct MaxPacketSizeSetter { + ep: endpoint::Default, + cx: Arc>, + port_number: u8, + slot_number: u8, +} +impl MaxPacketSizeSetter { + pub(super) fn new(i: SlotStructuresInitializer) -> Self { + let cx = i.context(); + let port_number = i.port_number(); + let slot_number = i.slot_number(); + let ep = i.ep0(); + + Self { + ep, + cx, + port_number, + slot_number, + } + } + + pub(super) fn set(mut self) -> DescriptorFetcher { + let s = self.max_packet_size(); + self.set_max_packet_size(s); + self.evaluate_context(); + + DescriptorFetcher::new(self) + } + + pub(super) fn port_number(&self) -> u8 { + self.port_number + } + + pub(super) fn slot_number(&self) -> u8 { + self.slot_number + } + + pub(super) fn context(&self) -> Arc> { + self.cx.clone() + } + + pub(super) fn ep0(self) -> endpoint::Default { + self.ep + } + + fn max_packet_size(&mut self) -> u16 { + self.ep.get_max_packet_size() + } + + fn set_max_packet_size(&mut self, s: u16) { + let mut cx = self.cx.lock(); + let ep_0 = cx.input.device_mut().endpoint_mut(1); + + ep_0.set_max_packet_size(s); + } + + fn evaluate_context(&self) { + let mut cx = self.cx.lock(); + let i = &mut cx.input; + + i.control_mut().set_add_context_flag(1); + + exchanger::command::evaluate_context(i.virt_addr(), self.slot_number) + } +} diff --git a/crates/driver_usb/src/host/port/init/mod.rs b/crates/driver_usb/src/host/port/init/mod.rs new file mode 100644 index 0000000000..9a19bfaf7d --- /dev/null +++ b/crates/driver_usb/src/host/port/init/mod.rs @@ -0,0 +1,24 @@ +use fully_operational::FullyOperational; +use log::debug; +use resetter::Resetter; + +mod descriptor_fetcher; +mod endpoints_initializer; +pub(super) mod fully_operational; +mod max_packet_size_setter; +mod resetter; +mod slot_structures_initializer; + +pub(super) fn init(port_number: u8) -> FullyOperational { + let resetter = Resetter::new(port_number); + debug!("reset"); + let slot_structures_initializer = resetter.reset(); + debug!("init"); + let max_packet_size_setter = slot_structures_initializer.init(); + debug!("set"); + let descriptor_fetcher = max_packet_size_setter.set(); + debug!("fetch"); + let endpoints_initializer = descriptor_fetcher.fetch(); + debug!("complete"); + endpoints_initializer.init() +} diff --git a/crates/driver_usb/src/host/port/init/resetter.rs b/crates/driver_usb/src/host/port/init/resetter.rs new file mode 100644 index 0000000000..790ed5b9f2 --- /dev/null +++ b/crates/driver_usb/src/host/port/init/resetter.rs @@ -0,0 +1,67 @@ +use crate::host::structures::registers; + +use super::slot_structures_initializer::SlotStructuresInitializer; +use log::debug; +use xhci::registers::PortRegisterSet; + +pub(super) struct Resetter { + port_number: u8, +} +impl Resetter { + pub(super) fn new(port_number: u8) -> Self { + Self { port_number } + } + + pub(super) fn port_number(&self) -> u8 { + self.port_number + } + + pub(super) fn reset(self) -> SlotStructuresInitializer { + self.start_resetting(); + self.wait_until_reset_is_completed(); + SlotStructuresInitializer::new(self) + } + + fn start_resetting(&self) { + self.update_port_register(|port| { + debug!("before reset Port, status: {:?}", port.portsc); + port.portsc.set_0_port_enabled_disabled(); + port.portsc.set_port_reset(); + }); + } + + fn wait_until_reset_is_completed(&self) { + while !self.reset_completed() {} + // self.update_port_register(|p| { + // // p.portsc.clear_port_reset_change(); + // }); + debug!( + "reset complete, state: {:?}", + self.read_port_register(|port| { port.portsc }) + ); + } + + fn reset_completed(&self) -> bool { + self.read_port_register(|r| r.portsc.port_reset_change()) + } + + fn read_port_register(&self, f: T) -> U + where + T: FnOnce(&PortRegisterSet) -> U, + { + registers::handle(|r| { + f(&r.port_register_set + .read_volatile_at((self.port_number - 1).into())) + }) + } + + fn update_port_register(&self, f: T) + where + T: FnOnce(&mut PortRegisterSet), + { + registers::handle(|r| { + r.port_register_set + .update_volatile_at((self.port_number - 1).into(), f) + }) + } +} diff --git a/crates/driver_usb/src/host/port/init/slot_structures_initializer.rs b/crates/driver_usb/src/host/port/init/slot_structures_initializer.rs new file mode 100644 index 0000000000..2abad72676 --- /dev/null +++ b/crates/driver_usb/src/host/port/init/slot_structures_initializer.rs @@ -0,0 +1,153 @@ +use crate::host::{ + exchanger::{ + self, + transfer::{self, DoorbellWriter}, + }, + port::endpoint, + structures::{context::Context, dcbaa, registers}, +}; + +use super::{max_packet_size_setter::MaxPacketSizeSetter, resetter::Resetter}; +use alloc::sync::Arc; +use spinning_top::Spinlock; +use xhci::context::EndpointType; + +pub(super) struct SlotStructuresInitializer { + port_number: u8, + slot_number: u8, + cx: Arc>, + ep: endpoint::Default, +} +impl SlotStructuresInitializer { + pub(super) fn new(r: Resetter) -> Self { + let slot_number = exchanger::command::enable_device_slot(); + let cx = Arc::new(Spinlock::new(Context::default())); + let dbl_writer = DoorbellWriter::new(slot_number, 1); + + Self { + port_number: r.port_number(), + slot_number, + cx, + ep: endpoint::Default::new(transfer::Sender::new(dbl_writer)), + } + } + + pub(super) fn init(self) -> MaxPacketSizeSetter { + self.init_input_context(); + self.init_endpoint0_context(); + self.register_with_dcbaa(); + self.issue_address_device(); + + MaxPacketSizeSetter::new(self) + } + + pub(super) fn port_number(&self) -> u8 { + self.port_number + } + + pub(super) fn slot_number(&self) -> u8 { + self.slot_number + } + + pub(super) fn context(&self) -> Arc> { + self.cx.clone() + } + + pub(super) fn ep0(self) -> endpoint::Default { + self.ep + } + + fn init_input_context(&self) { + InputContextInitializer::new(&mut self.cx.lock(), self.port_number).init() + } + + fn init_endpoint0_context(&self) { + Ep0ContextInitializer::new(&mut self.cx.lock(), self.port_number, &self.ep).init() + } + + fn register_with_dcbaa(&self) { + let a = self.cx.lock().output.virt_addr(); + dcbaa::register_device_context_addr(self.slot_number.into(), a); + } + + fn issue_address_device(&self) { + let cx_addr = self.cx.lock().input.virt_addr(); + exchanger::command::address_device(cx_addr, self.slot_number); + } +} + +struct InputContextInitializer<'a> { + context: &'a mut Context, + port_number: u8, +} +impl<'a> InputContextInitializer<'a> { + fn new(context: &'a mut Context, port_number: u8) -> Self { + Self { + context, + port_number, + } + } + + fn init(&mut self) { + self.init_input_control(); + self.init_input_slot(); + } + + fn init_input_control(&mut self) { + let input_control = self.context.input.control_mut(); + input_control.set_add_context_flag(0); + input_control.set_add_context_flag(1); + } + + fn init_input_slot(&mut self) { + let slot = self.context.input.device_mut().slot_mut(); + slot.set_context_entries(1); + slot.set_root_hub_port_number(self.port_number); + } +} + +struct Ep0ContextInitializer<'a> { + cx: &'a mut Context, + port_number: u8, + ep: &'a endpoint::Default, +} +impl<'a> Ep0ContextInitializer<'a> { + fn new(cx: &'a mut Context, port_number: u8, ep: &'a endpoint::Default) -> Self { + Self { + cx, + port_number, + ep, + } + } + + fn init(self) { + let s = self.get_max_packet_size(); + let ep_0 = self.cx.input.device_mut().endpoint_mut(1); + + ep_0.set_endpoint_type(EndpointType::Control); + ep_0.set_max_packet_size(s); + ep_0.set_tr_dequeue_pointer(self.ep.ring_addr().as_usize() as u64); + ep_0.set_dequeue_cycle_state(); + ep_0.set_error_count(3); + } + + // TODO: This function does not check the actual port speed, instead it uses the normal + // correspondence between PSI and the port speed. + // The actual port speed is listed on the xHCI supported protocol capability. + // Check the capability and fetch the actual port speed. Then return the max packet size. + fn get_max_packet_size(&self) -> u16 { + let psi = registers::handle(|r| { + r.port_register_set + .read_volatile_at((self.port_number - 1).into()) + .portsc + .port_speed() + }); + + match psi { + 1 | 3 => 64, + 2 => 8, + 4 => 512, + _ => unimplemented!("PSI: {}", psi), + } + } +} diff --git a/crates/driver_usb/src/host/port/mod.rs b/crates/driver_usb/src/host/port/mod.rs new file mode 100644 index 0000000000..1b5d7e912a --- /dev/null +++ b/crates/driver_usb/src/host/port/mod.rs @@ -0,0 +1,101 @@ +use alloc::collections::VecDeque; +use conquer_once::spin::Lazy; +use core::{future::Future, pin::Pin, task::Poll}; +use futures_util::task::AtomicWaker; +use init::fully_operational::FullyOperational; +use log::{debug, info, warn}; +use spinning_top::Spinlock; + +use super::structures::registers; + +mod endpoint; +mod init; +mod spawner; + +static CURRENT_RESET_PORT: Lazy> = + Lazy::new(|| Spinlock::new(ResetPort::new())); + +struct ResetPort { + resetting: bool, +} +impl ResetPort { + fn new() -> Self { + Self { resetting: false } + } + + fn complete_reset(&mut self) { + self.resetting = false; + } + + fn resettable(&mut self) -> bool { + if self.resetting { + false + } else { + self.resetting = true; + true + } + } +} + +pub(crate) fn try_spawn(port_idx: u8) -> Result<(), spawner::PortNotConnected> { + spawner::try_spawn(port_idx) +} + +fn main(port_number: u8) { + debug!("get op!"); + let mut fully_operational = init_port_and_slot_exclusively(port_number); + + fully_operational.issue_nop_trb(); +} + +fn init_port_and_slot_exclusively(port_number: u8) -> FullyOperational { + let reset_waiter = ResetWaiterFuture; + debug!("waiting reset!"); + reset_waiter.poll(); + + debug!("init!"); + let fully_operational = init::init(port_number); + debug!("complete reset!"); + CURRENT_RESET_PORT.lock().complete_reset(); + info!("Port {} reset completed.", port_number); + fully_operational +} + +pub(crate) fn enum_all_connected_port() { + spawner::spawn_all_connected_ports(); +} + +fn max_num() -> u8 { + registers::handle(|r| r.capability.hcsparams1.read_volatile().number_of_ports()) +} + +fn connected(port_number: u8) -> bool { + registers::handle(|r| { + r.port_register_set + .read_volatile_at((port_number - 1).into()) + .portsc + .current_connect_status() + }) +} + +fn dump_port_status(port_number: u8) { + registers::handle(|r| { + debug!( + "port sttaus: {:?}", + r.port_register_set + .read_volatile_at((port_number - 1) as usize) + .portsc + ) + }) +} + +struct ResetWaiterFuture; +impl ResetWaiterFuture { + pub fn poll(&self) { + loop { + if CURRENT_RESET_PORT.lock().resettable() { + return; + } + } + } +} diff --git a/crates/driver_usb/src/host/port/spawner.rs b/crates/driver_usb/src/host/port/spawner.rs new file mode 100644 index 0000000000..f492745920 --- /dev/null +++ b/crates/driver_usb/src/host/port/spawner.rs @@ -0,0 +1,56 @@ +use alloc::collections::BTreeSet; +use log::debug; +use spinning_top::Spinlock; +use tock_registers::registers; + +static SPAWN_STATUS: Spinlock> = Spinlock::new(BTreeSet::new()); + +pub(crate) fn spawn_all_connected_ports() { + let n = super::max_num(); + debug!("port numbers: {n}"); + for i in 0..n { + let _ = try_spawn(i + 1); + } + debug!("done"); +} + +pub(crate) fn try_spawn(port_number: u8) -> Result<(), PortNotConnected> { + if spawnable(port_number) { + debug!("spawn port {port_number}"); + spawn(port_number); + Ok(()) + } else { + // Err(PortNotConnected) + debug!("return!"); + Ok(()) + } +} + +fn spawn(p: u8) { + debug!("mark as spawned"); + mark_as_spawned(p); + debug!("add task!"); + add_task_for_port(p); +} + +fn add_task_for_port(p: u8) { + super::main(p); +} + +fn spawnable(p: u8) -> bool { + let port = super::connected(p) && !spawned(p); + debug!("port {p} is {port}"); + super::dump_port_status(p); + port +} + +fn spawned(p: u8) -> bool { + SPAWN_STATUS.lock().contains(&p.into()) +} + +fn mark_as_spawned(p: u8) { + SPAWN_STATUS.lock().insert(p.into()); +} + +#[derive(Debug)] +pub(crate) struct PortNotConnected; diff --git a/crates/driver_usb/src/host/structures/context.rs b/crates/driver_usb/src/host/structures/context.rs new file mode 100644 index 0000000000..1c32cd24c9 --- /dev/null +++ b/crates/driver_usb/src/host/structures/context.rs @@ -0,0 +1,77 @@ +use crate::host::page_box::PageBox; + +use super::registers; +use alloc::boxed::Box; + +use axhal::mem::VirtAddr; +use xhci::context::{ + Device32Byte, Device64Byte, DeviceHandler, Input32Byte, Input64Byte, InputControlHandler, + InputHandler, +}; + +pub(crate) struct Context { + pub(crate) input: Input, + pub(crate) output: PageBox, +} +impl Default for Context { + fn default() -> Self { + Self { + input: Input::default(), + output: Device::default().into(), + } + } +} + +pub(crate) enum Input { + Byte64(PageBox), + Byte32(PageBox), +} +impl Input { + pub(crate) fn control_mut(&mut self) -> &mut dyn InputControlHandler { + match self { + Self::Byte32(b32) => b32.control_mut(), + Self::Byte64(b64) => b64.control_mut(), + } + } + + pub(crate) fn device_mut(&mut self) -> &mut dyn DeviceHandler { + match self { + Self::Byte32(b32) => b32.device_mut(), + Self::Byte64(b64) => b64.device_mut(), + } + } + + pub(crate) fn virt_addr(&self) -> VirtAddr { + match self { + Self::Byte32(b32) => b32.virt_addr(), + Self::Byte64(b64) => b64.virt_addr(), + } + } +} +impl Default for Input { + fn default() -> Self { + if csz() { + Self::Byte64(Input64Byte::default().into()) + } else { + Self::Byte32(Input32Byte::default().into()) + } + } +} + +pub(crate) enum Device { + Byte64(Box), + Byte32(Box), +} +impl Default for Device { + fn default() -> Self { + if csz() { + Self::Byte64(Device64Byte::default().into()) + } else { + Self::Byte32(Device32Byte::default().into()) + } + } +} + +fn csz() -> bool { + registers::handle(|r| r.capability.hccparams1.read_volatile().context_size()) +} diff --git a/crates/driver_usb/src/host/structures/dcbaa.rs b/crates/driver_usb/src/host/structures/dcbaa.rs new file mode 100644 index 0000000000..24bd31d08f --- /dev/null +++ b/crates/driver_usb/src/host/structures/dcbaa.rs @@ -0,0 +1,48 @@ +use crate::host::page_box::PageBox; + +use super::registers; +use axhal::mem::VirtAddr; +use conquer_once::spin::OnceCell; +use core::ops::DerefMut; +use spinning_top::Spinlock; + +static DCBAA: OnceCell>> = OnceCell::uninit(); + +pub fn init() { + DCBAA.init_once(|| Spinlock::new(PageBox::new_slice(VirtAddr::from(0), array_len()))); + + registers::handle(|r| { + r.operational.dcbaap.update_volatile(|d| { + d.set(lock().virt_addr().as_usize() as u64); + }) + }) +} + +pub fn register_device_context_addr(port_id: usize, a: VirtAddr) { + assert_ne!(port_id, 0, "A port ID must be greater than 0."); + + lock()[port_id] = a; +} + +pub fn register_scratchpad_addr(a: VirtAddr) { + lock()[0] = a; +} + +fn lock() -> impl DerefMut> { + DCBAA + .try_get() + .expect("`DCBAA` is not initialized.") + .try_lock() + .expect("Failed to lock `DCBAA`.") +} + +fn array_len() -> usize { + registers::handle(|r| { + r.capability + .hcsparams1 + .read_volatile() + .number_of_device_slots() + + 1 + }) + .into() +} diff --git a/crates/driver_usb/src/host/structures/descriptor.rs b/crates/driver_usb/src/host/structures/descriptor.rs new file mode 100644 index 0000000000..a76c4c6150 --- /dev/null +++ b/crates/driver_usb/src/host/structures/descriptor.rs @@ -0,0 +1,160 @@ +use bit_field::BitField; +use core::{convert::TryInto, ptr}; +use num_derive::FromPrimitive; +use num_traits::FromPrimitive; +use xhci::context::EndpointType; + +#[derive(Copy, Clone, Debug)] +pub(crate) enum Descriptor { + Device(Device), + Configuration(Configuration), + Str, + Interface(Interface), + Endpoint(Endpoint), + Hid, +} +impl Descriptor { + pub(crate) fn from_slice(raw: &[u8]) -> Result { + assert_eq!(raw.len(), raw[0].into()); + match FromPrimitive::from_u8(raw[1]) { + Some(t) => { + let raw: *const [u8] = raw; + match t { + // SAFETY: This operation is safe because the length of `raw` is equivalent to the + // one of the descriptor. + Ty::Device => Ok(Self::Device(unsafe { ptr::read(raw.cast()) })), + Ty::Configuration => Ok(Self::Configuration(unsafe { ptr::read(raw.cast()) })), + Ty::Str => Ok(Self::Str), + Ty::Interface => Ok(Self::Interface(unsafe { ptr::read(raw.cast()) })), + Ty::Endpoint => Ok(Self::Endpoint(unsafe { ptr::read(raw.cast()) })), + Ty::Hid => Ok(Self::Hid), + } + } + None => Err(Error::UnrecognizedType(raw[1])), + } + } +} + +#[derive(Copy, Clone, Default, Debug)] +#[repr(C, packed)] +pub(crate) struct Device { + len: u8, + descriptor_type: u8, + cd_usb: u16, + class: u8, + subclass: u8, + protocol: u8, + max_packet_size0: u8, + vendor: u16, + product_id: u16, + device: u16, + manufacture: u8, + product: u8, + serial_number: u8, + num_configurations: u8, +} +impl Device { + pub(crate) fn max_packet_size(&self) -> u16 { + if let (3, _) = self.version() { + 2_u16.pow(self.max_packet_size0.into()) + } else { + self.max_packet_size0.into() + } + } + + fn version(&self) -> (u8, u8) { + let cd_usb = self.cd_usb; + + ( + (cd_usb >> 8).try_into().unwrap(), + (cd_usb & 0xff).try_into().unwrap(), + ) + } +} + +#[derive(Copy, Clone, Debug, Default)] +#[repr(C, packed)] +pub(crate) struct Configuration { + length: u8, + ty: u8, + total_length: u16, + num_interfaces: u8, + config_val: u8, + config_string: u8, + attributes: u8, + max_power: u8, +} +impl Configuration { + pub(crate) fn config_val(&self) -> u8 { + self.config_val + } +} + +#[derive(Copy, Clone, Default, Debug)] +#[repr(C, packed)] +pub(crate) struct Interface { + len: u8, + descriptor_type: u8, + interface_number: u8, + alternate_setting: u8, + num_endpoints: u8, + interface_class: u8, + interface_subclass: u8, + interface_protocol: u8, + interface: u8, +} +impl Interface { + pub(crate) fn ty(&self) -> (u8, u8, u8) { + ( + self.interface_class, + self.interface_subclass, + self.interface_protocol, + ) + } +} + +#[derive(Copy, Clone, Default, Debug)] +#[repr(C, packed)] +pub(crate) struct Endpoint { + len: u8, + descriptor_type: u8, + pub(crate) endpoint_address: u8, + pub(crate) attributes: u8, + pub(crate) max_packet_size: u16, + pub(crate) interval: u8, +} +impl Endpoint { + pub(crate) fn ty(self) -> EndpointType { + EndpointType::from_u8(if self.attributes == 0 { + 4 + } else { + self.attributes.get_bits(0..=1) + + if self.endpoint_address.get_bit(7) { + 4 + } else { + 0 + } + }) + .expect("EndpointType must be convertible from `attributes` and `endpoint_address`.") + } + + pub(crate) fn doorbell_value(self) -> u32 { + 2 * u32::from(self.endpoint_address.get_bits(0..=3)) + + self.endpoint_address.get_bit(7) as u32 + } +} + +#[derive(FromPrimitive)] +pub(crate) enum Ty { + Device = 1, + Configuration = 2, + Str = 3, + Interface = 4, + Endpoint = 5, + Hid = 33, +} + +#[derive(Debug)] +pub(crate) enum Error { + UnrecognizedType(u8), +} diff --git a/crates/driver_usb/src/host/structures/extended_capabilities.rs b/crates/driver_usb/src/host/structures/extended_capabilities.rs new file mode 100644 index 0000000000..138413a32e --- /dev/null +++ b/crates/driver_usb/src/host/structures/extended_capabilities.rs @@ -0,0 +1,42 @@ +use crate::host::mapper::Mapper; + +use super::registers; +use axhal::mem::VirtAddr; +use conquer_once::spin::OnceCell; +use core::convert::TryInto; +use spinning_top::Spinlock; + +use xhci::{extended_capabilities, ExtendedCapability}; + +static EXTENDED_CAPABILITIES: OnceCell>>> = + OnceCell::uninit(); + +/// # Safety +/// +/// `mmio_base` must be the correct one. +pub(crate) unsafe fn init(mmio_base: VirtAddr) { + let hccparams1 = registers::handle(|r| r.capability.hccparams1.read_volatile()); + + EXTENDED_CAPABILITIES + .try_init_once(|| { + Spinlock::new(extended_capabilities::List::new( + mmio_base.as_usize(), + hccparams1, + Mapper, + )) + }) + .expect("Failed to initialize `EXTENDED_CAPABILITIES`."); +} + +pub(crate) fn iter() -> Option< + impl Iterator, extended_capabilities::NotSupportedId>>, +> { + Some( + EXTENDED_CAPABILITIES + .try_get() + .expect("`EXTENDED_CAPABILITIES` is not initialized.`") + .lock() + .as_mut()? + .into_iter(), + ) +} diff --git a/crates/driver_usb/src/host/structures/mod.rs b/crates/driver_usb/src/host/structures/mod.rs new file mode 100644 index 0000000000..6093081fd2 --- /dev/null +++ b/crates/driver_usb/src/host/structures/mod.rs @@ -0,0 +1,7 @@ +pub(crate) mod context; +pub(crate) mod dcbaa; +pub(crate) mod descriptor; +pub(super) mod extended_capabilities; +pub(super) mod registers; +pub(crate) mod ring; +pub(crate) mod scratchpad; diff --git a/crates/driver_usb/src/host/structures/registers.rs b/crates/driver_usb/src/host/structures/registers.rs new file mode 100644 index 0000000000..9b57c24962 --- /dev/null +++ b/crates/driver_usb/src/host/structures/registers.rs @@ -0,0 +1,36 @@ +use axhal::mem::VirtAddr; +use conquer_once::spin::OnceCell; +use core::convert::TryInto; +use spinning_top::Spinlock; +use xhci::Registers; + +use crate::host::mapper::Mapper; + +static REGISTERS: OnceCell>> = OnceCell::uninit(); + +/// # Safety +/// +/// `mmio_base` must be the correct one. +pub(crate) unsafe fn init(mmio_base: VirtAddr) { + let mmio_base: usize = mmio_base.as_usize(); + + REGISTERS + .try_init_once(|| Spinlock::new(Registers::new(mmio_base, Mapper))) + .expect("Failed to initialize `REGISTERS`.") +} + +/// Handle xHCI registers. +/// +/// To avoid deadlocking, this method takes a closure. Caller is supposed not to call this method +/// inside the closure, otherwise a deadlock will happen. +/// +/// Alternative implementation is to define a method which returns `impl Deref`, but this will expand the scope of the mutex guard, increasing the possibility of +/// deadlocks. +pub(crate) fn handle(f: T) -> U +where + T: FnOnce(&mut Registers) -> U, +{ + let mut r = REGISTERS.try_get().unwrap().lock(); + f(&mut r) +} diff --git a/crates/driver_usb/src/host/structures/ring/command/mod.rs b/crates/driver_usb/src/host/structures/ring/command/mod.rs new file mode 100644 index 0000000000..ce4a7cf1a5 --- /dev/null +++ b/crates/driver_usb/src/host/structures/ring/command/mod.rs @@ -0,0 +1,140 @@ +use crate::host::{page_box::PageBox, structures::registers}; + +use super::CycleBit; +use axhal::mem::VirtAddr; +use page_table::PageSize; +use trb::Link; +use xhci::ring::{trb, trb::command}; + +#[allow(clippy::cast_possible_truncation)] +const NUM_OF_TRBS: usize = PageSize::Size4K as usize / trb::BYTES; + +pub(crate) struct Ring { + raw: Raw, +} +impl Ring { + pub(crate) fn new() -> Self { + Self { raw: Raw::new() } + } + + pub(crate) fn init(&mut self) { + Initializer::new(self).init(); + } + + pub(crate) fn enqueue(&mut self, trb: command::Allowed) -> VirtAddr { + let a = self.raw.enqueue(trb); + Self::notify_command_is_sent(); + a + } + + fn phys_addr(&self) -> VirtAddr { + self.raw.head_addr() + } + + fn notify_command_is_sent() { + registers::handle(|r| { + r.doorbell.update_volatile_at(0, |r| { + r.set_doorbell_target(0); + }); + }) + } +} +impl Default for Ring { + fn default() -> Self { + Self::new() + } +} + +struct Raw { + raw: PageBox<[[u32; 4]]>, + enq_p: usize, + c: CycleBit, +} +impl Raw { + fn new() -> Self { + Self { + raw: PageBox::new_slice([0; 4], NUM_OF_TRBS), + enq_p: 0, + c: CycleBit::new(true), + } + } + + fn enqueue(&mut self, mut trb: command::Allowed) -> VirtAddr { + self.set_cycle_bit(&mut trb); + self.write_trb(trb); + let trb_a = self.enq_addr(); + self.increment(); + trb_a + } + + fn write_trb(&mut self, trb: command::Allowed) { + self.raw[self.enq_p] = trb.into_raw(); + } + + fn increment(&mut self) { + self.enq_p += 1; + if !self.enq_p_within_ring() { + self.enq_link(); + self.move_enq_p_to_the_beginning(); + } + } + + fn enq_p_within_ring(&self) -> bool { + self.enq_p < self.len() - 1 + } + + fn enq_link(&mut self) { + // Don't call `enqueue`. It will return an `Err` value as there is no space for link TRB. + let t = *Link::default().set_ring_segment_pointer(self.head_addr().as_usize() as u64); + let mut t = command::Allowed::Link(t); + self.set_cycle_bit(&mut t); + self.raw[self.enq_p] = t.into_raw(); + } + + fn move_enq_p_to_the_beginning(&mut self) { + self.enq_p = 0; + self.c.toggle(); + } + + fn enq_addr(&self) -> VirtAddr { + self.head_addr() + trb::BYTES * self.enq_p + } + + fn head_addr(&self) -> VirtAddr { + self.raw.virt_addr() + } + + fn len(&self) -> usize { + self.raw.len() + } + + fn set_cycle_bit(&self, trb: &mut command::Allowed) { + if self.c == CycleBit::new(true) { + trb.set_cycle_bit(); + } else { + trb.clear_cycle_bit(); + } + } +} + +struct Initializer<'a> { + ring: &'a Ring, +} +impl<'a> Initializer<'a> { + fn new(ring: &'a Ring) -> Self { + Self { ring } + } + + fn init(&mut self) { + registers::handle(|r| { + let a = self.ring.phys_addr(); + + // Do not split this closure to avoid read-modify-write bug. Reading fields may return + // 0, this will cause writing 0 to fields. + r.operational.crcr.update_volatile(|c| { + c.set_command_ring_pointer(a.as_usize() as u64); + c.set_ring_cycle_state(); + }); + }) + } +} diff --git a/crates/driver_usb/src/host/structures/ring/event/mod.rs b/crates/driver_usb/src/host/structures/ring/event/mod.rs new file mode 100644 index 0000000000..52ac5c9380 --- /dev/null +++ b/crates/driver_usb/src/host/structures/ring/event/mod.rs @@ -0,0 +1,282 @@ +use crate::host::{exchanger::receiver, page_box::PageBox, port, structures::registers}; + +use super::CycleBit; +use alloc::vec::Vec; +use axhal::mem::VirtAddr; +use bit_field::BitField; +use conquer_once::spin::OnceCell; +use core::{convert::TryInto, pin::Pin}; +use log::{debug, info, warn}; +use page_table::PageSize; +use segment_table::SegmentTable; +use spinning_top::Spinlock; +use xhci::ring::trb::{ + self, + event::{self, CompletionCode}, +}; + +mod segment_table; + +static EVENT_RING: OnceCell> = OnceCell::uninit(); + +pub fn init() { + let ring = Spinlock::new(Ring::new()); + ring.lock().init(); + + EVENT_RING + .try_init_once(|| ring) + .expect("`EVENT_RING` is initialized more than once."); +} + +//TODO use this +pub(crate) fn poll() { + debug!("This is the Event ring task."); + + loop { + let trb = EVENT_RING + .get() + .expect("The event ring is not initialized") + .try_lock() + .expect("Failed to lock the event ring.") + .next(); + { + if let event::Allowed::CommandCompletion(x) = trb { + debug!("complete ! {:?}", x); + assert_eq!(x.completion_code(), Ok(CompletionCode::Success)); + + receiver::receive(trb); + return; + } else if let event::Allowed::TransferEvent(x) = trb { + debug!("transfer! {:?}", x); + assert_eq!(x.completion_code(), Ok(CompletionCode::Success)); + + receiver::receive(trb); + } else if let event::Allowed::PortStatusChange(p) = trb { + debug!("status change! {:?}", p); + let _ = port::try_spawn(p.port_id()); + debug!("evt spawnned!"); + } + } + } +} + +#[allow(clippy::cast_possible_truncation)] +const MAX_NUM_OF_TRB_IN_QUEUE: u16 = PageSize::Size4K as u16 / trb::BYTES as u16; + +pub(crate) struct Ring { + segment_table: SegmentTable, + raw: Raw, +} +impl Ring { + pub(crate) fn new() -> Self { + let max_num_of_erst = registers::handle(|r| { + r.capability + .hcsparams2 + .read_volatile() + .event_ring_segment_table_max() + }); + + Self { + segment_table: SegmentTable::new(max_num_of_erst.into()), + raw: Raw::new(), + } + } + + pub(crate) fn init(&mut self) { + self.init_dequeue_ptr(); + self.init_tbl(); + } + + fn init_dequeue_ptr(&mut self) { + self.raw.update_deq_p_with_xhci() + } + + fn virt_addr_to_segment_table(&self) -> VirtAddr { + self.segment_table.virt_addr() + } + + fn init_tbl(&mut self) { + SegTblInitializer::new(self).init(); + } + + fn try_dequeue(&mut self) -> Option { + self.raw.try_dequeue() + } + + fn ring_addrs(&self) -> Vec { + self.raw.head_addrs() + } + + fn iter_tbl_entries_mut(&mut self) -> impl Iterator { + self.segment_table.iter_mut() + } +} +impl Ring { + pub fn next(&mut self) -> event::Allowed { + loop { + if let Some(allowed) = self.try_dequeue() { + return allowed; + } + } + } +} + +struct Raw { + rings: Vec>, + c: CycleBit, + deq_p_seg: usize, + deq_p_trb: usize, +} +impl Raw { + fn new() -> Self { + let rings = Self::new_rings(); + Self { + rings, + c: CycleBit::new(true), + deq_p_seg: 0, + deq_p_trb: 0, + } + } + + fn new_rings() -> Vec> { + let mut v = Vec::new(); + for _ in 0..Self::max_num_of_erst() { + v.push(PageBox::new_slice([0; 4], MAX_NUM_OF_TRB_IN_QUEUE.into())); + } + + v + } + + fn max_num_of_erst() -> u16 { + registers::handle(|r| { + r.capability + .hcsparams2 + .read_volatile() + .event_ring_segment_table_max() + }) + } + + fn try_dequeue(&mut self) -> Option { + if self.empty() { + None + } else { + self.dequeue() + } + } + + fn empty(&self) -> bool { + self.c_bit_of_next_trb() != self.c + } + + fn c_bit_of_next_trb(&self) -> CycleBit { + let t = self.rings[self.deq_p_seg][self.deq_p_trb]; + CycleBit::new(t[3].get_bit(0)) + } + + fn dequeue(&mut self) -> Option { + let t = self.get_next_trb().ok(); + self.increment(); + t + } + + fn get_next_trb(&self) -> Result { + let r = self.rings[self.deq_p_seg][self.deq_p_trb]; + let t = r.try_into(); + if t.is_err() { + warn!("Unrecognized ID: {}", r[3].get_bits(10..=15)); + } + t + } + + fn increment(&mut self) { + self.deq_p_trb += 1; + if self.deq_p_trb >= MAX_NUM_OF_TRB_IN_QUEUE.into() { + self.deq_p_trb = 0; + self.deq_p_seg += 1; + + if self.deq_p_seg >= self.num_of_erst() { + self.deq_p_seg = 0; + self.c.toggle(); + } + } + } + + fn num_of_erst(&self) -> usize { + self.rings.len() + } + + fn update_deq_p_with_xhci(&self) { + registers::handle(|r| { + let _ = &self; + + r.interrupter_register_set + .interrupter_mut(0) + .erdp + .update_volatile(|r| { + r.set_event_ring_dequeue_pointer(self.next_trb_addr().as_usize() as u64) + }); + }); + } + + fn next_trb_addr(&self) -> VirtAddr { + self.rings[self.deq_p_seg].virt_addr() + trb::BYTES * self.deq_p_trb + } + + fn head_addrs(&self) -> Vec { + self.rings.iter().map(PageBox::virt_addr).collect() + } +} + +struct SegTblInitializer<'a> { + ring: &'a mut Ring, +} +impl<'a> SegTblInitializer<'a> { + fn new(ring: &'a mut Ring) -> Self { + Self { ring } + } + + fn init(&mut self) { + self.write_addrs(); + self.register_tbl_sz(); + self.enable_event_ring(); + } + + fn write_addrs(&mut self) { + let addrs = self.ring.ring_addrs(); + for (entry, addr) in self.ring.iter_tbl_entries_mut().zip(addrs) { + entry.set(addr, MAX_NUM_OF_TRB_IN_QUEUE); + } + } + + fn register_tbl_sz(&mut self) { + registers::handle(|r| { + let l = self.tbl_len(); + + r.interrupter_register_set + .interrupter_mut(0) + .erstsz + .update_volatile(|r| r.set(l.try_into().unwrap())); + }) + } + + fn enable_event_ring(&mut self) { + registers::handle(|r| { + let a = self.tbl_addr(); + + r.interrupter_register_set + .interrupter_mut(0) + .erstba + .update_volatile(|r| { + r.set(a.as_usize() as u64); + }) + }); + } + + fn tbl_addr(&self) -> VirtAddr { + self.ring.virt_addr_to_segment_table() + } + + fn tbl_len(&self) -> usize { + self.ring.segment_table.len() + } +} diff --git a/crates/driver_usb/src/host/structures/ring/event/segment_table.rs b/crates/driver_usb/src/host/structures/ring/event/segment_table.rs new file mode 100644 index 0000000000..09a432ba98 --- /dev/null +++ b/crates/driver_usb/src/host/structures/ring/event/segment_table.rs @@ -0,0 +1,69 @@ +use core::{ + ops::{Index, IndexMut}, + slice, +}; + +use axhal::mem::VirtAddr; + +use crate::host::page_box::PageBox; + +#[derive(Debug)] +pub struct SegmentTable(PageBox<[Entry]>); +impl SegmentTable { + pub fn new(len: usize) -> Self { + Self(PageBox::new_slice(Entry::null(), len)) + } + + pub fn virt_addr(&self) -> VirtAddr { + self.0.virt_addr() + } + + pub fn len(&self) -> usize { + self.0.len() + } + + pub fn iter_mut(&mut self) -> impl Iterator { + self.0.iter_mut() + } +} +impl Index for SegmentTable { + type Output = Entry; + + fn index(&self, index: usize) -> &Self::Output { + &self.0[index] + } +} +impl IndexMut for SegmentTable { + fn index_mut(&mut self, index: usize) -> &mut Self::Output { + &mut self.0[index] + } +} +impl<'a> IntoIterator for &'a mut SegmentTable { + type Item = &'a mut Entry; + type IntoIter = slice::IterMut<'a, Entry>; + + fn into_iter(self) -> Self::IntoIter { + self.0.iter_mut() + } +} + +#[repr(C, packed)] +#[derive(Copy, Clone, Debug)] +pub struct Entry { + base_address: u64, + segment_size: u64, +} +impl Entry { + // Although the size of segment_size is u64, bits 16:63 are reserved. + pub fn set(&mut self, addr: VirtAddr, size: u16) { + self.base_address = addr.as_usize() as u64; + self.segment_size = size.into(); + } + + fn null() -> Self { + Self { + base_address: 0, + segment_size: 0, + } + } +} diff --git a/crates/driver_usb/src/host/structures/ring/mod.rs b/crates/driver_usb/src/host/structures/ring/mod.rs new file mode 100644 index 0000000000..e33f4772e1 --- /dev/null +++ b/crates/driver_usb/src/host/structures/ring/mod.rs @@ -0,0 +1,20 @@ +pub(crate) mod command; +pub(crate) mod event; +pub(crate) mod transfer; + +#[derive(Copy, Clone, PartialOrd, Ord, PartialEq, Eq, Debug)] +pub struct CycleBit(bool); +impl CycleBit { + pub fn new(val: bool) -> Self { + Self(val) + } + + fn toggle(&mut self) { + self.0 = !self.0; + } +} +impl From for bool { + fn from(cycle_bit: CycleBit) -> Self { + cycle_bit.0 + } +} diff --git a/crates/driver_usb/src/host/structures/ring/transfer/mod.rs b/crates/driver_usb/src/host/structures/ring/transfer/mod.rs new file mode 100644 index 0000000000..79c23b6eb1 --- /dev/null +++ b/crates/driver_usb/src/host/structures/ring/transfer/mod.rs @@ -0,0 +1,101 @@ +use crate::host::page_box::PageBox; + +use super::CycleBit; +use alloc::vec::Vec; +use axhal::mem::VirtAddr; +use trb::Link; + +use xhci::ring::{trb, trb::transfer}; + +const SIZE_OF_RING: usize = 256; + +pub(crate) struct Ring { + raw: Raw, +} +impl Ring { + pub(crate) fn new() -> Self { + Self { raw: Raw::new() } + } + + pub(crate) fn virt_addr(&self) -> VirtAddr { + self.raw.virt_addr() + } + + pub(crate) fn enqueue(&mut self, trbs: &[transfer::Allowed]) -> Vec { + self.raw.enqueue_trbs(trbs) + } +} + +struct Raw { + ring: PageBox<[[u32; 4]]>, + enq_p: usize, + c: CycleBit, +} +impl Raw { + fn new() -> Self { + Self { + ring: PageBox::new_slice([0; 4], SIZE_OF_RING), + enq_p: 0, + c: CycleBit::new(true), + } + } + + fn enqueue_trbs(&mut self, trbs: &[transfer::Allowed]) -> Vec { + trbs.iter().map(|t| self.enqueue(*t)).collect() + } + + fn enqueue(&mut self, mut trb: transfer::Allowed) -> VirtAddr { + self.set_cycle_bit(&mut trb); + self.write_trb_on_memory(trb); + let addr_to_trb = self.addr_to_enqueue_ptr(); + self.increment_enqueue_ptr(); + + addr_to_trb + } + + fn write_trb_on_memory(&mut self, trb: transfer::Allowed) { + self.ring[self.enq_p] = trb.into_raw(); + } + + fn addr_to_enqueue_ptr(&self) -> VirtAddr { + self.virt_addr() + trb::BYTES * self.enq_p + } + + fn virt_addr(&self) -> VirtAddr { + self.ring.virt_addr() + } + + fn increment_enqueue_ptr(&mut self) { + self.enq_p += 1; + if self.enq_p < self.len() - 1 { + return; + } + + self.append_link_trb(); + self.move_enqueue_ptr_to_the_beginning(); + } + + fn len(&self) -> usize { + self.ring.len() + } + + fn append_link_trb(&mut self) { + let t = *Link::default().set_ring_segment_pointer(self.virt_addr().as_usize() as u64); + let mut t = transfer::Allowed::Link(t); + self.set_cycle_bit(&mut t); + self.ring[self.enq_p] = t.into_raw(); + } + + fn move_enqueue_ptr_to_the_beginning(&mut self) { + self.enq_p = 0; + self.c.toggle(); + } + + fn set_cycle_bit(&self, trb: &mut transfer::Allowed) { + if self.c == CycleBit::new(true) { + trb.set_cycle_bit(); + } else { + trb.clear_cycle_bit(); + } + } +} diff --git a/crates/driver_usb/src/host/structures/scratchpad.rs b/crates/driver_usb/src/host/structures/scratchpad.rs new file mode 100644 index 0000000000..acb6d1c47e --- /dev/null +++ b/crates/driver_usb/src/host/structures/scratchpad.rs @@ -0,0 +1,91 @@ +use crate::host::page_box::PageBox; + +use super::{dcbaa, registers}; +use alloc::vec::Vec; +use axhal::mem::VirtAddr; +use conquer_once::spin::OnceCell; +use core::alloc::Layout; +use core::convert::TryInto; +use os_units::Bytes; + +static SCRATCHPAD: OnceCell = OnceCell::uninit(); + +pub(crate) fn init() { + if Scratchpad::needed() { + init_static(); + } +} + +fn init_static() { + let mut scratchpad = Scratchpad::new(); + scratchpad.init(); + scratchpad.register_with_dcbaa(); + + SCRATCHPAD.init_once(|| scratchpad) +} + +struct Scratchpad { + arr: PageBox<[VirtAddr]>, + bufs: Vec>, +} +impl Scratchpad { + fn new() -> Self { + let len: usize = Self::num_of_buffers().try_into().unwrap(); + + Self { + arr: PageBox::new_slice(VirtAddr::from(0), len), + bufs: Vec::new(), + } + } + + fn needed() -> bool { + Self::num_of_buffers() > 0 + } + + fn init(&mut self) { + self.allocate_buffers(); + self.write_buffer_addresses(); + } + + fn register_with_dcbaa(&self) { + dcbaa::register_device_context_addr(0, self.arr.virt_addr()); + } + + fn allocate_buffers(&mut self) { + let layout = + Layout::from_size_align(Self::page_size().as_usize(), Self::page_size().as_usize()); + let layout = layout.unwrap_or_else(|_| { + panic!( + "Failed to create a layout for {} bytes with {} bytes alignment", + Self::page_size().as_usize(), + Self::page_size().as_usize() + ) + }); + + for _ in 0..Self::num_of_buffers() { + let b = PageBox::from_layout_zeroed(layout); + + self.bufs.push(b); + } + } + + fn write_buffer_addresses(&mut self) { + let page_size: usize = Self::page_size().as_usize(); + for (x, buf) in self.arr.iter_mut().zip(self.bufs.iter()) { + *x = buf.virt_addr().align_up(page_size); + } + } + + fn num_of_buffers() -> u32 { + registers::handle(|r| { + r.capability + .hcsparams2 + .read_volatile() + .max_scratchpad_buffers() + }) + } + + fn page_size() -> Bytes { + Bytes::new(registers::handle(|r| r.operational.pagesize.read_volatile().get()).into()) + } +} diff --git a/crates/driver_usb/src/host/usb/drivers/driver_usb_hid/mod.rs b/crates/driver_usb/src/host/usb/drivers/driver_usb_hid/mod.rs new file mode 100644 index 0000000000..dba3485d09 --- /dev/null +++ b/crates/driver_usb/src/host/usb/drivers/driver_usb_hid/mod.rs @@ -0,0 +1,284 @@ +use core::{marker::PhantomData, time::Duration}; + +use alloc::{collections::BTreeMap, fmt::format, string::String, sync::Arc}; +use alloc::{format, vec}; +use axhal::{paging::PageSize, time::busy_wait}; +use axtask::sleep_until; +use driver_common::BaseDriverOps; +use log::debug; +use num_traits::{FromPrimitive, ToPrimitive}; +use spinlock::SpinNoIrq; +use xhci::ring::trb::command; +use xhci::ring::trb::transfer::{self, Direction, Normal, TransferType}; + +use crate::host::xhci::ring::Ring; +use crate::{ + ax::USBDeviceDriverOps, + dma::DMA, + host::{ + usb::descriptors::{ + self, + desc_device::{Device, USBDeviceClassCode}, + desc_hid::{Hid, USBHIDProtocolDescriptorType, USBHIDSubclassDescriptorType}, + DescriptionTypeIndexPairForControlTransfer, Descriptor, DescriptorType, + }, + xhci::{xhci_device::DeviceAttached, Xhci}, + }, + OsDep, +}; + +const TAG: &str = "[USB-HID DRIVER]"; + +pub struct USBDeviceDriverHidMouseExample { + hub: usize, + port: usize, + slot: usize, + hid_desc: Hid, +} + +impl USBDeviceDriverHidMouseExample { + fn operate_device(&self, xhci: &Xhci, mut op: F) -> T + where + F: FnMut(&mut DeviceAttached) -> T, + O: OsDep, + { + op(xhci + .dev_ctx + .lock() + .attached_set + .get_mut(&(self.slot)) + .unwrap()) + } + + fn dump_out_ctx(&self, xhci: &Xhci) + where + O: OsDep, + { + debug!( + "dumped output context at slot {}:\n {:#?}", + self.slot, + **xhci + .dev_ctx + .lock() + .device_out_context_list + .get(self.slot) + .unwrap() + ); + } +} + +impl USBDeviceDriverOps for USBDeviceDriverHidMouseExample +where + O: OsDep, +{ + fn try_create( + device: &mut DeviceAttached + ) -> Option>> { + debug!("creating!"); + let fetch_desc_hid = &device.fetch_desc_hid(); + match { + let fetch_desc_devices = &device.fetch_desc_devices(); + debug!("desc_device: {:?}", fetch_desc_devices); + let dev_desc = fetch_desc_devices.first().unwrap(); + Some( + if dev_desc.class + == USBDeviceClassCode::ReferInterfaceDescriptor + .to_u8() + .unwrap() + { + device + .fetch_desc_interfaces() + .get(device.current_interface) + .map(|desc| { + ( + desc.interface_class, + desc.interface_subclass, + desc.interface_protocol, + ) + }) + .unwrap() + } else { + (dev_desc.class, dev_desc.subclass, dev_desc.protocol) + }, + ) + .map(|(class, subclass, protocol)| { + debug!("interface csp:{class},{subclass},{protocol}"); + ( + USBDeviceClassCode::from_u8(class), + USBHIDSubclassDescriptorType::from_u8(subclass), + USBHIDProtocolDescriptorType::from_u8(protocol), + ) + }) + .unwrap() + } { + (Some(USBDeviceClassCode::HID), Some(_), Some(USBHIDProtocolDescriptorType::Mouse)) => { + Some(Arc::new(SpinNoIrq::new(Self { + hub: device.hub, + port: device.port, + slot: device.slot_id, + hid_desc: fetch_desc_hid[0].clone(), + }))) + } + _ => None, + } + } + + fn work(&self, xhci: &Xhci) { + debug!("###driver usbhid working!###"); + self.dump_out_ctx(xhci); + + let interface_in_use = self.operate_device(xhci, |dev| { + dev.fetch_desc_interfaces()[dev.current_interface].clone() + }); + xhci.get_endpoint_status(0); + xhci.get_endpoint_status(1); + let idle_req = xhci.construct_no_data_transfer_req( + 0b00100001, //recipient:00001(interface),Type01:class,Direction:0(HostToDevice) //TODO, MAKE A Tool Module to convert type + 0x0A, //SET IDLE + 0x00, //recommended infini idle rate for mice, refer usb Hid 1.1 spec - page 53 + // upper 8 bit = 0-> infini idle, lower 8 bit = 0-> apply to all report + interface_in_use.interface_number as u16, + TransferType::No, //no data applied + ); + xhci.get_endpoint_status(0); + xhci.get_endpoint_status(1); + { + //set idle + debug!("{TAG}: post idle request to control endpoint"); + let result = self.operate_device(xhci, |dev| { + xhci.post_control_transfer_no_data_and_busy_wait( + idle_req, + dev.transfer_rings.get_mut(0).unwrap(), //ep0 ring + 1, //to ep0 + dev.slot_id, + ) + }); + debug!("{TAG}: result: {:?}", result); + // debug!("{TAG} buffer: {:?}", buffer); + } + xhci.get_endpoint_status(0); + xhci.get_endpoint_status(1); + { + busy_wait(Duration::from_millis(500)); + //request report rate + let buffer = DMA::new_vec( + 0u8, + self.hid_desc.report_descriptor_len as usize, + 64, + xhci.config.os.dma_alloc(), + ); + let request_report = xhci.construct_control_transfer_req( + &buffer, + 0x81, //recipient:00001(interface),Type00:standard,Direction:01(DeviceToHost) //TODO, MAKE A Tool Module to convert type + 0x06, //get descriptor + DescriptorType::HIDReport.forLowBit(0), //report descriptor + 0, //interface + (TransferType::In, Direction::In), + ); + xhci.get_endpoint_status(0); + xhci.get_endpoint_status(1); + debug!("{TAG}: post report request"); + let result = self + .operate_device(xhci, |dev| { + xhci.post_control_transfer_with_data_and_busy_wait( + request_report, + dev.transfer_rings.get_mut(0).unwrap(), //ep0 ring + 1, //to ep0 + dev.slot_id, + ) + }) + .unwrap(); + debug!("{TAG}: result: {:?}", result); + print_array(&buffer); + + // ReportHandler::new(&buffer).unwrap() + } //TODO parse Report context + + // loop { + // busy_wait(Duration::from_millis(500)); //too slow, just for debug + + // loop {} //TODO: check endpoint state to ensure data commit complete + + self.operate_device(xhci, |dev| { + let slot_id = dev.slot_id; + //get input endpoint dci, we only pick endpoint in #0 here + dev.operate_endpoint_in(|mut endpoints, rings| { + let in_dci = endpoints.get_mut(0).unwrap().doorbell_value_aka_dci(); //we use first in interrupt endpoint here, in actual environment, there might has multiple. + let buffer = DMA::new_vec(0u8, 4, 32, xhci.config.os.dma_alloc()); //enough for a mouse Report(should get from report above,but we not parse it yet) + xhci.get_endpoint_status(0); + xhci.get_endpoint_status(1); + debug!("{TAG}: post IN Transfer report request"); + let result = { + //temporary inlined, hass to be packed in to a function future + let this = &xhci; + let request = transfer::Allowed::Normal( + // just use normal trb to request interrupt transfer + *Normal::default() + .set_data_buffer_pointer(buffer.addr() as u64) + .set_td_size(0) + .set_trb_transfer_length(buffer.length_for_bytes() as u32) + .clear_interrupt_on_short_packet() + .clear_interrupt_on_completion(), + ); + let mut transfer_rings = rings.get_many_mut([3]).unwrap(); //chaos! + // xhci.get_endpoint_status(0); + // xhci.get_endpoint_status(1); + let dci = 3 as u8; + + { + let this = &this; + let mut transfer_trbs = vec![request]; + transfer_rings.iter_mut().for_each(|t| { + t.enque_trbs( + transfer_trbs + .iter_mut() + .map(|trb| { + if this.ring.lock().cycle { + trb.set_cycle_bit(); + } else { + trb.clear_cycle_bit(); + } + trb.into_raw() + }) + .collect(), + ) + }); + xhci.get_endpoint_status(0); + xhci.get_endpoint_status(1); + debug!("{TAG} Post control transfer! at slot_id:{slot_id},dci:{dci}"); + + let mut regs = this.regs.lock(); + + regs.regs.doorbell.update_volatile_at(slot_id, |r| { + r.set_doorbell_target(dci); + }); + + O::force_sync_cache(); + + this.busy_wait_for_event() + } + }; + // busy_wait(Duration::from_millis(5)); + debug!("{TAG}: result: {:?}", result); + print_array(&buffer); + }); + }) + // } + } +} + +fn print_array(arr: &[u8]) { + let mut line = String::new(); + for (i, &byte) in arr.iter().enumerate() { + line.push_str(&format!("{:02x} ", byte)); + if (i + 1) % 4 == 0 { + debug!("{}", line); + line.clear(); + } + } + if !line.is_empty() { + debug!("{}", line); + } +} + +struct USBHIDReportMouse {} diff --git a/crates/driver_usb/src/host/xhc.rs b/crates/driver_usb/src/host/xhc.rs new file mode 100644 index 0000000000..751da2cef1 --- /dev/null +++ b/crates/driver_usb/src/host/xhc.rs @@ -0,0 +1,130 @@ +use core::alloc::Allocator; + +use super::{ + exchanger, + structures::{dcbaa, extended_capabilities, registers, ring::event, scratchpad}, +}; +use driver_common::{BaseDriverOps, DeviceType}; +use xhci::extended_capabilities::ExtendedCapability; + +/// Initializes the host controller according to 4.2 of the xHCI specification. +pub(crate) fn init() { + stop_and_reset(); + set_num_of_enabled_slots(); + + dcbaa::init(); + scratchpad::init(); + exchanger::command::init(); + event::init(); + + run(); + ensure_no_error_occurs(); +} + +pub(crate) fn run() { + registers::handle(|r| { + let o = &mut r.operational; + o.usbcmd.update_volatile(|u| { + u.set_run_stop(); + }); + while o.usbsts.read_volatile().hc_halted() {} + }); +} + +pub(crate) fn ensure_no_error_occurs() { + registers::handle(|r| { + let s = r.operational.usbsts.read_volatile(); + + assert!(!s.hc_halted(), "HC is halted."); + assert!( + !s.host_system_error(), + "An error occured on the host system." + ); + assert!(!s.host_controller_error(), "An error occured on the xHC."); + }); +} + +pub(crate) fn get_ownership_from_bios() { + if let Some(iter) = extended_capabilities::iter() { + for c in iter.filter_map(Result::ok) { + if let ExtendedCapability::UsbLegacySupport(mut u) = c { + let l = &mut u.usblegsup; + l.update_volatile(|s| { + s.set_hc_os_owned_semaphore(); + }); + + while l.read_volatile().hc_bios_owned_semaphore() + || !l.read_volatile().hc_os_owned_semaphore() + {} + } + } + } +} + +fn stop_and_reset() { + stop(); + wait_until_halt(); + reset(); +} + +fn stop() { + registers::handle(|r| { + r.operational.usbcmd.update_volatile(|u| { + u.clear_run_stop(); + }); + }) +} + +fn wait_until_halt() { + registers::handle(|r| while !r.operational.usbsts.read_volatile().hc_halted() {}) +} + +fn reset() { + start_resetting(); + wait_until_reset_completed(); + wait_until_ready(); +} + +fn start_resetting() { + registers::handle(|r| { + r.operational.usbcmd.update_volatile(|u| { + u.set_host_controller_reset(); + }) + }) +} + +fn wait_until_reset_completed() { + registers::handle( + |r| { + while r.operational.usbcmd.read_volatile().host_controller_reset() {} + }, + ) +} + +fn wait_until_ready() { + registers::handle( + |r| { + while r.operational.usbsts.read_volatile().controller_not_ready() {} + }, + ) +} + +fn set_num_of_enabled_slots() { + // We choose the maximum number of device slots for simplicity. + let n = num_of_max_device_slots(); + + registers::handle(|r| { + r.operational.config.update_volatile(|c| { + c.set_max_device_slots_enabled(n); + }); + }) +} + +fn num_of_max_device_slots() -> u8 { + registers::handle(|r| { + r.capability + .hcsparams1 + .read_volatile() + .number_of_device_slots() + }) +} diff --git a/crates/driver_usb/src/host/xhci/xhci_device.rs b/crates/driver_usb/src/host/xhci/xhci_device.rs new file mode 100644 index 0000000000..559ff4c645 --- /dev/null +++ b/crates/driver_usb/src/host/xhci/xhci_device.rs @@ -0,0 +1,298 @@ +use core::{fmt::Error, ops::DerefMut, time::Duration}; + +use alloc::{borrow::ToOwned, collections::BTreeSet, sync::Arc, vec::Vec}; +use axhal::time::busy_wait_until; +use axtask::sleep; +use log::debug; +use num_derive::FromPrimitive; +use num_traits::{ops::mul_add, FromPrimitive, ToPrimitive}; +use spinlock::SpinNoIrq; +use xhci::{ + context::{Endpoint, EndpointType, Input64Byte, InputHandler}, + ring::{ + self, + trb::{ + command::{self, Allowed, ConfigureEndpoint}, + transfer, + }, + }, +}; + +use crate::{ + ax::{USBDeviceDriverOps, USBHostDriverOps}, + dma::DMA, + err::{self, Result}, + host::{ + usb::descriptors::{self, desc_interface::Interface, Descriptor}, + PortSpeed, + }, + OsDep, +}; + +const TAG: &str = "[XHCI DEVICE]"; + +use super::{ + event::{self, Ring}, + Xhci, +}; + +pub struct DeviceAttached +where + O: OsDep, +{ + pub hub: usize, + pub port: usize, + pub num_endp: usize, + pub slot_id: usize, + pub transfer_rings: Vec>, + pub descriptors: Vec, + pub current_interface: usize, +} + +impl DeviceAttached +where + O: OsDep, +{ + pub fn find_driver_impl>(&mut self) -> Option>> { + // let device = self.fetch_desc_devices()[0]; //only pick first device desc + debug!("try creating!"); + T::try_create(self) + } + + pub fn set_configuration( + &mut self, + port_speed: PortSpeed, + mut post_cmd: FC, + mut post_transfer: FT, + input_ref: &mut Vec>, + ) where + FC: FnMut(command::Allowed) -> Result, + FT: FnMut( + (transfer::Allowed, transfer::Allowed, transfer::Allowed), //setup,data,status + &mut Ring, //transfer ring + u8, //dci + usize, //slot + ) -> Result, + { + let last_entry = self + .fetch_desc_endpoints() + .iter() + .max_by_key(|e| e.doorbell_value_aka_dci()) + .unwrap() + .to_owned(); + + debug!("found last entry: 0x{:x}", last_entry.endpoint_address); + + let input = input_ref.get_mut(self.slot_id).unwrap().deref_mut(); + let slot_mut = input.device_mut().slot_mut(); + slot_mut.set_context_entries(last_entry.doorbell_value_aka_dci() as u8); + + let control_mut = input.control_mut(); + + let interface = self.fetch_desc_interfaces()[0].clone(); //hardcoded 0 interface + + let config_val = self.fetch_desc_configs()[0].config_val(); + self.current_interface = 0; + + control_mut.set_interface_number(interface.interface_number); + control_mut.set_alternate_setting(interface.alternate_setting); + + control_mut.set_add_context_flag(1); + control_mut.set_add_context_flag(2); + control_mut.set_add_context_flag(3); + control_mut.set_add_context_flag(4); + // control_mut.set_drop_context_flag(0); + //TODO: always choose last config here(always only 1 config exist, we assume.), need to change at future + control_mut.set_configuration_value(config_val); + + self.fetch_desc_endpoints().iter().for_each(|ep| { + self.init_endpoint_context(port_speed, ep, input); + }); + + // 打印 Input64Byte 结构体内容 + debug!("Input64Byte structure after configuration:"); + debug!("Control:"); + debug!(" Add Context Flags: 0x{:x}", control_mut.add_context_flags()); + + for (index, endpoint) in input.device().endpoints.iter().enumerate() { + if let Some(endpoint) = endpoint { + debug!(" Endpoint {}:", index + 1); + debug!(" Interval: {}", endpoint.interval()); + debug!(" Endpoint Type: {:?}", endpoint.endpoint_type()); + debug!(" Max Packet Size: {}", endpoint.max_packet_size()); + debug!(" Max Burst Size: {}", endpoint.max_burst_size()); + // 打印其他相关字段 + } + } + + debug!("{TAG} CMD: configure endpoint"); + let post_cmd = post_cmd(Allowed::ConfigureEndpoint({ + let mut configure_endpoint = *ConfigureEndpoint::default() + .set_slot_id(self.slot_id as u8) + .set_input_context_pointer((input as *mut Input64Byte).addr() as u64); + // if (config_val == 0) { + // configure_endpoint.set_deconfigure(); + // } + let input_context_pointer = (input as *mut Input64Byte).addr() as u64; + debug!("Input Context Pointer: {:#x}", input_context_pointer); + debug!("Slot ID: {}", self.slot_id); + debug!("Configure Endpoint: {:?}", configure_endpoint); + configure_endpoint + })); + debug!("{TAG} CMD: result:{:?}", post_cmd); + } + + fn init_endpoint_context( + &self, + port_speed: PortSpeed, + endpoint_desc: &descriptors::desc_endpoint::Endpoint, + input_ctx: &mut Input64Byte, + ) { + //set add content flag + let control_mut = input_ctx.control_mut(); + control_mut.add_context_flag(endpoint_desc.doorbell_value_aka_dci() as usize); + + let endpoint_mut = input_ctx + .device_mut() + .endpoint_mut(endpoint_desc.doorbell_value_aka_dci() as usize); + //set interval + // let port_speed = PortSpeed::get(port_number); + let endpoint_type = endpoint_desc.endpoint_type(); + let interval = endpoint_desc.calc_actual_interval(port_speed); + + endpoint_mut.set_interval(interval); + + //init endpoint type + let endpoint_type = endpoint_desc.endpoint_type(); + endpoint_mut.set_endpoint_type(endpoint_type); + + { + let max_packet_size = endpoint_desc.max_packet_size; + let ring_addr = self + .transfer_rings + .get(endpoint_desc.doorbell_value_aka_dci() as usize) + .unwrap() + .register(); + match endpoint_type { + EndpointType::Control => { + endpoint_mut.set_max_packet_size(max_packet_size); + endpoint_mut.set_error_count(3); + endpoint_mut.set_tr_dequeue_pointer(ring_addr); + endpoint_mut.set_dequeue_cycle_state(); + } + EndpointType::BulkOut | EndpointType::BulkIn => { + endpoint_mut.set_max_packet_size(max_packet_size); + endpoint_mut.set_max_burst_size(0); + endpoint_mut.set_error_count(3); + endpoint_mut.set_max_primary_streams(0); + endpoint_mut.set_tr_dequeue_pointer(ring_addr); + endpoint_mut.set_dequeue_cycle_state(); + } + EndpointType::IsochOut + | EndpointType::IsochIn + | EndpointType::InterruptOut + | EndpointType::InterruptIn => { + //init for isoch/interrupt + endpoint_mut.set_max_packet_size(max_packet_size & 0x7ff); //wtf + endpoint_mut + .set_max_burst_size(((max_packet_size & 0x1800) >> 11).try_into().unwrap()); + endpoint_mut.set_mult(0); + + if let EndpointType::IsochOut | EndpointType::IsochIn = endpoint_type { + endpoint_mut.set_error_count(0); + } else { + endpoint_mut.set_error_count(3); + } + + if let EndpointType::InterruptIn | EndpointType::InterruptOut = endpoint_type { + debug!( + "set a interrupt endpoint! addr:{}", + endpoint_desc.doorbell_value_aka_dci() + ); + } + + endpoint_mut.set_tr_dequeue_pointer(ring_addr); + endpoint_mut.set_dequeue_cycle_state(); + } + EndpointType::NotValid => unreachable!("Not Valid Endpoint should not exist."), + } + } + } + + //consider use marcos to these bunch of methods + pub fn fetch_desc_configs(&mut self) -> Vec { + self.descriptors + .iter() + .filter_map(|desc| match desc { + Descriptor::Configuration(config) => Some(config.clone()), + _ => None, + }) + .collect() + } + + pub fn fetch_desc_hid(&mut self) -> Vec { + self.descriptors + .iter() + .filter_map(|desc| match desc { + Descriptor::Hid(hid) => Some(hid.clone()), + _ => None, + }) + .collect() + } + + pub fn fetch_desc_devices(&mut self) -> Vec { + self.descriptors + .iter() + .filter_map(|desc| match desc { + Descriptor::Device(device) => Some(device.clone()), + _ => None, + }) + .collect() + } + + pub fn has_desc(&mut self, predicate: F) -> bool + where + F: FnMut(&Descriptor) -> bool, + { + self.descriptors.iter().any(predicate) + } + + pub fn fetch_desc_interfaces(&mut self) -> Vec { + self.descriptors + .iter() + .filter_map(|desc| { + if let Descriptor::Interface(int) = desc { + Some(int.clone()) + } else { + None + } + }) + .collect() + } + + pub fn fetch_desc_endpoints(&mut self) -> Vec { + self.descriptors + .iter() + .filter_map(|desc| { + if let Descriptor::Endpoint(e) = desc { + Some(e.clone()) + } else { + None + } + }) + .collect() + } + + pub fn operate_endpoint_in(&mut self, mapper: F) -> R + where + F: Fn(Vec<&descriptors::desc_endpoint::Endpoint>, &mut Vec>) -> R, + { + mapper( + self.fetch_desc_endpoints() + .iter() + .filter(|endpoint| endpoint.endpoint_type() == EndpointType::InterruptIn) + .collect(), + &mut self.transfer_rings, + ) + } +} diff --git a/crates/driver_usb/src/lib.rs b/crates/driver_usb/src/lib.rs new file mode 100644 index 0000000000..d66a4e9950 --- /dev/null +++ b/crates/driver_usb/src/lib.rs @@ -0,0 +1,37 @@ +//! Common traits and types for graphics display device drivers. + +#![no_std] +#![feature(allocator_api)] +#![feature(strict_provenance)] +#![feature(get_mut_unchecked)] +#![feature(new_uninit)] +#![allow(warnings)] +#![feature(if_let_guard)] +#![feature(let_chains)] +#![feature(generic_arg_infer)] + +extern crate alloc; +pub(crate) mod dma; +pub mod host; +use core::alloc::Allocator; +mod device_types; + +use axhal::mem::VirtAddr; +#[doc(no_inline)] +pub use driver_common::{BaseDriverOps, DevError, DevResult, DeviceType}; +use futures_intrusive::sync::{GenericMutex, GenericMutexGuard}; +use log::info; +use spinning_top::RawSpinlock; + +pub(crate) type Futurelock = GenericMutex; +pub(crate) type FuturelockGuard<'a, T> = GenericMutexGuard<'a, RawSpinlock, T>; + +pub fn try_init(mmio_base_paddr: usize) { + host::init_statics(0xffff_0000_31a0_8000 as usize); + host::init_xhci(); + enum_port(); +} + +pub fn enum_port() { + host::enum_port(); +} diff --git a/crates/driver_virtio/Cargo.toml b/crates/driver_virtio/Cargo.toml index 6131c34db7..f133167a9f 100644 --- a/crates/driver_virtio/Cargo.toml +++ b/crates/driver_virtio/Cargo.toml @@ -19,4 +19,4 @@ driver_common = { path = "../driver_common" } driver_block = { path = "../driver_block", optional = true } driver_net = { path = "../driver_net", optional = true } driver_display = { path = "../driver_display", optional = true} -virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers.git", rev = "409ee72" } +virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers.git", rev = "4b60f5d" } diff --git a/crates/driver_virtio/src/blk.rs b/crates/driver_virtio/src/blk.rs index 3edaa1a089..3afc9b40d6 100644 --- a/crates/driver_virtio/src/blk.rs +++ b/crates/driver_virtio/src/blk.rs @@ -44,13 +44,13 @@ impl BlockDriverOps for VirtIoBlkDev { fn read_block(&mut self, block_id: u64, buf: &mut [u8]) -> DevResult { self.inner - .read_block(block_id as _, buf) + .read_blocks(block_id as _, buf) .map_err(as_dev_err) } fn write_block(&mut self, block_id: u64, buf: &[u8]) -> DevResult { self.inner - .write_block(block_id as _, buf) + .write_blocks(block_id as _, buf) .map_err(as_dev_err) } diff --git a/crates/driver_virtio/src/gpu.rs b/crates/driver_virtio/src/gpu.rs index 1acc68841c..dd4e39410b 100644 --- a/crates/driver_virtio/src/gpu.rs +++ b/crates/driver_virtio/src/gpu.rs @@ -7,7 +7,7 @@ use virtio_drivers::{device::gpu::VirtIOGpu as InnerDev, transport::Transport, H /// The VirtIO GPU device driver. pub struct VirtIoGpuDev { - inner: InnerDev<'static, H, T>, + inner: InnerDev, info: DisplayInfo, } diff --git a/crates/driver_virtio/src/net.rs b/crates/driver_virtio/src/net.rs index e106f7e53f..10ca0eecc2 100644 --- a/crates/driver_virtio/src/net.rs +++ b/crates/driver_virtio/src/net.rs @@ -90,12 +90,12 @@ impl NetDriverOps for VirtIoNetDev bool { - !self.free_tx_bufs.is_empty() && self.inner.can_transmit() + !self.free_tx_bufs.is_empty() && self.inner.can_send() } #[inline] fn can_receive(&self) -> bool { - self.inner.can_receive() + self.inner.poll_receive().is_some() } #[inline] diff --git a/crates/flatten_objects/src/lib.rs b/crates/flatten_objects/src/lib.rs index d5637f001d..f431371ec0b 100644 --- a/crates/flatten_objects/src/lib.rs +++ b/crates/flatten_objects/src/lib.rs @@ -30,7 +30,6 @@ //! ``` #![no_std] -#![feature(const_maybe_uninit_zeroed)] #![feature(maybe_uninit_uninit_array)] #![feature(const_maybe_uninit_uninit_array)] diff --git a/crates/page_box/Cargo.toml b/crates/page_box/Cargo.toml new file mode 100644 index 0000000000..7ad6f9f1bb --- /dev/null +++ b/crates/page_box/Cargo.toml @@ -0,0 +1,17 @@ +[package] +name = "page_box" +version = "0.1.0" +authors = ["dbydd "] +edition = "2021" +license = "GPL-3.0-or-later" +description = "modified from toku-sa-n's pagebox crate, try to make it into multi platform, adapt for arceos" + +[dependencies] + +axhal = {path = "../../modules/axhal"} +axalloc = {path = "../../modules/axalloc"} +page_table = {path = "../page_table"} +page_table_entry = {path = "../page_table_entry"} +lazy_static = {version="1.4", features=["spin_no_std"]} +os_units = "0.4.0" +log="0.4" \ No newline at end of file diff --git a/crates/page_box/src/lib.rs b/crates/page_box/src/lib.rs new file mode 100644 index 0000000000..5be6e94e30 --- /dev/null +++ b/crates/page_box/src/lib.rs @@ -0,0 +1,185 @@ +#![cfg_attr(not(test), no_std)] +#![allow(clippy::type_repetition_in_bounds)] +#![feature(strict_provenance)] +#![feature(allocator_api)] +use axalloc::global_no_cache_allocator; +use axalloc::GlobalNoCacheAllocator; +use axhal::mem::VirtAddr; +use core::alloc::Allocator; +use core::alloc::Layout; +use core::fmt; +use core::fmt::Debug; +use core::fmt::Formatter; +use core::marker::PhantomData; +use core::ops::Deref; +use core::ops::DerefMut; +use core::ptr::NonNull; +use core::slice; +use lazy_static::lazy_static; +use os_units::Bytes; + +/// A `Box`-like type that locates the inner value at a 4K bytes page boundary. +/// +/// xHCI specification prohibits some structures from crossing the page +/// boundary. Here, the size of a page is determined by Page Size Register (See +/// 5.4.3 of the spec). However, the minimum size of a page is 4K bytes, meaning +/// that keeping a structure within a 4K bytes page is always safe. It is very +/// costly, but at least it works. +pub struct PageBox { + addr: VirtAddr, + layout: Layout, + _marker: PhantomData, +} +impl PageBox { + pub fn from_layout_zeroed(layout: Layout) -> Self { + assert!( + layout.size() > 0, + "The size of the layout must be greater than 0." + ); + + let addr = unsafe { + global_no_cache_allocator() + .allocate(layout) + .unwrap() + .as_ptr() + }; + + // SAFETY: Safe as the address is well-aligned. + unsafe { core::ptr::write_bytes(addr as *mut u8, 0, layout.size()) }; + + Self { + addr: VirtAddr::from(addr.addr()), + layout, + _marker: PhantomData, + } + } + + pub fn bytes(&self) -> Bytes { + Bytes::from(self.layout.size()) + } + + pub fn virt_addr(&self) -> VirtAddr { + self.addr + } +} +impl PageBox<[T]> { + pub fn new_slice(init: T, len: usize) -> Self { + let bytes = Bytes::from(len * core::mem::size_of::()); + let align = 4096.max(core::mem::align_of::()); + + let layout = Layout::from_size_align(bytes.as_usize(), align); + let layout = layout.unwrap_or_else(|_| { + panic!( + "Failed to create a layout for {} bytes with {} bytes alignment", + bytes.as_usize(), + align + ) + }); + + // SAFETY: `Layout::from_size_align` guarantees that the layout is valid. + let addr = unsafe { + global_no_cache_allocator() + .allocate(layout) + .unwrap() + .as_ptr() + }; + + // SAFETY: Safe as the address is well-aligned. + unsafe { + let mut slice = slice::from_raw_parts_mut(addr as *mut T, len); + for i in 0..len { + slice[i] = init.clone(); + } + }; + + Self { + addr: VirtAddr::from(addr.addr()), + layout, + _marker: PhantomData, + } + } +} +impl Deref for PageBox { + type Target = T; + fn deref(&self) -> &Self::Target { + // SAFETY: Safe as the address is well-aligned. + unsafe { &*(self.addr.as_ptr() as *const T) } + } +} +impl Deref for PageBox<[T]> { + type Target = [T]; + fn deref(&self) -> &Self::Target { + let len = self.bytes().as_usize() / core::mem::size_of::(); + + // SAFETY: Safe as the address is well-aligned and the memory is allocated. + unsafe { slice::from_raw_parts(self.addr.as_ptr() as *const T, len) } + } +} +impl DerefMut for PageBox { + fn deref_mut(&mut self) -> &mut Self::Target { + // SAFETY: Safe as the address is well-aligned. + unsafe { &mut *(self.addr.as_mut_ptr() as *mut T) } + } +} +impl DerefMut for PageBox<[T]> { + fn deref_mut(&mut self) -> &mut Self::Target { + let len = self.bytes().as_usize() / core::mem::size_of::(); + + // SAFETY: Safe as the address is well-aligned and the memory is allocated. + unsafe { slice::from_raw_parts_mut(self.addr.as_mut_ptr() as *mut T, len) } + } +} +impl From for PageBox { + fn from(inner: T) -> Self { + let bytes = Bytes::from(core::mem::size_of::()); + let align = 4096.max(core::mem::align_of::()); + + let layout = Layout::from_size_align(bytes.as_usize(), align); + let layout = layout.unwrap_or_else(|_| { + panic!( + "Failed to create a layout for {} bytes with {} bytes alignment", + bytes.as_usize(), + align + ) + }); + + // SAFETY: `Layout::from_size_align` guarantees that the layout is valid. + let addr = unsafe { + global_no_cache_allocator() + .allocate(layout) + .unwrap() + .as_ptr() + }; + + // SAFETY: Safe as the address is well-aligned. + unsafe { core::ptr::write(addr as *mut T, inner) }; + + Self { + addr: VirtAddr::from(addr.addr()), + layout, + _marker: PhantomData, + } + } +} +impl Default for PageBox { + fn default() -> Self { + let x: T = Default::default(); + + Self::from(x) + } +} +impl Debug for PageBox { + fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { + self.deref().fmt(f) + } +} +impl Drop for PageBox { + fn drop(&mut self) { + // SAFETY: `Layout::from_size_align` guarantees that the layout is valid. + + unsafe { + global_no_cache_allocator() + .deallocate(NonNull::new(self.addr.as_mut_ptr()).unwrap(), self.layout) + } + } +} diff --git a/crates/page_table/src/lib.rs b/crates/page_table/src/lib.rs index 0af6649941..79c62dfb64 100644 --- a/crates/page_table/src/lib.rs +++ b/crates/page_table/src/lib.rs @@ -19,7 +19,6 @@ #![no_std] #![feature(const_trait_impl)] -#![feature(result_option_inspect)] #![feature(doc_auto_cfg)] #[macro_use] diff --git a/crates/page_table_entry/src/arch/aarch64.rs b/crates/page_table_entry/src/arch/aarch64.rs index 5b88b97ec0..faf5f83bb7 100644 --- a/crates/page_table_entry/src/arch/aarch64.rs +++ b/crates/page_table_entry/src/arch/aarch64.rs @@ -81,6 +81,9 @@ impl DescriptorAttr { if matches!(idx, MemAttr::Normal | MemAttr::NormalNonCacheable) { bits |= Self::INNER.bits() | Self::SHAREABLE.bits(); } + if matches!(idx, MemAttr::Device) { + bits |= Self::SHAREABLE.bits(); + } Self::from_bits_retain(bits) } @@ -101,7 +104,7 @@ impl MemAttr { /// attributes in the descriptors. pub const MAIR_VALUE: u64 = { // Device-nGnRE memory - let attr0 = MAIR_EL1::Attr0_Device::nonGathering_nonReordering_EarlyWriteAck.value; + let attr0 = MAIR_EL1::Attr0_Device::nonGathering_nonReordering_noEarlyWriteAck.value; // Normal memory let attr1 = MAIR_EL1::Attr1_Normal_Inner::WriteBack_NonTransient_ReadWriteAlloc.value | MAIR_EL1::Attr1_Normal_Outer::WriteBack_NonTransient_ReadWriteAlloc.value; diff --git a/doc/XMODEM.TXT b/doc/XMODEM.TXT new file mode 100644 index 0000000000..a95592966f --- /dev/null +++ b/doc/XMODEM.TXT @@ -0,0 +1,102 @@ +Perception presents: +------------ Understanding The X-Modem File Transfer Protocol --------------- + + by Em Decay + +This has to be one of the most internationally accepted protocols for upload- + ing and downloading binary and text files. It is fairly straight-forward as + to how it is set up and there are some error checking capabilities. + + +--- Before you begin --- + +Things you need to know beforehand... + +The following terms are simply ascii codes: + SOH = chr(1) = CTRL-A = + EOT = chr(4) = CTRL-D = End of Transmission + ACK = chr(6) = CTRL-F = Positive Acknowledgement + NAK = chr(21) = CTRL-U = Negative Acknowledgement + CAN = chr(24) = CTRL-X = Cancel + +In order to send the file, you must first divide it into 128 byte sections + (packets). Bytes 0-127 of the file make up the first packet, bytes 128-255 + make up the second packet, etc. + +The packet number sent is simply the number of the packet. If the packet + number is greater than 255, then subtract 256 repeatedly until the number is + between 0 and 255. For example, if you were sending packet 731, then you + would send 731 - 256 - 256 = 219. + +The 1's complement of a byte (to make life easy) is simply 255 minus the + byte. For example, if you had to take the 1's complement of 142, the answer + would be 255 - 142 = 113. + +The checksum is the value of all the bytes in the packet added together. For + example, if the first five bytes were 45, 12, 64, 236, 173 and the other 123 + bytes were zeroes, the checksum would be 45+12+64+236+173+0+0+...+0 = 530. + However, to make each block one byte smaller, they repeatedly subtract 256 + from the checksum until it is between 0 and 255. In this case, the checksum + would be 530 - 256 - 256 = 18. + +The first byte the downloader sends is referred to as the NCGbyte. + +Provided that you aren't lost already, here is what happens next. The steps + below describe who sends what when :) + + +--- The Actual Transfer --- + +The uploader waits until the downloader sends a NAK byte. The NAK byte + is the signal that the downloader is ready to start. This byte is referred + to as the NCGbyte. If the downloader takes too long or an error occurs then + the uploader will stop waiting or "Time Out". If this happens, then the + file transfer must restart. + +With each packet sent... + + The uploader sends: + + 1. an SOH byte {1 byte} + 2. the packet number {1 byte} + 3. the 1's complement of the packet number {1 byte} + 4. the packet {128 bytes} + 5. the checksum {1 byte} + The above five things are called the block. + + The downloader: + + 1. ensures that the packet number sent matches the actual packet number + that it is (If the third block send has a '4' as the second byte, + something is wrong --> CANCEL TRANSFER (send CAN byte)) + 2. adds the packet number and the 1's complement of it together to make + sure that they add up to 255. if they don't --> CANCEL TRANSFER + 3. adds up all the bytes in the packet together --> THE SUM + 4. compares the last two significant digits of THE SUM with the checksum + 5. if everything looks ok (sum=checksum), then the downloader appends the + bytes in the packet to the file being created (sent). The down- + loader then sends an ACK byte which tells the uploader to send the + next block. + if the sums do not match then the downloader sends an NAK byte which + tells the uploader to send the same block it just sent over again. + +When the uploader sends an EOT byte instead of an SOH byte, the downloader + sends a NAK byte. If the uploader sends another EOT immediately after that, + the downloader sends an ACK byte and the transfer is complete. + +Another thing, the downloader can cancel the transfer at any time by sending + a CAN byte. The uploader can only cancel between blocks by sending a CAN + byte. It is recommended that you send anywhere between 2 and 8 consecutive + CAN bytes when you wish to cancel as some programs will not let you abort if + only 1 CAN byte is sent. + + +--- Wrap Up --- + +Hopefully, you were able to follow along. :) If not, you can e-mail me at + em_decay@norlink.net and I will try to clarify it for you. Have fun :) + +Perception: Em Decay -- Mark Korhonen + Cmf ------- Chris Fillion + +Written on Dec.28/95 diff --git a/doc/XMODEM1K.TXT b/doc/XMODEM1K.TXT new file mode 100644 index 0000000000..f3f2134b46 --- /dev/null +++ b/doc/XMODEM1K.TXT @@ -0,0 +1,109 @@ +Perception presents: +---------- Understanding The X-Modem 1K File Transfer Protocol -------------- + + by Em Decay + +This has to be one of the most internationally accepted protocols for upload- + ing and downloading binary and text files. It is fairly straight-forward as + to how it is set up and there are fairly good error checking capabilities. + + +--- Before you begin --- + +Look at my XMODEM.TXT and XMODEMCRC.TXT text file for a general understanding + of the X-Modem file transfer protocol and the terms used in it. + +New things you need to know beforehand... + +The following term is just an ASCII code: + STX = chr(2) = CTRL-B + +The CRC starts with a value of zero at the beginning of each block. Now to + update the CRC, with each byte in the 1024 byte packet simply do this (the + oldcrc is the crc value to be updated, data is the current byte): + CRC:=(oldcrc shl 8) xor (crctable[(oldcrc shr 8) xor data]); +The final value of the CRC (after all 1024 bytes) is what is being sent in + the X-Modem CRC protocol. + +If a 128 byte packet is sent, the CRC is calculated in the same manner as in + X-Modem CRC. + +These are the only new things that are needed in X-Modem 1K. :) + + +--- The Actual Transfer --- + +As in X-Modem, the uploader waits for the downloader to send the NCGbyte. + The NCGbyte for X-Modem 1K is identical to the NCGbyte for X-Modem CRC and + it is chr(67) or the capital letter C (unlike X-Modem where the NCGbyte is + chr(21), the NAK). If the downloader takes too long or an error occurs then + the uploader will stop waiting or "Time Out". If this happens, then the + file transfer must restart. + +The uploader can send either 1024 byte or 128 byte packets. 1024 byte + packets are faster but 128 bytes at the end of the transfer can save some + time at the end. This is because if there are only 125 bytes left to send, + only one 128 byte packet would be necessary (in which case you would send + 3 null (chr(0)) bytes) whereas sending a 1024 byte packet would send 999 + nulls. + +With each packet sent... + + In each 1024 byte (1k) packet, the uploader sends: + + 1. an STX byte {1 byte} + 2. the packet number {1 byte} + 3. the 1's complement of the packet number {1 byte} + 4. the packet {1024 bytes} + 5. the high byte of the CRC-16 {1 byte} + 6. the low byte of the CRC-16 {1 byte} + + In each 128 byte packet, the uploader sends: + + 1. an STX byte {1 byte} + 2. the packet number {1 byte} + 3. the 1's complement of the packet number {1 byte} + 4. the packet {128 bytes} + 5. the high byte of the CRC-16 {1 byte} + 6. the low byte of the CRC-16 {1 byte} + + These six things make up the block. + + The downloader: + + 1. ensures that the packet number sent matches the actual packet number + that it is (If the third block sent has a '4' as the second byte, + something is wrong --> CANCEL TRANSFER (send CAN byte)) + 2. adds the packet number and the 1's complement of the packet number + together to make sure that they add up to 255. if they don't --> + CANCEL TRANSFER + 3. sets the CRC to zero + 4. updates the CRC as each byte in the packet is sent + 5. compares the calculated CRC to the CRC that is sent + 6. if everything looks ok (calculated CRC=sent CRC), then the downloader + appends the bytes in the packet to the file being created (sent). + The downloader then sends an ACK byte which tells the uploader to + send the next block. + if the CRCs do not match, then the downloader sends a NAK byte which + tells the uploader to send the same block it just sent over again. + +When the uploader sends an EOT byte instead of an SOH or STX byte, the down- + loader sends a NAK byte. If the uploader sends another EOT immediately + after that, the downloader sends an ACK byte and the transfer is complete. + +Another thing, the downloader can cancel the transfer at any time by sending + a CAN byte. The uploadered can cancel only between blocks by sending a CAN + byte. It is recommended that you send between 2 and 8 consecutive CAN bytes + as some communication programs will not allow you to cancel with only 1 CAN + byte. + + +--- Wrap Up --- + +Hopefully, you were able to follow along. :) If not, you can e-mail me at + em_decay@norlink.net and I will try to clarify it for you. Have fun :) + +Perception: Em Decay -- Mark Korhonen + Cmf ------- Chris Fillion + +Written on Jan.19/95 diff --git a/doc/XMODMCRC.TXT b/doc/XMODMCRC.TXT new file mode 100644 index 0000000000..08de36cb54 --- /dev/null +++ b/doc/XMODMCRC.TXT @@ -0,0 +1,139 @@ +Perception presents: +---------- Understanding The X-Modem CRC File Transfer Protocol -------------- + + by Em Decay + +This has to be one of the most internationally accepted protocols for upload- + ing and downloading binary and text files. It is fairly straight-forward as + to how it is set up and there are some error checking capabilities. + + +--- Before you begin --- + +Look at my XMODEM.TXT text file for a general understanding of the X-Modem + file transfer protocol and the terms used in it. + +New things you need to know beforehand... + +One word is the same as two bytes. If you want the high byte and the low + byte of a word, simply do the following. + High byte = word DIV 256 (DIV is the same as divide except the answer is + truncated) + Low byte = $00ff AND word (AND refers to AND logic) + +To get a word from a high byte and a low byte, simply multiply the high byte + by 256 (or shift it left 8 bits, if you know assembly) and add the low byte + to it. + +CRC stands for Cyclical Redundancy Check. In X-Modem CRC, it is also refer- + red to as CRC-16 since there are 16 bits (1 word) at the end of the block + that contain the CRC. This 1 word CRC replaces the 1 byte checksum in + X-Modem. +CRC-16 guarantees detection of all single and double bit errors, all errors + with an odd number of bits and over 99.9969% of all burst errors (you don't + have to know what all these things are :). +The easiest and fastest way to calculate the CRC is to use a lookup table. + +Here is some source code about making a lookup table. Call this procedure + at the very beginning of the program. Make crctable an global variable. + It is an array [0..255] of word. + + procedure initcrc; + + var + i:integer; + + function calctable(data,genpoly,accum:word):word; + + var + j:word; + + begin + data:=data shl 8; + for j:=8 downto 1 do + begin + if ((data xor accum) and $8000)<>0 then + accum:=(accum shl 1) xor genpoly + else + accum:=accum shl 1; + data:=data shl1; + end; + calctable:=accum; + end; + + begin + for i:=0 to 255 do + crctable[i]:=calctable(i,4129,0); + end; + +The CRC starts with a value of zero at the beginning of each block. Now to + update the CRC, with each byte in the 128 byte packet simply do this (the + oldcrc is the crc value to be updated, data is the current byte): + CRC:=(oldcrc shl 8) xor (crctable[(oldcrc shr 8) xor data]); +The final value of the CRC (after all 128 bytes) is what is being sent in the + X-Modem CRC protocol. + +If you have somewhat understood what has just been described then you catch + on a lot faster than I did :) If you just use + + +--- The Actual Transfer --- + +As in X-Modem, the uploader waits for the downloader to send the NCGbyte. + The NCGbyte for X-Modem CRC is chr(67) or the capital letter C (unlike + X-Modem where the NCGbyte is chr(21), the NAK). If the downloader takes too + long or an error occurs then the uploader will stop waiting or "Time Out". + If this happens, then the file transfer must restart. + +With each packet sent... + + The uploader sends: + + 1. an SOH byte {1 byte} + 2. the packet number {1 byte} + 3. the 1's complement of the packet number {1 byte} + 4. the packet {128 bytes} + 5. the high byte of the CRC-16 {1 byte} + 6. the low byte of the CRC-16 {1 byte} + + These six things make up the block. + + The downloader: + + 1. ensures that the packet number sent matches the actual packet number + that it is (If the third block sent has a '4' as the second byte, + something is wrong --> CANCEL TRANSFER (send CAN byte)) + 2. adds the packet number and the 1's complement of the packet number + together to make sure that they add up to 255. if they don't --> + CANCEL TRANSFER + 3. sets the CRC to zero + 4. updates the CRC as each byte in the packet is sent + 5. compares the calculated CRC to the CRC that is sent + 6. if everything looks ok (calculated CRC=sent CRC), then the downloader + appends the bytes in the packet to the file being created (sent). + The downloader then sends an ACK byte which tells the uploader to + send the next block. + if the CRCs do not match, then the downloader sends a NAK byte which + tells the uploader to send the same block it just sent over again. + +When the uploader sends an EOT byte instead of an SOH byte, the downloader + sends a NAK byte. If the uploader sends another EOT immediately after that, + the downloader sends an ACK byte and the transfer is complete. + +Another thing, the downloader can cancel the transfer at any time by sending + a CAN byte. The uploadered can cancel only between blocks by sending a CAN + byte. It is recommended that you send between 2 and 8 consecutive CAN bytes + as some communication programs will not allow you to cancel with only 1 CAN + byte. + + +--- Wrap Up --- + +Hopefully, you were able to follow along. :) If not, you can e-mail me at + em_decay@norlink.net and I will try to clarify it for you. Have fun :) + +Perception: Em Decay -- Mark Korhonen + Cmf ------- Chris Fillion + +Written on Jan.3/95 + diff --git a/doc/figures/draw_jtag_connected.jpg b/doc/figures/draw_jtag_connected.jpg new file mode 100644 index 0000000000..0a3e0db2f5 Binary files /dev/null and b/doc/figures/draw_jtag_connected.jpg differ diff --git a/doc/figures/image_jtag_connected.jpg b/doc/figures/image_jtag_connected.jpg new file mode 100644 index 0000000000..43075cee85 Binary files /dev/null and b/doc/figures/image_jtag_connected.jpg differ diff --git a/doc/ixgbe.md b/doc/ixgbe.md index cba58e3b6a..ac93e3e9a3 100644 --- a/doc/ixgbe.md +++ b/doc/ixgbe.md @@ -13,3 +13,37 @@ You can also use the following command to start the iperf application: ```shell make A=apps/c/iperf PLATFORM=x86_64-pc-oslab FEATURES=driver-ixgbe,driver-ramdisk ``` + +## Use ixgbe NIC in QEMU with PCI passthrough + +1. Install the `vfio-pci` driver in the host: + + ```shell + sudo modprobe vfio-pci + ``` + +2. Bind the NIC to the `vfio-pci` driver (assume the PCI address is `02:00.0`): + + ```shell + sudo ./scripts/net/pci-bind.sh vfio-pci 02:00.0 + # Equivalent to: + # echo 0000:02:00.0 > /sys/bus/pci/drivers/ixgbe/unbind + # echo vfio-pci > /sys/bus/pci/devices/0000:02:00.0/driver_override + # echo 0000:02:00.0 > /sys/bus/pci/drivers/vfio-pci/bind + ``` + +3. Build and run ArceOS: + + ```shell + make A=apps/net/httpserver FEATURES=driver-ixgbe VFIO_PCI=02:00.0 IP=x.x.x.x GW=x.x.x.x run + ``` + +4. If no longer in use, bind the NIC back to the `ixgbe` driver: + + ```shell + sudo ./scripts/net/pci-bind.sh ixgbe 02:00.0 + # Equivalent to: + # echo 0000:02:00.0 > /sys/bus/pci/drivers/vfio-pci/unbind + # echo ixgbe > /sys/bus/pci/devices/0000:02:00.0/driver_override + # echo 0000:02:00.0 > /sys/bus/pci/drivers/ixgbe/bind + ``` diff --git a/doc/jtag_debug_in_raspi4.md b/doc/jtag_debug_in_raspi4.md new file mode 100644 index 0000000000..f732a59b15 --- /dev/null +++ b/doc/jtag_debug_in_raspi4.md @@ -0,0 +1,276 @@ +# Introduction + +This article describes a way to debug jtags via openocd, gdb, jlink debugger. + +## Requirement + +### Resources + +1. Authors using [H-JLINK v9 type c Universal ARM Downloader](https://m.tb.cn/h.5FpduM7jUbbFlzo?tk=Z6t5WlsfPtl), +but theoretically, you can use whatever you want. + +2. [Serial USB to TTL CH340 Module](https://www.amazon.com/HiLetgo-Module-Microcontroller-Download-Serial/dp/B00LZV1G6K/ref=sr_1_3?dib=eyJ2IjoiMSJ9.EVDg6VSjpenXHkAOIddkejC8NrNLBaiI9YKosxxcvxsvWHCkJuYWT97oslmx7iE-il7I7ilkI07pfXYrJnjb0-gM8hu4y8_hMEVA7hiUtPZtjhovoAeF0-L7rM0xTe-hdNscYjbIspct3yjOtYSF9QPNFmr9XmeC5Os2gCQxZihglIJJDxUWWAhJL_MNl06dDKZnk82pkR_p09laqdfg0nFMwJwdxLDObHv3gzDHWNk.pvOBDJ9aVLFwecXlCYuMONK54Z_7sxnzAvdO71qkHWI&dib_tag=se&keywords=CH340&qid=1709218438&sr=8-3) + +3. Some Female to Female [Dupont Wire](https://www.amazon.com/Elegoo-EL-CP-004-Multicolored-Breadboard-arduino/dp/B01EV70C78/ref=sr_1_3?dib=eyJ2IjoiMSJ9.OCLDs3D5By4QvSSJfVxcRa7LFdoHpv56YLqS9wbJRIGaY_r5UKFkopHdBRu0aVmyYfSaH77oX0ure59RTu2R0GWeOUm8DEzRUHiLTYnKqPa02peSrC0JWZMUQPaErE40BeYQpDl0ywu9vg7zI1gHJWxdYtOgrehyUhiT9G9657pN73jvrY3Vd5RrBH9-5aAYEDKpN_P1gS48Yqv9n7S3efD7AKdAsgYsLsN1QLBFeyI.VxVp4ZfND0S73SSXYiJlh6KJD8GRdD2Pn2LHUrCHSj4&dib_tag=se&keywords=DuPont+line&qid=1709218493&sr=8-3) + +4. A laptop + +### Preliminary preparation + +1. Connect CH304 from [bcm2711 pin 8,10,12](https://datasheets.raspberrypi.com/rpi4/raspberry-pi-4-reduced-schematics.pdf) (Rx to Tx, Tx to Rx, GND to GND). + By the ways, power indicator closest to 1. + +2. Connect H-JLINK based on the picture below: + +![connect_jtag_debugger](./figures/image_jtag_connected.jpg) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
GPIO # Name JTAG # Note Diagram
VTREF1to 3.3V
GND4to GND
22TRST3
26TDI5
27TMS7
25TCK9
23RTCK11
24TDO13
+

+*thanks for andre-richter provide this sections.* + +3. Try to test whether chainboot works properly + 1. go to tools/raspi4/chainloader + 2. run `make clean && make`, it should generate a kernel8.img under this directory. + if everything right, the image file should be 8576 via `ls -al`. + 3. move this image into your sd card. + 4. check if your sd card has contians following file + [start4.elf](https://raw.githubusercontent.com/raspberrypi/firmware/master/boot/start4.elf), + [fixup4.dat](https://github.com/raspberrypi/firmware/raw/master/boot/fixup4.dat), + [bcm2711-rpi-4-b.dtb](https://raw.githubusercontent.com/raspberrypi/firmware/master/boot/bcm2711-rpi-4-b.dtb) + 5. just run `make A=apps/helloworld PLATFORM=aarch64-raspi4 chainboot`, then should display this image. + + + + + + + + + + + + + + + + + + +
Minipush 1.0





[MP] ⏳ Waiting for /dev/ttyUSB0		[MP] ✅ Serial connected


[MP]  Please power the target now
This means that CH340 is not connected or connected in some other wayconnection is successful
maybe /dev/ttyUSB1 or something else
+ + After power up the board: + + ``` + + __ __ _ _ _ _ + | \/ (_)_ _ (_) | ___ __ _ __| | + | |\/| | | ' \| | |__/ _ \/ _` / _` | + |_| |_|_|_||_|_|____\___/\__,_\__,_| + + Raspberry Pi 4 + + [ML] Requesting binary + [MP] ⏩ Pushing 36 KiB =========================================🦀 100% 0 KiB/s Time: 00:00:00 + [ML] Loaded! Executing the payload now + + @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + @ You're using chainboot image . @ + @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + + d8888 .d88888b. .d8888b. + d88888 d88P" "Y88b d88P Y88b + d88P888 888 888 Y88b. + d88P 888 888d888 .d8888b .d88b. 888 888 "Y888b. + d88P 888 888P" d88P" d8P Y8b 888 888 "Y88b. + d88P 888 888 888 88888888 888 888 "888 + d8888888888 888 Y88b. Y8b. Y88b. .d88P Y88b d88P + d88P 888 888 "Y8888P "Y8888 "Y88888P" "Y8888P" + + arch = aarch64 + platform = aarch64-raspi4 + target = aarch64-unknown-none-softfloat + smp = 1 + build_mode = release + log_level = warn + + Hello, world! + ``` + +## Run + +### Preliminary preparation + + 1. go to tools/raspi4/chainloader + 2. run `make clean && make JTAG=y`, it should generate a kernel8.img under this directory. + if everything right, the image file should be 8576 via `ls -al`. + 3. move this image into your sd card. + 4. check if your sd card has contians following file + [start4.elf](https://raw.githubusercontent.com/raspberrypi/firmware/master/boot/start4.elf), + [fixup4.dat](https://github.com/raspberrypi/firmware/raw/master/boot/fixup4.dat), + [bcm2711-rpi-4-b.dtb](https://raw.githubusercontent.com/raspberrypi/firmware/master/boot/bcm2711-rpi-4-b.dtb) + +### Start Debugging + + 1. just run `make A=apps/helloworld PLATFORM=aarch64-raspi4 chainboot` and Power up the board., then should display this image. + + ``` + Minipush 1.0 + + [MP] ✅ Serial connected + [MP] 🔌 Please power the target now + + __ __ _ _ _ _ + | \/ (_)_ _ (_) | ___ __ _ __| | + | |\/| | | ' \| | |__/ _ \/ _` / _` | + |_| |_|_|_||_|_|____\___/\__,_\__,_| + + Raspberry Pi 4 + + [ML] Requesting binary + [MP] ⏩ Pushing 36 KiB =========================================🦀 100% 0 KiB/s Time: 00:00:00 + [ML] Loaded! Executing the payload now + + @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + @ You're using a JTAG debug image. @ + @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + @ 1. open openocd, gdb @ + @ 2. target extended-remote :3333; @ + @ 3. set $pc=0x80000 @ + @ 4. break rust_entry/others @ + @ 5. break $previous_addr @ + @ 6. delete 1 @ + @ 7. load @ + @ 8. continue @ + @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + + ``` + + *the following guidelines is basically like previous datasheets, In fact, if you're a senior developer, skip the following. XD* + 3. My personal suggestions is using zellij, but you could choice what ever you want. + 4. A: Keeping this miniload running (just don't terminate it) in terminal A. + 5. B: run `make A=apps/helloworld PLATFORM=aarch64-raspi4 openocd`, + the windows should display following, but it doesn't matter, we don't need to care about this. + + ``` + $ make A=apps/helloworld PLATFORM=aarch64-raspi4 openocd + + Launching OpenOCD + [sudo] password for jacky: + Open On-Chip Debugger 0.11.0+dev-g1ad6ed3 (2021-12-02-20:10) + Licensed under GNU GPL v2 + For bug reports, read + http://openocd.org/doc/doxygen/bugs.html + DEPRECATED! use 'adapter speed' not 'adapter_khz' + Warn : DEPRECATED! use '-baseaddr' not '-ctibase' + Warn : DEPRECATED! use '-baseaddr' not '-ctibase' + Warn : DEPRECATED! use '-baseaddr' not '-ctibase' + Warn : DEPRECATED! use '-baseaddr' not '-ctibase' + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : J-Link V9 compiled May 7 2021 16:26:12 + Info : Hardware version: 9.60 + Info : VTarget = 3.311 V + Info : clock speed 1000 kHz + Info : JTAG tap: rpi4.tap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) + Info : rpi4.core0: hardware has 6 breakpoints, 4 watchpoints + Info : rpi4.core1: hardware has 6 breakpoints, 4 watchpoints + Info : rpi4.core2: hardware has 6 breakpoints, 4 watchpoints + Info : rpi4.core3: hardware has 6 breakpoints, 4 watchpoints + Info : starting gdb server for rpi4.core0 on 3333 + Info : Listening on port 3333 for gdb connections + Info : starting gdb server for rpi4.core1 on 3334 + Info : Listening on port 3334 for gdb connections + Info : starting gdb server for rpi4.core2 on 3335 + Info : Listening on port 3335 for gdb connections + Info : starting gdb server for rpi4.core3 on 3336 + Info : Listening on port 3336 for gdb connections + + ``` + + 6. C: run `make A=apps/helloworld PLATFORM=aarch64-raspi4 gdb` in terminal C. + 7. You are now in GDB, but just don't start your debug immediately. + Because the use of minipush script, we could simple push our image to board before power up the board. + Like a double-edged sword. It also constrains our behavior, + which it's incapable for us to power up the board then use some kinds like halt command to halt the CPU. + (I think it can be done through script modification, but now there is no time to study and change ruby for a trivial upgrade.) + So we add a dead loop at the end of the image we generate lastest. + + ```gdb + (gdb) target extended-remote :3333 // connect to openocd gdb serve + // you should see $pc=0x2080db4 + (gdb) set $pc=0x80000 // The following behavior is unnecessary and can be debugged normally. + (gdb) monitor poll // MMU disable + (gdb) break rust_entry // Start debug module/axhal/ ... the location is VADDR will case error, + // you should use b *0x81a90 (manally remove 0xffff ... from output) + (gdb) b *0x81a90 + (gdb) break rust_main // as previous + (gdb) b *0x82888 + (gdb) delete 1 3 + (gdb) continue // first stop at rust_entry + (gdb) continue // second stop at rust_main + (gdb) monitor poll // MMU enable (in rust_entry) + ``` + +## Reference + +1. [rust-embedded/rust-raspberrypi-OS-tutorials](https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials) +2. [Raspberry Pi 4をJTAGデバッグしてみる（FTDI C232HM-DDHSL-0使用）](https://hikalium.hatenablog.jp/entry/2021/07/18/214013) +3. [Rust Raspberry Pi OS tutorials 08 HW debug JTAG by hikalium 2021-09-20](https://www.youtube.com/watch?v=6ULvzK1Drgo&t=21s) +4. [my record](https://bitbucket.org/jackyliu16/blog/src/master/content/jtag-load-failure-debug.cn.md) +4. openocd docs, bcm2711 docs, gdb docs ... etc. + + diff --git a/doc/ymodem.txt b/doc/ymodem.txt new file mode 100644 index 0000000000..f09f81ecf2 --- /dev/null +++ b/doc/ymodem.txt @@ -0,0 +1,1650 @@ + + + + - 1 - + + + + XMODEM/YMODEM PROTOCOL REFERENCE + A compendium of documents describing the + + XMODEM and YMODEM + + File Transfer Protocols + + + + + + + + + + + + Edited by Chuck Forsberg + + + + + + + + + + + + + + + Please distribute as widely as possible. + + Questions to Chuck Forsberg + + + + + + Omen Technology Inc + 17505-V Sauvie Island Road + Portland Oregon 97231 + Voice: 503-621-3406 + Modem (Telegodzilla): 503-621-3746 Speed 1200,300 + Compuserve: 70715,131 + UUCP: ...!tektronix!reed!omen!caf + + + + + + + + + + + + + + + + - 2 - + + + +1. ROSETTA STONE + +Here are some definitions which reflect the current vernacular in the +computer media. The attempt here is identify the file transfer protocol +rather than specific programs. + +XMODEM refers to the original 1979 file transfer etiquette introduced by + Ward Christensen's 1979 MODEM2 program. It's also called the + MODEM or MODEM2 protocol. Some who are unaware of MODEM7's + unusual batch file mode call it MODEM7. Other aliases include + "CP/M Users's Group" and "TERM II FTP 3". This protocol is + supported by every serious communications program because of its + universality, simplicity, and reasonable performance. + +XMODEM/CRC replaces XMODEM's 1 byte checksum with a two byte Cyclical + Redunancy Check (CRC-16), giving modern error detection + protection. + +YMODEM refers to the XMODEM/CRC protocol with the throughput and/or batch + transmission enhancements described below. + + +2. YET ANOTHER PROTOCOL? + +Since its development half a decade ago, the Ward Christensen modem +protocol has enabled a wide variety of computer systems to interchange +data. There is hardly a communications program that doesn't at least +claim to support this protocol. + +Recent advances in computing, modems and networking have revealed a number +of weaknesses in the original protocol: + + + The short block length caused throughput to suffer when used with + timesharing systems, packet switched networks, satellite circuits, + and buffered (error correcting) modems. + + + The 8 bit arithmetic checksum and other aspects allowed line + impairments to interfere with dependable, accurate transfers. + + + Only one file could be sent per command. The file name had to be + given twice, first to the sending program and then again to the + receiving program. + + + The transmitted file could accumulate as many as 127 extraneous + bytes. + + + The modification date of the file was lost. + +A number of other protocols have been developed over the years, but none +have displaced XMODEM to date: + + + + +Chapter 2 + + + + + + + +X/YMODEM Protocol Reference 10-10-85 3 + + + + + Lack of public domain documentation and example programs have kept + proprietary protocols such as MNP, Blast, and others tightly bound to + the fortunes of their suppliers. + + + Complexity discourages the widespread application of BISYNC, SDLC, + HDLC, X.25, and X.PC protocols. + + + Performance compromises and moderate complexity have limited the + popularity of the Kermit protocol, which was developed to allow file + transfers in environments hostile to XMODEM. + +The YMODEM Protocol extensions were developed as a means of addressing the +weaknesses described above while maintaining XMODEM's simplicity as much +as possible. + +YMODEM is supported by the public domain programs YAM (CP/M), +YAM(CP/M-86), YAM(CCPM-86), IMP (CP/M), KMD (CP/M), MODEM76.ASM (CP/M), +rb/sb (Unix, VMS, Berkeley Unix, Venix, Xenix, Coherent, IDRIS, Regulus) +as well as Professional-YAM.1 These programs have been in use since 1981. + +The 1k packet length capability described below may be used in conjunction +with the Batch Protocol, or with single file transfers identical to the +XMODEM/CRC protocol except for the minimal changes to support 1k packets. + +Another extension is simply called the g option. It provides maximum +throughput when used with end to end error correcting media, such as X.PC +and error correcting modems, including the emerging 9600 bps units by +Electronic Vaults and others. + +To complete this tome, Ward Christensen's original protocol document and +John Byrns's CRC-16 document are included for reference. + +References to the MODEM or MODEM7 protocol have been changed to XMODEM to +accommodate the vernacular. In Australia, it is properly called the +Christensen Portocol. + +Watch for an article describing the YMODEM protocol in a more coherent +fashion later this year. The article will include some interesting +history on the development of microcomputer file transfers. + + + + + + + + +__________ + + 1. Available for IBM PC,XT,AT, Unix and Xenix + + + + +Chapter 2 + + + + + + + +X/YMODEM Protocol Reference 10-10-85 4 + + + +2.1 Some Messages from the Pioneer + +#: 130940 S0/Communications 25-Apr-85 18:38:47 +Sb: my protocol +Fm: Ward Christensen 76703,302 (EDITED) +To: all + +Be aware the article2 DID quote me correctly in terms of the phrases like +"not robust", etc. + +It was a quick hack I threw together, very unplanned (like everything I +do), to satisfy a personal need to communicate with "some other" people. + +ONLY the fact that it was done in 8/77, and that I put it in the public +domain immediately, made it become the standard that it is. + +I think its time for me to + +(1) document it; (people call me and say "my product is going to include +it - what can I 'reference'", or "I'm writing a paper on it, what do I put +in the bibliography") and + +(2) propose an "incremental extension" to it, which might take "exactly" +the form of Chuck Forsberg's YAM protocol. He wrote YAM in C for CP/M and +put it in the public domain, and wrote a batch protocol for Unix3 called +rb and sb (receive batch, send batch), which was basically XMODEM with + (a) a record 0 containing filename date time and size + (b) a 1K block size option + (c) CRC-16. + +He did some clever programming to detect false ACK or EOT, but basically +left them the same. + +People who suggest I make SIGNIFICANT changes to the protocol, such as +"full duplex", "multiple outstanding blocks", "multiple destinations", etc +etc don't understand that the incredible simplicity of the protocol is one +of the reasons it survived to this day in as many machines and programs as +it may be found in! + +Consider the PC-NET group back in '77 or so - documenting to beat the band +- THEY had a protocol, but it was "extremely complex", because it tried to +be "all things to all people" - i.e. send binary files on a 7-bit system, +etc. I was not that "benevolent". I (emphasize > I < ) had an 8-bit UART, + + +__________ + + 2. Infoworld April 29 p. 16 + + 3. VAX/VMS versions of these programs are also available. + + + + +Chapter 2 + + + + + + + +X/YMODEM Protocol Reference 10-10-85 5 + + + +so "my protocol was an 8-bit protocol", and I would just say "sorry" to +people who were held back by 7-bit limitations. ... + +Block size: Chuck Forsberg created an extension of my protocol, called +YAM, which is also supported via his public domain programs for UNIX +called rb and sb - receive batch and send batch. They cleverly send a +"block 0" which contains the filename, date, time, and size. +Unfortunately, its UNIX style, and is a bit weird4 - octal numbers, etc. +BUT, it is a nice way to overcome the kludgy "echo the chars of the name" +introduced with MODEM7. Further, chuck uses CRC-16 and optional 1K +blocks. Thus the record 0, 1K, and CRC, make it a "pretty slick new +protocol" which is not significantly different from my own. + +Also, there is a catchy name - YMODEM. That means to some that it is the +"next thing after XMODEM", and to others that it is the Y(am)MODEM +protocol. I don't want to emphasize that too much - out of fear that +other mfgrs might think it is a "competitive" protocol, rather than an +"unaffiliated" protocol. Chuck is currently selling a much-enhanced +version of his CP/M-80 C program YAM, calling it Professional Yam, and its +for the PC - I'm using it right now. VERY slick! 32K capture buffer, +script, scrolling, previously captured text search, plus built-in commands +for just about everything - directory (sorted every which way), XMODEM, +YMODEM, KERMIT, and ASCII file upload/download, etc. You can program it +to "behave" with most any system - for example when trying a number for +CIS it detects the "busy" string back from the modem and substitutes a +diff phone # into the dialing string and branches back to try it. + + + +3. XMODEM PROTOCOL ENHANCEMENTS + +This chapter discusses the protocol extensions to Ward Christensen's 1982 +XMODEM protocol description document. + +The original document recommends the user be asked whether to continue +trying or abort after 10 retries. Most programs no longer ask the +operator whether he wishes to keep retrying. Virtually all correctable +errors are corrected within the first few retransmissions. If the line is +so bad that ten attempts are insufficient, there is a significant danger +of undetected errors. If the connection is that bad, it's better to +redial for a better connection, or mail a floppy disk. + + + + + +__________ + + 4. The file length, time, and file mode are optional. The pathname and + file length may be sent alone if desired. + + + + +Chapter 3 XMODEM Protocol Enhancements + + + + + + + +X/YMODEM Protocol Reference 10-10-85 6 + + + +3.1 Graceful Abort + +YAM and Professional-YAM recognize a sequence of two consecutive CAN (Hex +18) characters without modem errors (overrun, framing, etc.) as a transfer +abort command.1 The check for two consecutive CAN characters virtually +eliminates the possibility of a line hit aborting the transfer. YAM sends +five CAN characters when it aborts an XMODEM or YMODEM protocol file +transfer, followed by five backspaces to delete the CAN characters from +the remote's keyboard input buffer (in case the remote had already aborted +the transfer). + + +3.2 CRC-16 Option + +The XMODEM protocol uses an optional two character CRC-16 instead of the +one character arithmetic checksum used by the original protocol and by +most commercial implementations. CRC-16 guarantees detection of all +single and double bit errors, all errors with an odd number of error +bits, all burst errors of length 16 or less, 99.9969% of all 17-bit error +bursts, and 99.9984 per cent of all possible longer error bursts. By +contrast, a double bit error, or a burst error of 9 bits or more can sneak +past the XMODEM protocol arithmetic checksum. + +The XMODEM/CRC protocol is similar to the XMODEM protocol, except that the +receiver specifies CRC-16 by sending C (Hex 43) instead of NAK when +requesting the FIRST packet. A two byte CRC is sent in place of the one +byte arithmetic checksum. + +YAM's c option to the r command enables CRC-16 in single file reception, +corresponding to the original implementation in the MODEM7 series +programs. This remains the default because many commercial communications +programs and bulletin board systems still do not support CRC-16, +especially those written in Basic or Pascal. + +XMODEM protocol with CRC is accurate provided both sender and receiver +both report a successful transmission. The protocol is robust in the +presence of characters lost by buffer overloading on timesharing systems. + +The single character ACK/NAK responses generated by the receiving program +adapt well to split speed modems, where the reverse channel is limited to +ten per cent or less of the main channel's speed. + +XMODEM and YMODEM are half duplex protocols which do not attempt to +transmit information and control signals in both directions at the same + + +__________ + + 1. This is recognized when YAM is waiting for the beginning of a packet + or for an acknowledge to one that has been sent. + + + + +Chapter 3 XMODEM Protocol Enhancements + + + + + + + +X/YMODEM Protocol Reference 10-10-85 7 + + + +time. This avoids buffer overrun problems that have been reported by +users attempting to exploit full duplex aynchronous file transfer +protocols such as Blast. + +Professional-YAM adds several proprietary logic enhancements to XMODEM's +error detection and recovery. These compatible enhancements eliminate +most of the bad file transfers other programs make when using the XMODEM +protocol under less than ideal conditions. + + +3.3 1024 Byte Packet Option + +The choice to use 1024 byte packets is expressed to the sending program on +its command line or selection menu. + +Programs using the Hoff protocol use a two character sequence emitted by +the receiver (CK) to automatically trigger the use of 1024 byte packets as +an alternative to specifying this option on this command line. Although +this two character sequence works well on single process micros in direct +communication, timesharing systems and packet switched networks can +separate the successive characters by several seconds, rendering this +method unreliable. + +An STX (02) replaces the SOH (01) at the beginning of the transmitted +block to notify the receiver of the longer packet length. The transmitted +packet contains 1024 bytes of data. The receiver should be able to accept +any mixture of 128 and 1024 byte packets. The packet number is +incremented by one for each packet regardless of the packet length. + +The sender must not change between 128 and 1024 byte packet lengths if it +has not received a valid ACK for the current packet. Failure to observe +this restriction allows certain transmission errors to pass undetected. + +If 1024 byte packets are being used, it is possible for a file to "grow" +up to the next multiple of 1024 bytes. This does not waste disk space if +the allocation granularity is 1k or greater. When 1024 byte packets are +used with YMODEM batch transmission, the file length transmitted in the +file name packet allows the receiver to discard the padding, preserving +the exact file length and contents. + +CRC-16 should be used with the k option to preserve data integrity over +phone lines.2 1024 byte packets may be used with batch file transmission +or with single file transmission. + + + + +__________ + + 2. Some programs enforce this recommendation. + + + + +Chapter 3 XMODEM Protocol Enhancements + + + + + + + +X/YMODEM Protocol Reference 10-10-85 8 + + + + Figure 1. 1024 byte Packets + + SENDER RECEIVER + "s -k foo.bar" + "foo.bar open x.x minutes" + C + STX 01 FE Data[1024] CRC CRC + ACK + STX 02 FD Data[1024] CRC CRC + ACK + STX 03 FC Data[1000] CPMEOF[24] CRC CRC + ACK + EOT + ACK + + Figure 2. Mixed 1024 and 128 byte Packets + + SENDER RECEIVER + "s -k foo.bar" + "foo.bar open x.x minutes" + C + STX 01 FE Data[1024] CRC CRC + ACK + STX 02 FD Data[1024] CRC CRC + ACK + SOH 03 FC Data[128] CRC CRC + ACK + SOH 04 FB Data[100] CPMEOF[28] CRC CRC + ACK + EOT + ACK + +4. YMODEM Batch File Transmission + +The YMODEM Batch protocol is an extension to the XMODEM/CRC protocol that +allows 0 or more files to be transmitted with a single command. (Zero +files may be sent if none of the requested files is accessible.) The +design approach of the YMODEM Batch protocol is to use the normal routines +for sending and receiving XMODEM packets in a layered fashion similar to +packet switching methods. + +Why was it necessary to design a new batch protocol when one already +existed in MODEM7?1 The batch file mode used by MODEM7 is unsuitable + + +__________ + + 1. The MODEM7 batch protocol transmitted CP/M FCB bytes f1...f8 and + t1...t3 one character at a time. The receiver echoed these bytes as + received, one at a time. + + + + +Chapter 4 XMODEM Protocol Enhancements + + + + + + + +X/YMODEM Protocol Reference 10-10-85 9 + + + +because it does not permit full pathnames, file length, file date, or +other attribute information to be transmitted. Such a restrictive design, +hastily implemented with only CP/M in mind, would not have permitted +extensions to current areas of personal computing such as Unix, DOS, and +object oriented systems. In addition, the MODEM7 batch file mode is +somewhat susceptible to transmission impairments. + +As in the case of single a file transfer, the receiver initiates batch +file transmission by sending a "C" character (for CRC-16). + +The sender opens the first file and sends packet number 0 with the +following information.2 + +Only the pathname (file name) part is required for batch transfers. + +To maintain upwards compatibility, all unused bytes in packet 0 must be +set to null. + +Pathname The pathname (conventionally, the file name) is sent as a null + terminated ASCII string. This is the filename format used by the + handle oriented MSDOS(TM) functions and C library fopen functions. + An assembly language example follows: + DB 'foo.bar',0 + No spaces are included in the pathname. Normally only the file name + stem (no directory prefix) is transmitted unless the sender has + selected YAM's f option to send the full pathname. The source drive + (A:, B:, etc.) is never sent. + + Filename Considerations: + + + File names should be translated to lower case unless the sending + system supports upper/lower case file names. This is a + convenience for users of systems (such as Unix) which store + filenames in upper and lower case. + + + The receiver should accommodate file names in lower and upper + case. + + + The rb(1) program on Unix systems normally translates the + filename to lower case unless one or more letters in the + filename are already in lower case. + + + When transmitting files between different operating systems, + file names must be acceptable to both the sender and receiving + operating systems. + + +__________ + + 2. Only the data part of the packet is described here. + + + + +Chapter 4 XMODEM Protocol Enhancements + + + + + + + +X/YMODEM Protocol Reference 10-10-85 10 + + + + If directories are included, they are delimited by /; i.e., + "subdir/foo" is acceptable, "subdir\foo" is not. + +Length The file length and each of the succeeding fields are optional.3 + The length field is stored in the packet as a decimal string counting + the number of data bytes in the file. The file length does not + include any CPMEOF (^Z) characters used to pad the last packet. + + If the file being transmitted is growing during transmission, the + length field should be set to at least the final expected file + length, or not sent. + + The receiver stores the specified number of characters, discarding + any padding added by the sender to fill up the last packet. + +Modification Date A single space separates the modification date from the + file length. + + The mod date is optional, and the filename and length may be sent + without requiring the mod date to be sent. + + The mod date is sent as an octal number giving the time the contents + of the file were last changed measured in seconds from Jan 1 1970 + Universal Coordinated Time (GMT). A date of 0 implies the + modification date is unknown and should be left as the date the file + is received. + + This standard format was chosen to eliminate ambiguities arising from + transfers between different time zones. + + Two Microsoft blunders complicate the use of modification dates in + file transfers with MSDOS(TM) systems. The first is the lack of + timezone standardization in MS-DOS. A file's creation time can not + be known unless the timezone of the system that wrote the file4 is + known. Unix solved this problem (for planet Earth, anyway) by + stamping files with Universal Time (GMT). Microsoft would have to + include the timezone of origin in the directory entries, but does + not. Professional-YAM gets around this problem by using the z + parameter which is set to the number of minutes local time lags GMT. + For files known to originate from a different timezone, the -zT + option may be used to specify T as the timezone for an individual + file transfer. + + + +__________ + + 3. Fields may not be skipped. + + 4. Not necessarily that of the transmitting system! + + + + +Chapter 4 XMODEM Protocol Enhancements + + + + + + + +X/YMODEM Protocol Reference 10-10-85 11 + + + + The second problem is the lack of a separate file creation date in + DOS. Since some backup schemes used with DOS rely on the file + creation date to select files to be copied to the archive, back- + dating the file modification date could interfere with the safety of + the transferred files. For this reason, Professional-YAM does not + modify the date of received files with the header information unless + the d parameter is non zero. + + +Mode A single space separates the file mode from the modification date. + The file mode is stored as an octal string. Unless the file + originated from a Unix system, the file mode is set to 0. rb(1) + checks the file mode for the 0x8000 bit which indicates a Unix type + regular file. Files with the 0x8000 bit set are assumed to have been + sent from another Unix (or similar) system which uses the same file + conventions. Such files are not translated in any way. + + +Serial Number A single space separates the serial number from the file + mode. The serial number of the transmitting program is stored as an + octal string. Programs which do not have a serial number should omit + this field, or set it to 0. The receiver's use of this field is + optional. + +The rest of the packet is set to nulls. This is essential to preserve +upward compatibility.5 After the filename packet has been received, it is +ACK'ed if the write open is successful. The receiver then initiates +transfer of the file contents according to the standard XMODEM/CRC +protocol. If the file cannot be opened for writing, the receiver cancels +the transfer with CAN characters as described above. + +After the file contents have been transmitted, the receiver again asks for +the next pathname. Transmission of a null pathname terminates batch file +transmission. Note that transmission of no files is not necessarily an +error. This is possible if none of the files requested of the sender +could be opened for reading. + +In batch transmission, the receiver automatically requests CRC-16. + +The Unix programs sb(1) and rb(1) included in the source code file +RBSB.SHQ (rbsb.sh) should answer other questions about YMODEM batch +protocol. + + + +__________ + + 5. If, perchance, this information extends beyond 128 bytes (possible + with Unix 4.2 BSD extended file names), the packet should be sent as a + 1k packet as described above. + + + + +Chapter 4 XMODEM Protocol Enhancements + + + + + + + +X/YMODEM Protocol Reference 10-10-85 12 + + + + Figure 3. Batch Transmission Session + + SENDER RECEIVER + "sb foo.*" + "sending in batch mode etc." + C (command:rb) + SOH 00 FF foo.c NUL[123] CRC CRC + ACK + C + SOH 01 FE Data[128] CRC CRC + ACK + SOH 02 FD Data[1024] CRC CRC + ACK + SOH 03 FC Data[128] CRC CRC + ACK + SOH 04 FB Data[100] CPMEOF[28] CRC CRC + ACK + EOT + NAK + EOT + ACK + C + SOH 00 FF NUL[128] CRC CRC + ACK + + Figure 4. Filename packet transmitted by sb + + -rw-r--r-- 6347 Jun 17 1984 20:34 bbcsched.txt + + 00 0100FF62 62637363 6865642E 74787400 |...bbcsched.txt.| + 10 36333437 20333331 34373432 35313320 |6347 3314742513 | + 20 31303036 34340000 00000000 00000000 |100644..........| + 30 00000000 00000000 00000000 00000000 + 80 000000CA 56 + + + + + + + + + + + + + + + + + + + + +Chapter 4 XMODEM Protocol Enhancements + + + + + + + +X/YMODEM Protocol Reference 10-10-85 13 + + + + Figure 5. Header Information used by YMODEM Implementations + + +_____________________________________________________________________ +| Program | Batch | Length | Date | Mode | S/N | 1k-Blk | g-Option | +|___________|_______|________|______|______|_____|________|__________| +|Unix rb/sb | yes | yes | yes | yes | no | yes | sb only | +|___________|_______|________|______|______|_____|________|__________| +|VMS rb/sb | yes | yes | no | no | no | yes | no | +|___________|_______|________|______|______|_____|________|__________| +|Pro-YAM | yes | yes | yes | no | yes | yes | yes | +|___________|_______|________|______|______|_____|________|__________| +|CP/M YAM | yes | no | no | no | no | yes | no | +|___________|_______|________|______|______|_____|________|__________| +|KMD/IMP | yes | no | no | no | no | yes | no | +|___________|_______|________|______|______|_____|________|__________| +|MEX | no | no | no | no | no | yes | no | +|___________|_______|________|______|______|_____|________|__________| + +4.1 IMP/KMD Record Count + +Due to programming constraints, these programs do not send the file length +as described above. Instead, they send (and look for) the CP/M record +count stored in the last two bytes of the header packet. The least +significant bits are stored in the penultimate byte. + +KMD and IMP use the record count to allow the receiving program to display +the file size and estimated transmission time; the file length is +determined by the actual number of records sent. + + +5. g Option File Transmission + +Developing technology is providing phone line data transmission at ever +higher speeds using very specialized techniques. These high speed modems, +as well as session protocols such as X.PC, provide high speed, error free +communications at the expense of considerably increased delay time. + +This delay time is moderate compared to human interactions, but it +cripples the throughput of most error correcting protocols. + +The g option to YMODEM has proven effective under these circumstances. +The g option is driven by the receiver, which initiates the batch transfer +by transmitting a G instead of C. When the sender recognizes the G, it +bypasses the usual wait for an ACK to each transmitted packet, sending +succeeding packets at full speed, subject to XOFF/XON or other flow +control exerted by the medium. + +The sender expects an initial G to initiate the transmission of a +particular file, and also expects an ACK on the EOT sent at the end of +each file. This synchronization allows the receiver time to open and + + + +Chapter 5 XMODEM Protocol Enhancements + + + + + + + +X/YMODEM Protocol Reference 10-10-85 14 + + + +close files as necessary. + + + Figure 6. g Option Transmission Session + + SENDER RECEIVER + "sb foo.*" + "sending in batch mode etc..." + G (command:rb -g) + SOH 00 FF foo.c NUL[123] CRC CRC + G + SOH 01 FE Data[128] CRC CRC + SOH 02 FD Data[1024] CRC CRC + SOH 03 FC Data[128] CRC CRC + SOH 04 FB Data[100] CPMEOF[28] CRC CRC + EOT + ACK + G + SOH 00 FF NUL[128] CRC CRC + + +6. XMODEM PROTOCOL OVERVIEW + +8/9/82 by Ward Christensen. + +I will maintain a master copy of this. Please pass on changes or +suggestions via CBBS/Chicago at (312) 545-8086, CBBS/CPMUG (312) 849-1132 +or by voice at (312) 849-6279. + +6.1 Definitions + + 01H + 04H + 06H + 15H + 18H + 43H + + +6.2 Transmission Medium Level Protocol + +Asynchronous, 8 data bits, no parity, one stop bit. + +The protocol imposes no restrictions on the contents of the data being +transmitted. No control characters are looked for in the 128-byte data +messages. Absolutely any kind of data may be sent - binary, ASCII, etc. +The protocol has not formally been adopted to a 7-bit environment for the +transmission of ASCII-only (or unpacked-hex) data , although it could be +simply by having both ends agree to AND the protocol-dependent data with +7F hex before validating it. I specifically am referring to the checksum, +and the block numbers and their ones- complement. + + + +Chapter 6 Xmodem Protocol Overview + + + + + + + +X/YMODEM Protocol Reference 10-10-85 15 + + + +Those wishing to maintain compatibility of the CP/M file structure, i.e. +to allow modemming ASCII files to or from CP/M systems should follow this +data format: + + + ASCII tabs used (09H); tabs set every 8. + + + Lines terminated by CR/LF (0DH 0AH) + + + End-of-file indicated by ^Z, 1AH. (one or more) + + + Data is variable length, i.e. should be considered a continuous + stream of data bytes, broken into 128-byte chunks purely for the + purpose of transmission. + + + A CP/M "peculiarity": If the data ends exactly on a 128-byte + boundary, i.e. CR in 127, and LF in 128, a subsequent sector + containing the ^Z EOF character(s) is optional, but is preferred. + Some utilities or user programs still do not handle EOF without ^Zs. + + + The last block sent is no different from others, i.e. there is no + "short block". + Figure 7. XMODEM Message Block Level Protocol + +Each block of the transfer looks like: + <255-blk #><--128 data bytes--> +in which: + = 01 hex + = binary number, starts at 01 increments by 1, and + wraps 0FFH to 00H (not to 01) +<255-blk #> = blk # after going thru 8080 "CMA" instr, i.e. + each bit complemented in the 8-bit block number. + Formally, this is the "ones complement". + = the sum of the data bytes only. Toss any carry. + +6.3 File Level Protocol + +6.3.1 Common_to_Both_Sender_and_Receiver +All errors are retried 10 times. For versions running with an operator +(i.e. NOT with XMODEM), a message is typed after 10 errors asking the +operator whether to "retry or quit". + +Some versions of the protocol use , ASCII ^X, to cancel transmission. +This was never adopted as a standard, as having a single "abort" character +makes the transmission susceptible to false termination due to an + or being corrupted into a and cancelling transmission. + +The protocol may be considered "receiver driven", that is, the sender need +not automatically re-transmit, although it does in the current +implementations. + + + + + +Chapter 6 Xmodem Protocol Overview + + + + + + + +X/YMODEM Protocol Reference 10-10-85 16 + + + +6.3.2 Receive_Program_Considerations +The receiver has a 10-second timeout. It sends a every time it +times out. The receiver's first timeout, which sends a , signals the +transmitter to start. Optionally, the receiver could send a +immediately, in case the sender was ready. This would save the initial 10 +second timeout. However, the receiver MUST continue to timeout every 10 +seconds in case the sender wasn't ready. + +Once into a receiving a block, the receiver goes into a one-second timeout +for each character and the checksum. If the receiver wishes to a +block for any reason (invalid header, timeout receiving data), it must +wait for the line to clear. See "programming tips" for ideas + +Synchronizing: If a valid block number is received, it will be: 1) the +expected one, in which case everything is fine; or 2) a repeat of the +previously received block. This should be considered OK, and only +indicates that the receivers got glitched, and the sender re- +transmitted; 3) any other block number indicates a fatal loss of +synchronization, such as the rare case of the sender getting a line-glitch +that looked like an . Abort the transmission, sending a + + +6.3.3 Sending_program_considerations +While waiting for transmission to begin, the sender has only a single very +long timeout, say one minute. In the current protocol, the sender has a +10 second timeout before retrying. I suggest NOT doing this, and letting +the protocol be completely receiver-driven. This will be compatible with +existing programs. + +When the sender has no more data, it sends an , and awaits an , +resending the if it doesn't get one. Again, the protocol could be +receiver-driven, with the sender only having the high-level 1-minute +timeout to abort. + + +Here is a sample of the data flow, sending a 3-block message. It includes +the two most common line hits - a garbaged block, and an reply +getting garbaged. represents the checksum byte. + + + + + + + + + + + + + + + + +Chapter 6 Xmodem Protocol Overview + + + + + + + +X/YMODEM Protocol Reference 10-10-85 17 + + + + Figure 8. Data flow including Error Recovery + +SENDER RECEIVER + times out after 10 seconds, + <--- + 01 FE -data- ---> + <--- + 02 FD -data- xx ---> (data gets line hit) + <--- + 02 FD -data- xx ---> + <--- + 03 FC -data- xx ---> +(ack gets garbaged) <--- + 03 FC -data- xx ---> + ---> + <--- + ---> + <--- +(finished) + +6.4 Programming Tips + + + The character-receive subroutine should be called with a parameter + specifying the number of seconds to wait. The receiver should first + call it with a time of 10, then and try again, 10 times. + + After receiving the , the receiver should call the character + receive subroutine with a 1-second timeout, for the remainder of the + message and the . Since they are sent as a continuous stream, + timing out of this implies a serious like glitch that caused, say, + 127 characters to be seen instead of 128. + + + When the receiver wishes to , it should call a "PURGE" + subroutine, to wait for the line to clear. Recall the sender tosses + any characters in its UART buffer immediately upon completing sending + a block, to ensure no glitches were mis- interpreted. + + The most common technique is for "PURGE" to call the character + receive subroutine, specifying a 1-second timeout,1 and looping back + to PURGE until a timeout occurs. The is then sent, ensuring + the other end will see it. + + + You may wish to add code recommended by John Mahr to your character + receive routine - to set an error flag if the UART shows framing + error, or overrun. This will help catch a few more glitches - the + + +__________ + + 1. These times should be adjusted for use with timesharing systems. + + + + +Chapter 6 Xmodem Protocol Overview + + + + + + + +X/YMODEM Protocol Reference 10-10-85 18 + + + + most common of which is a hit in the high bits of the byte in two + consecutive bytes. The comes out OK since counting in 1-byte + produces the same result of adding 80H + 80H as with adding 00H + + 00H. + + + +7. XMODEM/CRC Overview + +1/13/85 by John Byrns -- CRC option. + +Please pass on any reports of errors in this document or suggestions for +improvement to me via Ward's/CBBS at (312) 849-1132, or by voice at (312) +885-1105. + +The CRC used in the Modem Protocol is an alternate form of block check +which provides more robust error detection than the original checksum. +Andrew S. Tanenbaum says in his book, Computer Networks, that the CRC- +CCITT used by the Modem Protocol will detect all single and double bit +errors, all errors with an odd number of bits, all burst errors of length +16 or less, 99.997% of 17-bit error bursts, and 99.998% of 18-bit and +longer bursts. + +The changes to the Modem Protocol to replace the checksum with the CRC are +straight forward. If that were all that we did we would not be able to +communicate between a program using the old checksum protocol and one +using the new CRC protocol. An initial handshake was added to solve this +problem. The handshake allows a receiving program with CRC capability to +determine whether the sending program supports the CRC option, and to +switch it to CRC mode if it does. This handshake is designed so that it +will work properly with programs which implement only the original +protocol. A description of this handshake is presented in section 10. + + Figure 9. Message Block Level Protocol, CRC mode + +Each block of the transfer in CRC mode looks like: + <255-blk #><--128 data bytes--> +in which: + = 01 hex + = binary number, starts at 01 increments by 1, and + wraps 0FFH to 00H (not to 01) +<255-blk #> = ones complement of blk #. + = byte containing the 8 hi order coefficients of the CRC. + = byte containing the 8 lo order coefficients of the CRC. + +7.1 CRC Calculation + +7.1.1 Formal_Definition +To calculate the 16 bit CRC the message bits are considered to be the +coefficients of a polynomial. This message polynomial is first multiplied +by X^16 and then divided by the generator polynomial (X^16 + X^12 + X^5 + + + + +Chapter 7 Xmodem Protocol Overview + + + + + + + +X/YMODEM Protocol Reference 10-10-85 19 + + + +1) using modulo two arithmetic. The remainder left after the division is +the desired CRC. Since a message block in the Modem Protocol is 128 bytes +or 1024 bits, the message polynomial will be of order X^1023. The hi order +bit of the first byte of the message block is the coefficient of X^1023 in +the message polynomial. The lo order bit of the last byte of the message +block is the coefficient of X^0 in the message polynomial. + + Figure 10. Example of CRC Calculation written in C + +/* + * This function calculates the CRC used by the XMODEM/CRC Protocol + * The first argument is a pointer to the message block. + * The second argument is the number of bytes in the message block. + * The function returns an integer which contains the CRC. + * The low order 16 bits are the coefficients of the CRC. + */ +int calcrc(ptr, count) +char *ptr; +int count; +{ + int crc, i; + + crc = 0; + while (--count >= 0) { + crc = crc ^ (int)*ptr++ << 8; + for (i = 0; i < 8; ++i) + if (crc & 0x8000) + crc = crc << 1 ^ 0x1021; + else + crc = crc << 1; + } + return (crc & 0xFFFF); +} + +7.2 CRC File Level Protocol Changes + +7.2.1 Common_to_Both_Sender_and_Receiver +The only change to the File Level Protocol for the CRC option is the +initial handshake which is used to determine if both the sending and the +receiving programs support the CRC mode. All Modem Programs should support +the checksum mode for compatibility with older versions. A receiving +program that wishes to receive in CRC mode implements the mode setting +handshake by sending a in place of the initial . If the sending +program supports CRC mode it will recognize the and will set itself +into CRC mode, and respond by sending the first block as if a had +been received. If the sending program does not support CRC mode it will +not respond to the at all. After the receiver has sent the it will +wait up to 3 seconds for the that starts the first block. If it +receives a within 3 seconds it will assume the sender supports CRC +mode and will proceed with the file exchange in CRC mode. If no is +received within 3 seconds the receiver will switch to checksum mode, send + + + +Chapter 7 Xmodem Protocol Overview + + + + + + + +X/YMODEM Protocol Reference 10-10-85 20 + + + +a , and proceed in checksum mode. If the receiver wishes to use +checksum mode it should send an initial and the sending program +should respond to the as defined in the original Modem Protocol. +After the mode has been set by the initial or the protocol +follows the original Modem Protocol and is identical whether the checksum +or CRC is being used. + + +7.2.2 Receive_Program_Considerations +There are at least 4 things that can go wrong with the mode setting +handshake. + + 1. the initial can be garbled or lost. + + 2. the initial can be garbled. + + 3. the initial can be changed to a . + + 4. the initial from a receiver which wants to receive in checksum + can be changed to a . + +The first problem can be solved if the receiver sends a second after +it times out the first time. This process can be repeated several times. +It must not be repeated too many times before sending a and +switching to checksum mode or a sending program without CRC support may +time out and abort. Repeating the will also fix the second problem if +the sending program cooperates by responding as if a were received +instead of ignoring the extra . + +It is possible to fix problems 3 and 4 but probably not worth the trouble +since they will occur very infrequently. They could be fixed by switching +modes in either the sending or the receiving program after a large number +of successive s. This solution would risk other problems however. + + +7.2.3 Sending_Program_Considerations +The sending program should start in the checksum mode. This will insure +compatibility with checksum only receiving programs. Anytime a is +received before the first or the sending program should set +itself into CRC mode and respond as if a were received. The sender +should respond to additional s as if they were s until the first + is received. This will assist the receiving program in determining +the correct mode when the is lost or garbled. After the first +is received the sending program should ignore s. + + + + + + + + + + +Chapter 7 Xmodem Protocol Overview + + + + + + + +X/YMODEM Protocol Reference 10-10-85 21 + + + +7.3 Data Flow Examples with CRC Option + +Here is a data flow example for the case where the receiver requests +transmission in the CRC mode but the sender does not support the CRC +option. This example also includes various transmission errors. +represents the checksum byte. + + Figure 11. Data Flow: Receiver has CRC Option, Sender Doesn't + +SENDER RECEIVER + <--- + times out after 3 seconds, + <--- + times out after 3 seconds, + <--- + times out after 3 seconds, + <--- + times out after 3 seconds, + <--- + 01 FE -data- ---> + <--- + 02 FD -data- ---> (data gets line hit) + <--- + 02 FD -data- ---> + <--- + 03 FC -data- ---> + (ack gets garbaged) <--- + times out after 10 seconds, + <--- + 03 FC -data- ---> + <--- + ---> + <--- + +Here is a data flow example for the case where the receiver requests +transmission in the CRC mode and the sender supports the CRC option. This +example also includes various transmission errors. represents the +2 CRC bytes. + + + + + + + + + + + + + + + + +Chapter 7 Xmodem Protocol Overview + + + + + + + +X/YMODEM Protocol Reference 10-10-85 22 + + + + Figure 12. Receiver and Sender Both have CRC Option + +SENDER RECEIVER + <--- + 01 FE -data- ---> + <--- + 02 FD -data- ---> (data gets line hit) + <--- + 02 FD -data- ---> + <--- + 03 FC -data- ---> +(ack gets garbaged) <--- + times out after 10 seconds, + <--- + 03 FC -data- ---> + <--- + ---> + <--- + + +8. MORE INFORMATION + +More information may be obtained by calling Telegodzilla at 503-621-3746. +Hit RETURNs for baud rate detection. + +A version this file with boldface, underlining, and superscripts for +printing on Epson or Gemini printers is available on Telegodzilla as +"YMODEME.DOC" or "YMODEME.DQC". + +UUCP sites can obtain this file with + uucp omen!/usr/spool/uucppublic/ymodem.doc /tmp + +The following L.sys line calls Telegodzilla (Pro-YAM in host operation). +Telegodzilla waits for carriage returns to determine the incoming speed. +If none is detected, 1200 bps is assumed and a greeting is displayed. + +In response to "Name Please:" uucico gives the Pro-YAM "link" command as a +user name. The password (Giznoid) controls access to the Xenix system +connected to the IBM PC's other serial port. Communications between +Pro-YAM and Xenix use 9600 bps; YAM converts this to the caller's speed. + +Finally, the calling uucico logs in as uucp. + +omen Any ACU 1200 1-503-621-3746 se:--se: link ord: Giznoid in:--in: uucp + +Contact omen!caf if you wish the troff sources. + + + + + + + + +Chapter 9 Xmodem Protocol Overview + + + + + + + +X/YMODEM Protocol Reference 10-10-85 23 + + + +9. YMODEM Programs + +A demonstration version of Professional-YAM is available as YAMDEMO.LQR (A +SQueezed Novosielski library). This may be used to test YMODEM +implementations. + +Unix programs supporting the YMODEM protocol are available on Telegodzilla +in the "upgrade" subdirectory as RBSB.SHQ (a SQueezed shell archive). +Most Unix like systems are supported, including V7, Sys III, 4.2 BSD, SYS +V, Idris, Coherent, and Regulus. + +A version for VAX-VMS is available in VRBSB.SHQ, in the same directory. + +A CP/M assembly version is available as MODEM76.AQM and MODEM7.LIB. + +Irv Hoff has added YMODEM 1k packets and YMODEM batch transfers to the KMD +and IMP series programs, which replace the XMODEM and MODEM7/MDM7xx series +respectively. Overlays are available for a wide variety of CP/M systems. + +MEX and MEX-PC also support some of the YMODEM extensions. + +Questions about YMODEM, the Professional-YAM communications program, and +requests for evaluation copies may be directed to: + Chuck Forsberg + Omen Technology Inc + 17505-V Sauvie Island Road + Portland Oregon 97231 + Voice: 503-621-3406 + Modem: 503-621-3746 Speed: 1200,300 + Usenet: ...!tektronix!reed!omen!caf + Compuserve: 70715,131 + Source: TCE022 + + + + + + + + + + + + + + + + + + + + + + +Chapter 9 Xmodem Protocol Overview + + + + + + + + + + + + CONTENTS + + +1. ROSETTA STONE..................................................... 2 + +2. YET ANOTHER PROTOCOL?............................................. 2 + 2.1 Some Messages from the Pioneer............................... 4 + +3. XMODEM PROTOCOL ENHANCEMENTS...................................... 5 + 3.1 Graceful Abort............................................... 6 + 3.2 CRC-16 Option................................................ 6 + 3.3 1024 Byte Packet Option...................................... 7 + +4. YMODEM Batch File Transmission.................................... 8 + 4.1 IMP/KMD Record Count......................................... 13 + +5. g Option File Transmission........................................ 13 + +6. XMODEM PROTOCOL OVERVIEW.......................................... 14 + 6.1 Definitions.................................................. 14 + 6.2 Transmission Medium Level Protocol........................... 14 + 6.3 File Level Protocol.......................................... 15 + 6.4 Programming Tips............................................. 17 + +7. XMODEM/CRC Overview............................................... 18 + 7.1 CRC Calculation.............................................. 18 + 7.2 CRC File Level Protocol Changes.............................. 19 + 7.3 Data Flow Examples with CRC Option........................... 21 + +8. MORE INFORMATION.................................................. 22 + +9. YMODEM Programs................................................... 23 + + + + + + + + + + + + + + + + + + + + + + + - i - + + + + + + + + + + + + + + + LIST OF FIGURES + + + Figure 1. 1024 byte Packets......................................... 7 + + Figure 2. Mixed 1024 and 128 byte Packets........................... 7 + + Figure 3. Batch Transmission Session................................ 11 + + Figure 4. Filename packet transmitted by sb......................... 11 + + Figure 5. Header Information used by YMODEM Implementations......... 13 + + Figure 6. g Option Transmission Session............................. 14 + + Figure 7. XMODEM Message Block Level Protocol....................... 15 + + Figure 8. Data flow including Error Recovery........................ 17 + + Figure 9. Message Block Level Protocol, CRC mode.................... 18 + +Figure 10. Example of CRC Calculation written in C................... 19 + +Figure 11. Data Flow: Receiver has CRC Option, Sender Doesn't........ 21 + +Figure 12. Receiver and Sender Both have CRC Option.................. 22 + + + + + + + + + + + + + + + + + + + + + + + + + + - ii - + + + + diff --git a/minicom_output.log b/minicom_output.log new file mode 100644 index 0000000000..8d1c8b69c3 --- /dev/null +++ b/minicom_output.log @@ -0,0 +1 @@ + diff --git a/modules/axalloc/Cargo.toml b/modules/axalloc/Cargo.toml index 40eedf404f..5988fdc925 100644 --- a/modules/axalloc/Cargo.toml +++ b/modules/axalloc/Cargo.toml @@ -22,3 +22,4 @@ spinlock = { path = "../../crates/spinlock" } memory_addr = { path = "../../crates/memory_addr" } allocator = { path = "../../crates/allocator", features = ["bitmap"] } axerrno = { path = "../../crates/axerrno" } +lazy_static = {version="1.4", features=["spin_no_std"]} \ No newline at end of file diff --git a/modules/axalloc/src/lib.rs b/modules/axalloc/src/lib.rs index 096ce95ae7..d2ea0ebc33 100644 --- a/modules/axalloc/src/lib.rs +++ b/modules/axalloc/src/lib.rs @@ -6,16 +6,21 @@ //! be registered as the standard library’s default allocator. #![no_std] +#![feature(allocator_api)] #[macro_use] extern crate log; +#[macro_use] +extern crate lazy_static; + extern crate alloc; mod page; +use alloc::sync::Arc; use allocator::{AllocResult, BaseAllocator, BitmapPageAllocator, ByteAllocator, PageAllocator}; -use core::alloc::{GlobalAlloc, Layout}; -use core::ptr::NonNull; +use core::alloc::{Allocator, GlobalAlloc, Layout}; +use core::ptr::{slice_from_raw_parts_mut, NonNull}; use spinlock::SpinNoIrq; const PAGE_SIZE: usize = 0x1000; @@ -45,16 +50,16 @@ cfg_if::cfg_if! { /// /// [`TlsfByteAllocator`]: allocator::TlsfByteAllocator pub struct GlobalAllocator { - balloc: SpinNoIrq, - palloc: SpinNoIrq>, + balloc_free: SpinNoIrq, + palloc_free: SpinNoIrq>, } impl GlobalAllocator { /// Creates an empty [`GlobalAllocator`]. pub const fn new() -> Self { Self { - balloc: SpinNoIrq::new(DefaultByteAllocator::new()), - palloc: SpinNoIrq::new(BitmapPageAllocator::new()), + balloc_free: SpinNoIrq::new(DefaultByteAllocator::new()), + palloc_free: SpinNoIrq::new(BitmapPageAllocator::new()), } } @@ -76,21 +81,24 @@ impl GlobalAllocator { /// It firstly adds the whole region to the page allocator, then allocates /// a small region (32 KB) to initialize the byte allocator. Therefore, /// the given region must be larger than 32 KB. - pub fn init(&self, start_vaddr: usize, size: usize) { - assert!(size > MIN_HEAP_SIZE); - let init_heap_size = MIN_HEAP_SIZE; - self.palloc.lock().init(start_vaddr, size); - let heap_ptr = self - .alloc_pages(init_heap_size / PAGE_SIZE, PAGE_SIZE) - .unwrap(); - self.balloc.lock().init(heap_ptr, init_heap_size); + /// added nocache allocator-2024.1.23 + pub fn init(&self, (free_base, free_size): (usize, usize)) { + { + assert!(free_size > MIN_HEAP_SIZE); + let init_heap_size = MIN_HEAP_SIZE; + self.palloc_free.lock().init(free_base, free_size); + let heap_ptr = self + .alloc_pages(init_heap_size / PAGE_SIZE, PAGE_SIZE) + .unwrap(); + self.balloc_free.lock().init(heap_ptr, init_heap_size); + } } /// Add the given region to the allocator. /// /// It will add the whole region to the byte allocator. - pub fn add_memory(&self, start_vaddr: usize, size: usize) -> AllocResult { - self.balloc.lock().add_memory(start_vaddr, size) + pub fn add_free_memory(&self, start_vaddr: usize, size: usize) -> AllocResult { + self.balloc_free.lock().add_memory(start_vaddr, size) } /// Allocate arbitrary number of bytes. Returns the left bound of the @@ -104,7 +112,7 @@ impl GlobalAllocator { /// aligned to it. pub fn alloc(&self, layout: Layout) -> AllocResult> { // simple two-level allocator: if no heap memory, allocate from the page allocator. - let mut balloc = self.balloc.lock(); + let mut balloc = self.balloc_free.lock(); loop { if let Ok(ptr) = balloc.alloc(layout) { return Ok(ptr); @@ -133,7 +141,7 @@ impl GlobalAllocator { /// /// [`alloc`]: GlobalAllocator::alloc pub fn dealloc(&self, pos: NonNull, layout: Layout) { - self.balloc.lock().dealloc(pos, layout) + self.balloc_free.lock().dealloc(pos, layout) } /// Allocates contiguous pages. @@ -143,7 +151,7 @@ impl GlobalAllocator { /// `align_pow2` must be a power of 2, and the returned region bound will be /// aligned to it. pub fn alloc_pages(&self, num_pages: usize, align_pow2: usize) -> AllocResult { - self.palloc.lock().alloc_pages(num_pages, align_pow2) + self.palloc_free.lock().alloc_pages(num_pages, align_pow2) } /// Gives back the allocated pages starts from `pos` to the page allocator. @@ -154,27 +162,27 @@ impl GlobalAllocator { /// /// [`alloc_pages`]: GlobalAllocator::alloc_pages pub fn dealloc_pages(&self, pos: usize, num_pages: usize) { - self.palloc.lock().dealloc_pages(pos, num_pages) + self.palloc_free.lock().dealloc_pages(pos, num_pages) } /// Returns the number of allocated bytes in the byte allocator. pub fn used_bytes(&self) -> usize { - self.balloc.lock().used_bytes() + self.balloc_free.lock().used_bytes() } /// Returns the number of available bytes in the byte allocator. pub fn available_bytes(&self) -> usize { - self.balloc.lock().available_bytes() + self.balloc_free.lock().available_bytes() } /// Returns the number of allocated pages in the page allocator. pub fn used_pages(&self) -> usize { - self.palloc.lock().used_pages() + self.palloc_free.lock().used_pages() } /// Returns the number of available pages in the page allocator. pub fn available_pages(&self) -> usize { - self.palloc.lock().available_pages() + self.palloc_free.lock().available_pages() } } @@ -199,6 +207,67 @@ static GLOBAL_ALLOCATOR: GlobalAllocator = GlobalAllocator::new(); pub fn global_allocator() -> &'static GlobalAllocator { &GLOBAL_ALLOCATOR } +lazy_static! { + static ref GLOBAL_NO_CACHE_ALLOCATOR: GlobalNoCacheAllocator = GlobalNoCacheAllocator::new(); +} +// static GLOBAL_NO_CACHE_ALLOCATOR: SyncUnsafeCell< GlobalNoCacheAllocator> = LazyCell::new(|| GlobalNoCacheAllocator::new()); + +/// Returns the reference to the global allocator. +pub fn global_no_cache_allocator() -> GlobalNoCacheAllocator { + GLOBAL_NO_CACHE_ALLOCATOR.clone() +} + +#[derive(Clone)] +pub struct GlobalNoCacheAllocator { + balloc: Arc>, +} + +impl GlobalNoCacheAllocator { + /// Creates an empty [`GlobalAllocator`]. + pub fn new() -> Self { + Self { + balloc: Arc::new(SpinNoIrq::new(DefaultByteAllocator::new())), + } + } + /// Add the given region to the allocator. + /// + /// It will add the whole region to the byte allocator. + pub fn add_memory(&self, start_vaddr: usize, size: usize) -> AllocResult { + let mut g = self.balloc.lock(); + if g.total_bytes() == 0 { + return Err(allocator::AllocError::NoMemory); + } + g.add_memory(start_vaddr, size) + } + /// Initializes the allocator with the given region. + /// + /// It firstly adds the whole region to the page allocator, then allocates + /// a small region (32 KB) to initialize the byte allocator. Therefore, + /// the given region must be larger than 32 KB. + /// added nocache allocator-2024.1.23 + pub fn init(&self, (nocache_base, nocache_size): (usize, usize)) { + if nocache_size > 0 { + self.balloc.lock().init(nocache_base, nocache_size); + } + } +} + +unsafe impl Allocator for GlobalNoCacheAllocator { + fn allocate(&self, layout: Layout) -> Result, core::alloc::AllocError> { + let mut balloc = self.balloc.lock(); + let data = balloc.alloc(layout).map_err(|_e| core::alloc::AllocError)?; + unsafe { + let ptr = data.as_ptr(); + let data = &mut *slice_from_raw_parts_mut(ptr, layout.size()); + let data = NonNull::from(data); + Ok(data) + } + } + + unsafe fn deallocate(&self, ptr: NonNull, layout: Layout) { + self.balloc.lock().dealloc(ptr, layout) + } +} /// Initializes the global allocator with the given memory region. /// @@ -208,26 +277,41 @@ pub fn global_allocator() -> &'static GlobalAllocator { /// valid. /// /// This function should be called only once, and before any allocation. -pub fn global_init(start_vaddr: usize, size: usize) { +pub fn global_init(free: (usize, usize)) { debug!( - "initialize global allocator at: [{:#x}, {:#x})", - start_vaddr, - start_vaddr + size + "initialize global allocator at: free-[{:#x}, {:#x})", + free.0, + free.0 + free.1, ); - GLOBAL_ALLOCATOR.init(start_vaddr, size); + GLOBAL_ALLOCATOR.init(free); +} +/// Initializes the global allocator with the given memory region. +/// +/// Note that the memory region bounds are just numbers, and the allocator +/// does not actually access the region. Users should ensure that the region +/// is valid and not being used by others, so that the allocated memory is also +/// valid. +/// +/// This function should be called only once, and before any allocation. +pub fn global_nocache_init(nocache: (usize, usize)) { + debug!( + "initialize global allocator at: nocache-[{:#x},{:#x})", + nocache.0, + nocache.0 + nocache.1 + ); + GLOBAL_NO_CACHE_ALLOCATOR.init(nocache) } - /// Add the given memory region to the global allocator. /// /// Users should ensure that the region is valid and not being used by others, /// so that the allocated memory is also valid. /// /// It's similar to [`global_init`], but can be called multiple times. -pub fn global_add_memory(start_vaddr: usize, size: usize) -> AllocResult { +pub fn global_add_free_memory(start_vaddr: usize, size: usize) -> AllocResult { debug!( "add a memory region to global allocator: [{:#x}, {:#x})", start_vaddr, start_vaddr + size ); - GLOBAL_ALLOCATOR.add_memory(start_vaddr, size) + GLOBAL_ALLOCATOR.add_free_memory(start_vaddr, size) } diff --git a/modules/axconfig/defconfig.toml b/modules/axconfig/defconfig.toml index e13488d9e5..ecf2432bf2 100644 --- a/modules/axconfig/defconfig.toml +++ b/modules/axconfig/defconfig.toml @@ -9,6 +9,8 @@ family = "dummy" phys-memory-base = "0" # Size of the whole physical memory. phys-memory-size = "0" +# Size of the nocache memory region +nocache-memory-size = "0" # Base physical address of the kernel image. kernel-base-paddr = "0" # Base virtual address of the kernel image. diff --git a/modules/axconfig/src/lib.rs b/modules/axconfig/src/lib.rs index 8705b803fe..4e4fca35fd 100644 --- a/modules/axconfig/src/lib.rs +++ b/modules/axconfig/src/lib.rs @@ -16,4 +16,4 @@ mod config { pub use config::*; /// End address of the whole physical memory. -pub const PHYS_MEMORY_END: usize = PHYS_MEMORY_BASE + PHYS_MEMORY_SIZE; +pub const PHYS_MEMORY_END: usize = PHYS_MEMORY_BASE + PHYS_MEMORY_SIZE - NOCACHE_MEMORY_SIZE; diff --git a/modules/axdriver/Cargo.toml b/modules/axdriver/Cargo.toml index 87280a27ee..ff2a7d538d 100644 --- a/modules/axdriver/Cargo.toml +++ b/modules/axdriver/Cargo.toml @@ -16,6 +16,7 @@ bus-pci = ["dep:driver_pci", "dep:axhal", "dep:axconfig"] net = ["driver_net"] block = ["driver_block"] display = ["driver_display"] +usb_host = ["dep:driver_usb"] # Enabled by features `virtio-*` virtio = ["driver_virtio", "dep:axalloc", "dep:axhal", "dep:axconfig"] @@ -27,6 +28,8 @@ virtio-gpu = ["display", "virtio", "driver_virtio/gpu"] ramdisk = ["block", "driver_block/ramdisk"] bcm2835-sdhci = ["block", "driver_block/bcm2835-sdhci"] ixgbe = ["net", "driver_net/ixgbe", "dep:axalloc", "dep:axhal"] +phytium-xhci = ["usb_host", "bus-pci","driver_usb/phytium-xhci","dep:axalloc" ] +phytium-pci = ["driver_pci/phytium-pci"] # more devices example: e1000 = ["net", "driver_net/e1000"] default = ["bus-mmio"] @@ -43,3 +46,4 @@ driver_virtio = { path = "../../crates/driver_virtio", optional = true } axalloc = { path = "../axalloc", optional = true } axhal = { path = "../axhal", optional = true } axconfig = { path = "../axconfig", optional = true } +driver_usb = {path = "../../crates/driver_usb",optional = true} diff --git a/modules/axdriver/build.rs b/modules/axdriver/build.rs index d418d5ec19..ad395a8936 100644 --- a/modules/axdriver/build.rs +++ b/modules/axdriver/build.rs @@ -1,6 +1,7 @@ -const NET_DEV_FEATURES: &[&str] = &["ixgbe", "virtio-net"]; +const NET_DEV_FEATURES: &[&str] = &["ixgbe", "virtio-net", "phytium"]; const BLOCK_DEV_FEATURES: &[&str] = &["ramdisk", "bcm2835-sdhci", "virtio-blk"]; const DISPLAY_DEV_FEATURES: &[&str] = &["virtio-gpu"]; +const USB_HOST_DEV_FEATURES: &[&str] = &["phytium-xhci"]; fn has_feature(feature: &str) -> bool { std::env::var(format!( @@ -17,10 +18,17 @@ fn enable_cfg(key: &str, value: &str) { fn main() { if has_feature("bus-pci") { enable_cfg("bus", "pci"); - } else { - enable_cfg("bus", "mmio"); } + // if has_feature("bus-mmio") { + // enable_cfg("bus", "mmio"); + // } + + // if #[cfg(platform = "aarch64-phytium-pi"{ + // if has_feature(feature) + // enable_cfg("bus", "mmio"); + // } + // Generate cfgs like `net_dev="virtio-net"`. if `dyn` is not enabled, only one device is // selected for each device category. If no device is selected, `dummy` is selected. let is_dyn = has_feature("dyn"); @@ -28,6 +36,7 @@ fn main() { ("net", NET_DEV_FEATURES), ("block", BLOCK_DEV_FEATURES), ("display", DISPLAY_DEV_FEATURES), + ("usb_host", USB_HOST_DEV_FEATURES), ] { if !has_feature(dev_kind) { continue; diff --git a/modules/axdriver/src/bus/mmio.rs b/modules/axdriver/src/bus/mmio.rs index 5a3573a6a6..4a400c4d86 100644 --- a/modules/axdriver/src/bus/mmio.rs +++ b/modules/axdriver/src/bus/mmio.rs @@ -4,6 +4,8 @@ use crate::{prelude::*, AllDevices}; impl AllDevices { pub(crate) fn probe_bus_devices(&mut self) { // TODO: parse device tree + //don't use cfg_if at here ramdomly!!!! might cause lld error + //waste time: 2days #[cfg(feature = "virtio")] for reg in axconfig::VIRTIO_MMIO_REGIONS { for_each_drivers!(type Driver, { diff --git a/modules/axdriver/src/bus/pci.rs b/modules/axdriver/src/bus/pci.rs index f47b2757e6..4c43039ede 100644 --- a/modules/axdriver/src/bus/pci.rs +++ b/modules/axdriver/src/bus/pci.rs @@ -1,122 +1,32 @@ use crate::{prelude::*, AllDevices}; use axhal::mem::phys_to_virt; -use driver_pci::{ - BarInfo, Cam, Command, DeviceFunction, HeaderType, MemoryBarType, PciRangeAllocator, PciRoot, -}; - -const PCI_BAR_NUM: u8 = 6; - -fn config_pci_device( - root: &mut PciRoot, - bdf: DeviceFunction, - allocator: &mut Option, -) -> DevResult { - let mut bar = 0; - while bar < PCI_BAR_NUM { - let info = root.bar_info(bdf, bar).unwrap(); - if let BarInfo::Memory { - address_type, - address, - size, - .. - } = info - { - // if the BAR address is not assigned, call the allocator and assign it. - if size > 0 && address == 0 { - let new_addr = allocator - .as_mut() - .expect("No memory ranges available for PCI BARs!") - .alloc(size as _) - .ok_or(DevError::NoMemory)?; - if address_type == MemoryBarType::Width32 { - root.set_bar_32(bdf, bar, new_addr as _); - } else if address_type == MemoryBarType::Width64 { - root.set_bar_64(bdf, bar, new_addr); - } - } - } - - // read the BAR info again after assignment. - let info = root.bar_info(bdf, bar).unwrap(); - match info { - BarInfo::IO { address, size } => { - if address > 0 && size > 0 { - debug!(" BAR {}: IO [{:#x}, {:#x})", bar, address, address + size); - } - } - BarInfo::Memory { - address_type, - prefetchable, - address, - size, - } => { - if address > 0 && size > 0 { - debug!( - " BAR {}: MEM [{:#x}, {:#x}){}{}", - bar, - address, - address + size as u64, - if address_type == MemoryBarType::Width64 { - " 64bit" - } else { - "" - }, - if prefetchable { " pref" } else { "" }, - ); - } - } - } - - bar += 1; - if info.takes_two_entries() { - bar += 1; - } - } - - // Enable the device. - let (_status, cmd) = root.get_status_command(bdf); - root.set_command( - bdf, - cmd | Command::IO_SPACE | Command::MEMORY_SPACE | Command::BUS_MASTER, - ); - Ok(()) -} +use driver_pci::*; impl AllDevices { pub(crate) fn probe_bus_devices(&mut self) { let base_vaddr = phys_to_virt(axconfig::PCI_ECAM_BASE.into()); - let mut root = unsafe { PciRoot::new(base_vaddr.as_mut_ptr(), Cam::Ecam) }; - - // PCI 32-bit MMIO space - let mut allocator = axconfig::PCI_RANGES - .get(1) - .map(|range| PciRangeAllocator::new(range.0 as u64, range.1 as u64)); - - for bus in 0..=axconfig::PCI_BUS_END as u8 { - for (bdf, dev_info) in root.enumerate_bus(bus) { - debug!("PCI {}: {}", bdf, dev_info); - if dev_info.header_type != HeaderType::Standard { - continue; - } - match config_pci_device(&mut root, bdf, &mut allocator) { - Ok(_) => for_each_drivers!(type Driver, { - if let Some(dev) = Driver::probe_pci(&mut root, bdf, &dev_info) { - info!( - "registered a new {:?} device at {}: {:?}", - dev.device_type(), - bdf, - dev.device_name(), - ); - self.add_device(dev); - continue; // skip to the next device - } - }), - Err(e) => warn!( - "failed to enable PCI device at {}({}): {:?}", - bdf, dev_info, e - ), - } - } + let pci_range = axconfig::PCI_RANGES.get(1).unwrap(); + let mut root = driver_pci::new_root_complex( + base_vaddr.as_usize(), + pci_range.0 as u64..pci_range.1 as u64, + ); + + debug!("probing in pci.rs!"); + + for (bdf, dev_info, cfg) in root.enumerate_bus() { + debug!("PCI {}: {}", bdf, dev_info); + for_each_drivers!(type Driver,{ + if let Some(dev) = Driver::probe_pci(&mut root, bdf.clone(), &dev_info, &cfg) { + info!( + "registered a new {:?} device at {}: {:?}", + dev.device_type(), + bdf, + dev.device_name(), + ); + self.add_device(dev); + continue; // skip to the next device + } + }); } } } diff --git a/modules/axdriver/src/drivers.rs b/modules/axdriver/src/drivers.rs index 5ee6dcacdb..ba82a2f0c4 100644 --- a/modules/axdriver/src/drivers.rs +++ b/modules/axdriver/src/drivers.rs @@ -3,13 +3,16 @@ #![allow(unused_imports)] use crate::AxDeviceEnum; +use axalloc::{global_allocator, global_no_cache_allocator}; +use cfg_if::cfg_if; use driver_common::DeviceType; +use driver_pci::device_types::{self, PCI_CLASS_NETWORK_ETHERNET}; #[cfg(feature = "virtio")] use crate::virtio::{self, VirtIoDevMeta}; #[cfg(feature = "bus-pci")] -use driver_pci::{DeviceFunction, DeviceFunctionInfo, PciRoot}; +use driver_pci::{types::ConfigSpace, DeviceFunction, DeviceFunctionInfo, PciAddress, PciRoot}; pub use super::dummy::*; @@ -28,7 +31,10 @@ pub trait DriverProbe { _root: &mut PciRoot, _bdf: DeviceFunction, _dev_info: &DeviceFunctionInfo, + _config: &ConfigSpace, ) -> Option { + use driver_pci::types::ConfigSpace; + None } } @@ -81,6 +87,30 @@ cfg_if::cfg_if! { } } +//todo maybe we should re arrange these code +cfg_if::cfg_if! { + if #[cfg(usb_host_dev = "phytium-xhci")] { + use axalloc::GlobalNoCacheAllocator; + pub struct VL805Driver; + register_usb_host_driver!(VL805Driver, driver_usb::host::VL805); + // use driver_usb::host::xhci::vl805::VL805; + + impl DriverProbe for VL805Driver { + fn probe_pci( + root: &mut PciRoot, + bdf: DeviceFunction, + dev_info: &DeviceFunctionInfo, + cfg: &ConfigSpace, + ) -> Option { + debug!("xhci probing!(actualy do nothing now)"); + + // VL805::probe_pci(cfg, global_no_cache_allocator()).map(|d| AxDeviceEnum::from_usb_host(d)) + None + } + } + } +} + cfg_if::cfg_if! { if #[cfg(net_dev = "ixgbe")] { use crate::ixgbe::IxgbeHalImpl; @@ -92,6 +122,7 @@ cfg_if::cfg_if! { root: &mut driver_pci::PciRoot, bdf: driver_pci::DeviceFunction, dev_info: &driver_pci::DeviceFunctionInfo, + _cfg: &ConfigSpace ) -> Option { use crate::ixgbe::IxgbeHalImpl; use driver_net::ixgbe::{INTEL_82599, INTEL_VEND, IxgbeNic}; @@ -105,7 +136,19 @@ cfg_if::cfg_if! { const QS: usize = 1024; let bar_info = root.bar_info(bdf, 0).unwrap(); match bar_info { - driver_pci::BarInfo::Memory { + driver_pci::BarInfo::Memory64 { + address, + size, + .. + } => { + let ixgbe_nic = IxgbeNic::::init( + phys_to_virt((address as usize).into()).into(), + size as usize + ) + .expect("failed to initialize ixgbe device"); + return Some(AxDeviceEnum::from_net(ixgbe_nic)); + } + driver_pci::BarInfo::Memory32 { address, size, .. @@ -117,7 +160,7 @@ cfg_if::cfg_if! { .expect("failed to initialize ixgbe device"); return Some(AxDeviceEnum::from_net(ixgbe_nic)); } - driver_pci::BarInfo::IO { .. } => { + driver_pci::BarInfo::Io { .. } => { error!("ixgbe: BAR0 is of I/O type"); return None; } diff --git a/modules/axdriver/src/lib.rs b/modules/axdriver/src/lib.rs index 05b5d98524..fc47b65faf 100644 --- a/modules/axdriver/src/lib.rs +++ b/modules/axdriver/src/lib.rs @@ -90,6 +90,8 @@ pub use self::structs::AxBlockDevice; pub use self::structs::AxDisplayDevice; #[cfg(feature = "net")] pub use self::structs::AxNetDevice; +#[cfg(feature = "usb_host")] +pub use self::structs::AxUSBHostDevice; /// A structure that contains all device drivers, organized by their category. #[derive(Default)] @@ -103,6 +105,8 @@ pub struct AllDevices { /// All graphics device drivers. #[cfg(feature = "display")] pub display: AxDeviceContainer, + #[cfg(feature = "usb_host")] + pub usb_host: AxDeviceContainer, } impl AllDevices { @@ -143,6 +147,8 @@ impl AllDevices { AxDeviceEnum::Block(dev) => self.block.push(dev), #[cfg(feature = "display")] AxDeviceEnum::Display(dev) => self.display.push(dev), + #[cfg(feature = "usb_host")] + AxDeviceEnum::USBHost(dev) => self.usb_host.push(dev), } } } @@ -179,6 +185,14 @@ pub fn init_drivers() -> AllDevices { debug!(" graphics device {}: {:?}", i, dev.device_name()); } } + #[cfg(feature = "usb_host")] + { + debug!("number of usb host controller: {}", all_devs.usb_host.len()); + for (i, dev) in all_devs.usb_host.iter().enumerate() { + assert_eq!(dev.device_type(), DeviceType::USBHost); + debug!(" usb host controller {}: {:?}", i, dev.device_name()); + } + } all_devs } diff --git a/modules/axdriver/src/macros.rs b/modules/axdriver/src/macros.rs index b90e813e70..0962c68631 100644 --- a/modules/axdriver/src/macros.rs +++ b/modules/axdriver/src/macros.rs @@ -26,6 +26,14 @@ macro_rules! register_display_driver { }; } +macro_rules! register_usb_host_driver { + ($driver_type:ty, $device_type:ty) => { + /// The unified type of the NIC devices. + #[cfg(not(feature = "dyn"))] + pub type AxUSBHostDevice = $device_type; + }; +} + macro_rules! for_each_drivers { (type $drv_type:ident, $code:block) => {{ #[allow(unused_imports)] @@ -64,5 +72,10 @@ macro_rules! for_each_drivers { type $drv_type = crate::drivers::IxgbeDriver; $code } + #[cfg(usb_host_dev = "phytium-xhci")] + { + type $drv_type = crate::drivers::VL805Driver; //TODO FIXIT + $code + } }}; } diff --git a/modules/axdriver/src/structs/dyn.rs b/modules/axdriver/src/structs/dyn.rs index c4d04cb97f..3c0d49a410 100644 --- a/modules/axdriver/src/structs/dyn.rs +++ b/modules/axdriver/src/structs/dyn.rs @@ -12,6 +12,9 @@ pub type AxBlockDevice = Box; /// The unified type of the graphics display devices. #[cfg(feature = "display")] pub type AxDisplayDevice = Box; +#[cfg(feature = "usb_host")] +/// The unified type of the usb host devices. +pub type AxUSBHostDevice = Box; impl super::AxDeviceEnum { /// Constructs a network device. @@ -31,6 +34,11 @@ impl super::AxDeviceEnum { pub fn from_display(dev: impl DisplayDriverOps + 'static) -> Self { Self::Display(Box::new(dev)) } + /// Constructs a display device. + #[cfg(feature = "usb_host")] + pub fn from_display(dev: impl XhciDriverOps + 'static) -> Self { + Self::USBHost(Box::new(dev)) + } } /// A structure that contains all device drivers of a certain category. diff --git a/modules/axdriver/src/structs/mod.rs b/modules/axdriver/src/structs/mod.rs index d373100fb9..8cf14fe2af 100644 --- a/modules/axdriver/src/structs/mod.rs +++ b/modules/axdriver/src/structs/mod.rs @@ -18,6 +18,9 @@ pub enum AxDeviceEnum { /// Graphic display device. #[cfg(feature = "display")] Display(AxDisplayDevice), + /// USB host controller. + #[cfg(feature = "usb_host")] + USBHost(AxUSBHostDevice), } impl BaseDriverOps for AxDeviceEnum { @@ -31,6 +34,8 @@ impl BaseDriverOps for AxDeviceEnum { Self::Block(_) => DeviceType::Block, #[cfg(feature = "display")] Self::Display(_) => DeviceType::Display, + #[cfg(feature = "usb_host")] + Self::USBHost(_) => DeviceType::USBHost, _ => unreachable!(), } } @@ -45,6 +50,8 @@ impl BaseDriverOps for AxDeviceEnum { Self::Block(dev) => dev.device_name(), #[cfg(feature = "display")] Self::Display(dev) => dev.device_name(), + #[cfg(feature = "usb_host")] + Self::USBHost(dev) => dev.device_name(), _ => unreachable!(), } } diff --git a/modules/axdriver/src/structs/static.rs b/modules/axdriver/src/structs/static.rs index 9adff2c240..1668ab886a 100644 --- a/modules/axdriver/src/structs/static.rs +++ b/modules/axdriver/src/structs/static.rs @@ -4,6 +4,8 @@ pub use crate::drivers::AxBlockDevice; pub use crate::drivers::AxDisplayDevice; #[cfg(feature = "net")] pub use crate::drivers::AxNetDevice; +#[cfg(feature = "usb_host")] +pub use crate::drivers::AxUSBHostDevice; impl super::AxDeviceEnum { /// Constructs a network device. @@ -23,6 +25,12 @@ impl super::AxDeviceEnum { pub const fn from_display(dev: AxDisplayDevice) -> Self { Self::Display(dev) } + + /// Constructs a usb host device. + #[cfg(feature = "usb_host")] + pub const fn from_usb_host(dev: AxUSBHostDevice) -> Self { + Self::USBHost(dev) + } } /// A structure that contains all device drivers of a certain category. diff --git a/modules/axhal/src/arch/aarch64/mod.rs b/modules/axhal/src/arch/aarch64/mod.rs index 46d3fc7acb..7f45bd6336 100644 --- a/modules/axhal/src/arch/aarch64/mod.rs +++ b/modules/axhal/src/arch/aarch64/mod.rs @@ -67,6 +67,7 @@ pub unsafe fn write_page_table_root(root_paddr: PhysAddr) { trace!("set page table root: {:#x} => {:#x}", old_root, root_paddr); if old_root != root_paddr { // kernel space page table use TTBR1 (0xffff_0000_0000_0000..0xffff_ffff_ffff_ffff) + TTBR0_EL1.set(root_paddr.as_usize() as _); TTBR1_EL1.set(root_paddr.as_usize() as _); flush_tlb(None); } diff --git a/modules/axhal/src/irq.rs b/modules/axhal/src/irq.rs index 46160d40f1..59c2afa91f 100644 --- a/modules/axhal/src/irq.rs +++ b/modules/axhal/src/irq.rs @@ -17,6 +17,7 @@ pub(crate) fn dispatch_irq_common(irq_num: usize) { trace!("IRQ {}", irq_num); if !IRQ_HANDLER_TABLE.handle(irq_num) { warn!("Unhandled IRQ {}", irq_num); + debug!("Unhandled IRQ {}", irq_num); } } diff --git a/modules/axhal/src/lib.rs b/modules/axhal/src/lib.rs index 9fd27a1b1f..7645dda810 100644 --- a/modules/axhal/src/lib.rs +++ b/modules/axhal/src/lib.rs @@ -27,10 +27,9 @@ #![no_std] #![feature(asm_const)] #![feature(naked_functions)] -#![feature(const_maybe_uninit_zeroed)] #![feature(const_option)] #![feature(doc_auto_cfg)] - +#![allow(warnings)] #[allow(unused_imports)] #[macro_use] extern crate log; diff --git a/modules/axhal/src/mem.rs b/modules/axhal/src/mem.rs index ee96c4dc5d..48dfc07bee 100644 --- a/modules/axhal/src/mem.rs +++ b/modules/axhal/src/mem.rs @@ -129,8 +129,9 @@ pub(crate) fn default_mmio_regions() -> impl Iterator { /// Returns the default free memory regions (kernel image end to physical memory end). #[allow(dead_code)] pub(crate) fn default_free_regions() -> impl Iterator { - let start = virt_to_phys((_ekernel as usize).into()).align_up_4k(); - let end = PhysAddr::from(axconfig::PHYS_MEMORY_END).align_down_4k(); + let start = VirtAddr::from(_ekernel as usize + axconfig::NOCACHE_MEMORY_SIZE).align_up_4k(); + let start = virt_to_phys(start); + let end = PhysAddr::from(axconfig::PHYS_MEMORY_END); core::iter::once(MemRegion { paddr: start, size: end.as_usize() - start.as_usize(), @@ -139,6 +140,20 @@ pub(crate) fn default_free_regions() -> impl Iterator { }) } +/// Returns the default free memory regions (kernel image end to physical memory end). +#[allow(dead_code)] +pub(crate) fn default_nocache_regions() -> impl Iterator { + let start = VirtAddr::from(_ekernel as usize).align_up_4k(); + let start = virt_to_phys(start); + + core::iter::once(MemRegion { + paddr: start, + size: axconfig::NOCACHE_MEMORY_SIZE, + flags: MemRegionFlags::DEVICE | MemRegionFlags::READ | MemRegionFlags::WRITE, + name: "nocache memory", + }) +} + /// Fills the `.bss` section with zeros. #[allow(dead_code)] pub(crate) fn clear_bss() { diff --git a/modules/axhal/src/platform/aarch64_common/boot.rs b/modules/axhal/src/platform/aarch64_common/boot.rs index a944e18116..b3010cc8cb 100644 --- a/modules/axhal/src/platform/aarch64_common/boot.rs +++ b/modules/axhal/src/platform/aarch64_common/boot.rs @@ -1,4 +1,5 @@ use aarch64_cpu::{asm, asm::barrier, registers::*}; +use core::ptr; use memory_addr::PhysAddr; use page_table_entry::aarch64::{MemAttr, A64PTE}; use tock_registers::interfaces::{ReadWriteable, Readable, Writeable}; @@ -109,17 +110,23 @@ unsafe extern "C" fn _start() -> ! { // X0 = dtb core::arch::asm!(" mrs x19, mpidr_el1 + bl {debug} // put debug a and x19, x19, #0xffffff // get current CPU id mov x20, x0 // save DTB pointer adrp x8, {boot_stack} // setup boot stack add x8, x8, {boot_stack_size} mov sp, x8 + bl {debug} bl {switch_to_el1} // switch to EL1 + bl {debug} bl {init_boot_page_table} + bl {debug} bl {init_mmu} // setup MMU + bl {debug_paged} bl {enable_fp} // enable fp/neon + bl {debug_paged} mov x8, {phys_virt_offset} // set SP to the high address add sp, sp, x8 @@ -129,6 +136,9 @@ unsafe extern "C" fn _start() -> ! { ldr x8, ={entry} blr x8 b .", + // TODO consider add some light? + debug = sym put_debug, + debug_paged = sym put_debug_paged, switch_to_el1 = sym switch_to_el1, init_boot_page_table = sym init_boot_page_table, init_mmu = sym init_mmu, @@ -141,6 +151,24 @@ unsafe extern "C" fn _start() -> ! { ) } +#[cfg(all(target_arch = "aarch64", platform_family = "aarch64-phytium-pi"))] +#[no_mangle] +unsafe extern "C" fn put_debug() { + let state = (0x2800D018 as usize) as *mut u8; + let put = (0x2800D000 as usize) as *mut u8; + while (ptr::read_volatile(state) & (0x20 as u8)) != 0 {} + *put = b'a'; +} + +#[cfg(all(target_arch = "aarch64", platform_family = "aarch64-phytium-pi"))] +#[no_mangle] +unsafe extern "C" fn put_debug_paged() { + let state = (0xFFFF00002800D018 as usize) as *mut u8; + let put = (0xFFFF00002800D000 as usize) as *mut u8; + while (ptr::read_volatile(state) & (0x20 as u8)) != 0 {} + *put = b'a'; +} + /// The earliest entry point for the secondary CPUs. #[cfg(feature = "smp")] #[naked] diff --git a/modules/axhal/src/platform/aarch64_common/mod.rs b/modules/axhal/src/platform/aarch64_common/mod.rs index c585541fe8..85ace61042 100644 --- a/modules/axhal/src/platform/aarch64_common/mod.rs +++ b/modules/axhal/src/platform/aarch64_common/mod.rs @@ -1,7 +1,10 @@ mod boot; pub mod generic_timer; -#[cfg(not(platform_family = "aarch64-raspi"))] +#[cfg(not(any( + all(platform_family = "aarch64-raspi"), + all(platform_family = "aarch64-phytium-pi"), +)))] pub mod psci; #[cfg(feature = "irq")] diff --git a/modules/axhal/src/platform/aarch64_phytium_pi/mem.rs b/modules/axhal/src/platform/aarch64_phytium_pi/mem.rs new file mode 100644 index 0000000000..75e6fc3dd7 --- /dev/null +++ b/modules/axhal/src/platform/aarch64_phytium_pi/mem.rs @@ -0,0 +1,47 @@ +use crate::mem::*; +use page_table_entry::{aarch64::A64PTE, GenericPTE, MappingFlags}; + +/// Returns platform-specific memory regions. +pub(crate) fn platform_regions() -> impl Iterator { + core::iter::once(MemRegion { + paddr: 0x0.into(), + size: 0x1000, + flags: MemRegionFlags::RESERVED | MemRegionFlags::READ | MemRegionFlags::WRITE, + name: "spintable", + }) + .chain(crate::mem::default_nocache_regions()) + .chain(crate::mem::default_free_regions()) + .chain(crate::mem::default_mmio_regions()) +} + +pub(crate) unsafe fn init_boot_page_table( + boot_pt_l0: &mut [A64PTE; 512], + boot_pt_l1: &mut [A64PTE; 512], +) { + // 0x0000_0000_0000 ~ 0x0080_0000_0000, table + boot_pt_l0[0] = A64PTE::new_table(PhysAddr::from(boot_pt_l1.as_ptr() as usize)); + // 0x0000_0000_0000..0x0000_8000_0000, 1G block, device memory + boot_pt_l1[0] = A64PTE::new_page( + PhysAddr::from(0), + MappingFlags::READ | MappingFlags::WRITE | MappingFlags::DEVICE, + true, + ); + // // 0x0000_4000_0000..0x0000_8000_0000, 1G block, normal memory + // boot_pt_l1[1] = A64PTE::new_page( + // PhysAddr::from(0x4000_0000), + // MappingFlags::READ | MappingFlags::WRITE | MappingFlags::EXECUTE, + // true, + // ); + // 0x0000_8000_0000..0x0000_C000_0000, 2G block, normal memory + boot_pt_l1[2] = A64PTE::new_page( + PhysAddr::from(0x8000_0000), + MappingFlags::READ | MappingFlags::WRITE | MappingFlags::EXECUTE, + true, + ); + // 0x0000_C000_0000..0x0001_0000_0000, 1G block, DEVICE memory + // boot_pt_l1[3] = A64PTE::new_page( + // PhysAddr::from(0xc000_0000), + // MappingFlags::READ | MappingFlags::WRITE | MappingFlags::DEVICE, + // true, + // ); +} diff --git a/modules/axhal/src/platform/aarch64_phytium_pi/mod.rs b/modules/axhal/src/platform/aarch64_phytium_pi/mod.rs new file mode 100644 index 0000000000..7e45df50d7 --- /dev/null +++ b/modules/axhal/src/platform/aarch64_phytium_pi/mod.rs @@ -0,0 +1,94 @@ +pub mod mem; +use core::ptr; + +#[cfg(feature = "smp")] +pub mod mp; + +#[cfg(feature = "irq")] +pub mod irq { + pub use crate::platform::aarch64_common::gic::*; +} + +pub mod console { + pub use crate::platform::aarch64_common::pl011::*; +} + +pub mod time { + pub use crate::platform::aarch64_common::generic_timer::*; +} + +pub mod misc { + pub fn terminate() -> ! { + info!("Shutting down..."); + loop { + crate::arch::halt(); + } + } +} + +extern "C" { + fn exception_vector_base(); + fn rust_main(cpu_id: usize, dtb: usize); + #[cfg(feature = "smp")] + fn rust_main_secondary(cpu_id: usize); +} + +pub(crate) unsafe extern "C" fn rust_entry(cpu_id: usize, dtb: usize) { + crate::mem::clear_bss(); + put_debug2(); + crate::arch::set_exception_vector_base(exception_vector_base as usize); + put_debug2(); + crate::arch::write_page_table_root0(0.into()); // disable low address access + put_debug_paged2(); + crate::cpu::init_primary(cpu_id); + put_debug_paged2(); + super::aarch64_common::pl011::init_early(); + put_debug_paged2(); + super::aarch64_common::generic_timer::init_early(); + put_debug_paged2(); + rust_main(cpu_id, dtb); +} + +#[cfg(all(target_arch = "aarch64", platform_family = "aarch64-phytium-pi"))] +#[no_mangle] +unsafe extern "C" fn put_debug2() { + let state = (0x2800D018 as usize) as *mut u8; + let put = (0x2800D000 as usize) as *mut u8; + while (ptr::read_volatile(state) & (0x20 as u8)) != 0 {} + *put = b'a'; +} + +#[cfg(all(target_arch = "aarch64", platform_family = "aarch64-phytium-pi"))] +#[no_mangle] +unsafe extern "C" fn put_debug_paged2() { + let state = (0xFFFF00002800D018 as usize) as *mut u8; + let put = (0xFFFF00002800D000 as usize) as *mut u8; + while (ptr::read_volatile(state) & (0x20 as u8)) != 0 {} + *put = b'a'; +} + +#[cfg(feature = "smp")] +pub(crate) unsafe extern "C" fn rust_entry_secondary(cpu_id: usize) { + crate::arch::set_exception_vector_base(exception_vector_base as usize); + crate::arch::write_page_table_root0(0.into()); // disable low address access + crate::cpu::init_secondary(cpu_id); + rust_main_secondary(cpu_id); +} + +/// Initializes the platform devices for the primary CPU. +/// +/// For example, the interrupt controller and the timer. +pub fn platform_init() { + #[cfg(feature = "irq")] + super::aarch64_common::gic::init_primary(); + super::aarch64_common::generic_timer::init_percpu(); + super::aarch64_common::pl011::init(); +} + +/// Initializes the platform devices for secondary CPUs. +#[cfg(feature = "smp")] +pub fn platform_init_secondary() { + #[cfg(feature = "irq")] + super::aarch64_common::gic::init_secondary(); + super::aarch64_common::generic_timer::init_percpu(); +} diff --git a/modules/axhal/src/platform/aarch64_phytium_pi/mp.rs b/modules/axhal/src/platform/aarch64_phytium_pi/mp.rs new file mode 100644 index 0000000000..23549c01f1 --- /dev/null +++ b/modules/axhal/src/platform/aarch64_phytium_pi/mp.rs @@ -0,0 +1,49 @@ +use crate::mem::{phys_to_virt, virt_to_phys, PhysAddr, VirtAddr}; + +static mut SECONDARY_STACK_TOP: usize = 0; + +extern "C" { + fn _start_secondary(); +} + +#[naked] +#[link_section = ".text.boot"] +unsafe extern "C" fn modify_stack_and_start() { + core::arch::asm!(" + ldr x21, ={secondary_boot_stack} // the secondary CPU hasn't set the TTBR1 + mov x8, {phys_virt_offset} // minus the offset to get the phys addr of the boot stack + sub x21, x21, x8 + ldr x21, [x21] + mov x0, x21 // x0 will be set to SP in the beginning of _start_secondary + b _start_secondary", + secondary_boot_stack = sym SECONDARY_STACK_TOP, + phys_virt_offset = const axconfig::PHYS_VIRT_OFFSET, + options(noreturn) + ); +} + +pub static CPU_SPIN_TABLE: [PhysAddr; 4] = [ + PhysAddr::from(0xd8), + PhysAddr::from(0xe0), + PhysAddr::from(0xe8), + PhysAddr::from(0xf0), +]; + +/// Starts the given secondary CPU with its boot stack. +pub fn start_secondary_cpu(cpu_id: usize, stack_top: PhysAddr) { + let entry_paddr = virt_to_phys(VirtAddr::from(modify_stack_and_start as usize)).as_usize(); + unsafe { + // set the boot code address of the given secondary CPU + let spintable_vaddr = phys_to_virt(CPU_SPIN_TABLE[cpu_id]); + let release_ptr = spintable_vaddr.as_mut_ptr() as *mut usize; + release_ptr.write_volatile(entry_paddr); + crate::arch::flush_dcache_line(spintable_vaddr); + + // set the boot stack of the given secondary CPU + SECONDARY_STACK_TOP = stack_top.as_usize(); + crate::arch::flush_dcache_line(VirtAddr::from( + (&SECONDARY_STACK_TOP as *const usize) as usize, + )); + } + aarch64_cpu::asm::sev(); +} diff --git a/modules/axhal/src/platform/aarch64_raspi/mem.rs b/modules/axhal/src/platform/aarch64_raspi/mem.rs index 7c426e08f9..0e838e1a16 100644 --- a/modules/axhal/src/platform/aarch64_raspi/mem.rs +++ b/modules/axhal/src/platform/aarch64_raspi/mem.rs @@ -9,6 +9,7 @@ pub(crate) fn platform_regions() -> impl Iterator { flags: MemRegionFlags::RESERVED | MemRegionFlags::READ | MemRegionFlags::WRITE, name: "spintable", }) + .chain(crate::mem::default_nocache_regions()) .chain(crate::mem::default_free_regions()) .chain(crate::mem::default_mmio_regions()) } diff --git a/modules/axhal/src/platform/mod.rs b/modules/axhal/src/platform/mod.rs index a39151c47f..8923b5dec2 100644 --- a/modules/axhal/src/platform/mod.rs +++ b/modules/axhal/src/platform/mod.rs @@ -19,6 +19,9 @@ cfg_if::cfg_if! { } else if #[cfg(all(target_arch = "aarch64", platform_family = "aarch64-raspi"))] { mod aarch64_raspi; pub use self::aarch64_raspi::*; + } else if #[cfg(all(target_arch = "aarch64", platform_family = "aarch64-phytium-pi"))] { + mod aarch64_phytium_pi; + pub use self::aarch64_phytium_pi::*; } else if #[cfg(all(target_arch = "aarch64", platform_family = "aarch64-bsta1000b"))] { mod aarch64_bsta1000b; pub use self::aarch64_bsta1000b::*; diff --git a/modules/axruntime/Cargo.toml b/modules/axruntime/Cargo.toml index ccd000b1d4..7be2028b9d 100644 --- a/modules/axruntime/Cargo.toml +++ b/modules/axruntime/Cargo.toml @@ -22,6 +22,8 @@ multitask = ["axtask/multitask"] fs = ["axdriver", "axfs"] net = ["axdriver", "axnet"] display = ["axdriver", "axdisplay"] +usb = ["axdriver"] + [dependencies] axhal = { path = "../axhal" } diff --git a/modules/axruntime/src/lib.rs b/modules/axruntime/src/lib.rs index a62c3055cb..81928c2543 100644 --- a/modules/axruntime/src/lib.rs +++ b/modules/axruntime/src/lib.rs @@ -21,6 +21,7 @@ #[macro_use] extern crate axlog; +use core::ptr; #[cfg(all(target_os = "none", not(test)))] mod lang_items; @@ -92,6 +93,13 @@ fn is_init_ok() -> bool { INITED_CPUS.load(Ordering::Acquire) == axconfig::SMP } +unsafe extern "C" fn put_debug_paged3() { + let state = (0xFFFF00002800D018 as usize) as *mut u8; + let put = (0xFFFF00002800D000 as usize) as *mut u8; + while (ptr::read_volatile(state) & (0x20 as u8)) != 0 {} + *put = b'c'; +} + /// The main entry point of the ArceOS runtime. /// /// It is called from the bootstrapping code in [axhal]. `cpu_id` is the ID of @@ -103,7 +111,8 @@ fn is_init_ok() -> bool { /// and the secondary CPUs call [`rust_main_secondary`]. #[cfg_attr(not(test), no_mangle)] pub extern "C" fn rust_main(cpu_id: usize, dtb: usize) -> ! { - ax_println!("{}", LOGO); + // ax_println!("{}", LOGO); + unsafe { put_debug_paged3() } ax_println!( "\ arch = {}\n\ @@ -120,13 +129,17 @@ pub extern "C" fn rust_main(cpu_id: usize, dtb: usize) -> ! { option_env!("AX_MODE").unwrap_or(""), option_env!("AX_LOG").unwrap_or(""), ); + unsafe { put_debug_paged3() } axlog::init(); + unsafe { put_debug_paged3() } axlog::set_max_level(option_env!("AX_LOG").unwrap_or("")); // no effect if set `log-level-*` features + unsafe { put_debug_paged3() } info!("Logging is enabled."); info!("Primary CPU {} started, dtb = {:#x}.", cpu_id, dtb); info!("Found physcial memory regions:"); + unsafe { put_debug_paged3() } for r in axhal::mem::memory_regions() { info!( " [{:x?}, {:x?}) {} ({:?})", @@ -146,13 +159,16 @@ pub extern "C" fn rust_main(cpu_id: usize, dtb: usize) -> ! { remap_kernel_memory().expect("remap kernel memoy failed"); } + #[cfg(feature = "alloc")] + init_allocator_no_cache(); + info!("Initialize platform devices..."); axhal::platform_init(); #[cfg(feature = "multitask")] axtask::init_scheduler(); - #[cfg(any(feature = "fs", feature = "net", feature = "display"))] + #[cfg(any(feature = "fs", feature = "net", feature = "display", feature = "usb"))] { #[allow(unused_variables)] let all_devices = axdriver::init_drivers(); @@ -215,23 +231,47 @@ fn init_allocator() { max_region_paddr = r.paddr; } } - for r in memory_regions() { - if r.flags.contains(MemRegionFlags::FREE) && r.paddr == max_region_paddr { - axalloc::global_init(phys_to_virt(r.paddr).as_usize(), r.size); - break; + + { + let mut free_init: (usize, usize) = (0, 0); + for r in memory_regions() { + if r.flags.contains(MemRegionFlags::FREE) && r.paddr == max_region_paddr { + // axalloc::global_init(phys_to_virt(r.paddr).as_usize(), r.size); + free_init = (phys_to_virt(r.paddr).as_usize(), r.size); + break; + } } + axalloc::global_init(free_init); } + for r in memory_regions() { if r.flags.contains(MemRegionFlags::FREE) && r.paddr != max_region_paddr { - axalloc::global_add_memory(phys_to_virt(r.paddr).as_usize(), r.size) + axalloc::global_add_free_memory(phys_to_virt(r.paddr).as_usize(), r.size) .expect("add heap memory region failed"); } } } +#[cfg(feature = "alloc")] +fn init_allocator_no_cache() { + use axhal::mem::memory_regions; + + info!("Initialize global no cache memory allocator..."); + { + let mut nocache_init: (usize, usize) = (0, 0); + + for r in memory_regions() { + if r.name == "nocache memory" { + nocache_init = (r.paddr.as_usize(), r.size); + break; + } + } + axalloc::global_nocache_init(nocache_init); + } +} #[cfg(feature = "paging")] fn remap_kernel_memory() -> Result<(), axhal::paging::PagingError> { - use axhal::mem::{memory_regions, phys_to_virt}; + use axhal::mem::{memory_regions, phys_to_virt, VirtAddr}; use axhal::paging::PageTable; use lazy_init::LazyInit; @@ -240,13 +280,13 @@ fn remap_kernel_memory() -> Result<(), axhal::paging::PagingError> { if axhal::cpu::this_cpu_is_bsp() { let mut kernel_page_table = PageTable::try_new()?; for r in memory_regions() { - kernel_page_table.map_region( - phys_to_virt(r.paddr), - r.paddr, - r.size, - r.flags.into(), - true, - )?; + // mailbox 需要物理地址和虚拟地址一致 + let vaddr = if r.name == "nocache memory" { + VirtAddr::from(r.paddr.as_usize()) + } else { + phys_to_virt(r.paddr) + }; + kernel_page_table.map_region(vaddr, r.paddr, r.size, r.flags.into(), true)?; } KERNEL_PAGE_TABLE.init_by(kernel_page_table); } diff --git a/modules/axruntime/src/trap.rs b/modules/axruntime/src/trap.rs index 5a8a80d384..9317805777 100644 --- a/modules/axruntime/src/trap.rs +++ b/modules/axruntime/src/trap.rs @@ -3,6 +3,7 @@ struct TrapHandlerImpl; #[crate_interface::impl_interface] impl axhal::trap::TrapHandler for TrapHandlerImpl { fn handle_irq(_irq_num: usize) { + debug!("handle irq {}", _irq_num); #[cfg(feature = "irq")] { let guard = kernel_guard::NoPreempt::new(); diff --git a/modules/axtask/src/run_queue.rs b/modules/axtask/src/run_queue.rs index 9c31f4384c..ddf3592cf3 100644 --- a/modules/axtask/src/run_queue.rs +++ b/modules/axtask/src/run_queue.rs @@ -69,11 +69,11 @@ impl AxRunQueue { // locking the run queue. let can_preempt = curr.can_preempt(1); - debug!( - "current task is to be preempted: {}, allow={}", - curr.id_name(), - can_preempt - ); + // debug!( + // "current task is to be preempted: {}, allow={}", + // curr.id_name(), + // can_preempt + // ); if can_preempt { self.resched(true); } else { diff --git a/platforms/aarch64-phytium-pi.toml b/platforms/aarch64-phytium-pi.toml new file mode 100644 index 0000000000..d1377511ae --- /dev/null +++ b/platforms/aarch64-phytium-pi.toml @@ -0,0 +1,80 @@ + # Architecture identifier. + arch = "aarch64" + # Platform identifier. + platform = "aarch64-phytium-pi" + # Platform family. + family = "aarch64-phytium-pi" + + # Base address of the whole physical memory. + phys-memory-base = "0x8000_0000" + # Size of the whole physical memory. + phys-memory-size = "0x8000_0000" # 2G + # Base physical address of the kernel image. + kernel-base-paddr = "0x9010_0000" + # Base virtual address of the kernel image. + kernel-base-vaddr = "0xffff_0000_9010_0000" + # kernel-base-vaddr = "0x9010_0000" + # Linear mapping offset, for quick conversions between physical and virtual + # addresses. + phys-virt-offset = "0xffff_0000_0000_0000" + #phys-virt-offset = "0x0000_0000_0000_0000" + # MMIO regions with format (`base_paddr`, `size`). + mmio-regions = [ + # ["0xFE00_B000", "0x1000"], # mailbox + # ["0xFE20_1000", "0x1000"], # PL011 UART + # ["0xFF84_1000", "0x8000"], # GICv2 + #["0x40000000", "0xfff_ffff"], # pcie ecam + + + # ["0x6_0000_0000", "0x4000_0000"] # pcie control + + + ["0x2800_C000", "0x1000"], # UART 0 + ["0x2800_D000", "0x1000"], # UART 1 + ["0x2800_E000", "0x1000"], # UART 2 + ["0x2800_F000", "0x1000"], # UART 3 + # ["0x32a0_0000", "0x2_0000"], # usb0 + # ["0x32a2_0000", "0x2_0000"], # usb0 + # ["0x3200_C000", "0x2000"], #Ethernet1 + # ["0x3200_E000", "0x2000"], #Ethernet2 + # ["0x3080_0000", "0x8000"], # GICv2 + ["0x3000_0000","0x800_0000"], #other devices + ["0x4000_0000", "0x1000_0000"], # pcie ecam + + ["0x2801_4000", "0x2000"], # MIO0 - I2C + ["0x2801_6000", "0x2000"], # MIO1 - I2C + ["0x2801_8000", "0x2000"], # MIO2 - I2C + ["0x2801_A000", "0x2000"], # MIO3 - I2C + ["0x2801_C000", "0x2000"], # MIO4 - I2C + + ["0x000_2803_4000", "0x1000"], # GPIO0 + ["0x000_2803_5000", "0x1000"], # GPIO1 + ["0x000_2803_6000", "0x1000"], # GPIO2 + ["0x000_2803_7000", "0x1000"], # GPIO3 + ["0x000_2803_8000", "0x1000"], # GPIO4 + ["0x000_2803_9000", "0x1000"], # GPIO5 + + # ["0x6_0000_0000", "0x4000_0000"] # pcie control + ] + virtio-mmio-regions = [] + # UART Address + uart-paddr = "0x2800_D000" + uart-irq = "24" + + # MIO0 I2C + MIO0 = "0x2801_4000" + + # GIC Address + gicc-paddr = "0xFF84_2000" + gicd-paddr = "0xFF84_1000" + + # Base physical address of the PCIe ECAM space. + pci-ecam-base = "0x40000000" + # End PCI bus number. + pci-bus-end = "0x2" + # PCI device memory ranges. + pci-ranges = [["0x58000000", "0x7fffffff"], ["0x6_0000_0000", "0x6_3fff_ffff"]] + + # Size of the nocache memory region + nocache-memory-size = "0x30_0000" + diff --git a/platforms/aarch64-raspi4.toml b/platforms/aarch64-raspi4.toml index f204d1d1a0..21a93c1c4d 100644 --- a/platforms/aarch64-raspi4.toml +++ b/platforms/aarch64-raspi4.toml @@ -18,8 +18,13 @@ kernel-base-vaddr = "0xffff_0000_0008_0000" phys-virt-offset = "0xffff_0000_0000_0000" # MMIO regions with format (`base_paddr`, `size`). mmio-regions = [ + ["0xFE00_B000", "0x1000"], # mailbox ["0xFE20_1000", "0x1000"], # PL011 UART - ["0xFF84_1000", "0x8000"], # GICv2 + ["0xFF84_1000", "0x8000"], # GICv2 + ["0xFD50_0000", "0x20_0000"], # pcie ecam + + + ["0x6_0000_0000", "0x4000_0000"] # pcie control ] virtio-mmio-regions = [] # UART Address @@ -29,3 +34,24 @@ uart-irq = "0x79" # GIC Address gicc-paddr = "0xFF84_2000" gicd-paddr = "0xFF84_1000" + + +# Base physical address of the PCIe ECAM space. +pci-ecam-base = "0xfd50_0000" +# End PCI bus number. +pci-bus-end = "0x2" #? +# PCI device memory ranges. +pci-ranges = [ + # just for known config structure, not real address + # copy from virt.toml or something + # ["0x3ef_f0000", "0x1_0000"], # PIO space + # ["0x1000_0000", "0x2eff_0000"], # 32-bit MMIO space + ["0x00","0x3800000"], + # ["0x6_0000_0000", "0x7_FFFF_FFFF"], # 64-bit MMIO space + ["0x6_0000_0000", "0x6_3fff_ffff"], # xhci space: https://blog.csdn.net/qq_26989627/article/details/122024901 + # ["0xFD50_0000", "0xFD50_9310"], # pcie + # ["0x04","0x7c000000"], +] #TODO: findout ranges + +# Size of the nocache memory region +nocache-memory-size = "0x20_0000" \ No newline at end of file diff --git a/pyvenv.cfg b/pyvenv.cfg new file mode 100644 index 0000000000..648747c658 --- /dev/null +++ b/pyvenv.cfg @@ -0,0 +1,5 @@ +home = /usr/sbin +include-system-site-packages = false +version = 3.11.8 +executable = /usr/bin/python3.11 +command = /usr/sbin/python -m venv /home/dbydd/gitRepos/arceos_experiment diff --git a/scripts/make/phytium-pi.mk b/scripts/make/phytium-pi.mk new file mode 100644 index 0000000000..fece5ba5a7 --- /dev/null +++ b/scripts/make/phytium-pi.mk @@ -0,0 +1,13 @@ +phytium: build + gzip -9 -cvf $(OUT_BIN) > arceos-phytium-pi.bin.gz + mkimage -f tools/phytium-pi/phytium-pi.its arceos-phytiym-pi.itb + @echo 'Built the FIT-uImage arceos-phytium-pi.itb' + +chainboot: build + python tools/phytium-pi/yet_another_uboot_transfer.py /dev/ttyUSB0 115200 $(OUT_BIN) + echo ' ' > minicom_output.log + minicom -D /dev/ttyUSB0 -b 115200 -C minicom_output.log +# python tools/phytium-pi/uboot_transfer.py /dev/ttyUSB0 115200 $(OUT_BIN) +# python tools/phytium-pi/uboot_test_send.py /dev/ttyUSB0 115200 $(OUT_BIN) +#ruby tools/phytium-pi/uboot_transfer.rb /dev/ttyUSB0 115200 $(OUT_BIN) + diff --git a/scripts/make/qemu.mk b/scripts/make/qemu.mk index c8acab2578..39abf2e87f 100644 --- a/scripts/make/qemu.mk +++ b/scripts/make/qemu.mk @@ -45,9 +45,18 @@ qemu_args-$(NET) += \ ifeq ($(NET_DEV), user) qemu_args-$(NET) += -netdev user,id=net0,hostfwd=tcp::5555-:5555,hostfwd=udp::5555-:5555 else ifeq ($(NET_DEV), tap) - qemu_args-$(NET) += -netdev tap,id=net0,ifname=tap0,script=no,downscript=no + qemu_args-$(NET) += -netdev tap,id=net0,script=scripts/net/qemu-ifup.sh,downscript=no,vhost=$(VHOST),vhostforce=$(VHOST) + QEMU := sudo $(QEMU) +else ifeq ($(NET_DEV), bridge) + qemu_args-$(NET) += -netdev bridge,id=net0,br=virbr0 + QEMU := sudo $(QEMU) else - $(error "NET_DEV" must be one of "user" or "tap") + $(error "NET_DEV" must be one of "user", "tap", or "bridge") +endif + +ifneq ($(VFIO_PCI),) + qemu_args-y += --device vfio-pci,host=$(VFIO_PCI) + QEMU := sudo $(QEMU) endif ifeq ($(NET_DUMP), y) diff --git a/scripts/make/raspi4.mk b/scripts/make/raspi4.mk index 66eea697b5..6d8b8c6e27 100644 --- a/scripts/make/raspi4.mk +++ b/scripts/make/raspi4.mk @@ -23,8 +23,10 @@ ifeq ($(BSP),rpi4) OBJDUMP_BINARY = aarch64-none-elf-objdump NM_BINARY = aarch64-none-elf-nm READELF_BINARY = aarch64-none-elf-readelf - OPENOCD_ARG = -f /openocd/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg -f /openocd/rpi4.cfg - JTAG_BOOT_IMAGE = tools/raspi4/X1_JTAG_boot/jtag_boot_rpi4.img + # OPENOCD_ARG = -f /openocd/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg -f /openocd/rpi4.cfg + OPENOCD_ARG = -f /openocd/tcl/interface/jlink.cfg -f /openocd/rpi4.cfg + # JTAG_BOOT_IMAGE = tools/raspi4/X1_JTAG_boot/jtag_boot_rpi4.img + JTAG_BOOT_IMAGE := $(OUT_BIN) RUSTC_MISC_ARGS = -C target-cpu=cortex-a72 endif @@ -33,12 +35,13 @@ EXEC_MINIPUSH = ruby tools/raspi4/common/serial/minipush.rb ##------------------------------------------------------------------------------ ## Dockerization ##------------------------------------------------------------------------------ -DOCKER_CMD = docker run -t --rm -v $(shell pwd):/work/tutorial -w /work/tutorial +DOCKER_CMD = sudo docker run -t --rm -v $(shell pwd):/work/tutorial -w /work/tutorial DOCKER_CMD_INTERACT = $(DOCKER_CMD) -i DOCKER_ARG_DIR_COMMON = -v $(shell pwd)/tools/raspi4/common:/work/common DOCKER_ARG_DIR_JTAG = -v $(shell pwd)/tools/raspi4/X1_JTAG_boot:/work/X1_JTAG_boot DOCKER_ARG_DEV = --privileged -v /dev:/dev -DOCKER_ARG_NET = --network host +# DOCKER_ARG_NET = --network host +DOCKER_ARG_NET = --expose 3333 # DOCKER_IMAGE defined in include file (see top of this file). DOCKER_GDB = $(DOCKER_CMD_INTERACT) $(DOCKER_ARG_NET) $(DOCKER_IMAGE) @@ -48,7 +51,7 @@ ifeq ($(shell uname -s),Linux) DOCKER_CMD_DEV = $(DOCKER_CMD_INTERACT) $(DOCKER_ARG_DEV) DOCKER_CHAINBOOT = $(DOCKER_CMD_DEV) $(DOCKER_ARG_DIR_COMMON) $(DOCKER_IMAGE) DOCKER_JTAGBOOT = $(DOCKER_CMD_DEV) $(DOCKER_ARG_DIR_COMMON) $(DOCKER_ARG_DIR_JTAG) $(DOCKER_IMAGE) - DOCKER_OPENOCD = $(DOCKER_CMD_DEV) $(DOCKER_ARG_NET) $(DOCKER_IMAGE) + DOCKER_OPENOCD = $(DOCKER_CMD_DEV) $(DOCKER_ARG_NET) $(DOCKER_IMAGE) else DOCKER_OPENOCD = echo "Not yet supported on non-Linux systems."; \# endif @@ -88,7 +91,8 @@ openocd: ##------------------------------------------------------------------------------ ## Start GDB session ##------------------------------------------------------------------------------ +KERNEL_ELF := $(patsubst %.bin,%.elf,$(KERNEL_BIN)) gdb: RUSTC_MISC_ARGS += -C debuginfo=2 gdb: $(KERNEL_ELF) - $(call color_header, "Launching GDB") + $(call color_header, "Launching GDB kernel: $(KERNEL_ELF)") @$(DOCKER_GDB) gdb-multiarch -q $(KERNEL_ELF) diff --git a/scripts/net/create-bridge.sh b/scripts/net/create-bridge.sh new file mode 100755 index 0000000000..3ed9cb01c2 --- /dev/null +++ b/scripts/net/create-bridge.sh @@ -0,0 +1,26 @@ +#!/bin/bash +# +# Create virtual bridge for QEMU. +# +# sudo ./create-bridge.sh [virbr0] + +BR=$1 +IP=10.0.2.2 + +if [ -z "$BR" ]; then + BR=virbr0 +fi + +echo "Deleting old virtual bridge $BR ..." + +ip link set dev $BR down 2> /dev/null +brctl delbr $BR 2> /dev/null + +echo "Setting up virtual bridge $BR ..." + +brctl addbr $BR +ip addr add $IP/24 dev $BR +ip link set dev $BR up +brctl show $BR + +ifconfig $BR diff --git a/scripts/net/del-iface.sh b/scripts/net/del-iface.sh new file mode 100755 index 0000000000..7d679b0a2c --- /dev/null +++ b/scripts/net/del-iface.sh @@ -0,0 +1,14 @@ +#!/bin/bash +# +# Delete virtual interface (e.g. virtual bridge). +# +# sudo ./del-iface.sh + +IFACE=$1 + +if [ -z "$IFACE" ]; then + echo "Usage: $0 " + exit 1 +fi + +ip link del $IFACE diff --git a/scripts/net/pci-bind.sh b/scripts/net/pci-bind.sh new file mode 100755 index 0000000000..d2479328bc --- /dev/null +++ b/scripts/net/pci-bind.sh @@ -0,0 +1,23 @@ +#!/bin/bash +# +# Bind a PCI device to the `vfio-pci` driver for PCI passthrough. +# +# Bind: sudo ./pci-bind.sh vfio-pci 02:00.0 +# Unbind: sudo ./pci-bind.sh ixgbe 02:00.0 + +new_drv=$1 +bdf=$2 + +if [ -z "$bdf" -o -z "$new_drv" ]; then + echo "Usage: $0 " + exit 1 +fi + +bdf=0000:$bdf +old_drv=$(readlink /sys/bus/pci/devices/$bdf/driver | awk -F/ '{print $NF}') + +echo "Bind $bdf from $old_drv to $new_drv" + +echo $bdf > /sys/bus/pci/drivers/$old_drv/unbind +echo $new_drv > /sys/bus/pci/devices/$bdf/driver_override +echo $bdf > /sys/bus/pci/drivers/$new_drv/bind diff --git a/scripts/net/qemu-ifup.sh b/scripts/net/qemu-ifup.sh new file mode 100755 index 0000000000..b3e2c21b2b --- /dev/null +++ b/scripts/net/qemu-ifup.sh @@ -0,0 +1,18 @@ +#!/bin/bash +# +# Create a TAP interface and add it to the bridge. +# +# It's used for the startup script of QEMU netdev, DO NOT run it manually. + +br=virbr0 +if [ -n "$1" ]; then + #create a TAP interface; qemu will handle it automatically. + #tunctl -u $(whoami) -t $1 + #start up the TAP interface + ip link set "$1" up + brctl addif $br "$1" + exit +else + echo "Error: no interface specified" + exit 1 +fi diff --git a/scripts/net/qemu-tap-ifdown.sh b/scripts/net/qemu-tap-ifdown.sh deleted file mode 100755 index 12622a36b4..0000000000 --- a/scripts/net/qemu-tap-ifdown.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -HOST_IF=$1 - -if [ -z "$HOST_IF" ]; then - echo "Usage: $0 " - exit 1 -fi - -echo "Deleting tap interface for QEMU" - -ip link del tap0 -sysctl -w net.ipv4.ip_forward=0 -iptables -t nat -D POSTROUTING -s 10.0.2.0/24 -o ${HOST_IF} -j MASQUERADE diff --git a/scripts/net/qemu-tap-ifup.sh b/scripts/net/qemu-tap-ifup.sh deleted file mode 100755 index 1adabc9b88..0000000000 --- a/scripts/net/qemu-tap-ifup.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - -HOST_IF=$1 - -if [ -z "$HOST_IF" ]; then - echo "Usage: $0 " - exit 1 -fi - -echo "Setting up tap interface for QEMU" - -ip tuntap add tap0 mode tap -ip addr add 10.0.2.2/24 dev tap0 -ip link set up dev tap0 - -sysctl -w net.ipv4.ip_forward=1 -iptables -t nat -A POSTROUTING -s 10.0.2.0/24 -o ${HOST_IF} -j MASQUERADE diff --git a/scripts/net/set-ip-forward.sh b/scripts/net/set-ip-forward.sh new file mode 100755 index 0000000000..3ccb8bf507 --- /dev/null +++ b/scripts/net/set-ip-forward.sh @@ -0,0 +1,18 @@ +#!/bin/bash +# +# Setup IP forwarding to allow Internet access in the VM. + +WLAN_IF=$1 +BR=virbr0 +IP_RANGE=10.0.2.0/24 + +if [ -z "$WLAN_IF" ]; then + echo "Usage: $0 " + exit 1 +fi + +sysctl -w net.ipv4.ip_forward=1 + +iptables -t nat -A POSTROUTING -s $IP_RANGE -o $WLAN_IF -j MASQUERADE +iptables -A FORWARD -i $BR -j ACCEPT +iptables -A FORWARD -o $BR -m state --state RELATED,ESTABLISHED -j ACCEPT diff --git a/scripts/net/unset-ip-forward.sh b/scripts/net/unset-ip-forward.sh new file mode 100755 index 0000000000..c361b64438 --- /dev/null +++ b/scripts/net/unset-ip-forward.sh @@ -0,0 +1,18 @@ +#!/bin/bash +# +# Disable IP forwarding and restore iptables rules. + +WLAN_IF=$1 +BR=virbr0 +IP_RANGE=10.0.2.0/24 + +if [ -z "$WLAN_IF" ]; then + echo "Usage: $0 " + exit 1 +fi + +sysctl -w net.ipv4.ip_forward=0 + +iptables -t nat -D POSTROUTING -s $IP_RANGE -o $WLAN_IF -j MASQUERADE +iptables -D FORWARD -i $BR -j ACCEPT +iptables -D FORWARD -o $BR -m state --state RELATED,ESTABLISHED -j ACCEPT diff --git a/tools/.gitignore b/tools/.gitignore index 632baf2a00..6d9144fdc8 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -2,4 +2,6 @@ deptool/Cargo.lock deptool/target deptool/output.txt bwbench_client/target -bwbench_client/Cargo.lock \ No newline at end of file +bwbench_client/Cargo.lock +!raspi4/common/image/*/* +!raspi4/X1_JTAG_boot/* \ No newline at end of file diff --git a/tools/PCI_SYMBOLS.c b/tools/PCI_SYMBOLS.c new file mode 100644 index 0000000000..e9a4155309 --- /dev/null +++ b/tools/PCI_SYMBOLS.c @@ -0,0 +1,3133 @@ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_SATA 0x0106 +#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 +#define PCI_CLASS_STORAGE_SAS 0x0107 +#define PCI_CLASS_STORAGE_EXPRESS 0x010802 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 +#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCI_NORMAL 0x060400 +#define PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE 0x060401 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 +#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 +#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCI_CLASS_SYSTEM_SDHCI 0x0805 +#define PCI_CLASS_SYSTEM_RCEC 0x0807 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_SCANNER 0x0903 +#define PCI_CLASS_INPUT_GAMEPORT 0x0904 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a80 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 +#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 +#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 +#define PCI_CLASS_SERIAL_USB_XHCI 0x0c0330 +#define PCI_CLASS_SERIAL_USB_DEVICE 0x0c03fe +#define PCI_CLASS_SERIAL_FIBER 0x0c04 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 +#define PCI_CLASS_SERIAL_IPMI 0x0c07 +#define PCI_CLASS_SERIAL_IPMI_SMIC 0x0c0700 +#define PCI_CLASS_SERIAL_IPMI_KCS 0x0c0701 +#define PCI_CLASS_SERIAL_IPMI_BT 0x0c0702 + +#define PCI_BASE_CLASS_WIRELESS 0x0d +#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 +#define PCI_CLASS_WIRELESS_WHCI 0x0d1010 + +#define PCI_BASE_CLASS_INTELLIGENT 0x0e +#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 + +#define PCI_BASE_CLASS_SATELLITE 0x0f +#define PCI_CLASS_SATELLITE_TV 0x0f00 +#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 +#define PCI_CLASS_SATELLITE_VOICE 0x0f03 +#define PCI_CLASS_SATELLITE_DATA 0x0f04 + +#define PCI_BASE_CLASS_CRYPT 0x10 +#define PCI_CLASS_CRYPT_NETWORK 0x1000 +#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 +#define PCI_CLASS_CRYPT_OTHER 0x1080 + +#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 +#define PCI_CLASS_SP_DPIO 0x1100 +#define PCI_CLASS_SP_OTHER 0x1180 + +#define PCI_CLASS_OTHERS 0xff + +/* Vendors and devices. Sort key: vendor first, device next. */ + +#define PCI_VENDOR_ID_LOONGSON 0x0014 + +#define PCI_VENDOR_ID_TTTECH 0x0357 +#define PCI_DEVICE_ID_TTTECH_MC322 0x000a + +#define PCI_VENDOR_ID_DYNALINK 0x0675 +#define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 + +#define PCI_VENDOR_ID_UBIQUITI 0x0777 + +#define PCI_VENDOR_ID_BERKOM 0x0871 +#define PCI_DEVICE_ID_BERKOM_A1T 0xffa1 +#define PCI_DEVICE_ID_BERKOM_T_CONCEPT 0xffa2 +#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4 +#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8 + +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 +#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc +#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 +#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 +#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 +#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060 +#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178 +#define PCI_DEVICE_ID_COMPAQ_CISSC 0x46 +#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 + +#define PCI_VENDOR_ID_NCR 0x1000 +#define PCI_VENDOR_ID_LSI_LOGIC 0x1000 +#define PCI_DEVICE_ID_NCR_53C810 0x0001 +#define PCI_DEVICE_ID_NCR_53C820 0x0002 +#define PCI_DEVICE_ID_NCR_53C825 0x0003 +#define PCI_DEVICE_ID_NCR_53C815 0x0004 +#define PCI_DEVICE_ID_LSI_53C810AP 0x0005 +#define PCI_DEVICE_ID_NCR_53C860 0x0006 +#define PCI_DEVICE_ID_LSI_53C1510 0x000a +#define PCI_DEVICE_ID_NCR_53C896 0x000b +#define PCI_DEVICE_ID_NCR_53C895 0x000c +#define PCI_DEVICE_ID_NCR_53C885 0x000d +#define PCI_DEVICE_ID_NCR_53C875 0x000f +#define PCI_DEVICE_ID_NCR_53C1510 0x0010 +#define PCI_DEVICE_ID_LSI_53C895A 0x0012 +#define PCI_DEVICE_ID_LSI_53C875A 0x0013 +#define PCI_DEVICE_ID_LSI_53C1010_33 0x0020 +#define PCI_DEVICE_ID_LSI_53C1010_66 0x0021 +#define PCI_DEVICE_ID_LSI_53C1030 0x0030 +#define PCI_DEVICE_ID_LSI_1030_53C1035 0x0032 +#define PCI_DEVICE_ID_LSI_53C1035 0x0040 +#define PCI_DEVICE_ID_NCR_53C875J 0x008f +#define PCI_DEVICE_ID_LSI_FC909 0x0621 +#define PCI_DEVICE_ID_LSI_FC929 0x0622 +#define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623 +#define PCI_DEVICE_ID_LSI_FC919 0x0624 +#define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625 +#define PCI_DEVICE_ID_LSI_FC929X 0x0626 +#define PCI_DEVICE_ID_LSI_FC939X 0x0642 +#define PCI_DEVICE_ID_LSI_FC949X 0x0640 +#define PCI_DEVICE_ID_LSI_FC949ES 0x0646 +#define PCI_DEVICE_ID_LSI_FC919X 0x0628 +#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701 +#define PCI_DEVICE_ID_LSI_61C102 0x0901 +#define PCI_DEVICE_ID_LSI_63C815 0x1000 +#define PCI_DEVICE_ID_LSI_SAS1064 0x0050 +#define PCI_DEVICE_ID_LSI_SAS1064R 0x0411 +#define PCI_DEVICE_ID_LSI_SAS1066 0x005E +#define PCI_DEVICE_ID_LSI_SAS1068 0x0054 +#define PCI_DEVICE_ID_LSI_SAS1064A 0x005C +#define PCI_DEVICE_ID_LSI_SAS1064E 0x0056 +#define PCI_DEVICE_ID_LSI_SAS1066E 0x005A +#define PCI_DEVICE_ID_LSI_SAS1068E 0x0058 +#define PCI_DEVICE_ID_LSI_SAS1078 0x0060 + +#define PCI_VENDOR_ID_ATI 0x1002 +/* Mach64 */ +#define PCI_DEVICE_ID_ATI_68800 0x4158 +#define PCI_DEVICE_ID_ATI_215CT222 0x4354 +#define PCI_DEVICE_ID_ATI_210888CX 0x4358 +#define PCI_DEVICE_ID_ATI_215ET222 0x4554 +/* Mach64 / Rage */ +#define PCI_DEVICE_ID_ATI_215GB 0x4742 +#define PCI_DEVICE_ID_ATI_215GD 0x4744 +#define PCI_DEVICE_ID_ATI_215GI 0x4749 +#define PCI_DEVICE_ID_ATI_215GP 0x4750 +#define PCI_DEVICE_ID_ATI_215GQ 0x4751 +#define PCI_DEVICE_ID_ATI_215XL 0x4752 +#define PCI_DEVICE_ID_ATI_215GT 0x4754 +#define PCI_DEVICE_ID_ATI_215GTB 0x4755 +#define PCI_DEVICE_ID_ATI_215_IV 0x4756 +#define PCI_DEVICE_ID_ATI_215_IW 0x4757 +#define PCI_DEVICE_ID_ATI_215_IZ 0x475A +#define PCI_DEVICE_ID_ATI_210888GX 0x4758 +#define PCI_DEVICE_ID_ATI_215_LB 0x4c42 +#define PCI_DEVICE_ID_ATI_215_LD 0x4c44 +#define PCI_DEVICE_ID_ATI_215_LG 0x4c47 +#define PCI_DEVICE_ID_ATI_215_LI 0x4c49 +#define PCI_DEVICE_ID_ATI_215_LM 0x4c4D +#define PCI_DEVICE_ID_ATI_215_LN 0x4c4E +#define PCI_DEVICE_ID_ATI_215_LR 0x4c52 +#define PCI_DEVICE_ID_ATI_215_LS 0x4c53 +#define PCI_DEVICE_ID_ATI_264_LT 0x4c54 +/* Mach64 VT */ +#define PCI_DEVICE_ID_ATI_264VT 0x5654 +#define PCI_DEVICE_ID_ATI_264VU 0x5655 +#define PCI_DEVICE_ID_ATI_264VV 0x5656 +/* Rage128 GL */ +#define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245 +#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246 +#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x5247 +/* Rage128 VR */ +#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b +#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c +#define PCI_DEVICE_ID_ATI_RAGE128_SE 0x5345 +#define PCI_DEVICE_ID_ATI_RAGE128_SF 0x5346 +#define PCI_DEVICE_ID_ATI_RAGE128_SG 0x5347 +#define PCI_DEVICE_ID_ATI_RAGE128_SH 0x5348 +#define PCI_DEVICE_ID_ATI_RAGE128_SK 0x534b +#define PCI_DEVICE_ID_ATI_RAGE128_SL 0x534c +#define PCI_DEVICE_ID_ATI_RAGE128_SM 0x534d +#define PCI_DEVICE_ID_ATI_RAGE128_SN 0x534e +/* Rage128 Ultra */ +#define PCI_DEVICE_ID_ATI_RAGE128_TF 0x5446 +#define PCI_DEVICE_ID_ATI_RAGE128_TL 0x544c +#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452 +#define PCI_DEVICE_ID_ATI_RAGE128_TS 0x5453 +#define PCI_DEVICE_ID_ATI_RAGE128_TT 0x5454 +#define PCI_DEVICE_ID_ATI_RAGE128_TU 0x5455 +/* Rage128 M3 */ +#define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45 +#define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46 +/* Rage128 M4 */ +#define PCI_DEVICE_ID_ATI_RAGE128_MF 0x4d46 +#define PCI_DEVICE_ID_ATI_RAGE128_ML 0x4d4c +/* Rage128 Pro GL */ +#define PCI_DEVICE_ID_ATI_RAGE128_PA 0x5041 +#define PCI_DEVICE_ID_ATI_RAGE128_PB 0x5042 +#define PCI_DEVICE_ID_ATI_RAGE128_PC 0x5043 +#define PCI_DEVICE_ID_ATI_RAGE128_PD 0x5044 +#define PCI_DEVICE_ID_ATI_RAGE128_PE 0x5045 +#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046 +/* Rage128 Pro VR */ +#define PCI_DEVICE_ID_ATI_RAGE128_PG 0x5047 +#define PCI_DEVICE_ID_ATI_RAGE128_PH 0x5048 +#define PCI_DEVICE_ID_ATI_RAGE128_PI 0x5049 +#define PCI_DEVICE_ID_ATI_RAGE128_PJ 0x504A +#define PCI_DEVICE_ID_ATI_RAGE128_PK 0x504B +#define PCI_DEVICE_ID_ATI_RAGE128_PL 0x504C +#define PCI_DEVICE_ID_ATI_RAGE128_PM 0x504D +#define PCI_DEVICE_ID_ATI_RAGE128_PN 0x504E +#define PCI_DEVICE_ID_ATI_RAGE128_PO 0x504F +#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050 +#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051 +#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052 +#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053 +#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054 +#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055 +#define PCI_DEVICE_ID_ATI_RAGE128_PV 0x5056 +#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057 +#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058 +/* Rage128 M4 */ +/* Radeon R100 */ +#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144 +#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145 +#define PCI_DEVICE_ID_ATI_RADEON_QF 0x5146 +#define PCI_DEVICE_ID_ATI_RADEON_QG 0x5147 +/* Radeon RV100 (VE) */ +#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 +#define PCI_DEVICE_ID_ATI_RADEON_QZ 0x515a +/* Radeon R200 (8500) */ +#define PCI_DEVICE_ID_ATI_RADEON_QL 0x514c +#define PCI_DEVICE_ID_ATI_RADEON_QN 0x514e +#define PCI_DEVICE_ID_ATI_RADEON_QO 0x514f +#define PCI_DEVICE_ID_ATI_RADEON_Ql 0x516c +#define PCI_DEVICE_ID_ATI_RADEON_BB 0x4242 +/* Radeon R200 (9100) */ +#define PCI_DEVICE_ID_ATI_RADEON_QM 0x514d +/* Radeon RV200 (7500) */ +#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157 +#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158 +/* Radeon NV-100 */ +/* Radeon RV250 (9000) */ +#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964 +#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965 +#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966 +#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967 +/* Radeon RV280 (9200) */ +#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961 +#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964 +/* Radeon R300 (9500) */ +/* Radeon R300 (9700) */ +#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44 +#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45 +#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46 +#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47 +/* Radeon R350 (9800) */ +/* Radeon RV350 (9600) */ +/* Radeon M6 */ +#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59 +#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a +/* Radeon M7 */ +#define PCI_DEVICE_ID_ATI_RADEON_LW 0x4c57 +#define PCI_DEVICE_ID_ATI_RADEON_LX 0x4c58 +/* Radeon M9 */ +#define PCI_DEVICE_ID_ATI_RADEON_Ld 0x4c64 +#define PCI_DEVICE_ID_ATI_RADEON_Le 0x4c65 +#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66 +#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67 +/* Radeon */ +/* RadeonIGP */ +#define PCI_DEVICE_ID_ATI_RS100 0xcab0 +#define PCI_DEVICE_ID_ATI_RS200 0xcab2 +#define PCI_DEVICE_ID_ATI_RS200_B 0xcbb2 +#define PCI_DEVICE_ID_ATI_RS250 0xcab3 +#define PCI_DEVICE_ID_ATI_RS300_100 0x5830 +#define PCI_DEVICE_ID_ATI_RS300_133 0x5831 +#define PCI_DEVICE_ID_ATI_RS300_166 0x5832 +#define PCI_DEVICE_ID_ATI_RS300_200 0x5833 +#define PCI_DEVICE_ID_ATI_RS350_100 0x7830 +#define PCI_DEVICE_ID_ATI_RS350_133 0x7831 +#define PCI_DEVICE_ID_ATI_RS350_166 0x7832 +#define PCI_DEVICE_ID_ATI_RS350_200 0x7833 +#define PCI_DEVICE_ID_ATI_RS400_100 0x5a30 +#define PCI_DEVICE_ID_ATI_RS400_133 0x5a31 +#define PCI_DEVICE_ID_ATI_RS400_166 0x5a32 +#define PCI_DEVICE_ID_ATI_RS400_200 0x5a33 +#define PCI_DEVICE_ID_ATI_RS480 0x5950 +/* ATI IXP Chipset */ +#define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349 +#define PCI_DEVICE_ID_ATI_IXP200_SMBUS 0x4353 +#define PCI_DEVICE_ID_ATI_IXP300_SMBUS 0x4363 +#define PCI_DEVICE_ID_ATI_IXP300_IDE 0x4369 +#define PCI_DEVICE_ID_ATI_IXP300_SATA 0x436e +#define PCI_DEVICE_ID_ATI_IXP400_SMBUS 0x4372 +#define PCI_DEVICE_ID_ATI_IXP400_IDE 0x4376 +#define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379 +#define PCI_DEVICE_ID_ATI_IXP400_SATA2 0x437a +#define PCI_DEVICE_ID_ATI_IXP600_SATA 0x4380 +#define PCI_DEVICE_ID_ATI_SBX00_SMBUS 0x4385 +#define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c +#define PCI_DEVICE_ID_ATI_IXP700_SATA 0x4390 +#define PCI_DEVICE_ID_ATI_IXP700_IDE 0x439c + +#define PCI_VENDOR_ID_VLSI 0x1004 +#define PCI_DEVICE_ID_VLSI_82C592 0x0005 +#define PCI_DEVICE_ID_VLSI_82C593 0x0006 +#define PCI_DEVICE_ID_VLSI_82C594 0x0007 +#define PCI_DEVICE_ID_VLSI_82C597 0x0009 +#define PCI_DEVICE_ID_VLSI_82C541 0x000c +#define PCI_DEVICE_ID_VLSI_82C543 0x000d +#define PCI_DEVICE_ID_VLSI_82C532 0x0101 +#define PCI_DEVICE_ID_VLSI_82C534 0x0102 +#define PCI_DEVICE_ID_VLSI_82C535 0x0104 +#define PCI_DEVICE_ID_VLSI_82C147 0x0105 +#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 + +/* AMD RD890 Chipset */ +#define PCI_DEVICE_ID_RD890_IOMMU 0x5a23 + +#define PCI_VENDOR_ID_ADL 0x1005 +#define PCI_DEVICE_ID_ADL_2301 0x2301 + +#define PCI_VENDOR_ID_NS 0x100b +#define PCI_DEVICE_ID_NS_87415 0x0002 +#define PCI_DEVICE_ID_NS_87560_LIO 0x000e +#define PCI_DEVICE_ID_NS_87560_USB 0x0012 +#define PCI_DEVICE_ID_NS_83815 0x0020 +#define PCI_DEVICE_ID_NS_83820 0x0022 +#define PCI_DEVICE_ID_NS_CS5535_ISA 0x002b +#define PCI_DEVICE_ID_NS_CS5535_IDE 0x002d +#define PCI_DEVICE_ID_NS_CS5535_AUDIO 0x002e +#define PCI_DEVICE_ID_NS_CS5535_USB 0x002f +#define PCI_DEVICE_ID_NS_GX_VIDEO 0x0030 +#define PCI_DEVICE_ID_NS_SATURN 0x0035 +#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 +#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 +#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 +#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 +#define PCI_DEVICE_ID_NS_SC1100_BRIDGE 0x0510 +#define PCI_DEVICE_ID_NS_SC1100_SMI 0x0511 +#define PCI_DEVICE_ID_NS_SC1100_XBUS 0x0515 +#define PCI_DEVICE_ID_NS_87410 0xd001 + +#define PCI_DEVICE_ID_NS_GX_HOST_BRIDGE 0x0028 + +#define PCI_VENDOR_ID_TSENG 0x100c +#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 +#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 +#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 +#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 +#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 + +#define PCI_VENDOR_ID_WEITEK 0x100e +#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 +#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 + +#define PCI_VENDOR_ID_DEC 0x1011 +#define PCI_DEVICE_ID_DEC_BRD 0x0001 +#define PCI_DEVICE_ID_DEC_TULIP 0x0002 +#define PCI_DEVICE_ID_DEC_TGA 0x0004 +#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 +#define PCI_DEVICE_ID_DEC_TGA2 0x000D +#define PCI_DEVICE_ID_DEC_FDDI 0x000F +#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 +#define PCI_DEVICE_ID_DEC_21142 0x0019 +#define PCI_DEVICE_ID_DEC_21052 0x0021 +#define PCI_DEVICE_ID_DEC_21150 0x0022 +#define PCI_DEVICE_ID_DEC_21152 0x0024 +#define PCI_DEVICE_ID_DEC_21153 0x0025 +#define PCI_DEVICE_ID_DEC_21154 0x0026 +#define PCI_DEVICE_ID_DEC_21285 0x1065 +#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 + +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 +#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 +#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 +#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 +#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac +#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 +#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc +#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0 +#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 +#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 +#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 +#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 +#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 +#define PCI_DEVICE_ID_CIRRUS_4610 0x6001 +#define PCI_DEVICE_ID_CIRRUS_4612 0x6003 +#define PCI_DEVICE_ID_CIRRUS_4615 0x6004 + +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_DEVICE_ID_IBM_TR 0x0018 +#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e +#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc +#define PCI_DEVICE_ID_IBM_SNIPE 0x0180 +#define PCI_DEVICE_ID_IBM_CITRINE 0x028C +#define PCI_DEVICE_ID_IBM_GEMSTONE 0xB166 +#define PCI_DEVICE_ID_IBM_OBSIDIAN 0x02BD +#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1 0x0031 +#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219 +#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX 0x021A +#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251 +#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361 +#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252 + +#define PCI_SUBVENDOR_ID_IBM 0x1014 +#define PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT 0x03d4 + +#define PCI_VENDOR_ID_UNISYS 0x1018 +#define PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR 0x001C + +#define PCI_VENDOR_ID_COMPEX2 0x101a /* pci.ids says "AT&T GIS (NCR)" */ +#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 + +#define PCI_VENDOR_ID_WD 0x101c +#define PCI_DEVICE_ID_WD_90C 0xc24a + +#define PCI_VENDOR_ID_AMI 0x101e +#define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960 +#define PCI_DEVICE_ID_AMI_MEGARAID 0x9010 +#define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060 + +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_DEVICE_ID_AMD_K8_NB 0x1100 +#define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP 0x1101 +#define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL 0x1102 +#define PCI_DEVICE_ID_AMD_K8_NB_MISC 0x1103 +#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 +#define PCI_DEVICE_ID_AMD_10H_NB_MAP 0x1201 +#define PCI_DEVICE_ID_AMD_10H_NB_DRAM 0x1202 +#define PCI_DEVICE_ID_AMD_10H_NB_MISC 0x1203 +#define PCI_DEVICE_ID_AMD_10H_NB_LINK 0x1204 +#define PCI_DEVICE_ID_AMD_11H_NB_HT 0x1300 +#define PCI_DEVICE_ID_AMD_11H_NB_MAP 0x1301 +#define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302 +#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303 +#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304 +#define PCI_DEVICE_ID_AMD_15H_M10H_F3 0x1403 +#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 0x141d +#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 0x141e +#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F3 0x1573 +#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F4 0x1574 +#define PCI_DEVICE_ID_AMD_15H_NB_F0 0x1600 +#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 +#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 +#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603 +#define PCI_DEVICE_ID_AMD_15H_NB_F4 0x1604 +#define PCI_DEVICE_ID_AMD_15H_NB_F5 0x1605 +#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533 +#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534 +#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583 +#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584 +#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463 +#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb +#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493 +#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 0x144b +#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443 +#define PCI_DEVICE_ID_AMD_VANGOGH_USB 0x163a +#define PCI_DEVICE_ID_AMD_19H_DF_F3 0x1653 +#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 +#define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 +#define PCI_DEVICE_ID_AMD_SERENADE 0x36c0 +#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 +#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 +#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C +#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E +#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 +#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 +#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B +#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 +#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 +#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 +#define PCI_DEVICE_ID_AMD_VIPER_7440 0x7440 +#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441 +#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443 +#define PCI_DEVICE_ID_AMD_VIPER_7443 0x7443 +#define PCI_DEVICE_ID_AMD_OPUS_7445 0x7445 +#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450 +#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460 +#define PCI_DEVICE_ID_AMD_8111_LPC 0x7468 +#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 +#define PCI_DEVICE_ID_AMD_8111_SMBUS2 0x746a +#define PCI_DEVICE_ID_AMD_8111_SMBUS 0x746b +#define PCI_DEVICE_ID_AMD_8111_AUDIO 0x746d +#define PCI_DEVICE_ID_AMD_8151_0 0x7454 +#define PCI_DEVICE_ID_AMD_8131_BRIDGE 0x7450 +#define PCI_DEVICE_ID_AMD_8131_APIC 0x7451 +#define PCI_DEVICE_ID_AMD_8132_BRIDGE 0x7458 +#define PCI_DEVICE_ID_AMD_NL_USB 0x7912 +#define PCI_DEVICE_ID_AMD_CS5535_IDE 0x208F +#define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090 +#define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091 +#define PCI_DEVICE_ID_AMD_CS5536_AUDIO 0x2093 +#define PCI_DEVICE_ID_AMD_CS5536_OHC 0x2094 +#define PCI_DEVICE_ID_AMD_CS5536_EHC 0x2095 +#define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096 +#define PCI_DEVICE_ID_AMD_CS5536_UOC 0x2097 +#define PCI_DEVICE_ID_AMD_CS5536_DEV_IDE 0x2092 +#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A +#define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081 +#define PCI_DEVICE_ID_AMD_LX_AES 0x2082 +#define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE 0x7800 +#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS 0x780b +#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c +#define PCI_DEVICE_ID_AMD_KERNCZ_SMBUS 0x790b + +#define PCI_VENDOR_ID_TRIDENT 0x1023 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001 +#define PCI_DEVICE_ID_TRIDENT_9320 0x9320 +#define PCI_DEVICE_ID_TRIDENT_9388 0x9388 +#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 +#define PCI_DEVICE_ID_TRIDENT_939A 0x939A +#define PCI_DEVICE_ID_TRIDENT_9520 0x9520 +#define PCI_DEVICE_ID_TRIDENT_9525 0x9525 +#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 +#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 +#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 +#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 +#define PCI_DEVICE_ID_TRIDENT_9850 0x9850 +#define PCI_DEVICE_ID_TRIDENT_9880 0x9880 +#define PCI_DEVICE_ID_TRIDENT_8400 0x8400 +#define PCI_DEVICE_ID_TRIDENT_8420 0x8420 +#define PCI_DEVICE_ID_TRIDENT_8500 0x8500 + +#define PCI_VENDOR_ID_AI 0x1025 +#define PCI_DEVICE_ID_AI_M1435 0x1435 + +#define PCI_VENDOR_ID_DELL 0x1028 +#define PCI_DEVICE_ID_DELL_RACIII 0x0008 +#define PCI_DEVICE_ID_DELL_RAC4 0x0012 +#define PCI_DEVICE_ID_DELL_PERC5 0x0015 + +#define PCI_VENDOR_ID_MATROX 0x102B +#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 +#define PCI_DEVICE_ID_MATROX_MIL 0x0519 +#define PCI_DEVICE_ID_MATROX_MYS 0x051A +#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b +#define PCI_DEVICE_ID_MATROX_MYS_AGP 0x051e +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f +#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 +#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000 +#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 +#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 +#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 +#define PCI_DEVICE_ID_MATROX_G400 0x0525 +#define PCI_DEVICE_ID_MATROX_G200EV_PCI 0x0530 +#define PCI_DEVICE_ID_MATROX_G550 0x2527 +#define PCI_DEVICE_ID_MATROX_VIA 0x4536 + +#define PCI_VENDOR_ID_MOBILITY_ELECTRONICS 0x14f2 + +#define PCI_VENDOR_ID_CT 0x102c +#define PCI_DEVICE_ID_CT_69000 0x00c0 +#define PCI_DEVICE_ID_CT_65545 0x00d8 +#define PCI_DEVICE_ID_CT_65548 0x00dc +#define PCI_DEVICE_ID_CT_65550 0x00e0 +#define PCI_DEVICE_ID_CT_65554 0x00e4 +#define PCI_DEVICE_ID_CT_65555 0x00e5 + +#define PCI_VENDOR_ID_MIRO 0x1031 +#define PCI_DEVICE_ID_MIRO_36050 0x5601 +#define PCI_DEVICE_ID_MIRO_DC10PLUS 0x7efe +#define PCI_DEVICE_ID_MIRO_DC30PLUS 0xd801 + +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_DEVICE_ID_NEC_CBUS_1 0x0001 /* PCI-Cbus Bridge */ +#define PCI_DEVICE_ID_NEC_LOCAL 0x0002 /* Local Bridge */ +#define PCI_DEVICE_ID_NEC_ATM 0x0003 /* ATM LAN Controller */ +#define PCI_DEVICE_ID_NEC_R4000 0x0004 /* R4000 Bridge */ +#define PCI_DEVICE_ID_NEC_486 0x0005 /* 486 Like Peripheral Bus Bridge */ +#define PCI_DEVICE_ID_NEC_ACCEL_1 0x0006 /* Graphic Accelerator */ +#define PCI_DEVICE_ID_NEC_UXBUS 0x0007 /* UX-Bus Bridge */ +#define PCI_DEVICE_ID_NEC_ACCEL_2 0x0008 /* Graphic Accelerator */ +#define PCI_DEVICE_ID_NEC_GRAPH 0x0009 /* PCI-CoreGraph Bridge */ +#define PCI_DEVICE_ID_NEC_VL 0x0016 /* PCI-VL Bridge */ +#define PCI_DEVICE_ID_NEC_STARALPHA2 0x002c /* STAR ALPHA2 */ +#define PCI_DEVICE_ID_NEC_CBUS_2 0x002d /* PCI-Cbus Bridge */ +#define PCI_DEVICE_ID_NEC_USB 0x0035 /* PCI-USB Host */ +#define PCI_DEVICE_ID_NEC_CBUS_3 0x003b +#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e +#define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */ +#define PCI_DEVICE_ID_NEC_VRC5476 0x009b +#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 +#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 +#define PCI_DEVICE_ID_NEC_PC9821CS01 0x800c /* PC-9821-CS01 */ +#define PCI_DEVICE_ID_NEC_PC9821NRB06 0x800d /* PC-9821NR-B06 */ + +#define PCI_VENDOR_ID_FD 0x1036 +#define PCI_DEVICE_ID_FD_36C70 0x0000 + +#define PCI_VENDOR_ID_SI 0x1039 +#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 +#define PCI_DEVICE_ID_SI_6202 0x0002 +#define PCI_DEVICE_ID_SI_503 0x0008 +#define PCI_DEVICE_ID_SI_ACPI 0x0009 +#define PCI_DEVICE_ID_SI_SMBUS 0x0016 +#define PCI_DEVICE_ID_SI_LPC 0x0018 +#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 +#define PCI_DEVICE_ID_SI_6205 0x0205 +#define PCI_DEVICE_ID_SI_501 0x0406 +#define PCI_DEVICE_ID_SI_496 0x0496 +#define PCI_DEVICE_ID_SI_300 0x0300 +#define PCI_DEVICE_ID_SI_315H 0x0310 +#define PCI_DEVICE_ID_SI_315 0x0315 +#define PCI_DEVICE_ID_SI_315PRO 0x0325 +#define PCI_DEVICE_ID_SI_530 0x0530 +#define PCI_DEVICE_ID_SI_540 0x0540 +#define PCI_DEVICE_ID_SI_550 0x0550 +#define PCI_DEVICE_ID_SI_540_VGA 0x5300 +#define PCI_DEVICE_ID_SI_550_VGA 0x5315 +#define PCI_DEVICE_ID_SI_620 0x0620 +#define PCI_DEVICE_ID_SI_630 0x0630 +#define PCI_DEVICE_ID_SI_633 0x0633 +#define PCI_DEVICE_ID_SI_635 0x0635 +#define PCI_DEVICE_ID_SI_640 0x0640 +#define PCI_DEVICE_ID_SI_645 0x0645 +#define PCI_DEVICE_ID_SI_646 0x0646 +#define PCI_DEVICE_ID_SI_648 0x0648 +#define PCI_DEVICE_ID_SI_650 0x0650 +#define PCI_DEVICE_ID_SI_651 0x0651 +#define PCI_DEVICE_ID_SI_655 0x0655 +#define PCI_DEVICE_ID_SI_661 0x0661 +#define PCI_DEVICE_ID_SI_730 0x0730 +#define PCI_DEVICE_ID_SI_733 0x0733 +#define PCI_DEVICE_ID_SI_630_VGA 0x6300 +#define PCI_DEVICE_ID_SI_735 0x0735 +#define PCI_DEVICE_ID_SI_740 0x0740 +#define PCI_DEVICE_ID_SI_741 0x0741 +#define PCI_DEVICE_ID_SI_745 0x0745 +#define PCI_DEVICE_ID_SI_746 0x0746 +#define PCI_DEVICE_ID_SI_755 0x0755 +#define PCI_DEVICE_ID_SI_760 0x0760 +#define PCI_DEVICE_ID_SI_900 0x0900 +#define PCI_DEVICE_ID_SI_961 0x0961 +#define PCI_DEVICE_ID_SI_962 0x0962 +#define PCI_DEVICE_ID_SI_963 0x0963 +#define PCI_DEVICE_ID_SI_965 0x0965 +#define PCI_DEVICE_ID_SI_966 0x0966 +#define PCI_DEVICE_ID_SI_968 0x0968 +#define PCI_DEVICE_ID_SI_1180 0x1180 +#define PCI_DEVICE_ID_SI_5511 0x5511 +#define PCI_DEVICE_ID_SI_5513 0x5513 +#define PCI_DEVICE_ID_SI_5517 0x5517 +#define PCI_DEVICE_ID_SI_5518 0x5518 +#define PCI_DEVICE_ID_SI_5571 0x5571 +#define PCI_DEVICE_ID_SI_5581 0x5581 +#define PCI_DEVICE_ID_SI_5582 0x5582 +#define PCI_DEVICE_ID_SI_5591 0x5591 +#define PCI_DEVICE_ID_SI_5596 0x5596 +#define PCI_DEVICE_ID_SI_5597 0x5597 +#define PCI_DEVICE_ID_SI_5598 0x5598 +#define PCI_DEVICE_ID_SI_5600 0x5600 +#define PCI_DEVICE_ID_SI_7012 0x7012 +#define PCI_DEVICE_ID_SI_7013 0x7013 +#define PCI_DEVICE_ID_SI_7016 0x7016 +#define PCI_DEVICE_ID_SI_7018 0x7018 + +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_VENDOR_ID_HP_3PAR 0x1590 +#define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005 +#define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006 +#define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008 +#define PCI_DEVICE_ID_HP_VISUALIZE_FX2 0x100a +#define PCI_DEVICE_ID_HP_TACHYON 0x1028 +#define PCI_DEVICE_ID_HP_TACHLITE 0x1029 +#define PCI_DEVICE_ID_HP_J2585A 0x1030 +#define PCI_DEVICE_ID_HP_J2585B 0x1031 +#define PCI_DEVICE_ID_HP_J2973A 0x1040 +#define PCI_DEVICE_ID_HP_J2970A 0x1042 +#define PCI_DEVICE_ID_HP_DIVA 0x1048 +#define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049 +#define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A +#define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B +#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1 +#define PCI_DEVICE_ID_HP_VISUALIZE_FXE 0x108b +#define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223 +#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226 +#define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227 +#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a +#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e +#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c +#define PCI_DEVICE_ID_HP_DIVA_EVEREST 0x1282 +#define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290 +#define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301 +#define PCI_DEVICE_ID_HP_DIVA_HURRICANE 0x132a +#define PCI_DEVICE_ID_HP_CISSA 0x3220 +#define PCI_DEVICE_ID_HP_CISSC 0x3230 +#define PCI_DEVICE_ID_HP_CISSD 0x3238 +#define PCI_DEVICE_ID_HP_CISSE 0x323a +#define PCI_DEVICE_ID_HP_CISSF 0x323b +#define PCI_DEVICE_ID_HP_CISSH 0x323c +#define PCI_DEVICE_ID_HP_CISSI 0x3239 +#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 + +#define PCI_VENDOR_ID_PCTECH 0x1042 +#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 +#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 + +#define PCI_VENDOR_ID_ASUSTEK 0x1043 +#define PCI_DEVICE_ID_ASUSTEK_0675 0x0675 + +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 + +#define PCI_VENDOR_ID_OPTI 0x1045 +#define PCI_DEVICE_ID_OPTI_82C558 0xc558 +#define PCI_DEVICE_ID_OPTI_82C621 0xc621 +#define PCI_DEVICE_ID_OPTI_82C700 0xc700 +#define PCI_DEVICE_ID_OPTI_82C825 0xd568 + +#define PCI_VENDOR_ID_ELSA 0x1048 +#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 +#define PCI_DEVICE_ID_ELSA_QS3000 0x3000 + +#define PCI_VENDOR_ID_STMICRO 0x104A +#define PCI_DEVICE_ID_STMICRO_USB_HOST 0xCC00 +#define PCI_DEVICE_ID_STMICRO_USB_OHCI 0xCC01 +#define PCI_DEVICE_ID_STMICRO_USB_OTG 0xCC02 +#define PCI_DEVICE_ID_STMICRO_UART_HWFC 0xCC03 +#define PCI_DEVICE_ID_STMICRO_UART_NO_HWFC 0xCC04 +#define PCI_DEVICE_ID_STMICRO_SOC_DMA 0xCC05 +#define PCI_DEVICE_ID_STMICRO_SATA 0xCC06 +#define PCI_DEVICE_ID_STMICRO_I2C 0xCC07 +#define PCI_DEVICE_ID_STMICRO_SPI_HS 0xCC08 +#define PCI_DEVICE_ID_STMICRO_MAC 0xCC09 +#define PCI_DEVICE_ID_STMICRO_SDIO_EMMC 0xCC0A +#define PCI_DEVICE_ID_STMICRO_SDIO 0xCC0B +#define PCI_DEVICE_ID_STMICRO_GPIO 0xCC0C +#define PCI_DEVICE_ID_STMICRO_VIP 0xCC0D +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA 0xCC0E +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS 0xCC0F +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS 0xCC10 +#define PCI_DEVICE_ID_STMICRO_CAN 0xCC11 +#define PCI_DEVICE_ID_STMICRO_MLB 0xCC12 +#define PCI_DEVICE_ID_STMICRO_DBP 0xCC13 +#define PCI_DEVICE_ID_STMICRO_SATA_PHY 0xCC14 +#define PCI_DEVICE_ID_STMICRO_ESRAM 0xCC15 +#define PCI_DEVICE_ID_STMICRO_VIC 0xCC16 + +#define PCI_VENDOR_ID_BUSLOGIC 0x104B +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 + +#define PCI_VENDOR_ID_TI 0x104c +#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 +#define PCI_DEVICE_ID_TI_4450 0x8011 +#define PCI_DEVICE_ID_TI_XX21_XX11 0x8031 +#define PCI_DEVICE_ID_TI_XX21_XX11_FM 0x8033 +#define PCI_DEVICE_ID_TI_XX21_XX11_SD 0x8034 +#define PCI_DEVICE_ID_TI_X515 0x8036 +#define PCI_DEVICE_ID_TI_XX12 0x8039 +#define PCI_DEVICE_ID_TI_XX12_FM 0x803b +#define PCI_DEVICE_ID_TI_XIO2000A 0x8231 +#define PCI_DEVICE_ID_TI_1130 0xac12 +#define PCI_DEVICE_ID_TI_1031 0xac13 +#define PCI_DEVICE_ID_TI_1131 0xac15 +#define PCI_DEVICE_ID_TI_1250 0xac16 +#define PCI_DEVICE_ID_TI_1220 0xac17 +#define PCI_DEVICE_ID_TI_1221 0xac19 +#define PCI_DEVICE_ID_TI_1210 0xac1a +#define PCI_DEVICE_ID_TI_1450 0xac1b +#define PCI_DEVICE_ID_TI_1225 0xac1c +#define PCI_DEVICE_ID_TI_1251A 0xac1d +#define PCI_DEVICE_ID_TI_1211 0xac1e +#define PCI_DEVICE_ID_TI_1251B 0xac1f +#define PCI_DEVICE_ID_TI_4410 0xac41 +#define PCI_DEVICE_ID_TI_4451 0xac42 +#define PCI_DEVICE_ID_TI_4510 0xac44 +#define PCI_DEVICE_ID_TI_4520 0xac46 +#define PCI_DEVICE_ID_TI_7510 0xac47 +#define PCI_DEVICE_ID_TI_7610 0xac48 +#define PCI_DEVICE_ID_TI_7410 0xac49 +#define PCI_DEVICE_ID_TI_1410 0xac50 +#define PCI_DEVICE_ID_TI_1420 0xac51 +#define PCI_DEVICE_ID_TI_1451A 0xac52 +#define PCI_DEVICE_ID_TI_1620 0xac54 +#define PCI_DEVICE_ID_TI_1520 0xac55 +#define PCI_DEVICE_ID_TI_1510 0xac56 +#define PCI_DEVICE_ID_TI_X620 0xac8d +#define PCI_DEVICE_ID_TI_X420 0xac8e +#define PCI_DEVICE_ID_TI_XX20_FM 0xac8f +#define PCI_DEVICE_ID_TI_DRA74x 0xb500 +#define PCI_DEVICE_ID_TI_DRA72x 0xb501 + +#define PCI_VENDOR_ID_SONY 0x104d + +/* Winbond have two vendor IDs! See 0x10ad as well */ +#define PCI_VENDOR_ID_WINBOND2 0x1050 +#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a +#define PCI_DEVICE_ID_WINBOND2_6692 0x6692 + +#define PCI_VENDOR_ID_ANIGMA 0x1051 +#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100 + +#define PCI_VENDOR_ID_EFAR 0x1055 +#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130 +#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463 + +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 +#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 +#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004 +#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 +#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 +#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803 +#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b +#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803 +#define PCI_DEVICE_ID_MOTOROLA_MPC5200B 0x5809 + +#define PCI_VENDOR_ID_PROMISE 0x105a +#define PCI_DEVICE_ID_PROMISE_20265 0x0d30 +#define PCI_DEVICE_ID_PROMISE_20267 0x4d30 +#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 +#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 +#define PCI_DEVICE_ID_PROMISE_20263 0x0D38 +#define PCI_DEVICE_ID_PROMISE_20268 0x4d68 +#define PCI_DEVICE_ID_PROMISE_20269 0x4d69 +#define PCI_DEVICE_ID_PROMISE_20270 0x6268 +#define PCI_DEVICE_ID_PROMISE_20271 0x6269 +#define PCI_DEVICE_ID_PROMISE_20275 0x1275 +#define PCI_DEVICE_ID_PROMISE_20276 0x5275 +#define PCI_DEVICE_ID_PROMISE_20277 0x7275 + +#define PCI_VENDOR_ID_FOXCONN 0x105b + +#define PCI_VENDOR_ID_UMC 0x1060 +#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 +#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a +#define PCI_DEVICE_ID_UMC_UM8886A 0x886a + +#define PCI_VENDOR_ID_PICOPOWER 0x1066 +#define PCI_DEVICE_ID_PICOPOWER_PT86C523 0x0002 +#define PCI_DEVICE_ID_PICOPOWER_PT86C523BBP 0x8002 + +#define PCI_VENDOR_ID_MYLEX 0x1069 +#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020 +#define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050 +#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 +#define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166 + +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 +#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e +#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d +#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032 +#define PCI_DEVICE_ID_APPLE_UNI_N_ATA 0x0033 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034 +#define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b +#define PCI_DEVICE_ID_APPLE_K2_ATA100 0x0043 +#define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b +#define PCI_DEVICE_ID_APPLE_K2_GMAC 0x004c +#define PCI_DEVICE_ID_APPLE_SH_ATA 0x0050 +#define PCI_DEVICE_ID_APPLE_SH_SUNGEM 0x0051 +#define PCI_DEVICE_ID_APPLE_U3L_AGP 0x0058 +#define PCI_DEVICE_ID_APPLE_U3H_AGP 0x0059 +#define PCI_DEVICE_ID_APPLE_U4_PCIE 0x005b +#define PCI_DEVICE_ID_APPLE_IPID2_AGP 0x0066 +#define PCI_DEVICE_ID_APPLE_IPID2_ATA 0x0069 +#define PCI_DEVICE_ID_APPLE_IPID2_FW 0x006a +#define PCI_DEVICE_ID_APPLE_IPID2_GMAC 0x006b +#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645 + +#define PCI_VENDOR_ID_YAMAHA 0x1073 +#define PCI_DEVICE_ID_YAMAHA_724 0x0004 +#define PCI_DEVICE_ID_YAMAHA_724F 0x000d +#define PCI_DEVICE_ID_YAMAHA_740 0x000a +#define PCI_DEVICE_ID_YAMAHA_740C 0x000c +#define PCI_DEVICE_ID_YAMAHA_744 0x0010 +#define PCI_DEVICE_ID_YAMAHA_754 0x0012 + +#define PCI_VENDOR_ID_QLOGIC 0x1077 +#define PCI_DEVICE_ID_QLOGIC_ISP10160 0x1016 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1080 0x1080 +#define PCI_DEVICE_ID_QLOGIC_ISP12160 0x1216 +#define PCI_DEVICE_ID_QLOGIC_ISP1240 0x1240 +#define PCI_DEVICE_ID_QLOGIC_ISP1280 0x1280 +#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 +#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 +#define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300 +#define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312 +#define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322 +#define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312 +#define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322 +#define PCI_DEVICE_ID_QLOGIC_ISP2422 0x2422 +#define PCI_DEVICE_ID_QLOGIC_ISP2432 0x2432 +#define PCI_DEVICE_ID_QLOGIC_ISP2512 0x2512 +#define PCI_DEVICE_ID_QLOGIC_ISP2522 0x2522 +#define PCI_DEVICE_ID_QLOGIC_ISP5422 0x5422 +#define PCI_DEVICE_ID_QLOGIC_ISP5432 0x5432 + +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_DEVICE_ID_CYRIX_5510 0x0000 +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 +#define PCI_DEVICE_ID_CYRIX_5520 0x0002 +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 +#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 + +#define PCI_VENDOR_ID_CONTAQ 0x1080 +#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 + +#define PCI_VENDOR_ID_OLICOM 0x108d +#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 +#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 +#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 + +#define PCI_VENDOR_ID_SUN 0x108e +#define PCI_DEVICE_ID_SUN_EBUS 0x1000 +#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 +#define PCI_DEVICE_ID_SUN_RIO_EBUS 0x1100 +#define PCI_DEVICE_ID_SUN_RIO_GEM 0x1101 +#define PCI_DEVICE_ID_SUN_RIO_1394 0x1102 +#define PCI_DEVICE_ID_SUN_RIO_USB 0x1103 +#define PCI_DEVICE_ID_SUN_GEM 0x2bad +#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 +#define PCI_DEVICE_ID_SUN_PBM 0x8000 +#define PCI_DEVICE_ID_SUN_SCHIZO 0x8001 +#define PCI_DEVICE_ID_SUN_SABRE 0xa000 +#define PCI_DEVICE_ID_SUN_HUMMINGBIRD 0xa001 +#define PCI_DEVICE_ID_SUN_TOMATILLO 0xa801 +#define PCI_DEVICE_ID_SUN_CASSINI 0xabba + +#define PCI_VENDOR_ID_NI 0x1093 +#define PCI_DEVICE_ID_NI_PCI2322 0xd130 +#define PCI_DEVICE_ID_NI_PCI2324 0xd140 +#define PCI_DEVICE_ID_NI_PCI2328 0xd150 +#define PCI_DEVICE_ID_NI_PXI8422_2322 0xd190 +#define PCI_DEVICE_ID_NI_PXI8422_2324 0xd1a0 +#define PCI_DEVICE_ID_NI_PXI8420_2322 0xd1d0 +#define PCI_DEVICE_ID_NI_PXI8420_2324 0xd1e0 +#define PCI_DEVICE_ID_NI_PXI8420_2328 0xd1f0 +#define PCI_DEVICE_ID_NI_PXI8420_23216 0xd1f1 +#define PCI_DEVICE_ID_NI_PCI2322I 0xd250 +#define PCI_DEVICE_ID_NI_PCI2324I 0xd270 +#define PCI_DEVICE_ID_NI_PCI23216 0xd2b0 +#define PCI_DEVICE_ID_NI_PXI8430_2322 0x7080 +#define PCI_DEVICE_ID_NI_PCI8430_2322 0x70db +#define PCI_DEVICE_ID_NI_PXI8430_2324 0x70dd +#define PCI_DEVICE_ID_NI_PCI8430_2324 0x70df +#define PCI_DEVICE_ID_NI_PXI8430_2328 0x70e2 +#define PCI_DEVICE_ID_NI_PCI8430_2328 0x70e4 +#define PCI_DEVICE_ID_NI_PXI8430_23216 0x70e6 +#define PCI_DEVICE_ID_NI_PCI8430_23216 0x70e7 +#define PCI_DEVICE_ID_NI_PXI8432_2322 0x70e8 +#define PCI_DEVICE_ID_NI_PCI8432_2322 0x70ea +#define PCI_DEVICE_ID_NI_PXI8432_2324 0x70ec +#define PCI_DEVICE_ID_NI_PCI8432_2324 0x70ee + +#define PCI_VENDOR_ID_CMD 0x1095 +#define PCI_DEVICE_ID_CMD_643 0x0643 +#define PCI_DEVICE_ID_CMD_646 0x0646 +#define PCI_DEVICE_ID_CMD_648 0x0648 +#define PCI_DEVICE_ID_CMD_649 0x0649 + +#define PCI_DEVICE_ID_SII_680 0x0680 +#define PCI_DEVICE_ID_SII_3112 0x3112 +#define PCI_DEVICE_ID_SII_1210SA 0x0240 + +#define PCI_VENDOR_ID_BROOKTREE 0x109e +#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 +#define PCI_DEVICE_ID_BROOKTREE_879 0x0879 + +#define PCI_VENDOR_ID_SGI 0x10a9 +#define PCI_DEVICE_ID_SGI_IOC3 0x0003 +#define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 + +#define PCI_VENDOR_ID_WINBOND 0x10ad +#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 +#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 + +#define PCI_VENDOR_ID_PLX 0x10b5 +#define PCI_DEVICE_ID_PLX_R685 0x1030 +#define PCI_DEVICE_ID_PLX_ROMULUS 0x106a +#define PCI_DEVICE_ID_PLX_SPCOM800 0x1076 +#define PCI_DEVICE_ID_PLX_1077 0x1077 +#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 +#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 +#define PCI_DEVICE_ID_PLX_R753 0x1152 +#define PCI_DEVICE_ID_PLX_OLITEC 0x1187 +#define PCI_DEVICE_ID_PLX_PCI200SYN 0x3196 +#define PCI_DEVICE_ID_PLX_9030 0x9030 +#define PCI_DEVICE_ID_PLX_9050 0x9050 +#define PCI_DEVICE_ID_PLX_9056 0x9056 +#define PCI_DEVICE_ID_PLX_9080 0x9080 +#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 + +#define PCI_VENDOR_ID_MADGE 0x10b6 +#define PCI_DEVICE_ID_MADGE_MK2 0x0002 + +#define PCI_VENDOR_ID_3COM 0x10b7 +#define PCI_DEVICE_ID_3COM_3C985 0x0001 +#define PCI_DEVICE_ID_3COM_3C940 0x1700 +#define PCI_DEVICE_ID_3COM_3C339 0x3390 +#define PCI_DEVICE_ID_3COM_3C359 0x3590 +#define PCI_DEVICE_ID_3COM_3C940B 0x80eb +#define PCI_DEVICE_ID_3COM_3CR990 0x9900 +#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902 +#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903 +#define PCI_DEVICE_ID_3COM_3CR990B 0x9904 +#define PCI_DEVICE_ID_3COM_3CR990_FX 0x9905 +#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908 +#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 +#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a + +#define PCI_VENDOR_ID_AL 0x10b9 +#define PCI_DEVICE_ID_AL_M1533 0x1533 +#define PCI_DEVICE_ID_AL_M1535 0x1535 +#define PCI_DEVICE_ID_AL_M1541 0x1541 +#define PCI_DEVICE_ID_AL_M1563 0x1563 +#define PCI_DEVICE_ID_AL_M1621 0x1621 +#define PCI_DEVICE_ID_AL_M1631 0x1631 +#define PCI_DEVICE_ID_AL_M1632 0x1632 +#define PCI_DEVICE_ID_AL_M1641 0x1641 +#define PCI_DEVICE_ID_AL_M1644 0x1644 +#define PCI_DEVICE_ID_AL_M1647 0x1647 +#define PCI_DEVICE_ID_AL_M1651 0x1651 +#define PCI_DEVICE_ID_AL_M1671 0x1671 +#define PCI_DEVICE_ID_AL_M1681 0x1681 +#define PCI_DEVICE_ID_AL_M1683 0x1683 +#define PCI_DEVICE_ID_AL_M1689 0x1689 +#define PCI_DEVICE_ID_AL_M5219 0x5219 +#define PCI_DEVICE_ID_AL_M5228 0x5228 +#define PCI_DEVICE_ID_AL_M5229 0x5229 +#define PCI_DEVICE_ID_AL_M5451 0x5451 +#define PCI_DEVICE_ID_AL_M7101 0x7101 + +#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 +#define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005 +#define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006 +#define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016 + +#define PCI_VENDOR_ID_TCONRAD 0x10da +#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 + +#define PCI_VENDOR_ID_ROHM 0x10db + +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 +#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 +#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 +#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN 0x002a +#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C +#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS 0x0034 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE 0x0035 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA 0x0036 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2 0x003e +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800 0x0041 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE 0x0042 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT 0x0045 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000 0x004E +#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS 0x0052 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE 0x0053 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA 0x0054 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2 0x0055 +#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059 +#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE 0x005d +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS 0x0064 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065 +#define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM 0x0069 +#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS 0x0084 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE 0x0085 +#define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM 0x0089 +#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA 0x008e +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT 0x0090 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX 0x0091 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800 0x0098 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX 0x0099 +#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 +#define PCI_DEVICE_ID_GEFORCE_6800A 0x00c1 +#define PCI_DEVICE_ID_GEFORCE_6800A_LE 0x00c2 +#define PCI_DEVICE_ID_GEFORCE_GO_6800 0x00c8 +#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA 0x00c9 +#define PCI_DEVICE_ID_QUADRO_FX_GO1400 0x00cc +#define PCI_DEVICE_ID_QUADRO_FX_1400 0x00ce +#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS 0x00d4 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5 +#define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM 0x00d9 +#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S 0x00e1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA 0x00e3 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS 0x00e4 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE 0x00e5 +#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2 0x00ee +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1 0x00f0 +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1 0x00f1 +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2 0x00f2 +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1 0x00f3 +#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT 0x00f9 +#define PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280 0x00fd +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 +#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT 0x0140 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600 0x0141 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL 0x0145 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540 0x014E +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200 0x014F +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200 0x0164 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250 0x0166 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1 0x0167 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1 0x0168 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 0x0170 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 0x0171 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 0x0172 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE 0x0173 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO 0x0174 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO 0x0175 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO 0x0177 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL 0x0178 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200 0x017A +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL 0x017B +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL 0x017C +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000 0x0185 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO 0x0186 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO 0x0187 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL 0x0188 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC 0x0189 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS 0x018A +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL 0x018B +#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 +#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4 +#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO 0x01b1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS 0x01b4 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc +#define PCI_DEVICE_ID_NVIDIA_MCP1_MODEM 0x01c1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B 0x0211 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE 0x0212 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT 0x0215 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600 0x0250 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400 0x0251 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200 0x0253 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS 0x0264 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE 0x0265 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA 0x0266 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2 0x0267 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS 0x0368 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE 0x036E +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA 0x037E +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2 0x037F +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X 0x0281 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE 0x0282 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO 0x0286 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL 0x0288 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL 0x0289 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL 0x028C +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA 0x0301 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800 0x0302 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000 0x0308 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000 0x0309 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA 0x0311 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600 0x0312 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE 0x0314 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600 0x031A +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650 0x031B +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700 0x031C +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 0x0320 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA 0x0321 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1 0x0322 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE 0x0323 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200 0x0324 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250 0x0325 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500 0x0326 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100 0x0327 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32 0x0328 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200 0x0329 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI 0x032A +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500 0x032B +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300 0x032C +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100 0x032D +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA 0x0330 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900 0x0331 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT 0x0332 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA 0x0333 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT 0x0334 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000 0x0338 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700 0x033F +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA 0x0341 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700 0x0342 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE 0x0343 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE 0x0344 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1 0x0347 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2 0x0348 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000 0x034C +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100 0x034E +#define PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0 0x0360 +#define PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4 0x0364 +#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA 0x03E7 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS 0x03EB +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE 0x03EC +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2 0x03F6 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3 0x03F7 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS 0x0446 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE 0x0448 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS 0x0542 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE 0x0560 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE 0x056C +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS 0x0752 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE 0x0759 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS 0x07D8 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_320M 0x08A0 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS 0x0AA2 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA 0x0D85 + +#define PCI_VENDOR_ID_IMS 0x10e0 +#define PCI_DEVICE_ID_IMS_TT128 0x9128 +#define PCI_DEVICE_ID_IMS_TT3D 0x9135 + +#define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_VENDOR_ID_AMPERE 0x1def + +#define PCI_VENDOR_ID_INTERG 0x10ea +#define PCI_DEVICE_ID_INTERG_1682 0x1682 +#define PCI_DEVICE_ID_INTERG_2000 0x2000 +#define PCI_DEVICE_ID_INTERG_2010 0x2010 +#define PCI_DEVICE_ID_INTERG_5000 0x5000 +#define PCI_DEVICE_ID_INTERG_5050 0x5050 + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_8139 0x8139 + +#define PCI_VENDOR_ID_XILINX 0x10ee +#define PCI_DEVICE_ID_RME_DIGI96 0x3fc0 +#define PCI_DEVICE_ID_RME_DIGI96_8 0x3fc1 +#define PCI_DEVICE_ID_RME_DIGI96_8_PRO 0x3fc2 +#define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3 +#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5 +#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6 + +#define PCI_VENDOR_ID_INIT 0x1101 + +#define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */ +#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002 +#define PCI_DEVICE_ID_CREATIVE_20K1 0x0005 +#define PCI_DEVICE_ID_CREATIVE_20K2 0x000b +#define PCI_SUBDEVICE_ID_CREATIVE_SB0760 0x0024 +#define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041 +#define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042 +#define PCI_SUBDEVICE_ID_CREATIVE_SB08803 0x0043 +#define PCI_SUBDEVICE_ID_CREATIVE_SB1270 0x0062 +#define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX 0x6000 + +#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */ +#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938 + +#define PCI_VENDOR_ID_TTI 0x1103 +#define PCI_DEVICE_ID_TTI_HPT343 0x0003 +#define PCI_DEVICE_ID_TTI_HPT366 0x0004 +#define PCI_DEVICE_ID_TTI_HPT372 0x0005 +#define PCI_DEVICE_ID_TTI_HPT302 0x0006 +#define PCI_DEVICE_ID_TTI_HPT371 0x0007 +#define PCI_DEVICE_ID_TTI_HPT374 0x0008 +#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 /* apparently a 372N variant? */ + +#define PCI_VENDOR_ID_SIGMA 0x1105 + +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_8763_0 0x0198 +#define PCI_DEVICE_ID_VIA_8380_0 0x0204 +#define PCI_DEVICE_ID_VIA_3238_0 0x0238 +#define PCI_DEVICE_ID_VIA_PT880 0x0258 +#define PCI_DEVICE_ID_VIA_PT880ULTRA 0x0308 +#define PCI_DEVICE_ID_VIA_PX8X0_0 0x0259 +#define PCI_DEVICE_ID_VIA_3269_0 0x0269 +#define PCI_DEVICE_ID_VIA_K8T800PRO_0 0x0282 +#define PCI_DEVICE_ID_VIA_3296_0 0x0296 +#define PCI_DEVICE_ID_VIA_8363_0 0x0305 +#define PCI_DEVICE_ID_VIA_P4M800CE 0x0314 +#define PCI_DEVICE_ID_VIA_P4M890 0x0327 +#define PCI_DEVICE_ID_VIA_VT3324 0x0324 +#define PCI_DEVICE_ID_VIA_VT3336 0x0336 +#define PCI_DEVICE_ID_VIA_VT3351 0x0351 +#define PCI_DEVICE_ID_VIA_VT3364 0x0364 +#define PCI_DEVICE_ID_VIA_8371_0 0x0391 +#define PCI_DEVICE_ID_VIA_6415 0x0415 +#define PCI_DEVICE_ID_VIA_8501_0 0x0501 +#define PCI_DEVICE_ID_VIA_82C561 0x0561 +#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 +#define PCI_DEVICE_ID_VIA_82C576 0x0576 +#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 +#define PCI_DEVICE_ID_VIA_82C596 0x0596 +#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 +#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 +#define PCI_DEVICE_ID_VIA_8601_0 0x0601 +#define PCI_DEVICE_ID_VIA_8605_0 0x0605 +#define PCI_DEVICE_ID_VIA_82C686 0x0686 +#define PCI_DEVICE_ID_VIA_82C691_0 0x0691 +#define PCI_DEVICE_ID_VIA_82C576_1 0x1571 +#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 +#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 +#define PCI_DEVICE_ID_VIA_82C596_3 0x3050 +#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051 +#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 +#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 +#define PCI_DEVICE_ID_VIA_8233_5 0x3059 +#define PCI_DEVICE_ID_VIA_8233_0 0x3074 +#define PCI_DEVICE_ID_VIA_8633_0 0x3091 +#define PCI_DEVICE_ID_VIA_8367_0 0x3099 +#define PCI_DEVICE_ID_VIA_8653_0 0x3101 +#define PCI_DEVICE_ID_VIA_8622 0x3102 +#define PCI_DEVICE_ID_VIA_8235_USB_2 0x3104 +#define PCI_DEVICE_ID_VIA_8233C_0 0x3109 +#define PCI_DEVICE_ID_VIA_8361 0x3112 +#define PCI_DEVICE_ID_VIA_XM266 0x3116 +#define PCI_DEVICE_ID_VIA_612X 0x3119 +#define PCI_DEVICE_ID_VIA_862X_0 0x3123 +#define PCI_DEVICE_ID_VIA_8753_0 0x3128 +#define PCI_DEVICE_ID_VIA_8233A 0x3147 +#define PCI_DEVICE_ID_VIA_8703_51_0 0x3148 +#define PCI_DEVICE_ID_VIA_8237_SATA 0x3149 +#define PCI_DEVICE_ID_VIA_XN266 0x3156 +#define PCI_DEVICE_ID_VIA_6410 0x3164 +#define PCI_DEVICE_ID_VIA_8754C_0 0x3168 +#define PCI_DEVICE_ID_VIA_8235 0x3177 +#define PCI_DEVICE_ID_VIA_8385_0 0x3188 +#define PCI_DEVICE_ID_VIA_8377_0 0x3189 +#define PCI_DEVICE_ID_VIA_8378_0 0x3205 +#define PCI_DEVICE_ID_VIA_8783_0 0x3208 +#define PCI_DEVICE_ID_VIA_8237 0x3227 +#define PCI_DEVICE_ID_VIA_8251 0x3287 +#define PCI_DEVICE_ID_VIA_8261 0x3402 +#define PCI_DEVICE_ID_VIA_8237A 0x3337 +#define PCI_DEVICE_ID_VIA_8237S 0x3372 +#define PCI_DEVICE_ID_VIA_SATA_EIDE 0x5324 +#define PCI_DEVICE_ID_VIA_8231 0x8231 +#define PCI_DEVICE_ID_VIA_8231_4 0x8235 +#define PCI_DEVICE_ID_VIA_8365_1 0x8305 +#define PCI_DEVICE_ID_VIA_CX700 0x8324 +#define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581 +#define PCI_DEVICE_ID_VIA_VX800 0x8353 +#define PCI_DEVICE_ID_VIA_VX855 0x8409 +#define PCI_DEVICE_ID_VIA_VX900 0x8410 +#define PCI_DEVICE_ID_VIA_8371_1 0x8391 +#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 +#define PCI_DEVICE_ID_VIA_838X_1 0xB188 +#define PCI_DEVICE_ID_VIA_83_87XX_1 0xB198 +#define PCI_DEVICE_ID_VIA_VX855_IDE 0xC409 +#define PCI_DEVICE_ID_VIA_ANON 0xFFFF + +#define PCI_VENDOR_ID_SIEMENS 0x110A +#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 + +#define PCI_VENDOR_ID_VORTEX 0x1119 +#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 +#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 +#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 +#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 +#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 +#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 +#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 +#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 +#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 +#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 +#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a +#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b +#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c +#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 + +#define PCI_VENDOR_ID_EF 0x111a +#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 +#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 +#define PCI_DEVICE_ID_EF_ATM_LANAI2 0x0003 +#define PCI_DEVICE_ID_EF_ATM_LANAIHB 0x0005 + +#define PCI_VENDOR_ID_IDT 0x111d +#define PCI_DEVICE_ID_IDT_IDT77201 0x0001 + +#define PCI_VENDOR_ID_FORE 0x1127 +#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 + +#define PCI_VENDOR_ID_PHILIPS 0x1131 +#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 +#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 + +#define PCI_VENDOR_ID_EICON 0x1133 +#define PCI_DEVICE_ID_EICON_DIVA20 0xe002 +#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004 +#define PCI_DEVICE_ID_EICON_DIVA201 0xe005 +#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b +#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010 +#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012 +#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013 +#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014 + +#define PCI_VENDOR_ID_CISCO 0x1137 + +#define PCI_VENDOR_ID_ZIATECH 0x1138 +#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550 + + +#define PCI_VENDOR_ID_SYSKONNECT 0x1148 +#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 +#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 +#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320 +#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 +#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 + +#define PCI_VENDOR_ID_DIGI 0x114f +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 +#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072 +#define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073 +#define PCI_DEVICE_ID_DIGI_NEO_8 0x00B1 +#define PCI_DEVICE_ID_NEO_2DB9 0x00C8 +#define PCI_DEVICE_ID_NEO_2DB9PRI 0x00C9 +#define PCI_DEVICE_ID_NEO_2RJ45 0x00CA +#define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB +#define PCIE_DEVICE_ID_NEO_4_IBM 0x00F4 + +#define PCI_VENDOR_ID_XIRCOM 0x115d +#define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101 +#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 + +#define PCI_VENDOR_ID_SERVERWORKS 0x1166 +#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 +#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 +#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 +#define PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB 0x0036 +#define PCI_DEVICE_ID_SERVERWORKS_EPB 0x0103 +#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 +#define PCI_DEVICE_ID_SERVERWORKS_HT1000SB 0x0205 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 +#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227 +#define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408 + +#define PCI_VENDOR_ID_ALTERA 0x1172 + +#define PCI_VENDOR_ID_SBE 0x1176 +#define PCI_DEVICE_ID_SBE_WANXL100 0x0301 +#define PCI_DEVICE_ID_SBE_WANXL200 0x0302 +#define PCI_DEVICE_ID_SBE_WANXL400 0x0104 +#define PCI_SUBDEVICE_ID_SBE_T3E3 0x0009 +#define PCI_SUBDEVICE_ID_SBE_2T3E3_P0 0x0901 +#define PCI_SUBDEVICE_ID_SBE_2T3E3_P1 0x0902 + +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1 0x0101 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2 0x0102 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_3 0x0103 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_5 0x0105 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f +#define PCI_DEVICE_ID_TOSHIBA_TOPIC100 0x0617 + +#define PCI_VENDOR_ID_TOSHIBA_2 0x102f +#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 +#define PCI_DEVICE_ID_TOSHIBA_TC35815_NWU 0x0031 +#define PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939 0x0032 +#define PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE 0x0105 +#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108 +#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3 + +#define PCI_VENDOR_ID_ATTO 0x117c + +#define PCI_VENDOR_ID_RICOH 0x1180 +#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 +#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 +#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 +#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 +#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 +#define PCI_DEVICE_ID_RICOH_R5C822 0x0822 +#define PCI_DEVICE_ID_RICOH_R5CE822 0xe822 +#define PCI_DEVICE_ID_RICOH_R5CE823 0xe823 +#define PCI_DEVICE_ID_RICOH_R5C832 0x0832 +#define PCI_DEVICE_ID_RICOH_R5C843 0x0843 + +#define PCI_VENDOR_ID_DLINK 0x1186 +#define PCI_DEVICE_ID_DLINK_DGE510T 0x4c00 + +#define PCI_VENDOR_ID_ARTOP 0x1191 +#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 +#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 +#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 +#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008 +#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009 +#define PCI_DEVICE_ID_ARTOP_ATP867A 0x000A +#define PCI_DEVICE_ID_ARTOP_ATP867B 0x000B +#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 +#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 +#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 +#define PCI_DEVICE_ID_ARTOP_AEC7612S 0x8030 +#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040 +#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050 +#define PCI_DEVICE_ID_ARTOP_8060 0x8060 + +#define PCI_VENDOR_ID_ZEITNET 0x1193 +#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 +#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 + +#define PCI_VENDOR_ID_FUJITSU_ME 0x119e +#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 +#define PCI_DEVICE_ID_FUJITSU_FS50 0x0003 + +#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9 +#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 + +#define PCI_VENDOR_ID_MARVELL 0x11ab +#define PCI_VENDOR_ID_MARVELL_EXT 0x1b4b +#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146 +#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430 +#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460 +#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480 +#define PCI_DEVICE_ID_MARVELL_88ALP01_NAND 0x4100 +#define PCI_DEVICE_ID_MARVELL_88ALP01_SD 0x4101 +#define PCI_DEVICE_ID_MARVELL_88ALP01_CCIC 0x4102 + +#define PCI_VENDOR_ID_V3 0x11b0 +#define PCI_DEVICE_ID_V3_V960 0x0001 +#define PCI_DEVICE_ID_V3_V351 0x0002 + +#define PCI_VENDOR_ID_ATT 0x11c1 +#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 + +#define PCI_VENDOR_ID_SPECIALIX 0x11cb +#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 + +#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 +#define PCI_DEVICE_ID_AD1889JS 0x1889 + +#define PCI_DEVICE_ID_SEGA_BBA 0x1234 + +#define PCI_VENDOR_ID_ZORAN 0x11de +#define PCI_DEVICE_ID_ZORAN_36057 0x6057 +#define PCI_DEVICE_ID_ZORAN_36120 0x6120 + +#define PCI_VENDOR_ID_COMPEX 0x11f6 +#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 + +#define PCI_VENDOR_ID_PMC_Sierra 0x11f8 +#define PCI_VENDOR_ID_MICROSEMI 0x11f8 + +#define PCI_VENDOR_ID_RP 0x11fe +#define PCI_DEVICE_ID_RP32INTF 0x0001 +#define PCI_DEVICE_ID_RP8INTF 0x0002 +#define PCI_DEVICE_ID_RP16INTF 0x0003 +#define PCI_DEVICE_ID_RP4QUAD 0x0004 +#define PCI_DEVICE_ID_RP8OCTA 0x0005 +#define PCI_DEVICE_ID_RP8J 0x0006 +#define PCI_DEVICE_ID_RP4J 0x0007 +#define PCI_DEVICE_ID_RP8SNI 0x0008 +#define PCI_DEVICE_ID_RP16SNI 0x0009 +#define PCI_DEVICE_ID_RPP4 0x000A +#define PCI_DEVICE_ID_RPP8 0x000B +#define PCI_DEVICE_ID_RP4M 0x000D +#define PCI_DEVICE_ID_RP2_232 0x000E +#define PCI_DEVICE_ID_RP2_422 0x000F +#define PCI_DEVICE_ID_URP32INTF 0x0801 +#define PCI_DEVICE_ID_URP8INTF 0x0802 +#define PCI_DEVICE_ID_URP16INTF 0x0803 +#define PCI_DEVICE_ID_URP8OCTA 0x0805 +#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C +#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D +#define PCI_DEVICE_ID_CRP16INTF 0x0903 + +#define PCI_VENDOR_ID_CYCLADES 0x120e +#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 +#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 +#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102 +#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103 +#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104 +#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105 +#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 +#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 +#define PCI_DEVICE_ID_PC300_RX_2 0x0300 +#define PCI_DEVICE_ID_PC300_RX_1 0x0301 +#define PCI_DEVICE_ID_PC300_TE_2 0x0310 +#define PCI_DEVICE_ID_PC300_TE_1 0x0311 +#define PCI_DEVICE_ID_PC300_TE_M_2 0x0320 +#define PCI_DEVICE_ID_PC300_TE_M_1 0x0321 + +#define PCI_VENDOR_ID_ESSENTIAL 0x120f +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 + +#define PCI_VENDOR_ID_O2 0x1217 +#define PCI_DEVICE_ID_O2_6729 0x6729 +#define PCI_DEVICE_ID_O2_6730 0x673a +#define PCI_DEVICE_ID_O2_6832 0x6832 +#define PCI_DEVICE_ID_O2_6836 0x6836 +#define PCI_DEVICE_ID_O2_6812 0x6872 +#define PCI_DEVICE_ID_O2_6933 0x6933 +#define PCI_DEVICE_ID_O2_8120 0x8120 +#define PCI_DEVICE_ID_O2_8220 0x8220 +#define PCI_DEVICE_ID_O2_8221 0x8221 +#define PCI_DEVICE_ID_O2_8320 0x8320 +#define PCI_DEVICE_ID_O2_8321 0x8321 + +#define PCI_VENDOR_ID_3DFX 0x121a +#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 +#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 +#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003 +#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 +#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 + +#define PCI_VENDOR_ID_AVM 0x1244 +#define PCI_DEVICE_ID_AVM_B1 0x0700 +#define PCI_DEVICE_ID_AVM_C4 0x0800 +#define PCI_DEVICE_ID_AVM_A1 0x0a00 +#define PCI_DEVICE_ID_AVM_A1_V2 0x0e00 +#define PCI_DEVICE_ID_AVM_C2 0x1100 +#define PCI_DEVICE_ID_AVM_T1 0x1200 + +#define PCI_VENDOR_ID_STALLION 0x124d + +/* Allied Telesyn */ +#define PCI_VENDOR_ID_AT 0x1259 +#define PCI_SUBDEVICE_ID_AT_2700FX 0x2701 +#define PCI_SUBDEVICE_ID_AT_2701FX 0x2703 + +#define PCI_VENDOR_ID_ESS 0x125d +#define PCI_DEVICE_ID_ESS_ESS1968 0x1968 +#define PCI_DEVICE_ID_ESS_ESS1978 0x1978 +#define PCI_DEVICE_ID_ESS_ALLEGRO_1 0x1988 +#define PCI_DEVICE_ID_ESS_ALLEGRO 0x1989 +#define PCI_DEVICE_ID_ESS_CANYON3D_2LE 0x1990 +#define PCI_DEVICE_ID_ESS_CANYON3D_2 0x1992 +#define PCI_DEVICE_ID_ESS_MAESTRO3 0x1998 +#define PCI_DEVICE_ID_ESS_MAESTRO3_1 0x1999 +#define PCI_DEVICE_ID_ESS_MAESTRO3_HW 0x199a +#define PCI_DEVICE_ID_ESS_MAESTRO3_2 0x199b + +#define PCI_VENDOR_ID_SATSAGEM 0x1267 +#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 + +#define PCI_VENDOR_ID_ENSONIQ 0x1274 +#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 +#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 +#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 + +#define PCI_VENDOR_ID_TRANSMETA 0x1279 +#define PCI_DEVICE_ID_EFFICEON 0x0060 + +#define PCI_VENDOR_ID_ROCKWELL 0x127A + +#define PCI_VENDOR_ID_ITE 0x1283 +#define PCI_DEVICE_ID_ITE_8172 0x8172 +#define PCI_DEVICE_ID_ITE_8211 0x8211 +#define PCI_DEVICE_ID_ITE_8212 0x8212 +#define PCI_DEVICE_ID_ITE_8213 0x8213 +#define PCI_DEVICE_ID_ITE_8152 0x8152 +#define PCI_DEVICE_ID_ITE_8872 0x8872 +#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 + +/* formerly Platform Tech */ +#define PCI_DEVICE_ID_ESS_ESS0100 0x0100 + +#define PCI_VENDOR_ID_ALTEON 0x12ae + +#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ 0x000C +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM 0x000D +#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI 0x0100 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2 0x0201 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4 0x0202 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232 0x0300 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232 0x0301 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232 0x0302 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1 0x0310 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2 0x0311 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4 0x0312 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2 0x0320 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4 0x0321 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8 0x0322 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485 0x0330 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485 0x0331 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485 0x0332 + +#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 + +#define PCI_VENDOR_ID_PERICOM 0x12D8 +#define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 +#define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 +#define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 +#define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 + +#define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16 0x0011 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC 0x0041 +#define PCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4 0xF001 +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8 0xF010 + +#define PCI_VENDOR_ID_AUREAL 0x12eb +#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001 +#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002 +#define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003 + +#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8 +#define PCI_DEVICE_ID_LML_33R10 0x8a02 + +#define PCI_VENDOR_ID_ESDGMBH 0x12fe +#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111 + +#define PCI_VENDOR_ID_CB 0x1307 /* Measurement Computing */ + +#define PCI_VENDOR_ID_SIIG 0x131f +#define PCI_SUBVENDOR_ID_SIIG 0x131f +#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 +#define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001 +#define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012 +#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020 +#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021 +#define PCI_DEVICE_ID_SIIG_2S_10x_550 0x1030 +#define PCI_DEVICE_ID_SIIG_2S_10x_650 0x1031 +#define PCI_DEVICE_ID_SIIG_2S_10x_850 0x1032 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036 +#define PCI_DEVICE_ID_SIIG_4S_10x_550 0x1050 +#define PCI_DEVICE_ID_SIIG_4S_10x_650 0x1051 +#define PCI_DEVICE_ID_SIIG_4S_10x_850 0x1052 +#define PCI_DEVICE_ID_SIIG_1S_20x_550 0x2000 +#define PCI_DEVICE_ID_SIIG_1S_20x_650 0x2001 +#define PCI_DEVICE_ID_SIIG_1S_20x_850 0x2002 +#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020 +#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021 +#define PCI_DEVICE_ID_SIIG_2S_20x_550 0x2030 +#define PCI_DEVICE_ID_SIIG_2S_20x_650 0x2031 +#define PCI_DEVICE_ID_SIIG_2S_20x_850 0x2032 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012 +#define PCI_DEVICE_ID_SIIG_4S_20x_550 0x2050 +#define PCI_DEVICE_ID_SIIG_4S_20x_650 0x2051 +#define PCI_DEVICE_ID_SIIG_4S_20x_850 0x2052 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 +#define PCI_DEVICE_ID_SIIG_8S_20x_550 0x2080 +#define PCI_DEVICE_ID_SIIG_8S_20x_650 0x2081 +#define PCI_DEVICE_ID_SIIG_8S_20x_850 0x2082 +#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL 0x2050 + +#define PCI_VENDOR_ID_RADISYS 0x1331 + +#define PCI_VENDOR_ID_MICRO_MEMORY 0x1332 +#define PCI_DEVICE_ID_MICRO_MEMORY_5415CN 0x5415 +#define PCI_DEVICE_ID_MICRO_MEMORY_5425CN 0x5425 +#define PCI_DEVICE_ID_MICRO_MEMORY_6155 0x6155 + +#define PCI_VENDOR_ID_DOMEX 0x134a +#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 + +#define PCI_VENDOR_ID_INTASHIELD 0x135a +#define PCI_DEVICE_ID_INTASHIELD_IS200 0x0d80 +#define PCI_DEVICE_ID_INTASHIELD_IS400 0x0dc0 + +#define PCI_VENDOR_ID_QUATECH 0x135C +#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 +#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 +#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030 +#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040 +#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 +#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 +#define PCI_DEVICE_ID_QUATECH_QSCP100 0x0120 +#define PCI_DEVICE_ID_QUATECH_DSCP100 0x0130 +#define PCI_DEVICE_ID_QUATECH_QSCP200 0x0140 +#define PCI_DEVICE_ID_QUATECH_DSCP200 0x0150 +#define PCI_DEVICE_ID_QUATECH_QSCLP100 0x0170 +#define PCI_DEVICE_ID_QUATECH_DSCLP100 0x0180 +#define PCI_DEVICE_ID_QUATECH_DSC100E 0x0181 +#define PCI_DEVICE_ID_QUATECH_SSCLP100 0x0190 +#define PCI_DEVICE_ID_QUATECH_QSCLP200 0x01A0 +#define PCI_DEVICE_ID_QUATECH_DSCLP200 0x01B0 +#define PCI_DEVICE_ID_QUATECH_DSC200E 0x01B1 +#define PCI_DEVICE_ID_QUATECH_SSCLP200 0x01C0 +#define PCI_DEVICE_ID_QUATECH_ESCLP100 0x01E0 +#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278 + +#define PCI_VENDOR_ID_SEALEVEL 0x135e +#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 +#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 +#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 +#define PCI_DEVICE_ID_SEALEVEL_7803 0x7803 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM8 0x7804 + +#define PCI_VENDOR_ID_HYPERCOPE 0x1365 +#define PCI_DEVICE_ID_HYPERCOPE_PLX 0x9050 +#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO 0x0104 +#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106 +#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107 +#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108 + +#define PCI_VENDOR_ID_DIGIGRAM 0x1369 +#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM 0xc001 +#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM 0xc002 +#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_SERIAL_SUBSYSTEM 0xc021 +#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_CAE_SERIAL_SUBSYSTEM 0xc022 + +#define PCI_VENDOR_ID_KAWASAKI 0x136b +#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01 + +#define PCI_VENDOR_ID_CNET 0x1371 +#define PCI_DEVICE_ID_CNET_GIGACARD 0x434e + +#define PCI_VENDOR_ID_LMC 0x1376 +#define PCI_DEVICE_ID_LMC_HSSI 0x0003 +#define PCI_DEVICE_ID_LMC_DS3 0x0004 +#define PCI_DEVICE_ID_LMC_SSI 0x0005 +#define PCI_DEVICE_ID_LMC_T1 0x0006 + +#define PCI_VENDOR_ID_NETGEAR 0x1385 +#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a + +#define PCI_VENDOR_ID_APPLICOM 0x1389 +#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001 +#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002 +#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003 + +#define PCI_VENDOR_ID_MOXA 0x1393 +#define PCI_DEVICE_ID_MOXA_RC7000 0x0001 +#define PCI_DEVICE_ID_MOXA_CP102 0x1020 +#define PCI_DEVICE_ID_MOXA_CP102UL 0x1021 +#define PCI_DEVICE_ID_MOXA_CP102U 0x1022 +#define PCI_DEVICE_ID_MOXA_C104 0x1040 +#define PCI_DEVICE_ID_MOXA_CP104U 0x1041 +#define PCI_DEVICE_ID_MOXA_CP104JU 0x1042 +#define PCI_DEVICE_ID_MOXA_CP104EL 0x1043 +#define PCI_DEVICE_ID_MOXA_CT114 0x1140 +#define PCI_DEVICE_ID_MOXA_CP114 0x1141 +#define PCI_DEVICE_ID_MOXA_CP118U 0x1180 +#define PCI_DEVICE_ID_MOXA_CP118EL 0x1181 +#define PCI_DEVICE_ID_MOXA_CP132 0x1320 +#define PCI_DEVICE_ID_MOXA_CP132U 0x1321 +#define PCI_DEVICE_ID_MOXA_CP134U 0x1340 +#define PCI_DEVICE_ID_MOXA_C168 0x1680 +#define PCI_DEVICE_ID_MOXA_CP168U 0x1681 +#define PCI_DEVICE_ID_MOXA_CP168EL 0x1682 +#define PCI_DEVICE_ID_MOXA_CP204J 0x2040 +#define PCI_DEVICE_ID_MOXA_C218 0x2180 +#define PCI_DEVICE_ID_MOXA_C320 0x3200 + +#define PCI_VENDOR_ID_CCD 0x1397 +#define PCI_DEVICE_ID_CCD_HFC4S 0x08B4 +#define PCI_SUBDEVICE_ID_CCD_PMX2S 0x1234 +#define PCI_DEVICE_ID_CCD_HFC8S 0x16B8 +#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0 +#define PCI_DEVICE_ID_CCD_HFCE1 0x30B1 +#define PCI_SUBDEVICE_ID_CCD_SPD4S 0x3136 +#define PCI_SUBDEVICE_ID_CCD_SPDE1 0x3137 +#define PCI_DEVICE_ID_CCD_B000 0xb000 +#define PCI_DEVICE_ID_CCD_B006 0xb006 +#define PCI_DEVICE_ID_CCD_B007 0xb007 +#define PCI_DEVICE_ID_CCD_B008 0xb008 +#define PCI_DEVICE_ID_CCD_B009 0xb009 +#define PCI_DEVICE_ID_CCD_B00A 0xb00a +#define PCI_DEVICE_ID_CCD_B00B 0xb00b +#define PCI_DEVICE_ID_CCD_B00C 0xb00c +#define PCI_DEVICE_ID_CCD_B100 0xb100 +#define PCI_SUBDEVICE_ID_CCD_IOB4ST 0xB520 +#define PCI_SUBDEVICE_ID_CCD_IOB8STR 0xB521 +#define PCI_SUBDEVICE_ID_CCD_IOB8ST 0xB522 +#define PCI_SUBDEVICE_ID_CCD_IOB1E1 0xB523 +#define PCI_SUBDEVICE_ID_CCD_SWYX4S 0xB540 +#define PCI_SUBDEVICE_ID_CCD_JH4S20 0xB550 +#define PCI_SUBDEVICE_ID_CCD_IOB8ST_1 0xB552 +#define PCI_SUBDEVICE_ID_CCD_JHSE1 0xB553 +#define PCI_SUBDEVICE_ID_CCD_JH8S 0xB55B +#define PCI_SUBDEVICE_ID_CCD_BN4S 0xB560 +#define PCI_SUBDEVICE_ID_CCD_BN8S 0xB562 +#define PCI_SUBDEVICE_ID_CCD_BNE1 0xB563 +#define PCI_SUBDEVICE_ID_CCD_BNE1D 0xB564 +#define PCI_SUBDEVICE_ID_CCD_BNE1DP 0xB565 +#define PCI_SUBDEVICE_ID_CCD_BN2S 0xB566 +#define PCI_SUBDEVICE_ID_CCD_BN1SM 0xB567 +#define PCI_SUBDEVICE_ID_CCD_BN4SM 0xB568 +#define PCI_SUBDEVICE_ID_CCD_BN2SM 0xB569 +#define PCI_SUBDEVICE_ID_CCD_BNE1M 0xB56A +#define PCI_SUBDEVICE_ID_CCD_BN8SP 0xB56B +#define PCI_SUBDEVICE_ID_CCD_HFC4S 0xB620 +#define PCI_SUBDEVICE_ID_CCD_HFC8S 0xB622 +#define PCI_DEVICE_ID_CCD_B700 0xb700 +#define PCI_DEVICE_ID_CCD_B701 0xb701 +#define PCI_SUBDEVICE_ID_CCD_HFCE1 0xC523 +#define PCI_SUBDEVICE_ID_CCD_OV2S 0xE884 +#define PCI_SUBDEVICE_ID_CCD_OV4S 0xE888 +#define PCI_SUBDEVICE_ID_CCD_OV8S 0xE998 + +#define PCI_VENDOR_ID_EXAR 0x13a8 +#define PCI_DEVICE_ID_EXAR_XR17C152 0x0152 +#define PCI_DEVICE_ID_EXAR_XR17C154 0x0154 +#define PCI_DEVICE_ID_EXAR_XR17C158 0x0158 +#define PCI_DEVICE_ID_EXAR_XR17V352 0x0352 +#define PCI_DEVICE_ID_EXAR_XR17V354 0x0354 +#define PCI_DEVICE_ID_EXAR_XR17V358 0x0358 + +#define PCI_VENDOR_ID_MICROGATE 0x13c0 +#define PCI_DEVICE_ID_MICROGATE_USC 0x0010 +#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 + +#define PCI_VENDOR_ID_3WARE 0x13C1 +#define PCI_DEVICE_ID_3WARE_1000 0x1000 +#define PCI_DEVICE_ID_3WARE_7000 0x1001 +#define PCI_DEVICE_ID_3WARE_9000 0x1002 + +#define PCI_VENDOR_ID_IOMEGA 0x13ca +#define PCI_DEVICE_ID_IOMEGA_BUZ 0x4231 + +#define PCI_VENDOR_ID_ABOCOM 0x13D1 +#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 + +#define PCI_VENDOR_ID_SUNDANCE 0x13f0 + +#define PCI_VENDOR_ID_CMEDIA 0x13f6 +#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 +#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 +#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 +#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 + +#define PCI_VENDOR_ID_ADVANTECH 0x13fe + +#define PCI_VENDOR_ID_MEILHAUS 0x1402 + +#define PCI_VENDOR_ID_LAVA 0x1407 +#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ +#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUATTRO_A 0x0120 /* 2x 16550A, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUATTRO_B 0x0121 /* 2x 16550A, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_A 0x0180 /* 4x 16550A, half of 8 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_B 0x0181 /* 4x 16550A, half of 8 port */ +#define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */ +#define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_SSERIAL 0x0500 /* 1x 16550 */ +#define PCI_DEVICE_ID_LAVA_PORT_650 0x0600 /* 1x 16650 */ +#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000 +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */ +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */ +#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800 + +#define PCI_VENDOR_ID_TIMEDIA 0x1409 +#define PCI_DEVICE_ID_TIMEDIA_1889 0x7168 + +#define PCI_VENDOR_ID_ICE 0x1412 +#define PCI_DEVICE_ID_ICE_1712 0x1712 +#define PCI_DEVICE_ID_VT1724 0x1724 + +#define PCI_VENDOR_ID_OXSEMI 0x1415 +#define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403 +#define PCI_DEVICE_ID_OXSEMI_PCIe840 0xC000 +#define PCI_DEVICE_ID_OXSEMI_PCIe840_G 0xC004 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_0 0xC100 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G 0xC104 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1 0xC110 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G 0xC114 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U 0xC118 +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU 0xC11C +#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501 +#define PCI_DEVICE_ID_OXSEMI_C950 0x950B +#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511 +#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513 +#define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521 +#define PCI_DEVICE_ID_OXSEMI_16PCI952PP 0x9523 +#define PCI_SUBDEVICE_ID_OXSEMI_C950 0x0001 + +#define PCI_VENDOR_ID_CHELSIO 0x1425 + +#define PCI_VENDOR_ID_ADLINK 0x144a + +#define PCI_VENDOR_ID_SAMSUNG 0x144d + +#define PCI_VENDOR_ID_GIGABYTE 0x1458 + +#define PCI_VENDOR_ID_AMBIT 0x1468 + +#define PCI_VENDOR_ID_MYRICOM 0x14c1 + +#define PCI_VENDOR_ID_MEDIATEK 0x14c3 +#define PCI_DEVICE_ID_MEDIATEK_7629 0x7629 + +#define PCI_VENDOR_ID_TITAN 0x14D2 +#define PCI_DEVICE_ID_TITAN_010L 0x8001 +#define PCI_DEVICE_ID_TITAN_100L 0x8010 +#define PCI_DEVICE_ID_TITAN_110L 0x8011 +#define PCI_DEVICE_ID_TITAN_200L 0x8020 +#define PCI_DEVICE_ID_TITAN_210L 0x8021 +#define PCI_DEVICE_ID_TITAN_400L 0x8040 +#define PCI_DEVICE_ID_TITAN_800L 0x8080 +#define PCI_DEVICE_ID_TITAN_100 0xA001 +#define PCI_DEVICE_ID_TITAN_200 0xA005 +#define PCI_DEVICE_ID_TITAN_400 0xA003 +#define PCI_DEVICE_ID_TITAN_800B 0xA004 + +#define PCI_VENDOR_ID_PANACOM 0x14d4 +#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 +#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 + +#define PCI_VENDOR_ID_SIPACKETS 0x14d9 +#define PCI_DEVICE_ID_SP1011 0x0010 + +#define PCI_VENDOR_ID_AFAVLAB 0x14db +#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 +#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 +#define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150 + +#define PCI_VENDOR_ID_AMPLICON 0x14dc + +#define PCI_VENDOR_ID_BCM_GVC 0x14a4 +#define PCI_VENDOR_ID_BROADCOM 0x14e4 +#define PCI_DEVICE_ID_TIGON3_5752 0x1600 +#define PCI_DEVICE_ID_TIGON3_5752M 0x1601 +#define PCI_DEVICE_ID_NX2_5709 0x1639 +#define PCI_DEVICE_ID_NX2_5709S 0x163a +#define PCI_DEVICE_ID_TIGON3_5700 0x1644 +#define PCI_DEVICE_ID_TIGON3_5701 0x1645 +#define PCI_DEVICE_ID_TIGON3_5702 0x1646 +#define PCI_DEVICE_ID_TIGON3_5703 0x1647 +#define PCI_DEVICE_ID_TIGON3_5704 0x1648 +#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649 +#define PCI_DEVICE_ID_NX2_5706 0x164a +#define PCI_DEVICE_ID_NX2_5708 0x164c +#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d +#define PCI_DEVICE_ID_NX2_57710 0x164e +#define PCI_DEVICE_ID_NX2_57711 0x164f +#define PCI_DEVICE_ID_NX2_57711E 0x1650 +#define PCI_DEVICE_ID_TIGON3_5705 0x1653 +#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 +#define PCI_DEVICE_ID_TIGON3_5719 0x1657 +#define PCI_DEVICE_ID_TIGON3_5721 0x1659 +#define PCI_DEVICE_ID_TIGON3_5722 0x165a +#define PCI_DEVICE_ID_TIGON3_5723 0x165b +#define PCI_DEVICE_ID_TIGON3_5705M 0x165d +#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e +#define PCI_DEVICE_ID_NX2_57712 0x1662 +#define PCI_DEVICE_ID_NX2_57712E 0x1663 +#define PCI_DEVICE_ID_NX2_57712_MF 0x1663 +#define PCI_DEVICE_ID_TIGON3_5714 0x1668 +#define PCI_DEVICE_ID_TIGON3_5714S 0x1669 +#define PCI_DEVICE_ID_TIGON3_5780 0x166a +#define PCI_DEVICE_ID_TIGON3_5780S 0x166b +#define PCI_DEVICE_ID_TIGON3_5705F 0x166e +#define PCI_DEVICE_ID_NX2_57712_VF 0x166f +#define PCI_DEVICE_ID_TIGON3_5754M 0x1672 +#define PCI_DEVICE_ID_TIGON3_5755M 0x1673 +#define PCI_DEVICE_ID_TIGON3_5756 0x1674 +#define PCI_DEVICE_ID_TIGON3_5750 0x1676 +#define PCI_DEVICE_ID_TIGON3_5751 0x1677 +#define PCI_DEVICE_ID_TIGON3_5715 0x1678 +#define PCI_DEVICE_ID_TIGON3_5715S 0x1679 +#define PCI_DEVICE_ID_TIGON3_5754 0x167a +#define PCI_DEVICE_ID_TIGON3_5755 0x167b +#define PCI_DEVICE_ID_TIGON3_5751M 0x167d +#define PCI_DEVICE_ID_TIGON3_5751F 0x167e +#define PCI_DEVICE_ID_TIGON3_5787F 0x167f +#define PCI_DEVICE_ID_TIGON3_5761E 0x1680 +#define PCI_DEVICE_ID_TIGON3_5761 0x1681 +#define PCI_DEVICE_ID_TIGON3_5764 0x1684 +#define PCI_DEVICE_ID_NX2_57800 0x168a +#define PCI_DEVICE_ID_NX2_57840 0x168d +#define PCI_DEVICE_ID_NX2_57810 0x168e +#define PCI_DEVICE_ID_TIGON3_5787M 0x1693 +#define PCI_DEVICE_ID_TIGON3_5782 0x1696 +#define PCI_DEVICE_ID_TIGON3_5784 0x1698 +#define PCI_DEVICE_ID_TIGON3_5786 0x169a +#define PCI_DEVICE_ID_TIGON3_5787 0x169b +#define PCI_DEVICE_ID_TIGON3_5788 0x169c +#define PCI_DEVICE_ID_TIGON3_5789 0x169d +#define PCI_DEVICE_ID_NX2_57840_4_10 0x16a1 +#define PCI_DEVICE_ID_NX2_57840_2_20 0x16a2 +#define PCI_DEVICE_ID_NX2_57840_MF 0x16a4 +#define PCI_DEVICE_ID_NX2_57800_MF 0x16a5 +#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 +#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 +#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 +#define PCI_DEVICE_ID_NX2_57800_VF 0x16a9 +#define PCI_DEVICE_ID_NX2_5706S 0x16aa +#define PCI_DEVICE_ID_NX2_5708S 0x16ac +#define PCI_DEVICE_ID_NX2_57840_VF 0x16ad +#define PCI_DEVICE_ID_NX2_57810_MF 0x16ae +#define PCI_DEVICE_ID_NX2_57810_VF 0x16af +#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 +#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 +#define PCI_DEVICE_ID_TIGON3_5781 0x16dd +#define PCI_DEVICE_ID_TIGON3_5753 0x16f7 +#define PCI_DEVICE_ID_TIGON3_5753M 0x16fd +#define PCI_DEVICE_ID_TIGON3_5753F 0x16fe +#define PCI_DEVICE_ID_TIGON3_5901 0x170d +#define PCI_DEVICE_ID_BCM4401B1 0x170c +#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e +#define PCI_DEVICE_ID_TIGON3_5906 0x1712 +#define PCI_DEVICE_ID_TIGON3_5906M 0x1713 +#define PCI_DEVICE_ID_BCM4401 0x4401 +#define PCI_DEVICE_ID_BCM4401B0 0x4402 + +#define PCI_VENDOR_ID_TOPIC 0x151f +#define PCI_DEVICE_ID_TOPIC_TP560 0x0000 + +#define PCI_VENDOR_ID_MAINPINE 0x1522 +#define PCI_DEVICE_ID_MAINPINE_PBRIDGE 0x0100 +#define PCI_VENDOR_ID_ENE 0x1524 +#define PCI_DEVICE_ID_ENE_CB710_FLASH 0x0510 +#define PCI_DEVICE_ID_ENE_CB712_SD 0x0550 +#define PCI_DEVICE_ID_ENE_CB712_SD_2 0x0551 +#define PCI_DEVICE_ID_ENE_CB714_SD 0x0750 +#define PCI_DEVICE_ID_ENE_CB714_SD_2 0x0751 +#define PCI_DEVICE_ID_ENE_1211 0x1211 +#define PCI_DEVICE_ID_ENE_1225 0x1225 +#define PCI_DEVICE_ID_ENE_1410 0x1410 +#define PCI_DEVICE_ID_ENE_710 0x1411 +#define PCI_DEVICE_ID_ENE_712 0x1412 +#define PCI_DEVICE_ID_ENE_1420 0x1420 +#define PCI_DEVICE_ID_ENE_720 0x1421 +#define PCI_DEVICE_ID_ENE_722 0x1422 + +#define PCI_SUBVENDOR_ID_PERLE 0x155f +#define PCI_SUBDEVICE_ID_PCI_RAS4 0xf001 +#define PCI_SUBDEVICE_ID_PCI_RAS8 0xf010 + +#define PCI_VENDOR_ID_SYBA 0x1592 +#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 +#define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 + +#define PCI_VENDOR_ID_MORETON 0x15aa +#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000 + +#define PCI_VENDOR_ID_VMWARE 0x15ad +#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07b0 + +#define PCI_VENDOR_ID_ZOLTRIX 0x15b0 +#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0 + +#define PCI_VENDOR_ID_MELLANOX 0x15b3 +#define PCI_DEVICE_ID_MELLANOX_CONNECTX3 0x1003 +#define PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO 0x1007 +#define PCI_DEVICE_ID_MELLANOX_CONNECTIB 0x1011 +#define PCI_DEVICE_ID_MELLANOX_CONNECTX4 0x1013 +#define PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX 0x1015 +#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 +#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 +#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c +#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 +#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 +#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 +#define PCI_DEVICE_ID_MELLANOX_HERMON_SDR 0x6340 +#define PCI_DEVICE_ID_MELLANOX_HERMON_DDR 0x634a +#define PCI_DEVICE_ID_MELLANOX_HERMON_QDR 0x6354 +#define PCI_DEVICE_ID_MELLANOX_HERMON_EN 0x6368 +#define PCI_DEVICE_ID_MELLANOX_CONNECTX_EN 0x6372 +#define PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2 0x6732 +#define PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2 0x673c +#define PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2 0x6746 +#define PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2 0x6750 +#define PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2 0x675a +#define PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2 0x6764 +#define PCI_DEVICE_ID_MELLANOX_CONNECTX2 0x676e + +#define PCI_VENDOR_ID_DFI 0x15bd + +#define PCI_VENDOR_ID_QUICKNET 0x15e2 +#define PCI_DEVICE_ID_QUICKNET_XJ 0x0500 + +/* + * ADDI-DATA GmbH communication cards + */ +#define PCI_VENDOR_ID_ADDIDATA 0x15B8 +#define PCI_DEVICE_ID_ADDIDATA_APCI7500 0x7000 +#define PCI_DEVICE_ID_ADDIDATA_APCI7420 0x7001 +#define PCI_DEVICE_ID_ADDIDATA_APCI7300 0x7002 +#define PCI_DEVICE_ID_ADDIDATA_APCI7500_2 0x7009 +#define PCI_DEVICE_ID_ADDIDATA_APCI7420_2 0x700A +#define PCI_DEVICE_ID_ADDIDATA_APCI7300_2 0x700B +#define PCI_DEVICE_ID_ADDIDATA_APCI7500_3 0x700C +#define PCI_DEVICE_ID_ADDIDATA_APCI7420_3 0x700D +#define PCI_DEVICE_ID_ADDIDATA_APCI7300_3 0x700E +#define PCI_DEVICE_ID_ADDIDATA_APCI7800_3 0x700F +#define PCI_DEVICE_ID_ADDIDATA_APCIe7300 0x7010 +#define PCI_DEVICE_ID_ADDIDATA_APCIe7420 0x7011 +#define PCI_DEVICE_ID_ADDIDATA_APCIe7500 0x7012 +#define PCI_DEVICE_ID_ADDIDATA_APCIe7800 0x7013 + +#define PCI_VENDOR_ID_PDC 0x15e9 + +#define PCI_VENDOR_ID_FARSITE 0x1619 +#define PCI_DEVICE_ID_FARSITE_T2P 0x0400 +#define PCI_DEVICE_ID_FARSITE_T4P 0x0440 +#define PCI_DEVICE_ID_FARSITE_T1U 0x0610 +#define PCI_DEVICE_ID_FARSITE_T2U 0x0620 +#define PCI_DEVICE_ID_FARSITE_T4U 0x0640 +#define PCI_DEVICE_ID_FARSITE_TE1 0x1610 +#define PCI_DEVICE_ID_FARSITE_TE1C 0x1612 + +#define PCI_VENDOR_ID_ARIMA 0x161f + +#define PCI_VENDOR_ID_BROCADE 0x1657 +#define PCI_DEVICE_ID_BROCADE_CT 0x0014 +#define PCI_DEVICE_ID_BROCADE_FC_8G1P 0x0017 +#define PCI_DEVICE_ID_BROCADE_CT_FC 0x0021 + +#define PCI_VENDOR_ID_SIBYTE 0x166d +#define PCI_DEVICE_ID_BCM1250_PCI 0x0001 +#define PCI_DEVICE_ID_BCM1250_HT 0x0002 + +#define PCI_VENDOR_ID_ATHEROS 0x168c + +#define PCI_VENDOR_ID_NETCELL 0x169c +#define PCI_DEVICE_ID_REVOLUTION 0x0044 + +#define PCI_VENDOR_ID_CENATEK 0x16CA +#define PCI_DEVICE_ID_CENATEK_IDE 0x0001 + +#define PCI_VENDOR_ID_SYNOPSYS 0x16c3 +#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd +#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce +#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf +#define PCI_DEVICE_ID_SYNOPSYS_EDDA 0xedda + +#define PCI_VENDOR_ID_USR 0x16ec + +#define PCI_VENDOR_ID_VITESSE 0x1725 +#define PCI_DEVICE_ID_VITESSE_VSC7174 0x7174 + +#define PCI_VENDOR_ID_LINKSYS 0x1737 +#define PCI_DEVICE_ID_LINKSYS_EG1064 0x1064 + +#define PCI_VENDOR_ID_ALTIMA 0x173b +#define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 +#define PCI_DEVICE_ID_ALTIMA_AC1001 0x03e9 +#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea +#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb + +#define PCI_VENDOR_ID_CAVIUM 0x177d + +#define PCI_VENDOR_ID_TECHWELL 0x1797 +#define PCI_DEVICE_ID_TECHWELL_6800 0x6800 +#define PCI_DEVICE_ID_TECHWELL_6801 0x6801 +#define PCI_DEVICE_ID_TECHWELL_6804 0x6804 +#define PCI_DEVICE_ID_TECHWELL_6816_1 0x6810 +#define PCI_DEVICE_ID_TECHWELL_6816_2 0x6811 +#define PCI_DEVICE_ID_TECHWELL_6816_3 0x6812 +#define PCI_DEVICE_ID_TECHWELL_6816_4 0x6813 + +#define PCI_VENDOR_ID_BELKIN 0x1799 +#define PCI_DEVICE_ID_BELKIN_F5D7010V7 0x701f + +#define PCI_VENDOR_ID_RDC 0x17f3 +#define PCI_DEVICE_ID_RDC_R6020 0x6020 +#define PCI_DEVICE_ID_RDC_R6030 0x6030 +#define PCI_DEVICE_ID_RDC_R6040 0x6040 +#define PCI_DEVICE_ID_RDC_R6060 0x6060 +#define PCI_DEVICE_ID_RDC_R6061 0x6061 +#define PCI_DEVICE_ID_RDC_D1010 0x1010 + +#define PCI_VENDOR_ID_GLI 0x17a0 + +#define PCI_VENDOR_ID_LENOVO 0x17aa + +#define PCI_VENDOR_ID_QCOM 0x17cb + +#define PCI_VENDOR_ID_CDNS 0x17cd + +#define PCI_VENDOR_ID_ARECA 0x17d3 +#define PCI_DEVICE_ID_ARECA_1110 0x1110 +#define PCI_DEVICE_ID_ARECA_1120 0x1120 +#define PCI_DEVICE_ID_ARECA_1130 0x1130 +#define PCI_DEVICE_ID_ARECA_1160 0x1160 +#define PCI_DEVICE_ID_ARECA_1170 0x1170 +#define PCI_DEVICE_ID_ARECA_1200 0x1200 +#define PCI_DEVICE_ID_ARECA_1201 0x1201 +#define PCI_DEVICE_ID_ARECA_1202 0x1202 +#define PCI_DEVICE_ID_ARECA_1210 0x1210 +#define PCI_DEVICE_ID_ARECA_1220 0x1220 +#define PCI_DEVICE_ID_ARECA_1230 0x1230 +#define PCI_DEVICE_ID_ARECA_1260 0x1260 +#define PCI_DEVICE_ID_ARECA_1270 0x1270 +#define PCI_DEVICE_ID_ARECA_1280 0x1280 +#define PCI_DEVICE_ID_ARECA_1380 0x1380 +#define PCI_DEVICE_ID_ARECA_1381 0x1381 +#define PCI_DEVICE_ID_ARECA_1680 0x1680 +#define PCI_DEVICE_ID_ARECA_1681 0x1681 + +#define PCI_VENDOR_ID_S2IO 0x17d5 +#define PCI_DEVICE_ID_S2IO_WIN 0x5731 +#define PCI_DEVICE_ID_S2IO_UNI 0x5831 +#define PCI_DEVICE_ID_HERC_WIN 0x5732 +#define PCI_DEVICE_ID_HERC_UNI 0x5832 + +#define PCI_VENDOR_ID_SITECOM 0x182d +#define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069 + +#define PCI_VENDOR_ID_TOPSPIN 0x1867 + +#define PCI_VENDOR_ID_COMMTECH 0x18f7 + +#define PCI_VENDOR_ID_SILAN 0x1904 + +#define PCI_VENDOR_ID_RENESAS 0x1912 +#define PCI_DEVICE_ID_RENESAS_SH7781 0x0001 +#define PCI_DEVICE_ID_RENESAS_SH7780 0x0002 +#define PCI_DEVICE_ID_RENESAS_SH7763 0x0004 +#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007 +#define PCI_DEVICE_ID_RENESAS_SH7786 0x0010 + +#define PCI_VENDOR_ID_SOLARFLARE 0x1924 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0 0x0703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1 0x6703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000B 0x0710 + +#define PCI_VENDOR_ID_TDI 0x192E +#define PCI_DEVICE_ID_TDI_EHCI 0x0101 + +#define PCI_VENDOR_ID_FREESCALE 0x1957 /* duplicate: NXP */ +#define PCI_VENDOR_ID_NXP 0x1957 /* duplicate: FREESCALE */ +#define PCI_DEVICE_ID_MPC8308 0xc006 +#define PCI_DEVICE_ID_MPC8315E 0x00b4 +#define PCI_DEVICE_ID_MPC8315 0x00b5 +#define PCI_DEVICE_ID_MPC8314E 0x00b6 +#define PCI_DEVICE_ID_MPC8314 0x00b7 +#define PCI_DEVICE_ID_MPC8378E 0x00c4 +#define PCI_DEVICE_ID_MPC8378 0x00c5 +#define PCI_DEVICE_ID_MPC8377E 0x00c6 +#define PCI_DEVICE_ID_MPC8377 0x00c7 +#define PCI_DEVICE_ID_MPC8548E 0x0012 +#define PCI_DEVICE_ID_MPC8548 0x0013 +#define PCI_DEVICE_ID_MPC8543E 0x0014 +#define PCI_DEVICE_ID_MPC8543 0x0015 +#define PCI_DEVICE_ID_MPC8547E 0x0018 +#define PCI_DEVICE_ID_MPC8545E 0x0019 +#define PCI_DEVICE_ID_MPC8545 0x001a +#define PCI_DEVICE_ID_MPC8569E 0x0061 +#define PCI_DEVICE_ID_MPC8569 0x0060 +#define PCI_DEVICE_ID_MPC8568E 0x0020 +#define PCI_DEVICE_ID_MPC8568 0x0021 +#define PCI_DEVICE_ID_MPC8567E 0x0022 +#define PCI_DEVICE_ID_MPC8567 0x0023 +#define PCI_DEVICE_ID_MPC8533E 0x0030 +#define PCI_DEVICE_ID_MPC8533 0x0031 +#define PCI_DEVICE_ID_MPC8544E 0x0032 +#define PCI_DEVICE_ID_MPC8544 0x0033 +#define PCI_DEVICE_ID_MPC8572E 0x0040 +#define PCI_DEVICE_ID_MPC8572 0x0041 +#define PCI_DEVICE_ID_MPC8536E 0x0050 +#define PCI_DEVICE_ID_MPC8536 0x0051 +#define PCI_DEVICE_ID_P2020E 0x0070 +#define PCI_DEVICE_ID_P2020 0x0071 +#define PCI_DEVICE_ID_P2010E 0x0078 +#define PCI_DEVICE_ID_P2010 0x0079 +#define PCI_DEVICE_ID_P1020E 0x0100 +#define PCI_DEVICE_ID_P1020 0x0101 +#define PCI_DEVICE_ID_P1021E 0x0102 +#define PCI_DEVICE_ID_P1021 0x0103 +#define PCI_DEVICE_ID_P1011E 0x0108 +#define PCI_DEVICE_ID_P1011 0x0109 +#define PCI_DEVICE_ID_P1022E 0x0110 +#define PCI_DEVICE_ID_P1022 0x0111 +#define PCI_DEVICE_ID_P1013E 0x0118 +#define PCI_DEVICE_ID_P1013 0x0119 +#define PCI_DEVICE_ID_P4080E 0x0400 +#define PCI_DEVICE_ID_P4080 0x0401 +#define PCI_DEVICE_ID_P4040E 0x0408 +#define PCI_DEVICE_ID_P4040 0x0409 +#define PCI_DEVICE_ID_P2040E 0x0410 +#define PCI_DEVICE_ID_P2040 0x0411 +#define PCI_DEVICE_ID_P3041E 0x041E +#define PCI_DEVICE_ID_P3041 0x041F +#define PCI_DEVICE_ID_P5020E 0x0420 +#define PCI_DEVICE_ID_P5020 0x0421 +#define PCI_DEVICE_ID_P5010E 0x0428 +#define PCI_DEVICE_ID_P5010 0x0429 +#define PCI_DEVICE_ID_MPC8641 0x7010 +#define PCI_DEVICE_ID_MPC8641D 0x7011 +#define PCI_DEVICE_ID_MPC8610 0x7018 + +#define PCI_VENDOR_ID_PASEMI 0x1959 + +#define PCI_VENDOR_ID_ATTANSIC 0x1969 +#define PCI_DEVICE_ID_ATTANSIC_L1 0x1048 +#define PCI_DEVICE_ID_ATTANSIC_L2 0x2048 + +#define PCI_VENDOR_ID_JMICRON 0x197B +#define PCI_DEVICE_ID_JMICRON_JMB360 0x2360 +#define PCI_DEVICE_ID_JMICRON_JMB361 0x2361 +#define PCI_DEVICE_ID_JMICRON_JMB362 0x2362 +#define PCI_DEVICE_ID_JMICRON_JMB363 0x2363 +#define PCI_DEVICE_ID_JMICRON_JMB364 0x2364 +#define PCI_DEVICE_ID_JMICRON_JMB365 0x2365 +#define PCI_DEVICE_ID_JMICRON_JMB366 0x2366 +#define PCI_DEVICE_ID_JMICRON_JMB368 0x2368 +#define PCI_DEVICE_ID_JMICRON_JMB369 0x2369 +#define PCI_DEVICE_ID_JMICRON_JMB38X_SD 0x2381 +#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382 +#define PCI_DEVICE_ID_JMICRON_JMB38X_MS 0x2383 +#define PCI_DEVICE_ID_JMICRON_JMB385_MS 0x2388 +#define PCI_DEVICE_ID_JMICRON_JMB388_SD 0x2391 +#define PCI_DEVICE_ID_JMICRON_JMB388_ESD 0x2392 +#define PCI_DEVICE_ID_JMICRON_JMB390_MS 0x2393 + +#define PCI_VENDOR_ID_KORENIX 0x1982 +#define PCI_DEVICE_ID_KORENIX_JETCARDF0 0x1600 +#define PCI_DEVICE_ID_KORENIX_JETCARDF1 0x16ff +#define PCI_DEVICE_ID_KORENIX_JETCARDF2 0x1700 +#define PCI_DEVICE_ID_KORENIX_JETCARDF3 0x17ff + +#define PCI_VENDOR_ID_HUAWEI 0x19e5 + +#define PCI_VENDOR_ID_NETRONOME 0x19ee +#define PCI_DEVICE_ID_NETRONOME_NFP4000 0x4000 +#define PCI_DEVICE_ID_NETRONOME_NFP5000 0x5000 +#define PCI_DEVICE_ID_NETRONOME_NFP6000 0x6000 +#define PCI_DEVICE_ID_NETRONOME_NFP6000_VF 0x6003 + +#define PCI_VENDOR_ID_QMI 0x1a32 + +#define PCI_VENDOR_ID_AZWAVE 0x1a3b + +#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 +#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 +#define PCI_SUBDEVICE_ID_QEMU 0x1100 + +#define PCI_VENDOR_ID_ASMEDIA 0x1b21 + +#define PCI_VENDOR_ID_REDHAT 0x1b36 + +#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS 0x1c36 + +#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8 +#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001 + +#define PCI_VENDOR_ID_AMAZON 0x1d0f + +#define PCI_VENDOR_ID_ZHAOXIN 0x1d17 + +#define PCI_VENDOR_ID_HYGON 0x1d94 + +#define PCI_VENDOR_ID_HXT 0x1dbf + +#define PCI_VENDOR_ID_TEKRAM 0x1de1 +#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 + +#define PCI_VENDOR_ID_TEHUTI 0x1fc9 +#define PCI_DEVICE_ID_TEHUTI_3009 0x3009 +#define PCI_DEVICE_ID_TEHUTI_3010 0x3010 +#define PCI_DEVICE_ID_TEHUTI_3014 0x3014 + +#define PCI_VENDOR_ID_SUNIX 0x1fd4 +#define PCI_DEVICE_ID_SUNIX_1999 0x1999 + +#define PCI_VENDOR_ID_HINT 0x3388 +#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + +#define PCI_VENDOR_ID_3DLABS 0x3d3d +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 + +#define PCI_VENDOR_ID_NETXEN 0x4040 +#define PCI_DEVICE_ID_NX2031_10GXSR 0x0001 +#define PCI_DEVICE_ID_NX2031_10GCX4 0x0002 +#define PCI_DEVICE_ID_NX2031_4GCU 0x0003 +#define PCI_DEVICE_ID_NX2031_IMEZ 0x0004 +#define PCI_DEVICE_ID_NX2031_HMEZ 0x0005 +#define PCI_DEVICE_ID_NX2031_XG_MGMT 0x0024 +#define PCI_DEVICE_ID_NX2031_XG_MGMT2 0x0025 +#define PCI_DEVICE_ID_NX3031 0x0100 + +#define PCI_VENDOR_ID_AKS 0x416c +#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 + +#define PCI_VENDOR_ID_ACCESSIO 0x494f +#define PCI_DEVICE_ID_ACCESSIO_WDG_CSM 0x22c0 + +#define PCI_VENDOR_ID_S3 0x5333 +#define PCI_DEVICE_ID_S3_TRIO 0x8811 +#define PCI_DEVICE_ID_S3_868 0x8880 +#define PCI_DEVICE_ID_S3_968 0x88f0 +#define PCI_DEVICE_ID_S3_SAVAGE4 0x8a25 +#define PCI_DEVICE_ID_S3_PROSAVAGE8 0x8d04 +#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 + +#define PCI_VENDOR_ID_DUNORD 0x5544 +#define PCI_DEVICE_ID_DUNORD_I3000 0x0001 + +#define PCI_VENDOR_ID_DCI 0x6666 +#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 +#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 +#define PCI_DEVICE_ID_DCI_PCCOM2 0x0004 + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_EESSC 0x0008 +#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320 +#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321 +#define PCI_DEVICE_ID_INTEL_PXH_0 0x0329 +#define PCI_DEVICE_ID_INTEL_PXH_1 0x032A +#define PCI_DEVICE_ID_INTEL_PXHV 0x032C +#define PCI_DEVICE_ID_INTEL_80332_0 0x0330 +#define PCI_DEVICE_ID_INTEL_80332_1 0x0332 +#define PCI_DEVICE_ID_INTEL_80333_0 0x0370 +#define PCI_DEVICE_ID_INTEL_80333_1 0x0372 +#define PCI_DEVICE_ID_INTEL_QAT_DH895XCC 0x0435 +#define PCI_DEVICE_ID_INTEL_QAT_DH895XCC_VF 0x0443 +#define PCI_DEVICE_ID_INTEL_82375 0x0482 +#define PCI_DEVICE_ID_INTEL_82424 0x0483 +#define PCI_DEVICE_ID_INTEL_82378 0x0484 +#define PCI_DEVICE_ID_INTEL_MRST_SD0 0x0807 +#define PCI_DEVICE_ID_INTEL_MRST_SD1 0x0808 +#define PCI_DEVICE_ID_INTEL_MFD_SD 0x0820 +#define PCI_DEVICE_ID_INTEL_MFD_SDIO1 0x0821 +#define PCI_DEVICE_ID_INTEL_MFD_SDIO2 0x0822 +#define PCI_DEVICE_ID_INTEL_MFD_EMMC0 0x0823 +#define PCI_DEVICE_ID_INTEL_MFD_EMMC1 0x0824 +#define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F +#define PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB 0x095E +#define PCI_DEVICE_ID_INTEL_I960 0x0960 +#define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 +#define PCI_DEVICE_ID_INTEL_8257X_SOL 0x1062 +#define PCI_DEVICE_ID_INTEL_82573E_SOL 0x1085 +#define PCI_DEVICE_ID_INTEL_82573L_SOL 0x108F +#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130 +#define PCI_DEVICE_ID_INTEL_82815_CGC 0x1132 +#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 +#define PCI_DEVICE_ID_INTEL_7505_0 0x2550 +#define PCI_DEVICE_ID_INTEL_7205_0 0x255d +#define PCI_DEVICE_ID_INTEL_82437 0x122d +#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e +#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 +#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_82380FB 0x124b +#define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_LIGHT_RIDGE 0x1513 /* Tbt 1 Gen 1 */ +#define PCI_DEVICE_ID_INTEL_EAGLE_RIDGE 0x151a +#define PCI_DEVICE_ID_INTEL_LIGHT_PEAK 0x151b +#define PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C 0x1547 /* Tbt 1 Gen 2 */ +#define PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C 0x1548 +#define PCI_DEVICE_ID_INTEL_PORT_RIDGE 0x1549 +#define PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_NHI 0x1566 /* Tbt 1 Gen 3 */ +#define PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_BRIDGE 0x1567 +#define PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_NHI 0x1568 +#define PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_BRIDGE 0x1569 +#define PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI 0x156a /* Thunderbolt 2 */ +#define PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE 0x156b +#define PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI 0x156c +#define PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE 0x156d +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI 0x1575 /* Thunderbolt 3 */ +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE 0x1576 +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI 0x1577 +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE 0x1578 +#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 +#define PCI_DEVICE_ID_INTEL_QAT_C3XXX 0x19e2 +#define PCI_DEVICE_ID_INTEL_QAT_C3XXX_VF 0x19e3 +#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 +#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 +#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f +#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 0x1d40 +#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 0x1d41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI 0x1e31 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e40 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f +#define PCI_DEVICE_ID_INTEL_VMD_201D 0x201d +#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN 0x2310 +#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX 0x231f +#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 +#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 +#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 +#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 +#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416 +#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418 +#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420 +#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421 +#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423 +#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425 +#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426 +#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428 +#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440 +#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443 +#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445 +#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448 +#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a +#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b +#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e +#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450 +#define PCI_DEVICE_ID_INTEL_82801E_11 0x245b +#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480 +#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 +#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485 +#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486 +#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a +#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b +#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c +#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0 +#define PCI_DEVICE_ID_INTEL_82801DB_1 0x24c1 +#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2 +#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3 +#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5 +#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6 +#define PCI_DEVICE_ID_INTEL_82801DB_9 0x24c9 +#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca +#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb +#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc +#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0 +#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1 +#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3 +#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5 +#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6 +#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db +#define PCI_DEVICE_ID_INTEL_82801EB_12 0x24dc +#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd +#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1 +#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2 +#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4 +#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6 +#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab +#define PCI_DEVICE_ID_INTEL_ESB_10 0x25ac +#define PCI_DEVICE_ID_INTEL_82820_HB 0x2500 +#define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501 +#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530 +#define PCI_DEVICE_ID_INTEL_82860_HB 0x2531 +#define PCI_DEVICE_ID_INTEL_E7501_MCH 0x254c +#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 +#define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562 +#define PCI_DEVICE_ID_INTEL_82865_HB 0x2570 +#define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 +#define PCI_DEVICE_ID_INTEL_82875_HB 0x2578 +#define PCI_DEVICE_ID_INTEL_82915G_HB 0x2580 +#define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 +#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590 +#define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 +#define PCI_DEVICE_ID_INTEL_5000_ERR 0x25F0 +#define PCI_DEVICE_ID_INTEL_5000_FBD0 0x25F5 +#define PCI_DEVICE_ID_INTEL_5000_FBD1 0x25F6 +#define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770 +#define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 +#define PCI_DEVICE_ID_INTEL_3000_HB 0x2778 +#define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0 +#define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2 +#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 +#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641 +#define PCI_DEVICE_ID_INTEL_ICH6_2 0x2642 +#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a +#define PCI_DEVICE_ID_INTEL_ICH6_17 0x266d +#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e +#define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f +#define PCI_DEVICE_ID_INTEL_ESB2_0 0x2670 +#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698 +#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b +#define PCI_DEVICE_ID_INTEL_ESB2_18 0x269e +#define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8 +#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9 +#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0 +#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc +#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd +#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da +#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd +#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de +#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df +#define PCI_DEVICE_ID_INTEL_ICH8_0 0x2810 +#define PCI_DEVICE_ID_INTEL_ICH8_1 0x2811 +#define PCI_DEVICE_ID_INTEL_ICH8_2 0x2812 +#define PCI_DEVICE_ID_INTEL_ICH8_3 0x2814 +#define PCI_DEVICE_ID_INTEL_ICH8_4 0x2815 +#define PCI_DEVICE_ID_INTEL_ICH8_5 0x283e +#define PCI_DEVICE_ID_INTEL_ICH8_6 0x2850 +#define PCI_DEVICE_ID_INTEL_VMD_28C0 0x28c0 +#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910 +#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917 +#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912 +#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913 +#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914 +#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919 +#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 +#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 +#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 +#define PCI_DEVICE_ID_INTEL_I7_MCR 0x2c18 +#define PCI_DEVICE_ID_INTEL_I7_MC_TAD 0x2c19 +#define PCI_DEVICE_ID_INTEL_I7_MC_RAS 0x2c1a +#define PCI_DEVICE_ID_INTEL_I7_MC_TEST 0x2c1c +#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL 0x2c20 +#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR 0x2c21 +#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK 0x2c22 +#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC 0x2c23 +#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL 0x2c28 +#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR 0x2c29 +#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK 0x2c2a +#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC 0x2c2b +#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL 0x2c30 +#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR 0x2c31 +#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK 0x2c32 +#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC 0x2c33 +#define PCI_DEVICE_ID_INTEL_I7_NONCORE 0x2c41 +#define PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT 0x2c40 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE 0x2c50 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT 0x2c51 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2 0x2c70 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_SAD 0x2c81 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0 0x2c90 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_PHY0 0x2c91 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR 0x2c98 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD 0x2c99 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST 0x2c9C +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL 0x2ca0 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR 0x2ca1 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK 0x2ca2 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC 0x2ca3 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL 0x2ca8 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR 0x2ca9 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK 0x2caa +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC 0x2cab +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2 0x2d98 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2 0x2d99 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2 0x2d9a +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2 0x2d9c +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2 0x2da0 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2 0x2da1 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2 0x2da2 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2 0x2da3 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2 0x2da8 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2 0x2da9 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2 0x2daa +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2 0x2dab +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2 0x2db0 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2 0x2db1 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2 0x2db2 +#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2 0x2db3 +#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG4 0x3429 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG5 0x342a +#define PCI_DEVICE_ID_INTEL_IOAT_TBG6 0x342b +#define PCI_DEVICE_ID_INTEL_IOAT_TBG7 0x342c +#define PCI_DEVICE_ID_INTEL_X58_HUB_MGMT 0x342e +#define PCI_DEVICE_ID_INTEL_IOAT_TBG0 0x3430 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG1 0x3431 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG2 0x3432 +#define PCI_DEVICE_ID_INTEL_IOAT_TBG3 0x3433 +#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 +#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 +#define PCI_DEVICE_ID_INTEL_82854_HB 0x358c +#define PCI_DEVICE_ID_INTEL_82854_IG 0x358e +#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580 +#define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582 +#define PCI_DEVICE_ID_INTEL_E7520_MCH 0x3590 +#define PCI_DEVICE_ID_INTEL_E7320_MCH 0x3592 +#define PCI_DEVICE_ID_INTEL_MCH_PA 0x3595 +#define PCI_DEVICE_ID_INTEL_MCH_PA1 0x3596 +#define PCI_DEVICE_ID_INTEL_MCH_PB 0x3597 +#define PCI_DEVICE_ID_INTEL_MCH_PB1 0x3598 +#define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599 +#define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a +#define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e +#define PCI_DEVICE_ID_INTEL_I7300_MCH_ERR 0x360c +#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 0x360f +#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 0x3610 +#define PCI_DEVICE_ID_INTEL_IOAT_CNB 0x360b +#define PCI_DEVICE_ID_INTEL_FBD_CNB 0x360c +#define PCI_DEVICE_ID_INTEL_IOAT_JSF0 0x3710 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF1 0x3711 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF2 0x3712 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF3 0x3713 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF4 0x3714 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF5 0x3715 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF6 0x3716 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF7 0x3717 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF8 0x3718 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF9 0x3719 +#define PCI_DEVICE_ID_INTEL_QAT_C62X 0x37c8 +#define PCI_DEVICE_ID_INTEL_QAT_C62X_VF 0x37c9 +#define PCI_DEVICE_ID_INTEL_ICH10_0 0x3a14 +#define PCI_DEVICE_ID_INTEL_ICH10_1 0x3a16 +#define PCI_DEVICE_ID_INTEL_ICH10_2 0x3a18 +#define PCI_DEVICE_ID_INTEL_ICH10_3 0x3a1a +#define PCI_DEVICE_ID_INTEL_ICH10_4 0x3a30 +#define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60 +#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00 +#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f +#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e +#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f +#define PCI_DEVICE_ID_INTEL_UNC_HA 0x3c46 +#define PCI_DEVICE_ID_INTEL_UNC_IMC0 0x3cb0 +#define PCI_DEVICE_ID_INTEL_UNC_IMC1 0x3cb1 +#define PCI_DEVICE_ID_INTEL_UNC_IMC2 0x3cb4 +#define PCI_DEVICE_ID_INTEL_UNC_IMC3 0x3cb5 +#define PCI_DEVICE_ID_INTEL_UNC_QPI0 0x3c41 +#define PCI_DEVICE_ID_INTEL_UNC_QPI1 0x3c42 +#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43 +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44 +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45 +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */ +#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0 +#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */ +#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */ +#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f +#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 +#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3 +#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 +#define PCI_DEVICE_ID_INTEL_5100_22 0x65f6 +#define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030 +#define PCI_DEVICE_ID_INTEL_5400_FBD0 0x4035 +#define PCI_DEVICE_ID_INTEL_5400_FBD1 0x4036 +#define PCI_DEVICE_ID_INTEL_IOAT_SCNB 0x65ff +#define PCI_DEVICE_ID_INTEL_EP80579_0 0x5031 +#define PCI_DEVICE_ID_INTEL_EP80579_1 0x5032 +#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 +#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 +#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 +#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 +#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 +#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 +#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 +#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 +#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 +#define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 +#define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 +#define PCI_DEVICE_ID_INTEL_82810_MC3 0x7122 +#define PCI_DEVICE_ID_INTEL_82810_IG3 0x7123 +#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124 +#define PCI_DEVICE_ID_INTEL_82810E_IG 0x7125 +#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 +#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 +#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 +#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 +#define PCI_DEVICE_ID_INTEL_440MX 0x7195 +#define PCI_DEVICE_ID_INTEL_440MX_6 0x7196 +#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198 +#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199 +#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b +#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0 +#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2 +#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 +#define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119 +#define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a +#define PCI_DEVICE_ID_INTEL_E6XX_CU 0x8183 +#define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186 +#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 +#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 +#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca +#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb +#define PCI_DEVICE_ID_INTEL_84460GX 0x84ea +#define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500 +#define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 +#define PCI_DEVICE_ID_INTEL_VMD_9A0B 0x9a0b +#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 + +#define PCI_VENDOR_ID_WANGXUN 0x8088 + +#define PCI_VENDOR_ID_SCALEMP 0x8686 +#define PCI_DEVICE_ID_SCALEMP_VSMP_CTL 0x1010 + +#define PCI_VENDOR_ID_COMPUTONE 0x8e0e +#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 +#define PCI_SUBVENDOR_ID_COMPUTONE 0x8e0e +#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003 + +#define PCI_VENDOR_ID_KTI 0x8e2e + +#define PCI_VENDOR_ID_ADAPTEC 0x9004 +#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 +#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178 +#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 +#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 +#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 +#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 +#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 +#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 +#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 +#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 +#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 +#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 +#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 +#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 +#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 +#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 +#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 +#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 +#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 +#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 +#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578 +#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 +#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 +#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 + +#define PCI_VENDOR_ID_ADAPTEC2 0x9005 +#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 +#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 +#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013 +#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f +#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 +#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051 +#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f +#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080 +#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081 +#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083 +#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f +#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0 +#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 +#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 +#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf +#define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN 0x0500 +#define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503 + +#define PCI_VENDOR_ID_HOLTEK 0x9412 +#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 + +#define PCI_VENDOR_ID_NETMOS 0x9710 +#define PCI_DEVICE_ID_NETMOS_9705 0x9705 +#define PCI_DEVICE_ID_NETMOS_9715 0x9715 +#define PCI_DEVICE_ID_NETMOS_9735 0x9735 +#define PCI_DEVICE_ID_NETMOS_9745 0x9745 +#define PCI_DEVICE_ID_NETMOS_9755 0x9755 +#define PCI_DEVICE_ID_NETMOS_9805 0x9805 +#define PCI_DEVICE_ID_NETMOS_9815 0x9815 +#define PCI_DEVICE_ID_NETMOS_9835 0x9835 +#define PCI_DEVICE_ID_NETMOS_9845 0x9845 +#define PCI_DEVICE_ID_NETMOS_9855 0x9855 +#define PCI_DEVICE_ID_NETMOS_9865 0x9865 +#define PCI_DEVICE_ID_NETMOS_9900 0x9900 +#define PCI_DEVICE_ID_NETMOS_9901 0x9901 +#define PCI_DEVICE_ID_NETMOS_9904 0x9904 +#define PCI_DEVICE_ID_NETMOS_9912 0x9912 +#define PCI_DEVICE_ID_NETMOS_9922 0x9922 + +#define PCI_VENDOR_ID_3COM_2 0xa727 + +#define PCI_VENDOR_ID_SOLIDRUN 0xd063 + +#define PCI_VENDOR_ID_DIGIUM 0xd161 +#define PCI_DEVICE_ID_DIGIUM_HFC4S 0xb410 + +#define PCI_SUBVENDOR_ID_EXSYS 0xd84d +#define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 +#define PCI_SUBDEVICE_ID_EXSYS_4055 0x4055 + +#define PCI_VENDOR_ID_TIGERJET 0xe159 +#define PCI_DEVICE_ID_TIGERJET_300 0x0001 +#define PCI_DEVICE_ID_TIGERJET_100 0x0002 + +#define PCI_VENDOR_ID_XILINX_RME 0xea60 +#define PCI_DEVICE_ID_RME_DIGI32 0x9896 +#define PCI_DEVICE_ID_RME_DIGI32_PRO 0x9897 +#define PCI_DEVICE_ID_RME_DIGI32_8 0x9898 + +#define PCI_VENDOR_ID_XEN 0x5853 +#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001 + +#define PCI_VENDOR_ID_OCZ 0x1b85 + +#define PCI_VENDOR_ID_NCUBE 0x10ff + +#define PCI_VENDOR_ID_PHYTIUM 0x1db7 + +#endif /* _LINUX_PCI_IDS_H */ diff --git a/tools/phytium-pi/__pycache__/py_terminal.cpython-311.pyc b/tools/phytium-pi/__pycache__/py_terminal.cpython-311.pyc new file mode 100644 index 0000000000..3cade90ed9 Binary files /dev/null and b/tools/phytium-pi/__pycache__/py_terminal.cpython-311.pyc differ diff --git a/tools/phytium-pi/phytium-pi-board.dtb b/tools/phytium-pi/phytium-pi-board.dtb new file mode 100755 index 0000000000..f26b397243 Binary files /dev/null and b/tools/phytium-pi/phytium-pi-board.dtb differ diff --git a/tools/phytium-pi/phytium-pi.its b/tools/phytium-pi/phytium-pi.its new file mode 100755 index 0000000000..83c6c42996 --- /dev/null +++ b/tools/phytium-pi/phytium-pi.its @@ -0,0 +1,50 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + */ + +/dts-v1/; + +/ { + description = "Various kernels, ramdisks and FDT blobs"; + #address-cells = <1>; + + images { + kernel { + description = "ArceOS for Phytium Pi"; + data = /incbin/("../../arceos-phytium-pi.bin.gz"); + type = "kernel"; + arch = "arm64"; + os = "linux"; + compression = "gzip"; + load = <0x90100000>; + entry = <0x90100000>; + hash-1 { + algo = "md5"; + }; + hash-2 { + algo = "sha1"; + }; + }; + + fdt-phytium { + description = "phytium-pi fdt"; + data = /incbin/("./phytium-pi-board.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + hash-1 { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "config-phytium-pi"; + + config-phytium-pi { + description = "phytium-pi configuration"; + kernel = "kernel"; + fdt = "fdt-phytium"; + }; + }; +}; diff --git a/tools/phytium-pi/uboot_test_send.py b/tools/phytium-pi/uboot_test_send.py new file mode 100644 index 0000000000..1907001aee --- /dev/null +++ b/tools/phytium-pi/uboot_test_send.py @@ -0,0 +1,99 @@ +import os +os.system('title Terminal S') + +from collections import deque +import threading +import sys + +import colorama +import click +from getch import getch +import serial +from serial.tools import list_ports + + +CONTEXT_SETTINGS = dict(help_option_names=['-h', '--help']) + +@click.command(context_settings=CONTEXT_SETTINGS) +@click.option('-p', '--port', default=None, help='serial port name') +@click.option('-b', '--baudrate', default=115200, help='set baud reate') +@click.option('--parity', default='N', type=click.Choice(['N', 'E', 'O', 'S', 'M']), help='set parity') +@click.option('-s', '--stopbits', default=1, help='set stop bits') +@click.option('-l', is_flag=True, help='list serial ports') +def main(port, baudrate, parity, stopbits, l): + if port is None: + ports = list_ports.comports() + if not ports: + print('--- No serial port available ---') + return + if len(ports) == 1: + port = ports[0][0] + else: + print('--- Available Ports ----') + for i, v in enumerate(ports): + print('--- {}: {}'.format(i, v)) + + if l: + return + raw = input('--- Select port index: ') + try: + n = int(raw) + port = ports[n][0] + except: + return + try: + device = serial.Serial(port=port, + baudrate=baudrate, + bytesize=8, + parity=parity, + stopbits=stopbits, + timeout=0.1) + except: + print('--- Failed to open {} ---'.format(port)) + return + + print('--- Press Ctrl+] to quit ---') + + queue = deque() + + def read_input(): + while device.is_open: + ch = getch() + # print(ch) + if ch == b'\x1d': # 'ctrl + ]' to quit + break + if ch == b'\x00' or ch == b'\xe0': # arrow keys' escape sequences + ch2 = getch() + conv = { b'H': b'A', b'P': b'B', b'M': b'C', b'K': b'D' } + if ch2 in conv: + # Esc[ + queue.append(b'\x1b[' + conv[ch2]) + else: + queue.append(ch + ch2) + else: + queue.append(ch) + + colorama.init() + + thread = threading.Thread(target=read_input) + thread.start() + while thread.is_alive(): + try: + length = len(queue) + if length > 0: + device.write(b''.join(queue.popleft() for _ in range(length))) + + line = device.readline() + if line: + print(line.decode(), end='', flush=True) + except IOError: + print('Device is disconnected') + break + except UnicodeDecodeError: + print([x for x in line]) + + device.close() + + +if __name__ == "__main__": + main() \ No newline at end of file diff --git a/tools/phytium-pi/uboot_transfer.py b/tools/phytium-pi/uboot_transfer.py new file mode 100644 index 0000000000..0322dcf672 --- /dev/null +++ b/tools/phytium-pi/uboot_transfer.py @@ -0,0 +1,118 @@ +import serial +import sys +import os +import time +import threading + +class UbootTransfer: + def __init__(self, device, baud, filePath): + self.device = device + self.baud = baud + self.filePath = filePath + # 打开串口 + print("Open serial device") + self.ser = serial.Serial(device, baud, timeout=1) + + def checkDevice(self): + # 检查串口设备是否存在 + if not os.path.exists(self.device): + print("Device {} does not exist".format(self.device)) + sys.exit(1) + + def readOutput(self): + while True: + line = self.ser.readline().decode().strip() + if line: + print(line) + if 'Phytium-Pi#' in line: + break + + def start(self): + while True: + if self.ser.in_waiting: + # 读取串口数据 + serial_data = self.ser.read(self.ser.in_waiting).decode('utf-8') + print(serial_data, end='') + + # 从终端获取用户输入，并发送到串口 + if serial_data.endswith('# '): + user_input = input() + '\r\n' + self.ser.write(user_input.encode('utf-8')) + + def transfer(self): + # 检查串口设备是否存在 + self.checkDevice() + + try: + # 等待串口输出 'Hit any key to stop autoboot:'，然后模拟输入 + # while True: + # line = self.ser.readline().decode().strip() + # if line: + # print(line) + # if 'Hit any key' in line: + # print("find the line: Hit any key to stop autoboot:") + # #self.sendCommand(); + # self.ser.write(b'qwertyuiop\n') + # self.ser.write(b'asdfghjkl\n') + # self.ser.write(b'zxcvbnm\n') + # break + + + # 他妈的我是真的服了啊，浪费将近一天的时间研究到底是怎么进入系统的 + # 一开始以为是发送的回车是有问题的，后面测试发送其他字符也没有问题 + # 手动进入中断后发送回车也是没有问题的，但是就是在等待'Hit any key to stop autoboot:'的时候不行了 + # 直接暴力做法在进入之前循环发送回车 + # 真的是太坐牢了啊 + # 在没有检测到'Phytium-Pi#'之前，循环发送回车 + while True: + self.ser.write(b'\n') + line = self.ser.readline().decode().strip() + if line: + print(line) + if 'Phytium-Pi#' in line: + break + + # 检测到输出'Phytium-Pi#'字样后，模拟输入指令 + while True: + line = self.ser.readline().decode().strip() + if line: + print(line) + if 'Phytium-Pi#' in line: + print("find the line: Phytium-Pi#") + # 发送命令：usb start; fatload usb 0 0x90100000 文件名; go 0x90100000 + self.ser.write(b'usb start\n') + self.readOutput() + self.ser.write(b'fatls usb 0\n') + self.readOutput() + self.ser.write(b'fatload usb 0 0x90100000 ' + filePath.encode() + b'\n') + self.readOutput() + self.ser.write(b'go 0x90100000\n') + self.readOutput() + print("finish send command") + break + + # 模拟终端，接收用户输入并发送到串口，同时打印串口输出 + # 用户输入一个指令之后，发送到串口，然后等待串口输出，然后打印输出 + # 等待出现 Phytium-Pi# 用户可以发送下一个指令 + self.start() + + + except serial.SerialException as e: + print("Serial error:", e) + + finally: + self.ser.close() + +# 入口函数 +if __name__ == '__main__': + print("-- Uboot Transfer --") + if len(sys.argv) != 4: + print("Usage: python uboot_transfer.py ") + sys.exit(1) + + device = sys.argv[1] + baud = int(sys.argv[2]) + filePath = sys.argv[3] + + ubootTransfer = UbootTransfer(device, baud, filePath) + ubootTransfer.transfer() diff --git a/tools/phytium-pi/uboot_transfer.rb b/tools/phytium-pi/uboot_transfer.rb new file mode 100644 index 0000000000..dc1b00c2db --- /dev/null +++ b/tools/phytium-pi/uboot_transfer.rb @@ -0,0 +1,69 @@ +require 'serialport' + +class UbootTransfer + def initialize(device, baud, file_path) + @device = device + @baud = baud + @file_path = file_path + end + + def check_device + unless File.exist?(@device) + puts "Device #{@device} does not exist" + exit(1) + end + end + + def transfer + check_device + + puts "Open serial device" + ser = SerialPort.new(@device, @baud, 8, 1, SerialPort::NONE) + + begin + loop do + line = ser.readline.strip + puts line unless line.empty? + break if line.include?('Hit any key') + + ser.write("\r\n") + end + + loop do + line = ser.readline.strip + puts line unless line.empty? + break if line.include?('Phytium-Pi#') + + ser.write("usb start; fatload usb 0 0x90100000 #{@file_path}\r\n") + ser.write("go 0x90100000\r\n") + end + + loop do + user_input = gets.chomp + ser.write("#{user_input}\r\n") + line = ser.readline.strip + puts line unless line.empty? + break if user_input == 'exit' + end + rescue IOError => e + puts "Serial error: #{e.message}" + ensure + ser.close + end + end +end + +if __FILE__ == $PROGRAM_NAME + puts "-- Uboot Transfer --" + unless ARGV.length == 3 + puts "Usage: ruby uboot_transfer.rb " + exit(1) + end + + device = ARGV[0] + baud = ARGV[1].to_i + file_path = ARGV[2] + + uboot_transfer = UbootTransfer.new(device, baud, file_path) + uboot_transfer.transfer +end diff --git a/tools/phytium-pi/yet_another_uboot_transfer.py b/tools/phytium-pi/yet_another_uboot_transfer.py new file mode 100644 index 0000000000..73207cf8fc --- /dev/null +++ b/tools/phytium-pi/yet_another_uboot_transfer.py @@ -0,0 +1,58 @@ +#↑兄啊你不知道uboot可以保存启动配置的嘛？设置为默认等待从串口传入内核就好了啊? +import sys +import time +import serial +from xmodem import XMODEM + +def send_file(port, baudrate, file_path): + # 打开串口 + ser = serial.Serial(port, baudrate, timeout=1) + + # 等待 U-Boot 提示符 + while True: + line = ser.readline().decode('utf-8', errors='ignore').strip() + print(line) + if line.endswith('Phytium-Pi#'): + break + + # 发送 loady 命令 + ser.write(b'loadx 0x90100000\n') + time.sleep(0.5) + + # 等待 U-Boot 准备好接收文件 + while True: + line = ser.readline().decode('utf-8', errors='ignore').strip() + print(line) + if 'Ready for binary' in line: + break + + # 发送 'C' 字符开始传输 + ser.write(b'C') + + # 使用 xmodem 协议传输文件 + with open(file_path, 'rb') as f: + def getc(size, timeout=1): + return ser.read(size) or None + + def putc(data, timeout=1): + return ser.write(data) + + modem = XMODEM(getc, putc) + modem.send(f) + print("transfer complete") + + ser.write(b'go 0x90100000\n') + + # 关闭串口 + ser.close() + +if __name__ == '__main__': + if len(sys.argv) != 4: + print("Usage: python script.py ") + sys.exit(1) + + port = sys.argv[1] + baudrate = int(sys.argv[2]) + file_path = sys.argv[3] + + send_file(port, baudrate, file_path) diff --git a/tools/raspi4/chainloader/.gitignore b/tools/raspi4/chainloader/.gitignore new file mode 100644 index 0000000000..1bebdabd4b --- /dev/null +++ b/tools/raspi4/chainloader/.gitignore @@ -0,0 +1,3 @@ +/target/ +target/ +/target diff --git a/tools/raspi4/chainloader/.vscode/settings.json b/tools/raspi4/chainloader/.vscode/settings.json new file mode 100644 index 0000000000..bfa278e9aa --- /dev/null +++ b/tools/raspi4/chainloader/.vscode/settings.json @@ -0,0 +1,10 @@ +{ + "editor.formatOnSave": true, + "editor.rulers": [100], + "rust-analyzer.cargo.target": "aarch64-unknown-none-softfloat", + "rust-analyzer.cargo.features": ["bsp_rpi3"], + "rust-analyzer.checkOnSave.allTargets": false, + "rust-analyzer.checkOnSave.extraArgs": ["--bins"], + "rust-analyzer.lens.debug": false, + "rust-analyzer.lens.run": false +} diff --git a/tools/raspi4/chainloader/Cargo.lock b/tools/raspi4/chainloader/Cargo.lock new file mode 100644 index 0000000000..047875fe58 --- /dev/null +++ b/tools/raspi4/chainloader/Cargo.lock @@ -0,0 +1,26 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 3 + +[[package]] +name = "aarch64-cpu" +version = "9.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3aceb88e55ba626a5479279268d009a92d9d00eacce0de1b8c236c7ad31b7225" +dependencies = [ + "tock-registers", +] + +[[package]] +name = "mingo" +version = "0.6.0" +dependencies = [ + "aarch64-cpu", + "tock-registers", +] + +[[package]] +name = "tock-registers" +version = "0.8.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "696941a0aee7e276a165a978b37918fd5d22c55c3d6bda197813070ca9c0f21c" diff --git a/tools/raspi4/chainloader/Cargo.toml b/tools/raspi4/chainloader/Cargo.toml new file mode 100644 index 0000000000..1fe55455ef --- /dev/null +++ b/tools/raspi4/chainloader/Cargo.toml @@ -0,0 +1,33 @@ +[package] +name = "mingo" +version = "0.6.0" +authors = ["Andre Richter "] +edition = "2021" + +[profile.release] +lto = true + +[features] +default = [] +bsp_rpi3 = ["tock-registers"] +bsp_rpi4 = ["tock-registers"] +enable_jtag_debug = [] + +[[bin]] +name = "kernel" +path = "src/main.rs" + +##-------------------------------------------------------------------------------------------------- +## Dependencies +##-------------------------------------------------------------------------------------------------- + +[dependencies] + +# Optional dependencies +tock-registers = { version = "0.8.x", default-features = false, features = ["register_types"], optional = true } + +# Platform specific dependencies +[target.'cfg(target_arch = "aarch64")'.dependencies] +aarch64-cpu = { version = "9.x.x" } + +[workspace] diff --git a/tools/raspi4/chainloader/Makefile b/tools/raspi4/chainloader/Makefile new file mode 100644 index 0000000000..2c3620ca98 --- /dev/null +++ b/tools/raspi4/chainloader/Makefile @@ -0,0 +1,236 @@ +## SPDX-License-Identifier: MIT OR Apache-2.0 +## +## Copyright (c) 2018-2023 Andre Richter + +include ../common/docker.mk +include ../common/format.mk +include ../common/operating_system.mk + +##-------------------------------------------------------------------------------------------------- +## Optional, user-provided configuration values +##-------------------------------------------------------------------------------------------------- + +# Default to the RPi3. +BSP ?= rpi4 + +# Default to a serial device name that is common in Linux. +DEV_SERIAL ?= /dev/ttyUSB0 + +# Default not to enable jtag debug +JTAG ?= n + +##-------------------------------------------------------------------------------------------------- +## BSP-specific configuration values +##-------------------------------------------------------------------------------------------------- +QEMU_MISSING_STRING = "This board is not yet supported for QEMU." + +TARGET = aarch64-unknown-none-softfloat +KERNEL_BIN = kernel8.img +QEMU_BINARY = qemu-system-aarch64 +QEMU_MACHINE_TYPE = +QEMU_RELEASE_ARGS = -serial stdio -display none +OBJDUMP_BINARY = aarch64-none-elf-objdump +NM_BINARY = aarch64-none-elf-nm +READELF_BINARY = aarch64-none-elf-readelf +LD_SCRIPT_PATH = $(shell pwd)/src/bsp/raspberrypi +RUSTC_MISC_ARGS = -C target-cpu=cortex-a72 +CHAINBOOT_DEMO_PAYLOAD = demo_payload_rpi4.img + +# Export for build.rs. +export LD_SCRIPT_PATH + + + +##-------------------------------------------------------------------------------------------------- +## Targets and Prerequisites +##-------------------------------------------------------------------------------------------------- +KERNEL_MANIFEST = Cargo.toml +KERNEL_LINKER_SCRIPT = kernel.ld +LAST_BUILD_CONFIG = target/$(BSP).build_config + +KERNEL_ELF = target/$(TARGET)/release/kernel +# This parses cargo's dep-info file. +# https://doc.rust-lang.org/cargo/guide/build-cache.html#dep-info-files +KERNEL_ELF_DEPS = $(filter-out %: ,$(file < $(KERNEL_ELF).d)) $(KERNEL_MANIFEST) $(LAST_BUILD_CONFIG) + + + +##-------------------------------------------------------------------------------------------------- +## Command building blocks +##-------------------------------------------------------------------------------------------------- +RUSTFLAGS = $(RUSTC_MISC_ARGS) \ + -C link-arg=--library-path=$(LD_SCRIPT_PATH) \ + -C link-arg=--script=$(KERNEL_LINKER_SCRIPT) + +RUSTFLAGS_PEDANTIC = $(RUSTFLAGS) \ + -D warnings \ + -D missing_docs + +FEATURES = --features bsp_$(BSP) +ifeq ($(JTAG),y) + FEATURES += --features enable_jtag_debug +endif +COMPILER_ARGS = --target=$(TARGET) \ + $(FEATURES) \ + --release + +RUSTC_CMD = cargo rustc $(COMPILER_ARGS) +DOC_CMD = cargo doc $(COMPILER_ARGS) +CLIPPY_CMD = cargo clippy $(COMPILER_ARGS) +OBJCOPY_CMD = rust-objcopy \ + --strip-all \ + -O binary + +EXEC_QEMU = $(QEMU_BINARY) -M $(QEMU_MACHINE_TYPE) +EXEC_TEST_MINIPUSH = ruby tests/chainboot_test.rb +EXEC_MINIPUSH = ruby ../common/serial/minipush.rb + +##------------------------------------------------------------------------------ +## Dockerization +##------------------------------------------------------------------------------ +DOCKER_CMD = docker run -t --rm -v $(shell pwd):/work/tutorial -w /work/tutorial +DOCKER_CMD_INTERACT = $(DOCKER_CMD) -i +DOCKER_ARG_DIR_COMMON = -v $(shell pwd)/../common:/work/common +DOCKER_ARG_DEV = --privileged -v /dev:/dev + +# DOCKER_IMAGE defined in include file (see top of this file). +DOCKER_QEMU = $(DOCKER_CMD_INTERACT) $(DOCKER_IMAGE) +DOCKER_TOOLS = $(DOCKER_CMD) $(DOCKER_IMAGE) +DOCKER_TEST = $(DOCKER_CMD) $(DOCKER_ARG_DIR_COMMON) $(DOCKER_IMAGE) + +# Dockerize commands, which require USB device passthrough, only on Linux. +ifeq ($(shell uname -s),Linux) + DOCKER_CMD_DEV = $(DOCKER_CMD_INTERACT) $(DOCKER_ARG_DEV) + + DOCKER_CHAINBOOT = $(DOCKER_CMD_DEV) $(DOCKER_ARG_DIR_COMMON) $(DOCKER_IMAGE) +endif + + + +##-------------------------------------------------------------------------------------------------- +## Targets +##-------------------------------------------------------------------------------------------------- +.PHONY: all doc qemu chainboot clippy clean readelf objdump nm check + +all: clean $(KERNEL_BIN) + +##------------------------------------------------------------------------------ +## Save the configuration as a file, so make understands if it changed. +##------------------------------------------------------------------------------ +$(LAST_BUILD_CONFIG): + @rm -f target/*.build_config + @mkdir -p target + @touch $(LAST_BUILD_CONFIG) + +##------------------------------------------------------------------------------ +## Compile the kernel ELF +##------------------------------------------------------------------------------ +$(KERNEL_ELF): $(KERNEL_ELF_DEPS) + $(call color_header, "Compiling kernel ELF - $(BSP)") + @RUSTFLAGS="$(RUSTFLAGS_PEDANTIC)" $(RUSTC_CMD) + +##------------------------------------------------------------------------------ +## Generate the stripped kernel binary +##------------------------------------------------------------------------------ +$(KERNEL_BIN): $(KERNEL_ELF) + $(call color_header, "Generating stripped binary") + @$(OBJCOPY_CMD) $(KERNEL_ELF) $(KERNEL_BIN) + $(call color_progress_prefix, "Name") + @echo $(KERNEL_BIN) + $(call color_progress_prefix, "Size") + $(call disk_usage_KiB, $(KERNEL_BIN)) + +##------------------------------------------------------------------------------ +## Generate the documentation +##------------------------------------------------------------------------------ +doc: + $(call color_header, "Generating docs") + @$(DOC_CMD) --document-private-items --open + +##------------------------------------------------------------------------------ +## Run the kernel in QEMU +##------------------------------------------------------------------------------ +ifeq ($(QEMU_MACHINE_TYPE),) # QEMU is not supported for the board. + +qemu qemuasm: + $(call color_header, "$(QEMU_MISSING_STRING)") + +else # QEMU is supported. + +qemu: $(KERNEL_BIN) + $(call color_header, "Launching QEMU") + @$(DOCKER_QEMU) $(EXEC_QEMU) $(QEMU_RELEASE_ARGS) -kernel $(KERNEL_BIN) + +qemuasm: $(KERNEL_BIN) + $(call color_header, "Launching QEMU with ASM output") + @$(DOCKER_QEMU) $(EXEC_QEMU) $(QEMU_RELEASE_ARGS) -kernel $(KERNEL_BIN) -d in_asm + +endif + +##------------------------------------------------------------------------------ +## Push the kernel to the real HW target +##------------------------------------------------------------------------------ +chainboot: $(KERNEL_BIN) + @$(DOCKER_CHAINBOOT) $(EXEC_MINIPUSH) $(DEV_SERIAL) $(CHAINBOOT_DEMO_PAYLOAD) + +##------------------------------------------------------------------------------ +## Run clippy +##------------------------------------------------------------------------------ +clippy: + @RUSTFLAGS="$(RUSTFLAGS_PEDANTIC)" $(CLIPPY_CMD) + +##------------------------------------------------------------------------------ +## Clean +##------------------------------------------------------------------------------ +clean: + rm -rf target $(KERNEL_BIN) + +##------------------------------------------------------------------------------ +## Run readelf +##------------------------------------------------------------------------------ +readelf: $(KERNEL_ELF) + $(call color_header, "Launching readelf") + @$(DOCKER_TOOLS) $(READELF_BINARY) --headers $(KERNEL_ELF) + +##------------------------------------------------------------------------------ +## Run objdump +##------------------------------------------------------------------------------ +objdump: $(KERNEL_ELF) + $(call color_header, "Launching objdump") + @$(DOCKER_TOOLS) $(OBJDUMP_BINARY) --disassemble --demangle \ + --section .text \ + --section .rodata \ + $(KERNEL_ELF) | rustfilt + +##------------------------------------------------------------------------------ +## Run nm +##------------------------------------------------------------------------------ +nm: $(KERNEL_ELF) + $(call color_header, "Launching nm") + @$(DOCKER_TOOLS) $(NM_BINARY) --demangle --print-size $(KERNEL_ELF) | sort | rustfilt + + + +##-------------------------------------------------------------------------------------------------- +## Testing targets +##-------------------------------------------------------------------------------------------------- +.PHONY: test test_boot + +ifeq ($(QEMU_MACHINE_TYPE),) # QEMU is not supported for the board. + +test_boot test: + $(call color_header, "$(QEMU_MISSING_STRING)") + +else # QEMU is supported. + +##------------------------------------------------------------------------------ +## Run boot test +##------------------------------------------------------------------------------ +test_boot: $(KERNEL_BIN) + $(call color_header, "Boot test - $(BSP)") + @$(DOCKER_TEST) $(EXEC_TEST_MINIPUSH) $(EXEC_QEMU) $(QEMU_RELEASE_ARGS) \ + -kernel $(KERNEL_BIN) $(CHAINBOOT_DEMO_PAYLOAD) + +test: test_boot + +endif diff --git a/tools/raspi4/chainloader/README.CN.md b/tools/raspi4/chainloader/README.CN.md new file mode 100644 index 0000000000..de7f51114a --- /dev/null +++ b/tools/raspi4/chainloader/README.CN.md @@ -0,0 +1,116 @@ +# 教程06 - UART链加载器 + +## tl;dr + +- 从SD卡上运行是一次不错的体验，但是每次都为每个新的二进制文件这样做将非常繁琐。 + 因此，让我们编写一个[chainloader]。 +- 这将是您需要放在SD卡上的最后一个二进制文件。 + 每个后续的教程都将在`Makefile`中提供一个`chainboot`，让您方便地通过`UART`加载内核。 + +[chainloader]: https://en.wikipedia.org/wiki/Chain_loading + + +## 注意 + +请注意，这个教程中有一些内容仅通过查看源代码很难理解。 + +大致的意思是，在`boot.s`中，我们编写了一段[position independent code]代码， +它会自动确定固件加载二进制文件的位置（`0x8_0000`），以及链接到的位置（`0x200_0000`，参见 `kernel.ld`）。 +然后，二进制文件将自身从加载地址复制到链接地址（也就是"重定位"自身），然后跳转到`_start_rust()`的重定位版本。 + +由于链加载程序现在已经"脱离了路径"，它现在可以从`UART`接收另一个内核二进制文件，并将其复制到RPi固件的标准加载地址`0x8_0000`。 +最后，它跳转到`0x8_0000`，新加载的二进制文件会透明地执行，就好像它一直从SD卡加载一样。 + +在我有时间详细写下这些内容之前，请耐心等待。目前，请将这个教程视为一种便利功能的启用程序，它允许快速启动以下教程。 +_对于那些渴望深入了解的人，可以直接跳到第[15章](../15_virtual_mem_part3_precomputed_tables)，阅读README的前半部分， +其中讨论了`Load Address != Link Address`的问题_。 + +[position independent code]: https://en.wikipedia.org/wiki/Position-independent_code + +## 安装并测试它 + +我们的链加载程序称为`MiniLoad`，受到了[raspbootin]的启发。 + +您可以按照以下教程尝试它： +1. 根据您的目标硬件运行命令：`make`或`BSP=rpi4 make`。 +1. 将`kernel8.img`复制到SD卡中，并将SD卡重新插入您的RPi。 +1. 运行命令`make chainboot`或`BSP=rpi4 make chainboot`。 +1. 将USB串口连接到您的主机PC上。 + - 请参考[top-level README](../README.md#-usb-serial-output)中的接线图。 + - 确保您**没有**连接USB串口的电源引脚，只连接RX/TX和GND。 +1. 将RPi连接到（USB）电源线。 +1. 观察加载程序通过`UART`获取内核： + +> ❗ **注意**: `make chainboot`假设默认的串行设备名称为`/dev/ttyUSB0`。根据您的主机操作系统，设备名称可能会有所不同。 +> 例如，在`macOS`上，它可能是类似于`/dev/tty.usbserial-0001`的名称。 +> 在这种情况下，请明确给出设备名称： + + +```console +$ DEV_SERIAL=/dev/tty.usbserial-0001 make chainboot +``` + +[raspbootin]: https://github.com/mrvn/raspbootin + +```console +$ make chainboot +[...] +Minipush 1.0 + +[MP] ⏳ Waiting for /dev/ttyUSB0 +[MP] ✅ Serial connected +[MP] 🔌 Please power the target now + + __ __ _ _ _ _ +| \/ (_)_ _ (_) | ___ __ _ __| | +| |\/| | | ' \| | |__/ _ \/ _` / _` | +|_| |_|_|_||_|_|____\___/\__,_\__,_| + + Raspberry Pi 3 + +[ML] Requesting binary +[MP] ⏩ Pushing 7 KiB ==========================================🦀 100% 0 KiB/s Time: 00:00:00 +[ML] Loaded! Executing the payload now + +[0] mingo version 0.5.0 +[1] Booting on: Raspberry Pi 3 +[2] Drivers loaded: + 1. BCM PL011 UART + 2. BCM GPIO +[3] Chars written: 117 +[4] Echoing input now +``` + +在这个教程中，为了演示目的，加载了上一个教程中的内核版本。在后续的教程中，将使用工作目录的内核。 + +## 测试它 + +这个教程中的`Makefile`有一个额外的目标`qemuasm`，它可以让你很好地观察到内核在重新定位后如何从加载地址区域（`0x80_XXX`） +跳转到重新定位的代码（`0x0200_0XXX`）： + +```console +$ make qemuasm +[...] +N: +0x00080030: 58000140 ldr x0, #0x80058 +0x00080034: 9100001f mov sp, x0 +0x00080038: 58000141 ldr x1, #0x80060 +0x0008003c: d61f0020 br x1 + +---------------- +IN: +0x02000070: 9400044c bl #0x20011a0 + +---------------- +IN: +0x020011a0: 90000008 adrp x8, #0x2001000 +0x020011a4: 90000009 adrp x9, #0x2001000 +0x020011a8: f9446508 ldr x8, [x8, #0x8c8] +0x020011ac: f9446929 ldr x9, [x9, #0x8d0] +0x020011b0: eb08013f cmp x9, x8 +0x020011b4: 54000109 b.ls #0x20011d4 +[...] +``` + +## 相比之前的变化（diff） +请检查[英文版本](README.md#diff-to-previous)，这是最新的。 \ No newline at end of file diff --git a/tools/raspi4/chainloader/README.md b/tools/raspi4/chainloader/README.md new file mode 100644 index 0000000000..5e4efe25dd --- /dev/null +++ b/tools/raspi4/chainloader/README.md @@ -0,0 +1,670 @@ +# Tutorial 06 - UART Chainloader + +## tl;dr + +- Running from an SD card was a nice experience, but it would be extremely tedious to do it for + every new binary. So let's write a [chainloader]. +- This will be the last binary you need to put on the SD card. Each following tutorial will provide + a `chainboot` target in the `Makefile` that lets you conveniently load the kernel over `UART`. + +[chainloader]: https://en.wikipedia.org/wiki/Chain_loading + + +## Note + +Please note that there is stuff going on in this tutorial that is very hard to grasp by only looking +at the source code changes. + +The gist of it is that in `boot.s`, we are writing a piece of [position independent code] which +automatically determines where the firmware has loaded the binary (`0x8_0000`), and where it was +linked to (`0x200_0000`, see `kernel.ld`). The binary then copies itself from loaded to linked +address (aka "relocating" itself), and then jumps to the relocated version of `_start_rust()`. + +Since the chainloader has put itself "out of the way" now, it can now receive another kernel binary +from the `UART` and copy it to the standard load address of the RPi firmware at `0x8_0000`. Finally, +it jumps to `0x8_0000` and the newly loaded binary transparently executes as if it had been loaded +from SD card all along. + +Please bear with me until I find the time to write it all down here elaborately. For the time being, +please see this tutorial as an enabler for a convenience feature that allows booting the following +tutorials in a quick manner. _For those keen to get a deeper understanding, it could make sense to +skip forward to [Chapter 15](../15_virtual_mem_part3_precomputed_tables) and read the first half of +the README, where `Load Address != Link Address` is discussed_. + +[position independent code]: https://en.wikipedia.org/wiki/Position-independent_code + +## Install and test it + +Our chainloader is called `MiniLoad` and is inspired by [raspbootin]. + +You can try it with this tutorial already: +1. Depending on your target hardware, run:`make` or `BSP=rpi4 make`. +1. Copy `kernel8.img` to the SD card and put the SD card back into your RPi. +1. Run `make chainboot` or `BSP=rpi4 make chainboot`. +1. Connect the USB serial to your host PC. + - Wiring diagram at [top-level README](../README.md#-usb-serial-output). + - Make sure that you **DID NOT** connect the power pin of the USB serial. Only RX/TX and GND. +1. Connect the RPi to the (USB) power cable. +1. Observe the loader fetching a kernel over `UART`: + +> ❗ **NOTE**: `make chainboot` assumes a default serial device name of `/dev/ttyUSB0`. Depending on +> your host operating system, the device name might differ. For example, on `macOS`, it might be +> something like `/dev/tty.usbserial-0001`. In this case, please give the name explicitly: + + +```console +$ DEV_SERIAL=/dev/tty.usbserial-0001 make chainboot +``` + +[raspbootin]: https://github.com/mrvn/raspbootin + +```console +$ make chainboot +[...] +Minipush 1.0 + +[MP] ⏳ Waiting for /dev/ttyUSB0 +[MP] ✅ Serial connected +[MP] 🔌 Please power the target now + + __ __ _ _ _ _ +| \/ (_)_ _ (_) | ___ __ _ __| | +| |\/| | | ' \| | |__/ _ \/ _` / _` | +|_| |_|_|_||_|_|____\___/\__,_\__,_| + + Raspberry Pi 3 + +[ML] Requesting binary +[MP] ⏩ Pushing 7 KiB ==========================================🦀 100% 0 KiB/s Time: 00:00:00 +[ML] Loaded! Executing the payload now + +[0] mingo version 0.5.0 +[1] Booting on: Raspberry Pi 3 +[2] Drivers loaded: + 1. BCM PL011 UART + 2. BCM GPIO +[3] Chars written: 117 +[4] Echoing input now +``` + +In this tutorial, a version of the kernel from the previous tutorial is loaded for demo purposes. In +subsequent tutorials, it will be the working directory's kernel. + +## Test it + +The `Makefile` in this tutorial has an additional target, `qemuasm`, that lets you nicely observe +how the kernel, after relocating itself, jumps the load address region (`0x80_XXX`) to the relocated +code at (`0x0200_0XXX`): + +```console +$ make qemuasm +[...] +N: +0x00080030: 58000140 ldr x0, #0x80058 +0x00080034: 9100001f mov sp, x0 +0x00080038: 58000141 ldr x1, #0x80060 +0x0008003c: d61f0020 br x1 + +---------------- +IN: +0x02000070: 9400044c bl #0x20011a0 + +---------------- +IN: +0x020011a0: 90000008 adrp x8, #0x2001000 +0x020011a4: 90000009 adrp x9, #0x2001000 +0x020011a8: f9446508 ldr x8, [x8, #0x8c8] +0x020011ac: f9446929 ldr x9, [x9, #0x8d0] +0x020011b0: eb08013f cmp x9, x8 +0x020011b4: 54000109 b.ls #0x20011d4 +[...] +``` + +## Diff to previous +```diff + +diff -uNr 05_drivers_gpio_uart/Cargo.toml 06_uart_chainloader/Cargo.toml +--- 05_drivers_gpio_uart/Cargo.toml ++++ 06_uart_chainloader/Cargo.toml +@@ -1,6 +1,6 @@ + [package] + name = "mingo" +-version = "0.5.0" ++version = "0.6.0" + authors = ["Andre Richter "] + edition = "2021" + +Binary files 05_drivers_gpio_uart/demo_payload_rpi3.img and 06_uart_chainloader/demo_payload_rpi3.img differ +Binary files 05_drivers_gpio_uart/demo_payload_rpi4.img and 06_uart_chainloader/demo_payload_rpi4.img differ + +diff -uNr 05_drivers_gpio_uart/Makefile 06_uart_chainloader/Makefile +--- 05_drivers_gpio_uart/Makefile ++++ 06_uart_chainloader/Makefile +@@ -24,27 +24,29 @@ + QEMU_MISSING_STRING = "This board is not yet supported for QEMU." + + ifeq ($(BSP),rpi3) +- TARGET = aarch64-unknown-none-softfloat +- KERNEL_BIN = kernel8.img +- QEMU_BINARY = qemu-system-aarch64 +- QEMU_MACHINE_TYPE = raspi3 +- QEMU_RELEASE_ARGS = -serial stdio -display none +- OBJDUMP_BINARY = aarch64-none-elf-objdump +- NM_BINARY = aarch64-none-elf-nm +- READELF_BINARY = aarch64-none-elf-readelf +- LD_SCRIPT_PATH = $(shell pwd)/src/bsp/raspberrypi +- RUSTC_MISC_ARGS = -C target-cpu=cortex-a53 ++ TARGET = aarch64-unknown-none-softfloat ++ KERNEL_BIN = kernel8.img ++ QEMU_BINARY = qemu-system-aarch64 ++ QEMU_MACHINE_TYPE = raspi3 ++ QEMU_RELEASE_ARGS = -serial stdio -display none ++ OBJDUMP_BINARY = aarch64-none-elf-objdump ++ NM_BINARY = aarch64-none-elf-nm ++ READELF_BINARY = aarch64-none-elf-readelf ++ LD_SCRIPT_PATH = $(shell pwd)/src/bsp/raspberrypi ++ RUSTC_MISC_ARGS = -C target-cpu=cortex-a53 ++ CHAINBOOT_DEMO_PAYLOAD = demo_payload_rpi3.img + else ifeq ($(BSP),rpi4) +- TARGET = aarch64-unknown-none-softfloat +- KERNEL_BIN = kernel8.img +- QEMU_BINARY = qemu-system-aarch64 +- QEMU_MACHINE_TYPE = +- QEMU_RELEASE_ARGS = -serial stdio -display none +- OBJDUMP_BINARY = aarch64-none-elf-objdump +- NM_BINARY = aarch64-none-elf-nm +- READELF_BINARY = aarch64-none-elf-readelf +- LD_SCRIPT_PATH = $(shell pwd)/src/bsp/raspberrypi +- RUSTC_MISC_ARGS = -C target-cpu=cortex-a72 ++ TARGET = aarch64-unknown-none-softfloat ++ KERNEL_BIN = kernel8.img ++ QEMU_BINARY = qemu-system-aarch64 ++ QEMU_MACHINE_TYPE = ++ QEMU_RELEASE_ARGS = -serial stdio -display none ++ OBJDUMP_BINARY = aarch64-none-elf-objdump ++ NM_BINARY = aarch64-none-elf-nm ++ READELF_BINARY = aarch64-none-elf-readelf ++ LD_SCRIPT_PATH = $(shell pwd)/src/bsp/raspberrypi ++ RUSTC_MISC_ARGS = -C target-cpu=cortex-a72 ++ CHAINBOOT_DEMO_PAYLOAD = demo_payload_rpi4.img + endif + + # Export for build.rs. +@@ -90,8 +92,8 @@ + -O binary + + EXEC_QEMU = $(QEMU_BINARY) -M $(QEMU_MACHINE_TYPE) +-EXEC_TEST_DISPATCH = ruby ../common/tests/dispatch.rb +-EXEC_MINITERM = ruby ../common/serial/miniterm.rb ++EXEC_TEST_MINIPUSH = ruby tests/chainboot_test.rb ++EXEC_MINIPUSH = ruby ../common/serial/minipush.rb + + ##------------------------------------------------------------------------------ + ## Dockerization +@@ -110,7 +112,7 @@ + ifeq ($(shell uname -s),Linux) + DOCKER_CMD_DEV = $(DOCKER_CMD_INTERACT) $(DOCKER_ARG_DEV) + +- DOCKER_MINITERM = $(DOCKER_CMD_DEV) $(DOCKER_ARG_DIR_COMMON) $(DOCKER_IMAGE) ++ DOCKER_CHAINBOOT = $(DOCKER_CMD_DEV) $(DOCKER_ARG_DIR_COMMON) $(DOCKER_IMAGE) + endif + + +@@ -118,7 +120,7 @@ + ##-------------------------------------------------------------------------------------------------- + ## Targets + ##-------------------------------------------------------------------------------------------------- +-.PHONY: all doc qemu miniterm clippy clean readelf objdump nm check ++.PHONY: all doc qemu chainboot clippy clean readelf objdump nm check + + all: $(KERNEL_BIN) + +@@ -160,7 +162,7 @@ + ##------------------------------------------------------------------------------ + ifeq ($(QEMU_MACHINE_TYPE),) # QEMU is not supported for the board. + +-qemu: ++qemu qemuasm: + $(call color_header, "$(QEMU_MISSING_STRING)") + + else # QEMU is supported. +@@ -169,13 +171,17 @@ + $(call color_header, "Launching QEMU") + @$(DOCKER_QEMU) $(EXEC_QEMU) $(QEMU_RELEASE_ARGS) -kernel $(KERNEL_BIN) + ++qemuasm: $(KERNEL_BIN) ++ $(call color_header, "Launching QEMU with ASM output") ++ @$(DOCKER_QEMU) $(EXEC_QEMU) $(QEMU_RELEASE_ARGS) -kernel $(KERNEL_BIN) -d in_asm ++ + endif + ##------------------------------------------------------------------------------ +-## Connect to the target's serial ++## Push the kernel to the real HW target + ##------------------------------------------------------------------------------ +-miniterm: +- @$(DOCKER_MINITERM) $(EXEC_MINITERM) $(DEV_SERIAL) ++chainboot: $(KERNEL_BIN) ++ @$(DOCKER_CHAINBOOT) $(EXEC_MINIPUSH) $(DEV_SERIAL) $(CHAINBOOT_DEMO_PAYLOAD) + + ##------------------------------------------------------------------------------ + ## Run clippy +@@ -232,7 +238,8 @@ + ##------------------------------------------------------------------------------ + test_boot: $(KERNEL_BIN) + $(call color_header, "Boot test - $(BSP)") +- @$(DOCKER_TEST) $(EXEC_TEST_DISPATCH) $(EXEC_QEMU) $(QEMU_RELEASE_ARGS) -kernel $(KERNEL_BIN) ++ @$(DOCKER_TEST) $(EXEC_TEST_MINIPUSH) $(EXEC_QEMU) $(QEMU_RELEASE_ARGS) \ ++ -kernel $(KERNEL_BIN) $(CHAINBOOT_DEMO_PAYLOAD) + + test: test_boot + + +diff -uNr 05_drivers_gpio_uart/src/_arch/aarch64/cpu/boot.s 06_uart_chainloader/src/_arch/aarch64/cpu/boot.s +--- 05_drivers_gpio_uart/src/_arch/aarch64/cpu/boot.s ++++ 06_uart_chainloader/src/_arch/aarch64/cpu/boot.s +@@ -18,6 +18,17 @@ + add \register, \register, #:lo12:\symbol + .endm + ++// Load the address of a symbol into a register, absolute. ++// ++// # Resources ++// ++// - https://sourceware.org/binutils/docs-2.36/as/AArch64_002dRelocations.html ++.macro ADR_ABS register, symbol ++ movz \register, #:abs_g2:\symbol ++ movk \register, #:abs_g1_nc:\symbol ++ movk \register, #:abs_g0_nc:\symbol ++.endm ++ + //-------------------------------------------------------------------------------------------------- + // Public Code + //-------------------------------------------------------------------------------------------------- +@@ -37,23 +48,35 @@ + // If execution reaches here, it is the boot core. + + // Initialize DRAM. +- ADR_REL x0, __bss_start +- ADR_REL x1, __bss_end_exclusive ++ ADR_ABS x0, __bss_start ++ ADR_ABS x1, __bss_end_exclusive + + .L_bss_init_loop: + cmp x0, x1 +- b.eq .L_prepare_rust ++ b.eq .L_relocate_binary + stp xzr, xzr, [x0], #16 + b .L_bss_init_loop + ++ // Next, relocate the binary. ++.L_relocate_binary: ++ ADR_REL x0, __binary_nonzero_start // The address the binary got loaded to. ++ ADR_ABS x1, __binary_nonzero_start // The address the binary was linked to. ++ ADR_ABS x2, __binary_nonzero_end_exclusive ++ ++.L_copy_loop: ++ ldr x3, [x0], #8 ++ str x3, [x1], #8 ++ cmp x1, x2 ++ b.lo .L_copy_loop ++ + // Prepare the jump to Rust code. +-.L_prepare_rust: + // Set the stack pointer. +- ADR_REL x0, __boot_core_stack_end_exclusive ++ ADR_ABS x0, __boot_core_stack_end_exclusive + mov sp, x0 + +- // Jump to Rust code. +- b _start_rust ++ // Jump to the relocated Rust code. ++ ADR_ABS x1, _start_rust ++ br x1 + + // Infinitely wait for events (aka "park the core"). + .L_parking_loop: + +diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs +--- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs ++++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs +@@ -275,7 +275,7 @@ + } + + /// Retrieve a character. +- fn read_char_converting(&mut self, blocking_mode: BlockingMode) -> Option { ++ fn read_char(&mut self, blocking_mode: BlockingMode) -> Option { + // If RX FIFO is empty, + if self.registers.FR.matches_all(FR::RXFE::SET) { + // immediately return in non-blocking mode. +@@ -290,12 +290,7 @@ + } + + // Read one character. +- let mut ret = self.registers.DR.get() as u8 as char; +- +- // Convert carrige return to newline. +- if ret == '\r' { +- ret = '\n' +- } ++ let ret = self.registers.DR.get() as u8 as char; + + // Update statistics. + self.chars_read += 1; +@@ -381,14 +376,14 @@ + impl console::interface::Read for PL011Uart { + fn read_char(&self) -> char { + self.inner +- .lock(|inner| inner.read_char_converting(BlockingMode::Blocking).unwrap()) ++ .lock(|inner| inner.read_char(BlockingMode::Blocking).unwrap()) + } + + fn clear_rx(&self) { + // Read from the RX FIFO until it is indicating empty. + while self + .inner +- .lock(|inner| inner.read_char_converting(BlockingMode::NonBlocking)) ++ .lock(|inner| inner.read_char(BlockingMode::NonBlocking)) + .is_some() + {} + } + +diff -uNr 05_drivers_gpio_uart/src/bsp/raspberrypi/console.rs 06_uart_chainloader/src/bsp/raspberrypi/console.rs +--- 05_drivers_gpio_uart/src/bsp/raspberrypi/console.rs ++++ 06_uart_chainloader/src/bsp/raspberrypi/console.rs +@@ -1,16 +0,0 @@ +-// SPDX-License-Identifier: MIT OR Apache-2.0 +-// +-// Copyright (c) 2018-2023 Andre Richter +- +-//! BSP console facilities. +- +-use crate::console; +- +-//-------------------------------------------------------------------------------------------------- +-// Public Code +-//-------------------------------------------------------------------------------------------------- +- +-/// Return a reference to the console. +-pub fn console() -> &'static dyn console::interface::All { +- &super::driver::PL011_UART +-} + +diff -uNr 05_drivers_gpio_uart/src/bsp/raspberrypi/kernel.ld 06_uart_chainloader/src/bsp/raspberrypi/kernel.ld +--- 05_drivers_gpio_uart/src/bsp/raspberrypi/kernel.ld ++++ 06_uart_chainloader/src/bsp/raspberrypi/kernel.ld +@@ -3,8 +3,6 @@ + * Copyright (c) 2018-2023 Andre Richter + */ + +-__rpi_phys_dram_start_addr = 0; +- + /* The physical address at which the the kernel binary will be loaded by the Raspberry's firmware */ + __rpi_phys_binary_load_addr = 0x80000; + +@@ -28,7 +26,8 @@ + + SECTIONS + { +- . = __rpi_phys_dram_start_addr; ++ /* Set the link address to 32 MiB */ ++ . = 0x2000000; + + /*********************************************************************************************** + * Boot Core Stack +@@ -45,6 +44,7 @@ + /*********************************************************************************************** + * Code + RO Data + Global Offset Table + ***********************************************************************************************/ ++ __binary_nonzero_start = .; + .text : + { + KEEP(*(.text._start)) +@@ -60,6 +60,10 @@ + ***********************************************************************************************/ + .data : { *(.data*) } :segment_data + ++ /* Fill up to 8 byte, b/c relocating the binary is done in u64 chunks */ ++ . = ALIGN(8); ++ __binary_nonzero_end_exclusive = .; ++ + /* Section is zeroed in pairs of u64. Align start and end to 16 bytes */ + .bss (NOLOAD) : ALIGN(16) + { + +diff -uNr 05_drivers_gpio_uart/src/bsp/raspberrypi/memory.rs 06_uart_chainloader/src/bsp/raspberrypi/memory.rs +--- 05_drivers_gpio_uart/src/bsp/raspberrypi/memory.rs ++++ 06_uart_chainloader/src/bsp/raspberrypi/memory.rs +@@ -11,6 +11,7 @@ + /// The board's physical memory map. + #[rustfmt::skip] + pub(super) mod map { ++ pub const BOARD_DEFAULT_LOAD_ADDRESS: usize = 0x8_0000; + + pub const GPIO_OFFSET: usize = 0x0020_0000; + pub const UART_OFFSET: usize = 0x0020_1000; +@@ -35,3 +36,13 @@ + pub const PL011_UART_START: usize = START + UART_OFFSET; + } + } ++ ++//-------------------------------------------------------------------------------------------------- ++// Public Code ++//-------------------------------------------------------------------------------------------------- ++ ++/// The address on which the Raspberry firmware loads every binary by default. ++#[inline(always)] ++pub fn board_default_load_addr() -> *const u64 { ++ map::BOARD_DEFAULT_LOAD_ADDRESS as _ ++} + +diff -uNr 05_drivers_gpio_uart/src/driver.rs 06_uart_chainloader/src/driver.rs +--- 05_drivers_gpio_uart/src/driver.rs ++++ 06_uart_chainloader/src/driver.rs +@@ -4,10 +4,7 @@ + + //! Driver support. + +-use crate::{ +- println, +- synchronization::{interface::Mutex, NullLock}, +-}; ++use crate::synchronization::{interface::Mutex, NullLock}; + + //-------------------------------------------------------------------------------------------------- + // Private Definitions +@@ -154,14 +151,4 @@ + } + }); + } +- +- /// Enumerate all registered device drivers. +- pub fn enumerate(&self) { +- let mut i: usize = 1; +- self.for_each_descriptor(|descriptor| { +- println!(" {}. {}", i, descriptor.device_driver.compatible()); +- +- i += 1; +- }); +- } + } + +diff -uNr 05_drivers_gpio_uart/src/main.rs 06_uart_chainloader/src/main.rs +--- 05_drivers_gpio_uart/src/main.rs ++++ 06_uart_chainloader/src/main.rs +@@ -142,27 +142,55 @@ + kernel_main() + } + ++const MINILOAD_LOGO: &str = r#" ++ __ __ _ _ _ _ ++| \/ (_)_ _ (_) | ___ __ _ __| | ++| |\/| | | ' \| | |__/ _ \/ _` / _` | ++|_| |_|_|_||_|_|____\___/\__,_\__,_| ++"#; ++ + /// The main function running after the early init. + fn kernel_main() -> ! { + use console::console; + +- println!( +- "[0] {} version {}", +- env!("CARGO_PKG_NAME"), +- env!("CARGO_PKG_VERSION") +- ); +- println!("[1] Booting on: {}", bsp::board_name()); ++ println!("{}", MINILOAD_LOGO); ++ println!("{:^37}", bsp::board_name()); ++ println!(); ++ println!("[ML] Requesting binary"); ++ console().flush(); + +- println!("[2] Drivers loaded:"); +- driver::driver_manager().enumerate(); ++ // Discard any spurious received characters before starting with the loader protocol. ++ console().clear_rx(); + +- println!("[3] Chars written: {}", console().chars_written()); +- println!("[4] Echoing input now"); ++ // Notify `Minipush` to send the binary. ++ for _ in 0..3 { ++ console().write_char(3 as char); ++ } + +- // Discard any spurious received characters before going into echo mode. +- console().clear_rx(); +- loop { +- let c = console().read_char(); +- console().write_char(c); ++ // Read the binary's size. ++ let mut size: u32 = u32::from(console().read_char() as u8); ++ size |= u32::from(console().read_char() as u8) << 8; ++ size |= u32::from(console().read_char() as u8) << 16; ++ size |= u32::from(console().read_char() as u8) << 24; ++ ++ // Trust it's not too big. ++ console().write_char('O'); ++ console().write_char('K'); ++ ++ let kernel_addr: *mut u8 = bsp::memory::board_default_load_addr() as *mut u8; ++ unsafe { ++ // Read the kernel byte by byte. ++ for i in 0..size { ++ core::ptr::write_volatile(kernel_addr.offset(i as isize), console().read_char() as u8) ++ } + } ++ ++ println!("[ML] Loaded! Executing the payload now\n"); ++ console().flush(); ++ ++ // Use black magic to create a function pointer. ++ let kernel: fn() -> ! = unsafe { core::mem::transmute(kernel_addr) }; ++ ++ // Jump to loaded kernel! ++ kernel() + } + +diff -uNr 05_drivers_gpio_uart/tests/boot_test_string.rb 06_uart_chainloader/tests/boot_test_string.rb +--- 05_drivers_gpio_uart/tests/boot_test_string.rb ++++ 06_uart_chainloader/tests/boot_test_string.rb +@@ -1,3 +0,0 @@ +-# frozen_string_literal: true +- +-EXPECTED_PRINT = 'Echoing input now' + +diff -uNr 05_drivers_gpio_uart/tests/chainboot_test.rb 06_uart_chainloader/tests/chainboot_test.rb +--- 05_drivers_gpio_uart/tests/chainboot_test.rb ++++ 06_uart_chainloader/tests/chainboot_test.rb +@@ -0,0 +1,78 @@ ++# frozen_string_literal: true ++ ++# SPDX-License-Identifier: MIT OR Apache-2.0 ++# ++# Copyright (c) 2020-2023 Andre Richter ++ ++require_relative '../../common/serial/minipush' ++require_relative '../../common/tests/boot_test' ++require 'pty' ++ ++# Match for the last print that 'demo_payload_rpiX.img' produces. ++EXPECTED_PRINT = 'Echoing input now' ++ ++# Wait for request to power the target. ++class PowerTargetRequestTest < SubtestBase ++ MINIPUSH_POWER_TARGET_REQUEST = 'Please power the target now' ++ ++ def initialize(qemu_cmd, pty_main) ++ super() ++ @qemu_cmd = qemu_cmd ++ @pty_main = pty_main ++ end ++ ++ def name ++ 'Waiting for request to power target' ++ end ++ ++ def run(qemu_out, _qemu_in) ++ expect_or_raise(qemu_out, MINIPUSH_POWER_TARGET_REQUEST) ++ ++ # Now is the time to start QEMU with the chainloader binary. QEMU's virtual tty connects to ++ # the MiniPush instance spawned on pty_main, so that the two processes talk to each other. ++ Process.spawn(@qemu_cmd, in: @pty_main, out: @pty_main, err: '/dev/null') ++ end ++end ++ ++# Extend BootTest so that it listens on the output of a MiniPush instance, which is itself connected ++# to a QEMU instance instead of a real HW. ++class ChainbootTest < BootTest ++ MINIPUSH = '../common/serial/minipush.rb' ++ ++ def initialize(qemu_cmd, payload_path) ++ super(qemu_cmd, EXPECTED_PRINT) ++ ++ @test_name = 'Boot test using Minipush' ++ ++ @payload_path = payload_path ++ end ++ ++ private ++ ++ # override ++ def setup ++ pty_main, pty_secondary = PTY.open ++ mp_out, _mp_in = PTY.spawn("ruby #{MINIPUSH} #{pty_secondary.path} #{@payload_path}") ++ ++ # The subtests (from this class and the parents) listen on @qemu_out_wrapped. Hence, point ++ # it to MiniPush's output. ++ @qemu_out_wrapped = PTYLoggerWrapper.new(mp_out, "\r\n") ++ ++ # Important: Run this subtest before the one in the parent class. ++ @console_subtests.prepend(PowerTargetRequestTest.new(@qemu_cmd, pty_main)) ++ end ++ ++ # override ++ def finish ++ super() ++ @test_output.map! { |x| x.gsub(/.*\r/, ' ') } ++ end ++end ++ ++##-------------------------------------------------------------------------------------------------- ++## Execution starts here ++##-------------------------------------------------------------------------------------------------- ++payload_path = ARGV.pop ++qemu_cmd = ARGV.join(' ') ++ ++ChainbootTest.new(qemu_cmd, payload_path).run + +diff -uNr 05_drivers_gpio_uart/update.sh 06_uart_chainloader/update.sh +--- 05_drivers_gpio_uart/update.sh ++++ 06_uart_chainloader/update.sh +@@ -0,0 +1,8 @@ ++#!/usr/bin/env bash ++ ++cd ../05_drivers_gpio_uart ++BSP=rpi4 make ++cp kernel8.img ../06_uart_chainloader/demo_payload_rpi4.img ++make ++cp kernel8.img ../06_uart_chainloader/demo_payload_rpi3.img ++rm kernel8.img + +``` diff --git a/tools/raspi4/chainloader/build.rs b/tools/raspi4/chainloader/build.rs new file mode 100644 index 0000000000..cab00bb377 --- /dev/null +++ b/tools/raspi4/chainloader/build.rs @@ -0,0 +1,20 @@ +use std::{env, fs, process}; + +fn main() { + let ld_script_path = match env::var("LD_SCRIPT_PATH") { + Ok(var) => var, + _ => process::exit(0), + }; + + let files = fs::read_dir(ld_script_path).unwrap(); + files + .filter_map(Result::ok) + .filter(|d| { + if let Some(e) = d.path().extension() { + e == "ld" + } else { + false + } + }) + .for_each(|f| println!("cargo:rerun-if-changed={}", f.path().display())); +} diff --git a/tools/raspi4/chainloader/src/_arch/aarch64/cpu.rs b/tools/raspi4/chainloader/src/_arch/aarch64/cpu.rs new file mode 100644 index 0000000000..f1f1e9aff7 --- /dev/null +++ b/tools/raspi4/chainloader/src/_arch/aarch64/cpu.rs @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! Architectural processor code. +//! +//! # Orientation +//! +//! Since arch modules are imported into generic modules using the path attribute, the path of this +//! file is: +//! +//! crate::cpu::arch_cpu + +use aarch64_cpu::asm; + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +pub use asm::nop; + +/// Spin for `n` cycles. +#[cfg(feature = "bsp_rpi3")] +#[inline(always)] +pub fn spin_for_cycles(n: usize) { + for _ in 0..n { + asm::nop(); + } +} + +/// Pause execution on the core. +#[inline(always)] +pub fn wait_forever() -> ! { + loop { + asm::wfe() + } +} diff --git a/tools/raspi4/chainloader/src/_arch/aarch64/cpu/boot.rs b/tools/raspi4/chainloader/src/_arch/aarch64/cpu/boot.rs new file mode 100644 index 0000000000..2a6c46492f --- /dev/null +++ b/tools/raspi4/chainloader/src/_arch/aarch64/cpu/boot.rs @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2021-2023 Andre Richter + +//! Architectural boot code. +//! +//! # Orientation +//! +//! Since arch modules are imported into generic modules using the path attribute, the path of this +//! file is: +//! +//! crate::cpu::boot::arch_boot + +use core::arch::global_asm; + +// Assembly counterpart to this file. +global_asm!( + include_str!("boot.s"), + CONST_CORE_ID_MASK = const 0b11 +); + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +/// The Rust entry of the `kernel` binary. +/// +/// The function is called from the assembly `_start` function. +#[no_mangle] +pub unsafe fn _start_rust() -> ! { + crate::kernel_init() +} diff --git a/tools/raspi4/chainloader/src/_arch/aarch64/cpu/boot.s b/tools/raspi4/chainloader/src/_arch/aarch64/cpu/boot.s new file mode 100644 index 0000000000..3ed0d4941d --- /dev/null +++ b/tools/raspi4/chainloader/src/_arch/aarch64/cpu/boot.s @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2021-2022 Andre Richter + +//-------------------------------------------------------------------------------------------------- +// Definitions +//-------------------------------------------------------------------------------------------------- + +// Load the address of a symbol into a register, PC-relative. +// +// The symbol must lie within +/- 4 GiB of the Program Counter. +// +// # Resources +// +// - https://sourceware.org/binutils/docs-2.36/as/AArch64_002dRelocations.html +.macro ADR_REL register, symbol + adrp \register, \symbol + add \register, \register, #:lo12:\symbol +.endm + +// Load the address of a symbol into a register, absolute. +// +// # Resources +// +// - https://sourceware.org/binutils/docs-2.36/as/AArch64_002dRelocations.html +.macro ADR_ABS register, symbol + movz \register, #:abs_g2:\symbol + movk \register, #:abs_g1_nc:\symbol + movk \register, #:abs_g0_nc:\symbol +.endm + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- +.section .text._start + +//------------------------------------------------------------------------------ +// fn _start() +//------------------------------------------------------------------------------ +_start: + // Only proceed on the boot core. Park it otherwise. + mrs x0, MPIDR_EL1 + and x0, x0, {CONST_CORE_ID_MASK} + ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs + cmp x0, x1 + b.ne .L_parking_loop + + // If execution reaches here, it is the boot core. + + // Initialize DRAM. + ADR_ABS x0, __bss_start + ADR_ABS x1, __bss_end_exclusive + +.L_bss_init_loop: + cmp x0, x1 + b.eq .L_relocate_binary + stp xzr, xzr, [x0], #16 + b .L_bss_init_loop + + // Next, relocate the binary. +.L_relocate_binary: + ADR_REL x0, __binary_nonzero_start // The address the binary got loaded to. + ADR_ABS x1, __binary_nonzero_start // The address the binary was linked to. + ADR_ABS x2, __binary_nonzero_end_exclusive + +.L_copy_loop: + ldr x3, [x0], #8 + str x3, [x1], #8 + cmp x1, x2 + b.lo .L_copy_loop + + // Prepare the jump to Rust code. + // Set the stack pointer. + ADR_ABS x0, __boot_core_stack_end_exclusive + mov sp, x0 + + // Jump to the relocated Rust code. + ADR_ABS x1, _start_rust + br x1 + + // Infinitely wait for events (aka "park the core"). +.L_parking_loop: + wfe + b .L_parking_loop + +.size _start, . - _start +.type _start, function +.global _start diff --git a/tools/raspi4/chainloader/src/bsp.rs b/tools/raspi4/chainloader/src/bsp.rs new file mode 100644 index 0000000000..246973bc04 --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp.rs @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! Conditional reexporting of Board Support Packages. + +mod device_driver; + +#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))] +mod raspberrypi; + +#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))] +pub use raspberrypi::*; diff --git a/tools/raspi4/chainloader/src/bsp/device_driver.rs b/tools/raspi4/chainloader/src/bsp/device_driver.rs new file mode 100644 index 0000000000..64049a4cfa --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/device_driver.rs @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! Device driver. + +#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))] +mod bcm; +mod common; + +#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))] +pub use bcm::*; diff --git a/tools/raspi4/chainloader/src/bsp/device_driver/bcm.rs b/tools/raspi4/chainloader/src/bsp/device_driver/bcm.rs new file mode 100644 index 0000000000..1c343d1d74 --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/device_driver/bcm.rs @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! BCM driver top level. + +mod bcm2xxx_gpio; +mod bcm2xxx_pl011_uart; + +pub use bcm2xxx_gpio::*; +pub use bcm2xxx_pl011_uart::*; diff --git a/tools/raspi4/chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/tools/raspi4/chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs new file mode 100644 index 0000000000..920b4c00cd --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! GPIO Driver. + +use crate::{ + bsp::device_driver::common::MMIODerefWrapper, driver, synchronization, + synchronization::NullLock, +}; +use tock_registers::{ + interfaces::{ReadWriteable, Writeable}, + register_bitfields, register_structs, + registers::ReadWrite, +}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions +//-------------------------------------------------------------------------------------------------- + +// GPIO registers. +// +// Descriptions taken from +// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf +// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf +register_bitfields! { + u32, + + /// GPIO Function Select 1 + GPFSEL1 [ + /// Pin 15 + FSEL15 OFFSET(15) NUMBITS(3) [ + Input = 0b000, + Output = 0b001, + AltFunc0 = 0b100 // PL011 UART RX + + ], + + /// Pin 14 + FSEL14 OFFSET(12) NUMBITS(3) [ + Input = 0b000, + Output = 0b001, + AltFunc0 = 0b100 // PL011 UART TX + ] + ], + + /// GPIO Pull-up/down Register + /// + /// BCM2837 only. + GPPUD [ + /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins. + PUD OFFSET(0) NUMBITS(2) [ + Off = 0b00, + PullDown = 0b01, + PullUp = 0b10 + ] + ], + + /// GPIO Pull-up/down Clock Register 0 + /// + /// BCM2837 only. + GPPUDCLK0 [ + /// Pin 15 + PUDCLK15 OFFSET(15) NUMBITS(1) [ + NoEffect = 0, + AssertClock = 1 + ], + + /// Pin 14 + PUDCLK14 OFFSET(14) NUMBITS(1) [ + NoEffect = 0, + AssertClock = 1 + ] + ], + + /// GPIO Pull-up / Pull-down Register 0 + /// + /// BCM2711 only. + GPIO_PUP_PDN_CNTRL_REG0 [ + /// Pin 15 + GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [ + NoResistor = 0b00, + PullUp = 0b01 + ], + + /// Pin 14 + GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [ + NoResistor = 0b00, + PullUp = 0b01 + ] + ] +} + +register_structs! { + #[allow(non_snake_case)] + RegisterBlock { + (0x00 => _reserved1), + (0x04 => GPFSEL1: ReadWrite), + (0x08 => _reserved2), + (0x94 => GPPUD: ReadWrite), + (0x98 => GPPUDCLK0: ReadWrite), + (0x9C => _reserved3), + (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite), + (0xE8 => @END), + } +} + +/// Abstraction for the associated MMIO registers. +type Registers = MMIODerefWrapper; + +struct GPIOInner { + registers: Registers, +} + +//-------------------------------------------------------------------------------------------------- +// Public Definitions +//-------------------------------------------------------------------------------------------------- + +/// Representation of the GPIO HW. +pub struct GPIO { + inner: NullLock, +} + +//-------------------------------------------------------------------------------------------------- +// Private Code +//-------------------------------------------------------------------------------------------------- + +impl GPIOInner { + /// Create an instance. + /// + /// # Safety + /// + /// - The user must ensure to provide a correct MMIO start address. + pub const unsafe fn new(mmio_start_addr: usize) -> Self { + Self { + registers: Registers::new(mmio_start_addr), + } + } + + /// Disable pull-up/down on pins 14 and 15. + #[cfg(feature = "bsp_rpi3")] + fn disable_pud_14_15_bcm2837(&mut self) { + use crate::cpu; + + // Make an educated guess for a good delay value (Sequence described in the BCM2837 + // peripherals PDF). + // + // - According to Wikipedia, the fastest RPi4 clocks around 1.5 GHz. + // - The Linux 2837 GPIO driver waits 1 µs between the steps. + // + // So lets try to be on the safe side and default to 2000 cycles, which would equal 1 µs + // would the CPU be clocked at 2 GHz. + const DELAY: usize = 2000; + + self.registers.GPPUD.write(GPPUD::PUD::Off); + cpu::spin_for_cycles(DELAY); + + self.registers + .GPPUDCLK0 + .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock); + cpu::spin_for_cycles(DELAY); + + self.registers.GPPUD.write(GPPUD::PUD::Off); + self.registers.GPPUDCLK0.set(0); + } + + /// Disable pull-up/down on pins 14 and 15. + #[cfg(feature = "bsp_rpi4")] + fn disable_pud_14_15_bcm2711(&mut self) { + self.registers.GPIO_PUP_PDN_CNTRL_REG0.write( + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp + + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp, + ); + } + + /// Map PL011 UART as standard output. + /// + /// TX to pin 14 + /// RX to pin 15 + pub fn map_pl011_uart(&mut self) { + // Select the UART on pins 14 and 15. + self.registers + .GPFSEL1 + .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0); + + // Disable pull-up/down on pins 14 and 15. + #[cfg(feature = "bsp_rpi3")] + self.disable_pud_14_15_bcm2837(); + + #[cfg(feature = "bsp_rpi4")] + self.disable_pud_14_15_bcm2711(); + } +} + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +impl GPIO { + pub const COMPATIBLE: &'static str = "BCM GPIO"; + + /// Create an instance. + /// + /// # Safety + /// + /// - The user must ensure to provide a correct MMIO start address. + pub const unsafe fn new(mmio_start_addr: usize) -> Self { + Self { + inner: NullLock::new(GPIOInner::new(mmio_start_addr)), + } + } + + /// Concurrency safe version of `GPIOInner.map_pl011_uart()` + pub fn map_pl011_uart(&self) { + self.inner.lock(|inner| inner.map_pl011_uart()) + } +} + +//------------------------------------------------------------------------------ +// OS Interface Code +//------------------------------------------------------------------------------ +use synchronization::interface::Mutex; + +impl driver::interface::DeviceDriver for GPIO { + fn compatible(&self) -> &'static str { + Self::COMPATIBLE + } +} diff --git a/tools/raspi4/chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs b/tools/raspi4/chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs new file mode 100644 index 0000000000..50a069ea1b --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! PL011 UART driver. +//! +//! # Resources +//! +//! - +//! - + +use crate::{ + bsp::device_driver::common::MMIODerefWrapper, console, cpu, driver, synchronization, + synchronization::NullLock, +}; +use core::fmt; +use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, register_structs, + registers::{ReadOnly, ReadWrite, WriteOnly}, +}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions +//-------------------------------------------------------------------------------------------------- + +// PL011 UART registers. +// +// Descriptions taken from "PrimeCell UART (PL011) Technical Reference Manual" r1p5. +register_bitfields! { + u32, + + /// Flag Register. + FR [ + /// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the + /// Line Control Register, LCR_H. + /// + /// - If the FIFO is disabled, this bit is set when the transmit holding register is empty. + /// - If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. + /// - This bit does not indicate if there is data in the transmit shift register. + TXFE OFFSET(7) NUMBITS(1) [], + + /// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the + /// LCR_H Register. + /// + /// - If the FIFO is disabled, this bit is set when the transmit holding register is full. + /// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + TXFF OFFSET(5) NUMBITS(1) [], + + /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the + /// LCR_H Register. + /// + /// - If the FIFO is disabled, this bit is set when the receive holding register is empty. + /// - If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + RXFE OFFSET(4) NUMBITS(1) [], + + /// UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains + /// set until the complete byte, including all the stop bits, has been sent from the shift + /// register. + /// + /// This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether + /// the UART is enabled or not. + BUSY OFFSET(3) NUMBITS(1) [] + ], + + /// Integer Baud Rate Divisor. + IBRD [ + /// The integer baud rate divisor. + BAUD_DIVINT OFFSET(0) NUMBITS(16) [] + ], + + /// Fractional Baud Rate Divisor. + FBRD [ + /// The fractional baud rate divisor. + BAUD_DIVFRAC OFFSET(0) NUMBITS(6) [] + ], + + /// Line Control Register. + LCR_H [ + /// Word length. These bits indicate the number of data bits transmitted or received in a + /// frame. + #[allow(clippy::enum_variant_names)] + WLEN OFFSET(5) NUMBITS(2) [ + FiveBit = 0b00, + SixBit = 0b01, + SevenBit = 0b10, + EightBit = 0b11 + ], + + /// Enable FIFOs: + /// + /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding + /// registers. + /// + /// 1 = Transmit and receive FIFO buffers are enabled (FIFO mode). + FEN OFFSET(4) NUMBITS(1) [ + FifosDisabled = 0, + FifosEnabled = 1 + ] + ], + + /// Control Register. + CR [ + /// Receive enable. If this bit is set to 1, the receive section of the UART is enabled. + /// Data reception occurs for either UART signals or SIR signals depending on the setting of + /// the SIREN bit. When the UART is disabled in the middle of reception, it completes the + /// current character before stopping. + RXE OFFSET(9) NUMBITS(1) [ + Disabled = 0, + Enabled = 1 + ], + + /// Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. + /// Data transmission occurs for either UART signals, or SIR signals depending on the + /// setting of the SIREN bit. When the UART is disabled in the middle of transmission, it + /// completes the current character before stopping. + TXE OFFSET(8) NUMBITS(1) [ + Disabled = 0, + Enabled = 1 + ], + + /// UART enable: + /// + /// 0 = UART is disabled. If the UART is disabled in the middle of transmission or + /// reception, it completes the current character before stopping. + /// + /// 1 = The UART is enabled. Data transmission and reception occurs for either UART signals + /// or SIR signals depending on the setting of the SIREN bit + UARTEN OFFSET(0) NUMBITS(1) [ + /// If the UART is disabled in the middle of transmission or reception, it completes the + /// current character before stopping. + Disabled = 0, + Enabled = 1 + ] + ], + + /// Interrupt Clear Register. + ICR [ + /// Meta field for all pending interrupts. + ALL OFFSET(0) NUMBITS(11) [] + ] +} + +register_structs! { + #[allow(non_snake_case)] + pub RegisterBlock { + (0x00 => DR: ReadWrite), + (0x04 => _reserved1), + (0x18 => FR: ReadOnly), + (0x1c => _reserved2), + (0x24 => IBRD: WriteOnly), + (0x28 => FBRD: WriteOnly), + (0x2c => LCR_H: WriteOnly), + (0x30 => CR: WriteOnly), + (0x34 => _reserved3), + (0x44 => ICR: WriteOnly), + (0x48 => @END), + } +} + +/// Abstraction for the associated MMIO registers. +type Registers = MMIODerefWrapper; + +#[derive(PartialEq)] +enum BlockingMode { + Blocking, + NonBlocking, +} + +struct PL011UartInner { + registers: Registers, + chars_written: usize, + chars_read: usize, +} + +//-------------------------------------------------------------------------------------------------- +// Public Definitions +//-------------------------------------------------------------------------------------------------- + +/// Representation of the UART. +pub struct PL011Uart { + inner: NullLock, +} + +//-------------------------------------------------------------------------------------------------- +// Private Code +//-------------------------------------------------------------------------------------------------- + +impl PL011UartInner { + /// Create an instance. + /// + /// # Safety + /// + /// - The user must ensure to provide a correct MMIO start address. + pub const unsafe fn new(mmio_start_addr: usize) -> Self { + Self { + registers: Registers::new(mmio_start_addr), + chars_written: 0, + chars_read: 0, + } + } + + /// Set up baud rate and characteristics. + /// + /// This results in 8N1 and 921_600 baud. + /// + /// The calculation for the BRD is (we set the clock to 48 MHz in config.txt): + /// `(48_000_000 / 16) / 921_600 = 3.2552083`. + /// + /// This means the integer part is `3` and goes into the `IBRD`. + /// The fractional part is `0.2552083`. + /// + /// `FBRD` calculation according to the PL011 Technical Reference Manual: + /// `INTEGER((0.2552083 * 64) + 0.5) = 16`. + /// + /// Therefore, the generated baud rate divider is: `3 + 16/64 = 3.25`. Which results in a + /// genrated baud rate of `48_000_000 / (16 * 3.25) = 923_077`. + /// + /// Error = `((923_077 - 921_600) / 921_600) * 100 = 0.16%`. + pub fn init(&mut self) { + // Execution can arrive here while there are still characters queued in the TX FIFO and + // actively being sent out by the UART hardware. If the UART is turned off in this case, + // those queued characters would be lost. + // + // For example, this can happen during runtime on a call to panic!(), because panic!() + // initializes its own UART instance and calls init(). + // + // Hence, flush first to ensure all pending characters are transmitted. + self.flush(); + + // Turn the UART off temporarily. + self.registers.CR.set(0); + + // Clear all pending interrupts. + self.registers.ICR.write(ICR::ALL::CLEAR); + + // From the PL011 Technical Reference Manual: + // + // The LCR_H, IBRD, and FBRD registers form the single 30-bit wide LCR Register that is + // updated on a single write strobe generated by a LCR_H write. So, to internally update the + // contents of IBRD or FBRD, a LCR_H write must always be performed at the end. + // + // Set the baud rate, 8N1 and FIFO enabled. + self.registers.IBRD.write(IBRD::BAUD_DIVINT.val(3)); + self.registers.FBRD.write(FBRD::BAUD_DIVFRAC.val(16)); + self.registers + .LCR_H + .write(LCR_H::WLEN::EightBit + LCR_H::FEN::FifosEnabled); + + // Turn the UART on. + self.registers + .CR + .write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled); + } + + /// Send a character. + fn write_char(&mut self, c: char) { + // Spin while TX FIFO full is set, waiting for an empty slot. + while self.registers.FR.matches_all(FR::TXFF::SET) { + cpu::nop(); + } + + // Write the character to the buffer. + self.registers.DR.set(c as u32); + + self.chars_written += 1; + } + + /// Block execution until the last buffered character has been physically put on the TX wire. + fn flush(&self) { + // Spin until the busy bit is cleared. + while self.registers.FR.matches_all(FR::BUSY::SET) { + cpu::nop(); + } + } + + /// Retrieve a character. + fn read_char(&mut self, blocking_mode: BlockingMode) -> Option { + // If RX FIFO is empty, + if self.registers.FR.matches_all(FR::RXFE::SET) { + // immediately return in non-blocking mode. + if blocking_mode == BlockingMode::NonBlocking { + return None; + } + + // Otherwise, wait until a char was received. + while self.registers.FR.matches_all(FR::RXFE::SET) { + cpu::nop(); + } + } + + // Read one character. + let ret = self.registers.DR.get() as u8 as char; + + // Update statistics. + self.chars_read += 1; + + Some(ret) + } +} + +/// Implementing `core::fmt::Write` enables usage of the `format_args!` macros, which in turn are +/// used to implement the `kernel`'s `print!` and `println!` macros. By implementing `write_str()`, +/// we get `write_fmt()` automatically. +/// +/// The function takes an `&mut self`, so it must be implemented for the inner struct. +/// +/// See [`src/print.rs`]. +/// +/// [`src/print.rs`]: ../../print/index.html +impl fmt::Write for PL011UartInner { + fn write_str(&mut self, s: &str) -> fmt::Result { + for c in s.chars() { + self.write_char(c); + } + + Ok(()) + } +} + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +impl PL011Uart { + pub const COMPATIBLE: &'static str = "BCM PL011 UART"; + + /// Create an instance. + /// + /// # Safety + /// + /// - The user must ensure to provide a correct MMIO start address. + pub const unsafe fn new(mmio_start_addr: usize) -> Self { + Self { + inner: NullLock::new(PL011UartInner::new(mmio_start_addr)), + } + } +} + +//------------------------------------------------------------------------------ +// OS Interface Code +//------------------------------------------------------------------------------ +use synchronization::interface::Mutex; + +impl driver::interface::DeviceDriver for PL011Uart { + fn compatible(&self) -> &'static str { + Self::COMPATIBLE + } + + unsafe fn init(&self) -> Result<(), &'static str> { + self.inner.lock(|inner| inner.init()); + + Ok(()) + } +} + +impl console::interface::Write for PL011Uart { + /// Passthrough of `args` to the `core::fmt::Write` implementation, but guarded by a Mutex to + /// serialize access. + fn write_char(&self, c: char) { + self.inner.lock(|inner| inner.write_char(c)); + } + + fn write_fmt(&self, args: core::fmt::Arguments) -> fmt::Result { + // Fully qualified syntax for the call to `core::fmt::Write::write_fmt()` to increase + // readability. + self.inner.lock(|inner| fmt::Write::write_fmt(inner, args)) + } + + fn flush(&self) { + // Spin until TX FIFO empty is set. + self.inner.lock(|inner| inner.flush()); + } +} + +impl console::interface::Read for PL011Uart { + fn read_char(&self) -> char { + self.inner + .lock(|inner| inner.read_char(BlockingMode::Blocking).unwrap()) + } + + fn clear_rx(&self) { + // Read from the RX FIFO until it is indicating empty. + while self + .inner + .lock(|inner| inner.read_char(BlockingMode::NonBlocking)) + .is_some() + {} + } +} + +impl console::interface::Statistics for PL011Uart { + fn chars_written(&self) -> usize { + self.inner.lock(|inner| inner.chars_written) + } + + fn chars_read(&self) -> usize { + self.inner.lock(|inner| inner.chars_read) + } +} + +impl console::interface::All for PL011Uart {} diff --git a/tools/raspi4/chainloader/src/bsp/device_driver/common.rs b/tools/raspi4/chainloader/src/bsp/device_driver/common.rs new file mode 100644 index 0000000000..dfe7d8ef31 --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/device_driver/common.rs @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2020-2023 Andre Richter + +//! Common device driver code. + +use core::{marker::PhantomData, ops}; + +//-------------------------------------------------------------------------------------------------- +// Public Definitions +//-------------------------------------------------------------------------------------------------- + +pub struct MMIODerefWrapper { + start_addr: usize, + phantom: PhantomData T>, +} + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +impl MMIODerefWrapper { + /// Create an instance. + pub const unsafe fn new(start_addr: usize) -> Self { + Self { + start_addr, + phantom: PhantomData, + } + } +} + +impl ops::Deref for MMIODerefWrapper { + type Target = T; + + fn deref(&self) -> &Self::Target { + unsafe { &*(self.start_addr as *const _) } + } +} diff --git a/tools/raspi4/chainloader/src/bsp/raspberrypi.rs b/tools/raspi4/chainloader/src/bsp/raspberrypi.rs new file mode 100644 index 0000000000..3ea864dc78 --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/raspberrypi.rs @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! Top-level BSP file for the Raspberry Pi 3 and 4. + +pub mod cpu; +pub mod driver; +pub mod memory; + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +/// Board identification. +pub fn board_name() -> &'static str { + #[cfg(feature = "bsp_rpi3")] + { + "Raspberry Pi 3" + } + + #[cfg(feature = "bsp_rpi4")] + { + "Raspberry Pi 4" + } +} diff --git a/tools/raspi4/chainloader/src/bsp/raspberrypi/cpu.rs b/tools/raspi4/chainloader/src/bsp/raspberrypi/cpu.rs new file mode 100644 index 0000000000..65cf5abbe0 --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/raspberrypi/cpu.rs @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! BSP Processor code. + +//-------------------------------------------------------------------------------------------------- +// Public Definitions +//-------------------------------------------------------------------------------------------------- + +/// Used by `arch` code to find the early boot core. +#[no_mangle] +#[link_section = ".text._start_arguments"] +pub static BOOT_CORE_ID: u64 = 0; diff --git a/tools/raspi4/chainloader/src/bsp/raspberrypi/driver.rs b/tools/raspi4/chainloader/src/bsp/raspberrypi/driver.rs new file mode 100644 index 0000000000..2a80ee2c53 --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/raspberrypi/driver.rs @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! BSP driver support. + +use super::memory::map::mmio; +use crate::{bsp::device_driver, console, driver as generic_driver}; +use core::sync::atomic::{AtomicBool, Ordering}; + +//-------------------------------------------------------------------------------------------------- +// Global instances +//-------------------------------------------------------------------------------------------------- + +static PL011_UART: device_driver::PL011Uart = + unsafe { device_driver::PL011Uart::new(mmio::PL011_UART_START) }; +static GPIO: device_driver::GPIO = unsafe { device_driver::GPIO::new(mmio::GPIO_START) }; + +//-------------------------------------------------------------------------------------------------- +// Private Code +//-------------------------------------------------------------------------------------------------- + +/// This must be called only after successful init of the UART driver. +fn post_init_uart() -> Result<(), &'static str> { + console::register_console(&PL011_UART); + + Ok(()) +} + +/// This must be called only after successful init of the GPIO driver. +fn post_init_gpio() -> Result<(), &'static str> { + GPIO.map_pl011_uart(); + Ok(()) +} + +fn driver_uart() -> Result<(), &'static str> { + let uart_descriptor = + generic_driver::DeviceDriverDescriptor::new(&PL011_UART, Some(post_init_uart)); + generic_driver::driver_manager().register_driver(uart_descriptor); + + Ok(()) +} + +fn driver_gpio() -> Result<(), &'static str> { + let gpio_descriptor = generic_driver::DeviceDriverDescriptor::new(&GPIO, Some(post_init_gpio)); + generic_driver::driver_manager().register_driver(gpio_descriptor); + + Ok(()) +} + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +/// Initialize the driver subsystem. +/// +/// # Safety +/// +/// See child function calls. +pub unsafe fn init() -> Result<(), &'static str> { + static INIT_DONE: AtomicBool = AtomicBool::new(false); + if INIT_DONE.load(Ordering::Relaxed) { + return Err("Init already done"); + } + + driver_uart()?; + driver_gpio()?; + + INIT_DONE.store(true, Ordering::Relaxed); + Ok(()) +} diff --git a/tools/raspi4/chainloader/src/bsp/raspberrypi/kernel.ld b/tools/raspi4/chainloader/src/bsp/raspberrypi/kernel.ld new file mode 100644 index 0000000000..c84b62381d --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/raspberrypi/kernel.ld @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: MIT OR Apache-2.0 + * + * Copyright (c) 2018-2022 Andre Richter + */ + +/* The physical address at which the the kernel binary will be loaded by the Raspberry's firmware */ +__rpi_phys_binary_load_addr = 0x80000; + + +ENTRY(__rpi_phys_binary_load_addr) + +/* Flags: + * 4 == R + * 5 == RX + * 6 == RW + * + * Segments are marked PT_LOAD below so that the ELF file provides virtual and physical addresses. + * It doesn't mean all of them need actually be loaded. + */ +PHDRS +{ + segment_boot_core_stack PT_LOAD FLAGS(6); + segment_code PT_LOAD FLAGS(5); + segment_data PT_LOAD FLAGS(6); +} + +SECTIONS +{ + /* Set the link address to 32 MiB */ + . = 0x2000000; + + /*********************************************************************************************** + * Boot Core Stack + ***********************************************************************************************/ + .boot_core_stack (NOLOAD) : + { + /* ^ */ + /* | stack */ + . += __rpi_phys_binary_load_addr; /* | growth */ + /* | direction */ + __boot_core_stack_end_exclusive = .; /* | */ + } :segment_boot_core_stack + + /*********************************************************************************************** + * Code + RO Data + Global Offset Table + ***********************************************************************************************/ + __binary_nonzero_start = .; + .text : + { + KEEP(*(.text._start)) + *(.text._start_arguments) /* Constants (or statics in Rust speak) read by _start(). */ + *(.text._start_rust) /* The Rust entry point */ + *(.text*) /* Everything else */ + } :segment_code + + .rodata : ALIGN(8) { *(.rodata*) } :segment_code + + /*********************************************************************************************** + * Data + BSS + ***********************************************************************************************/ + .data : { *(.data*) } :segment_data + + /* Fill up to 8 byte, b/c relocating the binary is done in u64 chunks */ + . = ALIGN(8); + __binary_nonzero_end_exclusive = .; + + /* Section is zeroed in pairs of u64. Align start and end to 16 bytes */ + .bss (NOLOAD) : ALIGN(16) + { + __bss_start = .; + *(.bss*); + . = ALIGN(16); + __bss_end_exclusive = .; + } :segment_data + + /*********************************************************************************************** + * Misc + ***********************************************************************************************/ + .got : { *(.got*) } + ASSERT(SIZEOF(.got) == 0, "Relocation support not expected") + + /DISCARD/ : { *(.comment*) } +} diff --git a/tools/raspi4/chainloader/src/bsp/raspberrypi/memory.rs b/tools/raspi4/chainloader/src/bsp/raspberrypi/memory.rs new file mode 100644 index 0000000000..ee72b27a04 --- /dev/null +++ b/tools/raspi4/chainloader/src/bsp/raspberrypi/memory.rs @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! BSP Memory Management. + +//-------------------------------------------------------------------------------------------------- +// Public Definitions +//-------------------------------------------------------------------------------------------------- + +/// The board's physical memory map. +#[rustfmt::skip] +pub(super) mod map { + pub const BOARD_DEFAULT_LOAD_ADDRESS: usize = 0x8_0000; + + pub const GPIO_OFFSET: usize = 0x0020_0000; + pub const UART_OFFSET: usize = 0x0020_1000; + + /// Physical devices. + #[cfg(feature = "bsp_rpi3")] + pub mod mmio { + use super::*; + + pub const START: usize = 0x3F00_0000; + pub const GPIO_START: usize = START + GPIO_OFFSET; + pub const PL011_UART_START: usize = START + UART_OFFSET; + } + + /// Physical devices. + #[cfg(feature = "bsp_rpi4")] + pub mod mmio { + use super::*; + + pub const START: usize = 0xFE00_0000; + pub const GPIO_START: usize = START + GPIO_OFFSET; + pub const PL011_UART_START: usize = START + UART_OFFSET; + } +} + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +/// The address on which the Raspberry firmware loads every binary by default. +#[inline(always)] +pub fn board_default_load_addr() -> *const u64 { + map::BOARD_DEFAULT_LOAD_ADDRESS as _ +} diff --git a/tools/raspi4/chainloader/src/console.rs b/tools/raspi4/chainloader/src/console.rs new file mode 100644 index 0000000000..a83f86fe01 --- /dev/null +++ b/tools/raspi4/chainloader/src/console.rs @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! System console. + +mod null_console; + +use crate::synchronization::{self, NullLock}; + +//-------------------------------------------------------------------------------------------------- +// Public Definitions +//-------------------------------------------------------------------------------------------------- + +/// Console interfaces. +pub mod interface { + use core::fmt; + + /// Console write functions. + pub trait Write { + /// Write a single character. + fn write_char(&self, c: char); + + /// Write a Rust format string. + fn write_fmt(&self, args: fmt::Arguments) -> fmt::Result; + + /// Block until the last buffered character has been physically put on the TX wire. + fn flush(&self); + } + + /// Console read functions. + pub trait Read { + /// Read a single character. + fn read_char(&self) -> char { + ' ' + } + + /// Clear RX buffers, if any. + fn clear_rx(&self); + } + + /// Console statistics. + pub trait Statistics { + /// Return the number of characters written. + fn chars_written(&self) -> usize { + 0 + } + + /// Return the number of characters read. + fn chars_read(&self) -> usize { + 0 + } + } + + /// Trait alias for a full-fledged console. + pub trait All: Write + Read + Statistics {} +} + +//-------------------------------------------------------------------------------------------------- +// Global instances +//-------------------------------------------------------------------------------------------------- + +static CUR_CONSOLE: NullLock<&'static (dyn interface::All + Sync)> = + NullLock::new(&null_console::NULL_CONSOLE); + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- +use synchronization::interface::Mutex; + +/// Register a new console. +pub fn register_console(new_console: &'static (dyn interface::All + Sync)) { + CUR_CONSOLE.lock(|con| *con = new_console); +} + +/// Return a reference to the currently registered console. +/// +/// This is the global console used by all printing macros. +pub fn console() -> &'static dyn interface::All { + CUR_CONSOLE.lock(|con| *con) +} diff --git a/tools/raspi4/chainloader/src/console/null_console.rs b/tools/raspi4/chainloader/src/console/null_console.rs new file mode 100644 index 0000000000..e92a022b6c --- /dev/null +++ b/tools/raspi4/chainloader/src/console/null_console.rs @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2022-2023 Andre Richter + +//! Null console. + +use super::interface; +use core::fmt; + +//-------------------------------------------------------------------------------------------------- +// Public Definitions +//-------------------------------------------------------------------------------------------------- + +pub struct NullConsole; + +//-------------------------------------------------------------------------------------------------- +// Global instances +//-------------------------------------------------------------------------------------------------- + +pub static NULL_CONSOLE: NullConsole = NullConsole {}; + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +impl interface::Write for NullConsole { + fn write_char(&self, _c: char) {} + + fn write_fmt(&self, _args: fmt::Arguments) -> fmt::Result { + fmt::Result::Ok(()) + } + + fn flush(&self) {} +} + +impl interface::Read for NullConsole { + fn clear_rx(&self) {} +} + +impl interface::Statistics for NullConsole {} +impl interface::All for NullConsole {} diff --git a/tools/raspi4/chainloader/src/cpu.rs b/tools/raspi4/chainloader/src/cpu.rs new file mode 100644 index 0000000000..eacb8924a4 --- /dev/null +++ b/tools/raspi4/chainloader/src/cpu.rs @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2020-2023 Andre Richter + +//! Processor code. + +#[cfg(target_arch = "aarch64")] +#[path = "_arch/aarch64/cpu.rs"] +mod arch_cpu; + +mod boot; + +//-------------------------------------------------------------------------------------------------- +// Architectural Public Reexports +//-------------------------------------------------------------------------------------------------- +pub use arch_cpu::{nop, wait_forever}; + +#[cfg(feature = "bsp_rpi3")] +pub use arch_cpu::spin_for_cycles; diff --git a/tools/raspi4/chainloader/src/cpu/boot.rs b/tools/raspi4/chainloader/src/cpu/boot.rs new file mode 100644 index 0000000000..b1e98328ac --- /dev/null +++ b/tools/raspi4/chainloader/src/cpu/boot.rs @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2021-2023 Andre Richter + +//! Boot code. + +#[cfg(target_arch = "aarch64")] +#[path = "../_arch/aarch64/cpu/boot.rs"] +mod arch_boot; diff --git a/tools/raspi4/chainloader/src/driver.rs b/tools/raspi4/chainloader/src/driver.rs new file mode 100644 index 0000000000..53592c66b1 --- /dev/null +++ b/tools/raspi4/chainloader/src/driver.rs @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! Driver support. + +use crate::synchronization::{interface::Mutex, NullLock}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions +//-------------------------------------------------------------------------------------------------- + +const NUM_DRIVERS: usize = 5; + +struct DriverManagerInner { + next_index: usize, + descriptors: [Option; NUM_DRIVERS], +} + +//-------------------------------------------------------------------------------------------------- +// Public Definitions +//-------------------------------------------------------------------------------------------------- + +/// Driver interfaces. +pub mod interface { + /// Device Driver functions. + pub trait DeviceDriver { + /// Return a compatibility string for identifying the driver. + fn compatible(&self) -> &'static str; + + /// Called by the kernel to bring up the device. + /// + /// # Safety + /// + /// - During init, drivers might do stuff with system-wide impact. + unsafe fn init(&self) -> Result<(), &'static str> { + Ok(()) + } + } +} + +/// Tpye to be used as an optional callback after a driver's init() has run. +pub type DeviceDriverPostInitCallback = unsafe fn() -> Result<(), &'static str>; + +/// A descriptor for device drivers. +#[derive(Copy, Clone)] +pub struct DeviceDriverDescriptor { + device_driver: &'static (dyn interface::DeviceDriver + Sync), + post_init_callback: Option, +} + +/// Provides device driver management functions. +pub struct DriverManager { + inner: NullLock, +} + +//-------------------------------------------------------------------------------------------------- +// Global instances +//-------------------------------------------------------------------------------------------------- + +static DRIVER_MANAGER: DriverManager = DriverManager::new(); + +//-------------------------------------------------------------------------------------------------- +// Private Code +//-------------------------------------------------------------------------------------------------- + +impl DriverManagerInner { + /// Create an instance. + pub const fn new() -> Self { + Self { + next_index: 0, + descriptors: [None; NUM_DRIVERS], + } + } +} + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +impl DeviceDriverDescriptor { + /// Create an instance. + pub fn new( + device_driver: &'static (dyn interface::DeviceDriver + Sync), + post_init_callback: Option, + ) -> Self { + Self { + device_driver, + post_init_callback, + } + } +} + +/// Return a reference to the global DriverManager. +pub fn driver_manager() -> &'static DriverManager { + &DRIVER_MANAGER +} + +impl DriverManager { + /// Create an instance. + pub const fn new() -> Self { + Self { + inner: NullLock::new(DriverManagerInner::new()), + } + } + + /// Register a device driver with the kernel. + pub fn register_driver(&self, descriptor: DeviceDriverDescriptor) { + self.inner.lock(|inner| { + inner.descriptors[inner.next_index] = Some(descriptor); + inner.next_index += 1; + }) + } + + /// Helper for iterating over registered drivers. + fn for_each_descriptor<'a>(&'a self, f: impl FnMut(&'a DeviceDriverDescriptor)) { + self.inner.lock(|inner| { + inner + .descriptors + .iter() + .filter_map(|x| x.as_ref()) + .for_each(f) + }) + } + + /// Fully initialize all drivers. + /// + /// # Safety + /// + /// - During init, drivers might do stuff with system-wide impact. + pub unsafe fn init_drivers(&self) { + self.for_each_descriptor(|descriptor| { + // 1. Initialize driver. + if let Err(x) = descriptor.device_driver.init() { + panic!( + "Error initializing driver: {}: {}", + descriptor.device_driver.compatible(), + x + ); + } + + // 2. Call corresponding post init callback. + if let Some(callback) = &descriptor.post_init_callback { + if let Err(x) = callback() { + panic!( + "Error during driver post-init callback: {}: {}", + descriptor.device_driver.compatible(), + x + ); + } + } + }); + } +} diff --git a/tools/raspi4/chainloader/src/main.rs b/tools/raspi4/chainloader/src/main.rs new file mode 100644 index 0000000000..e5e547252f --- /dev/null +++ b/tools/raspi4/chainloader/src/main.rs @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +// Rust embedded logo for `make doc`. +#![doc( + html_logo_url = "https://raw.githubusercontent.com/rust-embedded/wg/master/assets/logo/ewg-logo-blue-white-on-transparent.png" +)] + +//! The `kernel` binary. +//! +//! # Code organization and architecture +//! +//! The code is divided into different *modules*, each representing a typical **subsystem** of the +//! `kernel`. Top-level module files of subsystems reside directly in the `src` folder. For example, +//! `src/memory.rs` contains code that is concerned with all things memory management. +//! +//! ## Visibility of processor architecture code +//! +//! Some of the `kernel`'s subsystems depend on low-level code that is specific to the target +//! processor architecture. For each supported processor architecture, there exists a subfolder in +//! `src/_arch`, for example, `src/_arch/aarch64`. +//! +//! The architecture folders mirror the subsystem modules laid out in `src`. For example, +//! architectural code that belongs to the `kernel`'s MMU subsystem (`src/memory/mmu.rs`) would go +//! into `src/_arch/aarch64/memory/mmu.rs`. The latter file is loaded as a module in +//! `src/memory/mmu.rs` using the `path attribute`. Usually, the chosen module name is the generic +//! module's name prefixed with `arch_`. +//! +//! For example, this is the top of `src/memory/mmu.rs`: +//! +//! ``` +//! #[cfg(target_arch = "aarch64")] +//! #[path = "../_arch/aarch64/memory/mmu.rs"] +//! mod arch_mmu; +//! ``` +//! +//! Often times, items from the `arch_ module` will be publicly reexported by the parent module. +//! This way, each architecture specific module can provide its implementation of an item, while the +//! caller must not be concerned which architecture has been conditionally compiled. +//! +//! ## BSP code +//! +//! `BSP` stands for Board Support Package. `BSP` code is organized under `src/bsp.rs` and contains +//! target board specific definitions and functions. These are things such as the board's memory map +//! or instances of drivers for devices that are featured on the respective board. +//! +//! Just like processor architecture code, the `BSP` code's module structure tries to mirror the +//! `kernel`'s subsystem modules, but there is no reexporting this time. That means whatever is +//! provided must be called starting from the `bsp` namespace, e.g. `bsp::driver::driver_manager()`. +//! +//! ## Kernel interfaces +//! +//! Both `arch` and `bsp` contain code that is conditionally compiled depending on the actual target +//! and board for which the kernel is compiled. For example, the `interrupt controller` hardware of +//! the `Raspberry Pi 3` and the `Raspberry Pi 4` is different, but we want the rest of the `kernel` +//! code to play nicely with any of the two without much hassle. +//! +//! In order to provide a clean abstraction between `arch`, `bsp` and `generic kernel code`, +//! `interface` traits are provided *whenever possible* and *where it makes sense*. They are defined +//! in the respective subsystem module and help to enforce the idiom of *program to an interface, +//! not an implementation*. For example, there will be a common IRQ handling interface which the two +//! different interrupt controller `drivers` of both Raspberrys will implement, and only export the +//! interface to the rest of the `kernel`. +//! +//! ``` +//! +-------------------+ +//! | Interface (Trait) | +//! | | +//! +--+-------------+--+ +//! ^ ^ +//! | | +//! | | +//! +----------+--+ +--+----------+ +//! | kernel code | | bsp code | +//! | | | arch code | +//! +-------------+ +-------------+ +//! ``` +//! +//! # Summary +//! +//! For a logical `kernel` subsystem, corresponding code can be distributed over several physical +//! locations. Here is an example for the **memory** subsystem: +//! +//! - `src/memory.rs` and `src/memory/**/*` +//! - Common code that is agnostic of target processor architecture and `BSP` characteristics. +//! - Example: A function to zero a chunk of memory. +//! - Interfaces for the memory subsystem that are implemented by `arch` or `BSP` code. +//! - Example: An `MMU` interface that defines `MMU` function prototypes. +//! - `src/bsp/__board_name__/memory.rs` and `src/bsp/__board_name__/memory/**/*` +//! - `BSP` specific code. +//! - Example: The board's memory map (physical addresses of DRAM and MMIO devices). +//! - `src/_arch/__arch_name__/memory.rs` and `src/_arch/__arch_name__/memory/**/*` +//! - Processor architecture specific code. +//! - Example: Implementation of the `MMU` interface for the `__arch_name__` processor +//! architecture. +//! +//! From a namespace perspective, **memory** subsystem code lives in: +//! +//! - `crate::memory::*` +//! - `crate::bsp::memory::*` +//! +//! # Boot flow +//! +//! 1. The kernel's entry point is the function `cpu::boot::arch_boot::_start()`. +//! - It is implemented in `src/_arch/__arch_name__/cpu/boot.s`. +//! 2. Once finished with architectural setup, the arch code calls `kernel_init()`. + +#![allow(dead_code)] +#![allow(clippy::upper_case_acronyms)] +#![feature(asm_const)] +#![feature(format_args_nl)] +#![feature(panic_info_message)] +#![feature(trait_alias)] +#![no_main] +#![no_std] + +mod bsp; +mod console; +mod cpu; +mod driver; +mod panic_wait; +mod print; +mod synchronization; + +/// Early init code. +/// +/// # Safety +/// +/// - Only a single core must be active and running this function. +/// - The init calls in this function must appear in the correct order. +unsafe fn kernel_init() -> ! { + // Initialize the BSP driver subsystem. + if let Err(x) = bsp::driver::init() { + panic!("Error initializing BSP driver subsystem: {}", x); + } + + // Initialize all device drivers. + driver::driver_manager().init_drivers(); + // println! is usable from here on. + + // Transition from unsafe to safe. + kernel_main() +} + +const MINILOAD_LOGO: &str = r#" + __ __ _ _ _ _ +| \/ (_)_ _ (_) | ___ __ _ __| | +| |\/| | | ' \| | |__/ _ \/ _` / _` | +|_| |_|_|_||_|_|____\___/\__,_\__,_| +"#; + +/// The main function running after the early init. +fn kernel_main() -> ! { + use console::console; + + println!("{}", MINILOAD_LOGO); + println!("{:^37}", bsp::board_name()); + println!(); + println!("[ML] Requesting binary"); + console().flush(); + + // Discard any spurious received characters before starting with the loader protocol. + console().clear_rx(); + + // Notify `Minipush` to send the binary. + for _ in 0..3 { + console().write_char(3 as char); + } + + // Read the binary's size. + let mut size: u32 = u32::from(console().read_char() as u8); + size |= u32::from(console().read_char() as u8) << 8; + size |= u32::from(console().read_char() as u8) << 16; + size |= u32::from(console().read_char() as u8) << 24; + + // Trust it's not too big. + console().write_char('O'); + console().write_char('K'); + + let kernel_addr: *mut u8 = bsp::memory::board_default_load_addr() as *mut u8; + unsafe { + // Read the kernel byte by byte. + for i in 0..size { + core::ptr::write_volatile(kernel_addr.offset(i as isize), console().read_char() as u8) + } + } + + println!("[ML] Loaded! Executing the payload now\n"); + console().flush(); + + #[cfg(feature = "enable_jtag_debug")] + print_jtag_info_and_wait_forever(); + + println!("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@"); + println!("@ You're using chainboot image . @"); + println!("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@"); + // Use black magic to create a function pointer. + let kernel: fn() -> ! = unsafe { core::mem::transmute(kernel_addr) }; + + // Jump to loaded kernel! + kernel() +} + +#[cfg(feature = "enable_jtag_debug")] +fn print_jtag_info_and_wait_forever() { + println!("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@"); + println!("@ You're using a JTAG debug image. @"); + println!("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@"); + println!("@ 1. open openocd, gdb @"); + println!("@ 2. target extended-remote :3333; @"); + println!("@ 3. set $pc=0x80000 @"); + println!("@ 4. break rust_entry/others @"); + println!("@ 5. break $previous_addr @"); + println!("@ 6. delete 1 @"); + println!("@ 7. load @"); + println!("@ 8. continue @"); + println!("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@"); + + // wait for gdb connect + cpu::wait_forever() +} diff --git a/tools/raspi4/chainloader/src/panic_wait.rs b/tools/raspi4/chainloader/src/panic_wait.rs new file mode 100644 index 0000000000..5bb0896e42 --- /dev/null +++ b/tools/raspi4/chainloader/src/panic_wait.rs @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! A panic handler that infinitely waits. + +use crate::{cpu, println}; +use core::panic::PanicInfo; + +//-------------------------------------------------------------------------------------------------- +// Private Code +//-------------------------------------------------------------------------------------------------- + +/// Stop immediately if called a second time. +/// +/// # Note +/// +/// Using atomics here relieves us from needing to use `unsafe` for the static variable. +/// +/// On `AArch64`, which is the only implemented architecture at the time of writing this, +/// [`AtomicBool::load`] and [`AtomicBool::store`] are lowered to ordinary load and store +/// instructions. They are therefore safe to use even with MMU + caching deactivated. +/// +/// [`AtomicBool::load`]: core::sync::atomic::AtomicBool::load +/// [`AtomicBool::store`]: core::sync::atomic::AtomicBool::store +fn panic_prevent_reenter() { + use core::sync::atomic::{AtomicBool, Ordering}; + + #[cfg(not(target_arch = "aarch64"))] + compile_error!("Add the target_arch to above's check if the following code is safe to use"); + + static PANIC_IN_PROGRESS: AtomicBool = AtomicBool::new(false); + + if !PANIC_IN_PROGRESS.load(Ordering::Relaxed) { + PANIC_IN_PROGRESS.store(true, Ordering::Relaxed); + + return; + } + + cpu::wait_forever() +} + +#[panic_handler] +fn panic(info: &PanicInfo) -> ! { + // Protect against panic infinite loops if any of the following code panics itself. + panic_prevent_reenter(); + + let (location, line, column) = match info.location() { + Some(loc) => (loc.file(), loc.line(), loc.column()), + _ => ("???", 0, 0), + }; + + println!( + "Kernel panic!\n\n\ + Panic location:\n File '{}', line {}, column {}\n\n\ + {}", + location, + line, + column, + info.message().unwrap_or(&format_args!("")), + ); + + cpu::wait_forever() +} diff --git a/tools/raspi4/chainloader/src/print.rs b/tools/raspi4/chainloader/src/print.rs new file mode 100644 index 0000000000..6de99572d0 --- /dev/null +++ b/tools/raspi4/chainloader/src/print.rs @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2023 Andre Richter + +//! Printing. + +use crate::console; +use core::fmt; + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +#[doc(hidden)] +pub fn _print(args: fmt::Arguments) { + console::console().write_fmt(args).unwrap(); +} + +/// Prints without a newline. +/// +/// Carbon copy from +#[macro_export] +macro_rules! print { + ($($arg:tt)*) => ($crate::print::_print(format_args!($($arg)*))); +} + +/// Prints with a newline. +/// +/// Carbon copy from +#[macro_export] +macro_rules! println { + () => ($crate::print!("\n")); + ($($arg:tt)*) => ({ + $crate::print::_print(format_args_nl!($($arg)*)); + }) +} diff --git a/tools/raspi4/chainloader/src/synchronization.rs b/tools/raspi4/chainloader/src/synchronization.rs new file mode 100644 index 0000000000..94c83de1c7 --- /dev/null +++ b/tools/raspi4/chainloader/src/synchronization.rs @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2020-2023 Andre Richter + +//! Synchronization primitives. +//! +//! # Resources +//! +//! - +//! - +//! - + +use core::cell::UnsafeCell; + +//-------------------------------------------------------------------------------------------------- +// Public Definitions +//-------------------------------------------------------------------------------------------------- + +/// Synchronization interfaces. +pub mod interface { + + /// Any object implementing this trait guarantees exclusive access to the data wrapped within + /// the Mutex for the duration of the provided closure. + pub trait Mutex { + /// The type of the data that is wrapped by this mutex. + type Data; + + /// Locks the mutex and grants the closure temporary mutable access to the wrapped data. + fn lock<'a, R>(&'a self, f: impl FnOnce(&'a mut Self::Data) -> R) -> R; + } +} + +/// A pseudo-lock for teaching purposes. +/// +/// In contrast to a real Mutex implementation, does not protect against concurrent access from +/// other cores to the contained data. This part is preserved for later lessons. +/// +/// The lock will only be used as long as it is safe to do so, i.e. as long as the kernel is +/// executing single-threaded, aka only running on a single core with interrupts disabled. +pub struct NullLock +where + T: ?Sized, +{ + data: UnsafeCell, +} + +//-------------------------------------------------------------------------------------------------- +// Public Code +//-------------------------------------------------------------------------------------------------- + +unsafe impl Send for NullLock where T: ?Sized + Send {} +unsafe impl Sync for NullLock where T: ?Sized + Send {} + +impl NullLock { + /// Create an instance. + pub const fn new(data: T) -> Self { + Self { + data: UnsafeCell::new(data), + } + } +} + +//------------------------------------------------------------------------------ +// OS Interface Code +//------------------------------------------------------------------------------ + +impl interface::Mutex for NullLock { + type Data = T; + + fn lock<'a, R>(&'a self, f: impl FnOnce(&'a mut Self::Data) -> R) -> R { + // In a real lock, there would be code encapsulating this line that ensures that this + // mutable reference will ever only be given out once at a time. + let data = unsafe { &mut *self.data.get() }; + + f(data) + } +} diff --git a/tools/raspi4/chainloader/tests/chainboot_test.rb b/tools/raspi4/chainloader/tests/chainboot_test.rb new file mode 100644 index 0000000000..00de42a367 --- /dev/null +++ b/tools/raspi4/chainloader/tests/chainboot_test.rb @@ -0,0 +1,78 @@ +# frozen_string_literal: true + +# SPDX-License-Identifier: MIT OR Apache-2.0 +# +# Copyright (c) 2020-2023 Andre Richter + +require_relative '../../common/serial/minipush' +require_relative '../../common/tests/boot_test' +require 'pty' + +# Match for the last print that 'demo_payload_rpiX.img' produces. +EXPECTED_PRINT = 'Echoing input now' + +# Wait for request to power the target. +class PowerTargetRequestTest < SubtestBase + MINIPUSH_POWER_TARGET_REQUEST = 'Please power the target now' + + def initialize(qemu_cmd, pty_main) + super() + @qemu_cmd = qemu_cmd + @pty_main = pty_main + end + + def name + 'Waiting for request to power target' + end + + def run(qemu_out, _qemu_in) + expect_or_raise(qemu_out, MINIPUSH_POWER_TARGET_REQUEST) + + # Now is the time to start QEMU with the chainloader binary. QEMU's virtual tty connects to + # the MiniPush instance spawned on pty_main, so that the two processes talk to each other. + Process.spawn(@qemu_cmd, in: @pty_main, out: @pty_main, err: '/dev/null') + end +end + +# Extend BootTest so that it listens on the output of a MiniPush instance, which is itself connected +# to a QEMU instance instead of a real HW. +class ChainbootTest < BootTest + MINIPUSH = '../common/serial/minipush.rb' + + def initialize(qemu_cmd, payload_path) + super(qemu_cmd, EXPECTED_PRINT) + + @test_name = 'Boot test using Minipush' + + @payload_path = payload_path + end + + private + + # override + def setup + pty_main, pty_secondary = PTY.open + mp_out, _mp_in = PTY.spawn("ruby #{MINIPUSH} #{pty_secondary.path} #{@payload_path}") + + # The subtests (from this class and the parents) listen on @qemu_out_wrapped. Hence, point + # it to MiniPush's output. + @qemu_out_wrapped = PTYLoggerWrapper.new(mp_out, "\r\n") + + # Important: Run this subtest before the one in the parent class. + @console_subtests.prepend(PowerTargetRequestTest.new(@qemu_cmd, pty_main)) + end + + # override + def finish + super() + @test_output.map! { |x| x.gsub(/.*\r/, ' ') } + end +end + +## ------------------------------------------------------------------------------------------------- +## Execution starts here +## ------------------------------------------------------------------------------------------------- +payload_path = ARGV.pop +qemu_cmd = ARGV.join(' ') + +ChainbootTest.new(qemu_cmd, payload_path).run diff --git a/tools/raspi4/chainloader/update.sh b/tools/raspi4/chainloader/update.sh new file mode 100755 index 0000000000..5fac48ba07 --- /dev/null +++ b/tools/raspi4/chainloader/update.sh @@ -0,0 +1,8 @@ +#!/usr/bin/env bash + +cd ../05_drivers_gpio_uart +BSP=rpi4 make +cp kernel8.img ../06_uart_chainloader/demo_payload_rpi4.img +make +cp kernel8.img ../06_uart_chainloader/demo_payload_rpi3.img +rm kernel8.img diff --git a/tools/raspi4/common/image/chainboot/kernel8.img b/tools/raspi4/common/image/chainboot/kernel8.img new file mode 100755 index 0000000000..6bbc69d352 Binary files /dev/null and b/tools/raspi4/common/image/chainboot/kernel8.img differ diff --git a/tools/raspi4/common/image/jtag/kernel8.img b/tools/raspi4/common/image/jtag/kernel8.img new file mode 100755 index 0000000000..5321b8e08f Binary files /dev/null and b/tools/raspi4/common/image/jtag/kernel8.img differ