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Merged
merged 7 commits into from
Jan 8, 2025
Merged

[FMV][AArch64] Simplify version selection according to ACLE. #121921

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785c6ec
[FMV][AArch64] Simplify version selection according to ACLE.
labrinea Jan 7, 2025
24e9178
Use bitmask for FMV priority and add a corresponding test.
labrinea Jan 7, 2025
9391d8d
Merge branch 'main' into fmv-priority
labrinea Jan 7, 2025
89b8c63
Move FeatPriorities in a separate file because AArch64CPUFeatures.inc
labrinea Jan 8, 2025
f197b26
Forgot to add the new file AArch64FeatPriorities.inc
labrinea Jan 8, 2025
665b4f1
reference ACLE pull request on test file
labrinea Jan 8, 2025
1d9d131
Merge branch 'main' into fmv-priority
labrinea Jan 8, 2025
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48 changes: 24 additions & 24 deletions clang/test/CodeGen/attr-target-clones-aarch64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -64,20 +64,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33664
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33664
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @ftc._MaesMlse
// CHECK-NEXT: ret ptr @ftc._Msve2
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 69793284352
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 69793284352
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @ftc._Msve2
// CHECK-NEXT: ret ptr @ftc._MaesMlse
// CHECK: resolver_else2:
// CHECK-NEXT: ret ptr @ftc.default
//
Expand Down Expand Up @@ -411,20 +411,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817985280
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817985280
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
// CHECK-NEXT: ret ptr @ftc_inline3._Mbti
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 70369817985280
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 70369817985280
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @ftc_inline3._Mbti
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
// CHECK: resolver_else2:
// CHECK-NEXT: ret ptr @ftc_inline3.default
//
Expand Down Expand Up @@ -521,20 +521,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-MTE-BTI-NEXT: resolver_entry:
// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver()
// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33664
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33664
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 69793284352
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 69793284352
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK-MTE-BTI: resolver_return:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._MaesMlse
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._Msve2
// CHECK-MTE-BTI: resolver_else:
// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 69793284352
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 69793284352
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33664
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33664
// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK-MTE-BTI: resolver_return1:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._Msve2
// CHECK-MTE-BTI-NEXT: ret ptr @ftc._MaesMlse
// CHECK-MTE-BTI: resolver_else2:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc.default
//
Expand Down Expand Up @@ -868,20 +868,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-MTE-BTI-NEXT: resolver_entry:
// CHECK-MTE-BTI-NEXT: call void @__init_cpu_features_resolver()
// CHECK-MTE-BTI-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817985280
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817985280
// CHECK-MTE-BTI-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624
// CHECK-MTE-BTI-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK-MTE-BTI: resolver_return:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._MsbMsve
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._Mbti
// CHECK-MTE-BTI: resolver_else:
// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 70369817985280
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 70369817985280
// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK-MTE-BTI: resolver_return1:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._Mbti
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3._MsbMsve
// CHECK-MTE-BTI: resolver_else2:
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3.default
//
Expand Down
78 changes: 39 additions & 39 deletions clang/test/CodeGen/attr-target-version.c
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Original file line number Diff line number Diff line change
Expand Up @@ -463,12 +463,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 66315
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66315
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144119586256651008
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 144119586256651008
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng
// CHECK-NEXT: ret ptr @fmv._Msme2
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 72061992218723078
Expand All @@ -495,44 +495,44 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK-NEXT: ret ptr @fmv._McrcMls64
// CHECK: resolver_else6:
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 17592186110728
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 17592186110728
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 1125899906842624
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1125899906842624
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
// CHECK: resolver_return7:
// CHECK-NEXT: ret ptr @fmv._Mfp16fmlMmemtag
// CHECK-NEXT: ret ptr @fmv._Mbti
// CHECK: resolver_else8:
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 33536
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 33536
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 17592186110728
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 17592186110728
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
// CHECK: resolver_return9:
// CHECK-NEXT: ret ptr @fmv._MaesMfp
// CHECK-NEXT: ret ptr @fmv._Mfp16fmlMmemtag
// CHECK: resolver_else10:
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 4992
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 4992
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 66315
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 66315
// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]]
// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
// CHECK: resolver_return11:
// CHECK-NEXT: ret ptr @fmv._MlseMsha2
// CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng
// CHECK: resolver_else12:
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 144119586256651008
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 144119586256651008
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 33536
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 33536
// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]]
// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
// CHECK: resolver_return13:
// CHECK-NEXT: ret ptr @fmv._Msme2
// CHECK-NEXT: ret ptr @fmv._MaesMfp
// CHECK: resolver_else14:
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 1125899906842624
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 1125899906842624
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 4992
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 4992
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
// CHECK: resolver_return15:
// CHECK-NEXT: ret ptr @fmv._Mbti
// CHECK-NEXT: ret ptr @fmv._MlseMsha2
// CHECK: resolver_else16:
// CHECK-NEXT: ret ptr @fmv.default
//
Expand Down Expand Up @@ -773,60 +773,60 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4398182892352
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4398182892352
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 864708720653762560
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 864708720653762560
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 864708720653762560
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864708720653762560
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 19861002584864
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 19861002584864
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMsve2-sm4
// CHECK: resolver_else2:
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 894427038464
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 894427038464
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4398182892352
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4398182892352
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
// CHECK: resolver_return3:
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm
// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme
// CHECK: resolver_else4:
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 35433583360
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 35433583360
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 1444182864640
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 1444182864640
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
// CHECK: resolver_return5:
// CHECK-NEXT: ret ptr @fmv_inline._MaesMf64mmMsha2
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
// CHECK: resolver_else6:
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 18320798464
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 18320798464
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 894427038464
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 894427038464
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
// CHECK: resolver_return7:
// CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm
// CHECK: resolver_else8:
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 19861002584864
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 19861002584864
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 35433583360
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 35433583360
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
// CHECK: resolver_return9:
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMsve2-sm4
// CHECK-NEXT: ret ptr @fmv_inline._MaesMf64mmMsha2
// CHECK: resolver_else10:
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 1444182864640
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 1444182864640
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 18320798464
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 18320798464
// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]]
// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
// CHECK: resolver_return11:
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
// CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3
// CHECK: resolver_else12:
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1208025856
Expand Down
57 changes: 55 additions & 2 deletions llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,13 @@
// changes in this file, first modify the primary copy and copy it over to
// compiler-rt. compiler-rt tests will fail if the two files are not synced up.
//
// Additionally this file enumerates the feature priorities in ascending order,
// as defined in the ACLE specification.
//
//===----------------------------------------------------------------------===//

#ifndef AARCH64_CPU_FEATURS_INC_H
#define AARCH64_CPU_FEATURS_INC_H
#ifndef AARCH64_CPU_FEATURES_INC_H
#define AARCH64_CPU_FEATURES_INC_H

// Function Multi Versioning CPU features.
enum CPUFeatures {
Expand Down Expand Up @@ -88,4 +91,54 @@ enum CPUFeatures {
FEAT_INIT // Used as flag of features initialization completion
};

// Function Multi Versioning feature priorities in ascending order.
enum FeatPriorities {
PRIOR_RNG,
PRIOR_FLAGM,
PRIOR_FLAGM2,
PRIOR_LSE,
PRIOR_FP,
PRIOR_SIMD,
PRIOR_DOTPROD,
PRIOR_SM4,
PRIOR_RDM,
PRIOR_CRC,
PRIOR_SHA2,
PRIOR_SHA3,
PRIOR_PMULL,
PRIOR_FP16,
PRIOR_FP16FML,
PRIOR_DIT,
PRIOR_DPB,
PRIOR_DPB2,
PRIOR_JSCVT,
PRIOR_FCMA,
PRIOR_RCPC,
PRIOR_RCPC2,
PRIOR_RCPC3,
PRIOR_FRINTTS,
PRIOR_I8MM,
PRIOR_BF16,
PRIOR_SVE,
PRIOR_SVE_F32MM,
PRIOR_SVE_F64MM,
PRIOR_SVE2,
PRIOR_SVE_PMULL128,
PRIOR_SVE_BITPERM,
PRIOR_SVE_SHA3,
PRIOR_SVE_SM4,
PRIOR_SME,
PRIOR_MEMTAG2,
PRIOR_SB,
PRIOR_PREDRES,
PRIOR_SSBS2,
PRIOR_BTI,
PRIOR_LS64_ACCDATA,
PRIOR_WFXT,
PRIOR_SME_F64,
PRIOR_SME_I64,
PRIOR_SME2,
PRIOR_MOPS
};

#endif
10 changes: 5 additions & 5 deletions llvm/include/llvm/TargetParser/AArch64TargetParser.h
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Original file line number Diff line number Diff line change
Expand Up @@ -70,12 +70,12 @@ struct ExtensionInfo {

struct FMVInfo {
StringRef Name; // The target_version/target_clones spelling.
CPUFeatures Bit; // Index of the bit in the FMV feature bitset.
CPUFeatures FeatureBit; // Index of the bit in the FMV feature bitset.
FeatPriorities PriorityBit; // Index of the bit in the FMV priority bitset.
std::optional<ArchExtKind> ID; // The architecture extension to enable.
unsigned Priority; // FMV priority.
FMVInfo(StringRef Name, CPUFeatures Bit, std::optional<ArchExtKind> ID,
unsigned Priority)
: Name(Name), Bit(Bit), ID(ID), Priority(Priority) {};
FMVInfo(StringRef Name, CPUFeatures FeatureBit, FeatPriorities PriorityBit,
std::optional<ArchExtKind> ID)
: Name(Name), FeatureBit(FeatureBit), PriorityBit(PriorityBit), ID(ID) {};
};

const std::vector<FMVInfo> &getFMVInfo();
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