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mir-gen-aarch64.c
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mir-gen-aarch64.c
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/* This file is a part of MIR project.
Copyright (C) 2020 Vladimir Makarov <[email protected]>.
*/
static void fancy_abort (int code) {
if (!code) abort ();
}
#undef gen_assert
#define gen_assert(c) fancy_abort (c)
#include <limits.h>
#define HREG_EL(h) h##_HARD_REG
#define REP_SEP ,
enum {
REP8 (HREG_EL, R0, R1, R2, R3, R4, R5, R6, R7),
REP8 (HREG_EL, R8, R9, R10, R11, R12, R13, R14, R15),
REP8 (HREG_EL, R16, R17, R18, R19, R20, R21, R22, R23),
REP8 (HREG_EL, R24, R25, R26, R27, R28, R29, R30, SP),
ZR_HARD_REG = SP_HARD_REG,
REP8 (HREG_EL, V0, V1, V2, V3, V4, V5, V6, V7),
REP8 (HREG_EL, V8, V9, V10, V11, V12, V13, V14, V15),
REP8 (HREG_EL, V16, V17, V18, V19, V20, V21, V22, V23),
REP8 (HREG_EL, V24, V25, V26, V27, V28, V29, V30, V31),
};
#undef REP_SEP
static const MIR_reg_t MAX_HARD_REG = V31_HARD_REG;
static const MIR_reg_t FP_HARD_REG = R29_HARD_REG;
static const MIR_reg_t LINK_HARD_REG = R30_HARD_REG;
static int target_locs_num (MIR_reg_t loc, MIR_type_t type) {
return loc > MAX_HARD_REG && type == MIR_T_LD ? 2 : 1;
}
/* Hard regs not used in machinized code, preferably call used ones. */
const MIR_reg_t TEMP_INT_HARD_REG1 = R9_HARD_REG, TEMP_INT_HARD_REG2 = R10_HARD_REG;
const MIR_reg_t TEMP_FLOAT_HARD_REG1 = V16_HARD_REG, TEMP_FLOAT_HARD_REG2 = V17_HARD_REG;
const MIR_reg_t TEMP_DOUBLE_HARD_REG1 = V16_HARD_REG, TEMP_DOUBLE_HARD_REG2 = V17_HARD_REG;
const MIR_reg_t TEMP_LDOUBLE_HARD_REG1 = V16_HARD_REG;
const MIR_reg_t TEMP_LDOUBLE_HARD_REG2 = V17_HARD_REG;
static inline int target_hard_reg_type_ok_p (MIR_reg_t hard_reg, MIR_type_t type) {
assert (hard_reg <= MAX_HARD_REG);
return MIR_fp_type_p (type) ? hard_reg >= V0_HARD_REG : hard_reg < V0_HARD_REG;
}
static inline int target_fixed_hard_reg_p (MIR_reg_t hard_reg) {
assert (hard_reg <= MAX_HARD_REG);
return (hard_reg == FP_HARD_REG || hard_reg == SP_HARD_REG || hard_reg == TEMP_INT_HARD_REG1
|| hard_reg == TEMP_INT_HARD_REG2 || hard_reg == TEMP_FLOAT_HARD_REG1
|| hard_reg == TEMP_FLOAT_HARD_REG2 || hard_reg == TEMP_DOUBLE_HARD_REG1
|| hard_reg == TEMP_DOUBLE_HARD_REG2 || hard_reg == TEMP_LDOUBLE_HARD_REG1
|| hard_reg == TEMP_LDOUBLE_HARD_REG2);
}
static inline int target_call_used_hard_reg_p (MIR_reg_t hard_reg) {
assert (hard_reg <= MAX_HARD_REG);
return !((hard_reg >= R19_HARD_REG && hard_reg <= R28_HARD_REG)
|| (hard_reg >= V8_HARD_REG && hard_reg <= V15_HARD_REG));
}
/* Stack layout (sp refers to the last reserved stack slot address)
from higher address to lower address memory:
| ... | prev func stack (start aligned to 16 bytes)
|---------------|
| gr save area | 64 bytes optional area for vararg func integer reg save area
|---------------|
| vr save area | 128 bytes optional area for vararg func fp reg save area
|---------------|
| saved regs | callee saved regs used in the func (known only after RA), rounded 16 bytes
|---------------|
| slots assigned| can be absent for small functions (known only after RA), rounded 16 bytes
| to pseudos |
|---------------|
| previous | 16-bytes setup in prolog, used only for varag func or args passed on stack
| stack start | to move args and to setup va_start on machinize pass
|---------------|
| LR | sp before prologue and after saving LR = start sp
|---------------|
| old FP | frame pointer for previous func stack frame; new FP refers for here
| | it has lowest address as 12-bit offsets are only positive
|---------------|
| alloca areas | optional
|---------------|
| slots for | dynamically allocated/deallocated by caller
| passing args |
size of slots and saved regs is multiple of 16 bytes
*/
static const int int_reg_save_area_size = 8 * 8;
static const int reg_save_area_size = 8 * 8 + 8 * 16;
static const MIR_insn_code_t target_io_dup_op_insn_codes[] = {MIR_INSN_BOUND};
static MIR_insn_code_t get_ext_code (MIR_type_t type) {
switch (type) {
case MIR_T_I8: return MIR_EXT8;
case MIR_T_U8: return MIR_UEXT8;
case MIR_T_I16: return MIR_EXT16;
case MIR_T_U16: return MIR_UEXT16;
case MIR_T_I32: return MIR_EXT32;
case MIR_T_U32: return MIR_UEXT32;
default: return MIR_INVALID_INSN;
}
}
static MIR_reg_t get_arg_reg (MIR_type_t arg_type, size_t *int_arg_num, size_t *fp_arg_num,
MIR_insn_code_t *mov_code) {
MIR_reg_t arg_reg;
if (arg_type == MIR_T_F || arg_type == MIR_T_D || arg_type == MIR_T_LD) {
switch (*fp_arg_num) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7: arg_reg = V0_HARD_REG + *fp_arg_num; break;
default: arg_reg = MIR_NON_HARD_REG; break;
}
(*fp_arg_num)++;
*mov_code = arg_type == MIR_T_F ? MIR_FMOV : arg_type == MIR_T_D ? MIR_DMOV : MIR_LDMOV;
} else {
switch (*int_arg_num) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7: arg_reg = R0_HARD_REG + *int_arg_num; break;
default: arg_reg = MIR_NON_HARD_REG; break;
}
(*int_arg_num)++;
*mov_code = MIR_MOV;
}
return arg_reg;
}
static void machinize_call (MIR_context_t ctx, MIR_insn_t call_insn) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_func_t func = curr_func_item->u.func;
MIR_proto_t proto = call_insn->ops[0].u.ref->u.proto;
size_t nargs, nops = MIR_insn_nops (ctx, call_insn), start = proto->nres + 2;
size_t int_arg_num = 0, fp_arg_num = 0, mem_size = 0;
MIR_type_t type, mem_type;
MIR_op_mode_t mode;
MIR_var_t *arg_vars = NULL;
MIR_reg_t arg_reg;
MIR_op_t arg_op, temp_op, arg_reg_op, ret_reg_op, mem_op;
MIR_insn_code_t new_insn_code, ext_code;
MIR_insn_t new_insn, prev_insn, next_insn, ext_insn;
MIR_insn_t prev_call_insn = DLIST_PREV (MIR_insn_t, call_insn);
uint32_t n_iregs, n_vregs;
if (call_insn->code == MIR_INLINE) call_insn->code = MIR_CALL;
if (proto->args == NULL) {
nargs = 0;
} else {
gen_assert (nops >= VARR_LENGTH (MIR_var_t, proto->args)
&& (proto->vararg_p || nops - start == VARR_LENGTH (MIR_var_t, proto->args)));
nargs = VARR_LENGTH (MIR_var_t, proto->args);
arg_vars = VARR_ADDR (MIR_var_t, proto->args);
}
if (call_insn->ops[1].mode != MIR_OP_REG && call_insn->ops[1].mode != MIR_OP_HARD_REG) {
// ??? to optimize (can be immediate operand for func call)
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, temp_op, call_insn->ops[1]);
call_insn->ops[1] = temp_op;
gen_add_insn_before (ctx, call_insn, new_insn);
}
for (size_t i = start; i < nops; i++) {
arg_op = call_insn->ops[i];
gen_assert (arg_op.mode == MIR_OP_REG || arg_op.mode == MIR_OP_HARD_REG);
if (i - start < nargs) {
type = arg_vars[i - start].type;
} else {
mode = call_insn->ops[i].value_mode; // ??? smaller ints
gen_assert (mode == MIR_OP_INT || mode == MIR_OP_UINT || mode == MIR_OP_FLOAT
|| mode == MIR_OP_DOUBLE || mode == MIR_OP_LDOUBLE);
if (mode == MIR_OP_FLOAT)
(*MIR_get_error_func (ctx)) (MIR_call_op_error,
"passing float variadic arg (should be passed as double)");
type = mode == MIR_OP_DOUBLE ? MIR_T_D : mode == MIR_OP_LDOUBLE ? MIR_T_LD : MIR_T_I64;
}
ext_insn = NULL;
if ((ext_code = get_ext_code (type)) != MIR_INVALID_INSN) { /* extend arg if necessary */
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
ext_insn = MIR_new_insn (ctx, ext_code, temp_op, arg_op);
call_insn->ops[i] = arg_op = temp_op;
}
if ((arg_reg = get_arg_reg (type, &int_arg_num, &fp_arg_num, &new_insn_code))
!= MIR_NON_HARD_REG) {
/* put arguments to argument hard regs */
if (ext_insn != NULL) gen_add_insn_before (ctx, call_insn, ext_insn);
arg_reg_op = _MIR_new_hard_reg_op (ctx, arg_reg);
new_insn = MIR_new_insn (ctx, new_insn_code, arg_reg_op, arg_op);
gen_add_insn_before (ctx, call_insn, new_insn);
call_insn->ops[i] = arg_reg_op;
} else { /* put arguments on the stack */
if (type == MIR_T_LD && mem_size % 16 != 0) mem_size = (mem_size + 15) / 16 * 16;
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
new_insn_code
= (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV : type == MIR_T_LD ? MIR_LDMOV : MIR_MOV);
mem_op = _MIR_new_hard_reg_mem_op (ctx, mem_type, mem_size, SP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, new_insn_code, mem_op, arg_op);
gen_assert (prev_call_insn != NULL); /* call_insn should not be 1st after simplification */
MIR_insert_insn_after (ctx, curr_func_item, prev_call_insn, new_insn);
prev_insn = DLIST_PREV (MIR_insn_t, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (ctx, prev_insn, next_insn, call_insn);
call_insn->ops[i] = mem_op;
mem_size += type == MIR_T_LD ? 16 : 8;
if (ext_insn != NULL) gen_add_insn_after (ctx, prev_call_insn, ext_insn);
}
}
n_iregs = n_vregs = 0;
for (size_t i = 0; i < proto->nres; i++) {
int float_p;
ret_reg_op = call_insn->ops[i + 2];
gen_assert (ret_reg_op.mode == MIR_OP_REG || ret_reg_op.mode == MIR_OP_HARD_REG);
type = proto->res_types[i];
float_p = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD;
if (float_p && n_vregs < 8) {
new_insn
= MIR_new_insn (ctx, type == MIR_T_F ? MIR_FMOV : type == MIR_T_D ? MIR_DMOV : MIR_LDMOV,
ret_reg_op, _MIR_new_hard_reg_op (ctx, V0_HARD_REG + n_vregs));
n_vregs++;
} else if (!float_p && n_iregs < 8) {
new_insn = MIR_new_insn (ctx, MIR_MOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, R0_HARD_REG + n_iregs));
n_iregs++;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"aarch64 can not handle this combination of return values");
}
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
call_insn->ops[i + 2] = new_insn->ops[1];
if ((ext_code = get_ext_code (type)) != MIR_INVALID_INSN) {
MIR_insert_insn_after (ctx, curr_func_item, new_insn,
MIR_new_insn (ctx, ext_code, ret_reg_op, ret_reg_op));
new_insn = DLIST_NEXT (MIR_insn_t, new_insn);
}
create_new_bb_insns (ctx, call_insn, DLIST_NEXT (MIR_insn_t, new_insn), call_insn);
}
if (mem_size != 0) { /* allocate/deallocate stack for args passed on stack */
mem_size = (mem_size + 15) / 16 * 16; /* make it of several 16 bytes */
new_insn
= MIR_new_insn (ctx, MIR_SUB, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
_MIR_new_hard_reg_op (ctx, SP_HARD_REG), MIR_new_int_op (ctx, mem_size));
MIR_insert_insn_after (ctx, curr_func_item, prev_call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (ctx, prev_call_insn, next_insn, call_insn);
new_insn
= MIR_new_insn (ctx, MIR_ADD, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
_MIR_new_hard_reg_op (ctx, SP_HARD_REG), MIR_new_int_op (ctx, mem_size));
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (ctx, call_insn, next_insn, call_insn);
}
}
static long double mir_i2ld (int64_t i) { return i; }
static const char *I2LD = "mir.i2ld";
static const char *I2LD_P = "mir.i2ld.p";
static long double mir_ui2ld (uint64_t i) { return i; }
static const char *UI2LD = "mir.ui2ld";
static const char *UI2LD_P = "mir.ui2ld.p";
static long double mir_f2ld (float f) { return f; }
static const char *F2LD = "mir.f2ld";
static const char *F2LD_P = "mir.f2ld.p";
static long double mir_d2ld (double d) { return d; }
static const char *D2LD = "mir.d2ld";
static const char *D2LD_P = "mir.d2ld.p";
static int64_t mir_ld2i (long double ld) { return ld; }
static const char *LD2I = "mir.ld2i";
static const char *LD2I_P = "mir.ld2i.p";
static float mir_ld2f (long double ld) { return ld; }
static const char *LD2F = "mir.ld2f";
static const char *LD2F_P = "mir.ld2f.p";
static double mir_ld2d (long double ld) { return ld; }
static const char *LD2D = "mir.ld2d";
static const char *LD2D_P = "mir.ld2d.p";
static long double mir_ldadd (long double d1, long double d2) { return d1 + d2; }
static const char *LDADD = "mir.ldadd";
static const char *LDADD_P = "mir.ldadd.p";
static long double mir_ldsub (long double d1, long double d2) { return d1 - d2; }
static const char *LDSUB = "mir.ldsub";
static const char *LDSUB_P = "mir.ldsub.p";
static long double mir_ldmul (long double d1, long double d2) { return d1 * d2; }
static const char *LDMUL = "mir.ldmul";
static const char *LDMUL_P = "mir.ldmul.p";
static long double mir_lddiv (long double d1, long double d2) { return d1 / d2; }
static const char *LDDIV = "mir.lddiv";
static const char *LDDIV_P = "mir.lddiv.p";
static long double mir_ldneg (long double d) { return -d; }
static const char *LDNEG = "mir.ldneg";
static const char *LDNEG_P = "mir.ldneg.p";
static const char *VA_ARG_P = "mir.va_arg.p";
static const char *VA_ARG = "mir.va_arg";
static int64_t mir_ldeq (long double d1, long double d2) { return d1 == d2; }
static const char *LDEQ = "mir.ldeq";
static const char *LDEQ_P = "mir.ldeq.p";
static int64_t mir_ldne (long double d1, long double d2) { return d1 != d2; }
static const char *LDNE = "mir.ldne";
static const char *LDNE_P = "mir.ldne.p";
static int64_t mir_ldlt (long double d1, long double d2) { return d1 < d2; }
static const char *LDLT = "mir.ldlt";
static const char *LDLT_P = "mir.ldlt.p";
static int64_t mir_ldge (long double d1, long double d2) { return d1 >= d2; }
static const char *LDGE = "mir.ldge";
static const char *LDGE_P = "mir.ldge.p";
static int64_t mir_ldgt (long double d1, long double d2) { return d1 > d2; }
static const char *LDGT = "mir.ldgt";
static const char *LDGT_P = "mir.ldgt.p";
static int64_t mir_ldle (long double d1, long double d2) { return d1 <= d2; }
static const char *LDLE = "mir.ldle";
static const char *LDLE_P = "mir.ldle.p";
static int get_builtin (MIR_context_t ctx, MIR_insn_code_t code, MIR_item_t *proto_item,
MIR_item_t *func_import_item) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_type_t res_type;
*func_import_item = *proto_item = NULL; /* to remove uninitialized warning */
switch (code) {
case MIR_I2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, I2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, I2LD, mir_i2ld);
return 1;
case MIR_UI2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2LD, mir_ui2ld);
return 1;
case MIR_F2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, F2LD_P, 1, &res_type, 1, MIR_T_F, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, F2LD, mir_f2ld);
return 1;
case MIR_D2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, D2LD_P, 1, &res_type, 1, MIR_T_D, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, D2LD, mir_d2ld);
return 1;
case MIR_LD2I:
res_type = MIR_T_I64;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2I_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2I, mir_ld2i);
return 1;
case MIR_LD2F:
res_type = MIR_T_F;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2F_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2F, mir_ld2f);
return 1;
case MIR_LD2D:
res_type = MIR_T_D;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2D_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2D, mir_ld2d);
return 1;
case MIR_LDADD:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDADD_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDADD, mir_ldadd);
return 2;
case MIR_LDSUB:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDSUB_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDSUB, mir_ldsub);
return 2;
case MIR_LDMUL:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDMUL_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDMUL, mir_ldmul);
return 2;
case MIR_LDDIV:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDDIV_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDDIV, mir_lddiv);
return 2;
case MIR_LDNEG:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LDNEG_P, 1, &res_type, 1, MIR_T_LD, "d");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDNEG, mir_ldneg);
return 1;
case MIR_LDEQ:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDEQ_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDEQ, mir_ldeq);
return 2;
case MIR_LDNE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDNE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDNE, mir_ldne);
return 2;
case MIR_LDLT:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDLT_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDLT, mir_ldlt);
return 2;
case MIR_LDGE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDGE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDGE, mir_ldge);
return 2;
case MIR_LDGT:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDGT_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDGT, mir_ldgt);
return 2;
case MIR_LDLE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDLE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDLE, mir_ldle);
return 2;
case MIR_VA_ARG:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, VA_ARG_P, 1, &res_type, 2,
MIR_T_I64, "va", MIR_T_I64, "type");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, VA_ARG, va_arg_builtin);
return 2;
default: return 0;
}
}
static void gen_mov (MIR_context_t ctx, MIR_insn_t anchor, MIR_insn_code_t code, MIR_op_t dst_op,
MIR_op_t src_op) {
gen_add_insn_before (ctx, anchor, MIR_new_insn (ctx, code, dst_op, src_op));
}
DEF_VARR (int);
DEF_VARR (uint8_t);
DEF_VARR (uint64_t);
struct insn_pattern_info {
int start, num;
};
typedef struct insn_pattern_info insn_pattern_info_t;
DEF_VARR (insn_pattern_info_t);
struct label_ref {
int abs_addr_p, short_p;
size_t label_val_disp;
MIR_label_t label;
};
typedef struct label_ref label_ref_t;
DEF_VARR (label_ref_t);
DEF_VARR (MIR_code_reloc_t);
struct target_ctx {
unsigned char alloca_p, stack_arg_func_p, leaf_p;
VARR (int) * pattern_indexes;
VARR (insn_pattern_info_t) * insn_pattern_info;
VARR (uint8_t) * result_code;
VARR (label_ref_t) * label_refs;
VARR (uint64_t) * abs_address_locs;
VARR (MIR_code_reloc_t) * relocs;
};
#define alloca_p gen_ctx->target_ctx->alloca_p
#define stack_arg_func_p gen_ctx->target_ctx->stack_arg_func_p
#define leaf_p gen_ctx->target_ctx->leaf_p
#define pattern_indexes gen_ctx->target_ctx->pattern_indexes
#define insn_pattern_info gen_ctx->target_ctx->insn_pattern_info
#define result_code gen_ctx->target_ctx->result_code
#define label_refs gen_ctx->target_ctx->label_refs
#define abs_address_locs gen_ctx->target_ctx->abs_address_locs
#define relocs gen_ctx->target_ctx->relocs
static MIR_disp_t target_get_stack_slot_offset (MIR_context_t ctx, MIR_type_t type,
MIR_reg_t slot) {
/* slot is 0, 1, ... */
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
size_t offset = curr_func_item->u.func->vararg_p || stack_arg_func_p ? 32 : 16;
return ((MIR_disp_t) slot * 8 + offset);
}
static void target_machinize (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_func_t func;
MIR_type_t type, mem_type, res_type;
MIR_insn_code_t code, new_insn_code;
MIR_insn_t insn, next_insn, new_insn, anchor;
MIR_reg_t ret_reg, arg_reg;
MIR_op_t ret_reg_op, arg_reg_op, mem_op, prev_sp_op, temp_op;
size_t i, int_arg_num, fp_arg_num, mem_size;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
stack_arg_func_p = FALSE;
anchor = DLIST_HEAD (MIR_insn_t, func->insns);
for (i = int_arg_num = fp_arg_num = mem_size = 0; i < func->nargs; i++) {
/* Argument extensions is already done in simplify */
/* Prologue: generate arg_var = hard_reg|stack mem ... */
type = VARR_GET (MIR_var_t, func->vars, i).type;
arg_reg = get_arg_reg (type, &int_arg_num, &fp_arg_num, &new_insn_code);
if (arg_reg != MIR_NON_HARD_REG) {
arg_reg_op = _MIR_new_hard_reg_op (ctx, arg_reg);
gen_mov (ctx, anchor, new_insn_code, MIR_new_reg_op (ctx, i + 1), arg_reg_op);
} else {
/* arg is on the stack */
if (!stack_arg_func_p) {
stack_arg_func_p = TRUE;
prev_sp_op = _MIR_new_hard_reg_op (ctx, R8_HARD_REG);
gen_mov (ctx, anchor, MIR_MOV, prev_sp_op,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 16, FP_HARD_REG, MIR_NON_HARD_REG, 1));
}
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
if (type == MIR_T_LD) mem_size = (mem_size + 15) / 16 * 16;
new_insn_code
= (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV : type == MIR_T_LD ? MIR_LDMOV : MIR_MOV);
mem_op = _MIR_new_hard_reg_mem_op (ctx, mem_type, mem_size, R8_HARD_REG, MIR_NON_HARD_REG, 1);
gen_mov (ctx, anchor, new_insn_code, MIR_new_reg_op (ctx, i + 1), mem_op);
mem_size += type == MIR_T_LD ? 16 : 8;
}
}
alloca_p = FALSE;
leaf_p = TRUE;
for (insn = DLIST_HEAD (MIR_insn_t, func->insns); insn != NULL; insn = next_insn) {
MIR_item_t proto_item, func_import_item;
int nargs;
next_insn = DLIST_NEXT (MIR_insn_t, insn);
code = insn->code;
if (code == MIR_LDBEQ || code == MIR_LDBNE || code == MIR_LDBLT || code == MIR_LDBGE
|| code == MIR_LDBGT || code == MIR_LDBLE) {
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
code = (code == MIR_LDBEQ
? MIR_LDEQ
: code == MIR_LDBNE
? MIR_LDNE
: code == MIR_LDBLT
? MIR_LDLT
: code == MIR_LDBGE ? MIR_LDGE : code == MIR_LDBGT ? MIR_LDGT : MIR_LDLE);
new_insn = MIR_new_insn (ctx, code, temp_op, insn->ops[1], insn->ops[2]);
gen_add_insn_before (ctx, insn, new_insn);
next_insn = MIR_new_insn (ctx, MIR_BT, insn->ops[0], temp_op);
gen_add_insn_after (ctx, new_insn, next_insn);
gen_delete_insn (ctx, insn);
insn = new_insn;
}
if ((nargs = get_builtin (ctx, code, &proto_item, &func_import_item)) > 0) {
if (code == MIR_VA_ARG) { /* do nothing */
/* Use a builtin func call:
mov func_reg, func ref; mov flag_reg, <type>; call proto, func_reg, res_reg, va_reg,
flag_reg */
MIR_op_t ops[5], func_reg_op, flag_reg_op;
MIR_op_t res_reg_op = insn->ops[0], va_reg_op = insn->ops[1], mem_op = insn->ops[2];
assert (res_reg_op.mode == MIR_OP_REG && va_reg_op.mode == MIR_OP_REG
&& mem_op.mode == MIR_OP_MEM);
func_reg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
flag_reg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, func_reg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (ctx, insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_MOV, flag_reg_op,
MIR_new_int_op (ctx, (int64_t) mem_op.u.mem.type));
gen_add_insn_before (ctx, insn, new_insn);
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = func_reg_op;
ops[2] = res_reg_op;
ops[3] = va_reg_op;
ops[4] = flag_reg_op;
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, 5, ops);
gen_add_insn_before (ctx, insn, new_insn);
gen_delete_insn (ctx, insn);
} else { /* Use builtin: mov freg, func ref; call proto, freg, res_reg, op_reg[, op_reg2] */
MIR_op_t freg_op, res_reg_op = insn->ops[0], op_reg_op = insn->ops[1], ops[5];
assert (res_reg_op.mode == MIR_OP_REG && op_reg_op.mode == MIR_OP_REG);
freg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, freg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (ctx, insn, new_insn);
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = freg_op;
ops[2] = res_reg_op;
ops[3] = op_reg_op;
if (nargs == 2) ops[4] = insn->ops[2];
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, nargs + 3, ops);
gen_add_insn_before (ctx, insn, new_insn);
gen_delete_insn (ctx, insn);
}
} else if (code == MIR_VA_START) {
MIR_op_t treg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
MIR_op_t prev_sp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
MIR_op_t va_op = insn->ops[0];
MIR_reg_t va_reg;
int gp_offset, fp_offset;
MIR_var_t var;
assert (func->vararg_p && va_op.mode == MIR_OP_REG);
gp_offset = (int_arg_num >= 8 ? 0 : 8 * int_arg_num - 64);
fp_offset = (fp_arg_num >= 8 ? 0 : 16 * fp_arg_num - 128);
va_reg = va_op.u.reg;
/* Insns can be not simplified as soon as they match a machine insn. */
/* mem32[va_reg].__gr_offset = gp_offset; mem32[va_reg].__vr_offset = fp_offset */
gen_mov (ctx, insn, MIR_MOV, treg_op, MIR_new_int_op (ctx, gp_offset));
gen_mov (ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_U32, 24, va_reg, 0, 1), treg_op);
gen_mov (ctx, insn, MIR_MOV, treg_op, MIR_new_int_op (ctx, fp_offset));
gen_mov (ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_U32, 28, va_reg, 0, 1), treg_op);
/* __stack: prev_sp = mem64[fp + 16]; mem64[va_reg].__stack = prev_sp + mem_size */
gen_mov (ctx, insn, MIR_MOV, prev_sp_op,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 16, FP_HARD_REG, MIR_NON_HARD_REG, 1));
new_insn = MIR_new_insn (ctx, MIR_ADD, treg_op, prev_sp_op, MIR_new_int_op (ctx, mem_size));
gen_add_insn_before (ctx, insn, new_insn);
gen_mov (ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_I64, 0, va_reg, 0, 1), treg_op);
/* __gr_top: mem64[va_reg].__gr_top = prev_sp */
gen_mov (ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_I64, 8, va_reg, 0, 1), prev_sp_op);
/* __vr_top: treg = prev_sp - int_reg_save_area; mem64[va_reg].__vr_top = treg */
new_insn = MIR_new_insn (ctx, MIR_SUB, treg_op, prev_sp_op,
MIR_new_int_op (ctx, int_reg_save_area_size));
gen_add_insn_before (ctx, insn, new_insn);
gen_mov (ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_I64, 16, va_reg, 0, 1), treg_op);
gen_delete_insn (ctx, insn);
} else if (code == MIR_VA_END) { /* do nothing */
gen_delete_insn (ctx, insn);
} else if (MIR_call_code_p (code)) {
machinize_call (ctx, insn);
leaf_p = FALSE;
} else if (code == MIR_ALLOCA) {
alloca_p = TRUE;
} else if (code == MIR_RET) {
/* In simplify we already transformed code for one return insn
and added extension insn (if any). */
uint32_t n_iregs = 0, n_vregs = 0;
assert (func->nres == MIR_insn_nops (ctx, insn));
for (size_t i = 0; i < func->nres; i++) {
assert (insn->ops[i].mode == MIR_OP_REG);
res_type = func->res_types[i];
if ((res_type == MIR_T_F || res_type == MIR_T_D || res_type == MIR_T_LD) && n_vregs < 8) {
new_insn_code
= res_type == MIR_T_F ? MIR_FMOV : res_type == MIR_T_D ? MIR_DMOV : MIR_LDMOV;
ret_reg = V0_HARD_REG + n_vregs++;
} else if (n_iregs < 8) {
new_insn_code = MIR_MOV;
ret_reg = R0_HARD_REG + n_iregs++;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"aarch64 can not handle this combination of return values");
}
ret_reg_op = _MIR_new_hard_reg_op (ctx, ret_reg);
gen_mov (ctx, insn, new_insn_code, ret_reg_op, insn->ops[i]);
insn->ops[i] = ret_reg_op;
}
}
}
}
static void isave (MIR_context_t ctx, MIR_insn_t anchor, int disp, MIR_reg_t hard_reg) {
gen_mov (ctx, anchor, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, disp, SP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, hard_reg));
}
static void fsave (MIR_context_t ctx, MIR_insn_t anchor, int disp, MIR_reg_t hard_reg) {
gen_mov (ctx, anchor, MIR_LDMOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_LD, disp, SP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, hard_reg));
}
static void target_make_prolog_epilog (MIR_context_t ctx, bitmap_t used_hard_regs,
size_t stack_slots_num) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_func_t func;
MIR_insn_t anchor, new_insn;
MIR_op_t sp_reg_op, fp_reg_op, treg_op;
int64_t start;
int save_prev_stack_p;
size_t i, offset, frame_size, frame_size_after_saved_regs, saved_iregs_num, saved_fregs_num;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
for (i = saved_iregs_num = saved_fregs_num = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i) && bitmap_bit_p (used_hard_regs, i)) {
if (i < V0_HARD_REG)
saved_iregs_num++;
else
saved_fregs_num++;
}
if (leaf_p && !alloca_p && saved_iregs_num == 0 && saved_fregs_num == 0 && !func->vararg_p
&& stack_slots_num == 0)
return;
sp_reg_op = _MIR_new_hard_reg_op (ctx, SP_HARD_REG);
fp_reg_op = _MIR_new_hard_reg_op (ctx, FP_HARD_REG);
/* Prologue: */
anchor = DLIST_HEAD (MIR_insn_t, func->insns);
frame_size = func->vararg_p ? reg_save_area_size : 0;
for (i = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i) && bitmap_bit_p (used_hard_regs, i)) {
if (i < V0_HARD_REG) {
frame_size += 8;
} else {
if (frame_size % 16 != 0) frame_size = (frame_size + 15) / 16 * 16;
frame_size += 16;
}
}
if (frame_size % 16 != 0) frame_size = (frame_size + 15) / 16 * 16;
frame_size_after_saved_regs = frame_size;
frame_size += stack_slots_num * 8;
if (frame_size % 16 != 0) frame_size = (frame_size + 15) / 16 * 16;
save_prev_stack_p = func->vararg_p || stack_arg_func_p;
if (save_prev_stack_p) { /* prev stack pointer */
treg_op = _MIR_new_hard_reg_op (ctx, R9_HARD_REG);
gen_mov (ctx, anchor, MIR_MOV, treg_op, sp_reg_op);
frame_size += 16;
}
frame_size += 16; /* lr/fp */
new_insn = MIR_new_insn (ctx, MIR_SUB, sp_reg_op, sp_reg_op, MIR_new_int_op (ctx, frame_size));
gen_add_insn_before (ctx, anchor, new_insn); /* sp = sp - frame_size */
if (save_prev_stack_p)
gen_mov (ctx, anchor, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 16, SP_HARD_REG, MIR_NON_HARD_REG, 1),
treg_op); /* mem[sp + 16] = treg */
gen_mov (ctx, anchor, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 8, SP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, LINK_HARD_REG)); /* mem[sp + 8] = lr */
gen_mov (ctx, anchor, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 0, SP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, FP_HARD_REG)); /* mem[sp] = fp */
gen_mov (ctx, anchor, MIR_MOV, fp_reg_op, sp_reg_op); /* fp = sp */
if (func->vararg_p) {
start = (int64_t) frame_size - reg_save_area_size;
fsave (ctx, anchor, start, V0_HARD_REG);
fsave (ctx, anchor, start + 16, V1_HARD_REG);
fsave (ctx, anchor, start + 32, V2_HARD_REG);
fsave (ctx, anchor, start + 48, V3_HARD_REG);
fsave (ctx, anchor, start + 64, V4_HARD_REG);
fsave (ctx, anchor, start + 80, V5_HARD_REG);
fsave (ctx, anchor, start + 96, V6_HARD_REG);
fsave (ctx, anchor, start + 112, V7_HARD_REG);
isave (ctx, anchor, start + 128, R0_HARD_REG);
isave (ctx, anchor, start + 136, R1_HARD_REG);
isave (ctx, anchor, start + 144, R2_HARD_REG);
isave (ctx, anchor, start + 152, R3_HARD_REG);
isave (ctx, anchor, start + 160, R4_HARD_REG);
isave (ctx, anchor, start + 168, R5_HARD_REG);
isave (ctx, anchor, start + 176, R6_HARD_REG);
isave (ctx, anchor, start + 184, R7_HARD_REG);
}
/* Saving callee saved hard registers: */
offset = frame_size - frame_size_after_saved_regs;
for (i = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i) && bitmap_bit_p (used_hard_regs, i)) {
if (i < V0_HARD_REG) {
gen_mov (ctx, anchor, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, offset, FP_HARD_REG, MIR_NON_HARD_REG,
1),
_MIR_new_hard_reg_op (ctx, i));
offset += 8;
} else {
if (offset % 16 != 0) offset = (offset + 15) / 16 * 16;
gen_mov (ctx, anchor, MIR_LDMOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_LD, offset, FP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, i));
offset += 16;
}
}
/* Epilogue: */
anchor = DLIST_TAIL (MIR_insn_t, func->insns);
assert (anchor->code == MIR_RET);
/* Restoring hard registers: */
offset = frame_size - frame_size_after_saved_regs;
for (i = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i) && bitmap_bit_p (used_hard_regs, i)) {
if (i < V0_HARD_REG) {
gen_mov (ctx, anchor, MIR_MOV, _MIR_new_hard_reg_op (ctx, i),
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, offset, FP_HARD_REG, MIR_NON_HARD_REG,
1));
offset += 8;
} else {
if (offset % 16 != 0) offset = (offset + 15) / 16 * 16;
gen_mov (ctx, anchor, MIR_LDMOV, _MIR_new_hard_reg_op (ctx, i),
_MIR_new_hard_reg_mem_op (ctx, MIR_T_LD, offset, FP_HARD_REG, MIR_NON_HARD_REG,
1));
offset += 16;
}
}
/* Restore lr, sp, fp */
gen_mov (ctx, anchor, MIR_MOV, _MIR_new_hard_reg_op (ctx, LINK_HARD_REG),
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 8, FP_HARD_REG, MIR_NON_HARD_REG, 1));
new_insn = MIR_new_insn (ctx, MIR_ADD, sp_reg_op, fp_reg_op, MIR_new_int_op (ctx, frame_size));
gen_add_insn_before (ctx, anchor, new_insn); /* sp = fp + frame_size */
gen_mov (ctx, anchor, MIR_MOV, fp_reg_op,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 0, FP_HARD_REG, MIR_NON_HARD_REG, 1));
}
struct pattern {
MIR_insn_code_t code;
/* Pattern elements:
blank - ignore
X - match everything
$ - finish successfully matching
r - register
h[0-63] - hard register with given number
memory with indexed reg offset:
m[0-3] - int (signed or unsigned) type memory of size 8,16,32,64-bits
ms[0-3] - signed int type memory of size 8,16,32,64-bits
mu[0-3] - unsigned int type memory of size 8,16,32,64-bits
option(field[13..15]) == 011 -- shifted reg (Rm=R31 means SP)
option == 010 (UXTW), 110 (SXTW), 111 (SXTX) -- extended reg (RM=R31 means ZR)
we use option == 111 only for non-index mem and 011 for indexed memory
memory with immediate offset:
M[0-3] - int (signed or unsigned) type memory of size 8,16,32,64-bits
Ms[0-3] - signed int type memory of size 8,16,32,64-bits
Mu[0-3] - unsigned int type memory of size 8,16,32,64-bits
zero extended scaled 12-bit offset (field[10..21])
N[0-2] - 2nd immediate (or reference) operand can be created by movn and n movk insns
Z[0-2] - 2nd immediate (or reference) operand can be created by movz and n movk insns
Z3 - any 2nd 64-bit immediate (or reference) operand
Zf - floating point 0.0
Zd - double floating point 0.0
memory with indexed reg offset:
mf - memory of float
md - memory of double
mld - memory of long double
memory with immediate offset:
Mf - memory of float
Md - memory of double
Mld - memory of long double
I -- immediate as 3th op for arithemtic insn (12-bit unsigned with possible 12-bit LSL)
Iu -- immediate for arithemtic insn roundup to 16
SR -- any immediate for right 64-bit shift (0-63)
Sr -- any immediate for right 32-bit shift (0-31)
SL -- any immediate for left 64-bit shift (0-63)
Sl -- any immediate for left 32-bit shift (0-31)
L - reference or label as the 1st or 2nd op which can be present by signed 26-bit pc offset (in
4 insn bytes) l - label as the 1st op which can be present by signed 19-bit pc offset (in 4
insn bytes)
Remember we have no float or (long) double immediate at this stage. They are represented
by a reference to data item. */
const char *pattern;
/* Replacement elements:
blank - ignore
; - insn separation
hex:hex - opcode and its mask (the mask should include opcode, the mask defines bits
which can not be changed by other fields)
rd[0-2] - put n-th operand register into rd field [0..4]
rn[0-2] - put n-th operand register into rn field [5..9]
rm[0-2] - put n-th operand register into rm field [16..20]
ra[0-2] - put n-th operand register into ra field [10..14]
h(d,n,m)<one or two hex digits> - hardware register with given number in rd,rn,rm field
m = 1st or 2nd operand is (8-,16-,32-,64-bit) mem with base, scaled index
M = 1st or 2nd operand is (8-,16-,32-,64-bit) mem with base, scaled imm12 disp [10..21]
S - immr[16..21] for right shift SR/Sr
SL, Sl - immr[16..21] and imms[10..15] for left shift SL/Sl
Z[0-3] -- n-th 16-bit immediate[5..20] from Z[0-3] and its shift [21..22]
N[0-3] -- n-th 16-bit immediate[5..20] from N[0-3] and its shift [21..22]
I -- arithmetic op 12-bit immediate [10..21] and its shift [22..23]
Iu -- arithmetic op immediate [10..21] got from roundup value to 16 and its shift [22..23]
L -- operand-label as 26-bit offset
l -- operand-label as 19-bit offset
T -- pc-relative address [5..23]
*/
const char *replacement;
};
static const struct pattern patterns[] = {
{MIR_MOV, "r h31", "91000000:fffffc00 rd0 hn1f"}, /* mov Rd,SP */
{MIR_MOV, "h31 r", "91000000:fffffc00 hd1f rn1"}, /* mov SP,Rn */
{MIR_MOV, "r r", "aa0003e0:ffe0ffe0 rd0 rm1"}, /* mov Rd,Rm */
// ??? patterns to extend 32-bit index register
{MIR_MOV, "r m3", "f8600800:ffe00c00 rd0 m"}, /* ldr Rd,[Rn,Rm{,#3}] */
{MIR_MOV, "m3 r", "f8200800:ffe00c00 rd1 m"}, /* str Rd,[Rn,Rm{,#3}] */
{MIR_MOV, "r M3", "f9400000:ffc00000 rd0 M"}, /* ldr Rd,[Rn,{,#imm12}] */
{MIR_MOV, "M3 r", "f9000000:ffc00000 rd1 M"}, /* str Rd,[Rn,Rm{,#imm12}] */
{MIR_MOV, "r mu2", "b8600800:ffe00c00 rd0 m"}, /* ldr Wd,[Rn,Rm{,#2}] */
{MIR_MOV, "m2 r", "b8200800:ffe00c00 rd1 m"}, /* str Wd,[Rn,Rm{,#2}] */
{MIR_MOV, "r Mu2", "b9400000:ffc00000 rd0 M"}, /* ldr Wd,[Rn{,#imm12}] */
{MIR_MOV, "M2 r", "b9000000:ffc00000 rd1 M"}, /* str Wd,[Rn,Rm{,#imm12}] */
{MIR_MOV, "r ms2", "b8a00800:ffe00c00 rd0 m"}, /* ldrsw Rd,[Rn,Rm{,#2}] */
{MIR_MOV, "r Ms2", "b9800000:ffc00000 rd0 M"}, /* ldrsw Rd,[Rn{,#imm12}] */
{MIR_MOV, "r mu1", "78600800:ffe00c00 rd0 m"}, /* ldrh Wd,[Rn,Rm{,#1}] */
{MIR_MOV, "m1 r", "78200800:ffe00c00 rd1 m"}, /* strh Wd,[Rn,Rm{,#1}] */
{MIR_MOV, "r Mu1", "79400000:ffc00000 rd0 M"}, /* ldrh Wd,[Rn{,#imm12}] */
{MIR_MOV, "M1 r", "79000000:ffc00000 rd1 M"}, /* strh Wd,[Rn,Rm{,#imm12}] */
{MIR_MOV, "r ms1", "78a00800:ffe00c00 rd0 m"}, /* ldrsh Wd,[Rn,Rm{,#2}] */
{MIR_MOV, "r Ms1", "79800000:ffc00000 rd0 M"}, /* ldrsh Wd,[Rn{,#imm12}] */
{MIR_MOV, "r mu0", "38600800:ffe00c00 rd0 m"}, /* ldrb Wd,[Rn,Rm{,#1}] */
{MIR_MOV, "m0 r", "38200800:ffe00c00 rd1 m"}, /* strb Wd,[Rn,Rm{,#1}] */
{MIR_MOV, "r Mu0", "39400000:ffc00000 rd0 M"}, /* ldrb Wd,[Rn{,#imm12}] */
{MIR_MOV, "M0 r", "39000000:ffc00000 rd1 M"}, /* strb Wd,[Rn,Rm{,#imm12}] */
{MIR_MOV, "r ms0", "38a00800:ffa00c00 rd0 m"}, /* ldrsb Rd,[Rn,Rm{,#1}] */
{MIR_MOV, "r Ms0", "39800000:ffc00000 rd0 M"}, /* ldrsb Rd,[Rn{,#imm12}] */
{MIR_MOV, "r Z0", "d2800000:ff800000 rd0 Z0"}, /* movz Rd, imm */
{MIR_MOV, "r N0", "92800000:ff800000 rd0 N0"}, /* movn Rd, imm */
/* movn Rd, imm0, sh0; movk Rd, imm1, sh1: */
{MIR_MOV, "r Z1", "d2800000:ff800000 rd0 Z0; f2800000:ff800000 rd0 Z1"},
/* movn imm0, sh0; movk Rd, imm1, sh1: */
{MIR_MOV, "r N1", "92800000:ff800000 rd0 N0; f2800000:ff800000 rd0 N1"},
/* movz Rd, imm0, sh0; movk Rd, imm1, sh1; movk Rd, imm3, sh3: */
{MIR_MOV, "r Z2", "d2800000:ff800000 rd0 Z0; f2800000:ff800000 rd0 Z1; f2800000:ff800000 rd0 Z2"},
/* movn Rd, imm0, sh0; movk Rd, imm1, sh1; movk Rd, imm3, sh3: */
{MIR_MOV, "r N2", "92800000:ff800000 rd0 N0; f2800000:ff800000 rd0 N1; f2800000:ff800000 rd0 N2"},
/* movz Rd, imm0, sh0; movk Rd, imm1, sh1; movk Rd, imm2, sh2; movk Rd, imm3, sh3: */
{MIR_MOV, "r Z3",
"d2800000:ff800000 rd0 Z0; f2800000:ff800000 rd0 Z1; f2800000:ff800000 rd0 Z2;"
"f2800000:ff800000 rd0 Z3"},
{MIR_FMOV, "r r", "1e204000:fffffc00 vd0 vn1"}, /* fmov Sd,Sn */
{MIR_FMOV, "r mf", "bc600800:ff600c00 vd0 m"}, /* ldr Sd,[Rn,Rm{,#2}] */
{MIR_FMOV, "mf r", "bc200800:ff600c00 vd1 m"}, /* str Sd,[Rn,Rm{,#2}] */
{MIR_FMOV, "r Mf", "bd400000:ffc00000 vd0 M"}, /* ldr Sd,[Rn,{,#imm12}] */
{MIR_FMOV, "Mf r", "bd000000:ffc00000 vd1 M"}, /* str Sd,[Rn,Rm{,#imm12}] */
{MIR_DMOV, "r r", "1e604000:fffffc00 vd0 vn1"}, /* fmov Dd,Dn */
{MIR_DMOV, "r md", "fc600800:ff600c00 vd0 m"}, /* ldr Dd,[Rn,Rm{,#3}] */
{MIR_DMOV, "md r", "fc200800:ff600c00 vd1 m"}, /* str Dd,[Rn,Rm{,#3}] */
{MIR_DMOV, "r Md", "fd400000:ffc00000 vd0 M"}, /* ldr Dd,[Rn,{,#imm12}] */
{MIR_DMOV, "Md r", "fd000000:ffc00000 vd1 M"}, /* str Dd,[Rn,Rm{,#imm12}] */
{MIR_LDMOV, "r r", "4ea01c00:ffe0fc00 vd0 vm1 vn1"}, /* orr Qd.16b,Qm.16b,Qn.16b */
{MIR_LDMOV, "r mld", "3ce00800:ffe00c00 vd0 m"}, /* ldr Qd,[Rn,Rm{,#4}] */
{MIR_LDMOV, "mld r", "3ca00800:ffe00c00 vd1 m"}, /* str Qd,[Rn,Rm{,#4}] */
{MIR_LDMOV, "r Mld", "3dc00000:ffc00000 vd0 M"}, /* ldr Qd,[Rn,{,#imm12}] */
{MIR_LDMOV, "Mld r", "3d800000:ffc00000 vd1 M"}, /* str Qd,[Rn,Rm{,#imm12}] */
{MIR_EXT8, "r r", "93401c00:fffffc00 rd0 rn1"}, /* sxtb rd, wn */
{MIR_EXT16, "r r", "93403c00:fffffc00 rd0 rn1"}, /* sxth rd, wn */
{MIR_EXT32, "r r", "93407c00:fffffc00 rd0 rn1"}, /* sxtw rd, wn */
{MIR_UEXT8, "r r", "53001c00:fffffc00 rd0 rn1"}, /* uxtb wd, wn */
{MIR_UEXT16, "r r", "53003c00:fffffc00 rd0 rn1"}, /* uxth wd, wn */
{MIR_UEXT32, "r r", "2a0003e0:7fe0ffe0 rd0 rm1"}, /* mov wd, wm */
// ??? add extended reg insns:
{MIR_ADD, "r r r", "8b000000:ff200000 rd0 rn1 rm2"}, /* add Rd,Rn,Rm*/
{MIR_ADD, "r r I", "91000000:ff000000 rd0 rn1 I"}, /* add Rd,Rn,I,shift */
{MIR_ADDS, "r r r", "0b000000:ff200000 rd0 rn1 rm2"}, /* add Wd,Wn,Wm*/
{MIR_ADDS, "r r I", "11000000:ff000000 rd0 rn1 I"}, /* add Wd,Wn,I,shift */