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circuits_main.js
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circuits_main.js
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/*
LogicEmu
Copyright (c) 2018-2023 Lode Vandevenne
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
This JS file contains various demo circuits and single devices,
and injects them into a dropdown from logicemu.js
*/
registerCircuitGroup('circuits');
registerTitle('Binary Logic');
registerCircuit('16 gates', `
0"Because a 2-input gate has 4 combinations of inputs, and for each input"
0"combination has some output, there are in total 2^4 = 16 different possible"
0"behaviours of 16-input gate. Here, all 16 are implemented and their"
0"properties and names from logic shown"
"gate name value properties logic name"
. .
. ... ..>l "ZERO" "0" 0"nullary, symmetric" 0"contradiction"
. .
..+..
. .
. ...>a..>l "AND" "a.b" 0"binary, symmetric" 0"conjunction"
. . ^
..+....
. .
. ...>a..>l "a NIMPLY b""a>b" 0"universal, asymmetric" 0"nonimplication, abjunction"
. . m
..+....
. .
. .......>l "A" "a" 0"unary, asymmetric" 0"statement"
. .
..+..
. .
. ...]a..>l "b NIMPLY a" "a<b" 0"universal, asymmetric" 0"converse nonimplication"
. . ^
..+....
. .
. ... ...>l "B" "b" 0"unary, asymmetric" 0"statement"
. . .
..+....
. .
. ...>e..>l "XOR" "a!=b" 0"binary, symmetric" 0"exclusive disjunction"
. . ^ "a+b mod 2"
..+....
. .
. ...>o..>l "OR" "a+b" 0"binary, symmetric" 0"(inclusive) disjunction"
. . ^
..+....
. .
. ...>O..>l "NOR" 0"universal, symmetric" 0"joint denial"
. . ^
..+....
. .
. ...>E..>l "XNOR, EQV" "a==b" 0"binary, symmetric" 0"biconditional"
. . ^
..+....
. .
. ... O..>l "NOT B" 0"unary, asymmetric" 0"negation"
. . ^
..+....
. .
. ...>o..>l "b IMPLY a" "a>=b" 0"universal, asymmetric" 0"converse implication"
. . m
..+....
. .
. ...>O..>l "NOT A" 0"unary, asymmetric" 0"negation"
. .
..+..
. .
. ...]o..>l "a IMPLY b" "a<=b" 0"universal, asymmetric" 0"implication"
. . ^
..+....
. .
. ...>A..>l "NAND" 0"universal, symmetric" 0"alternative denial"
. . ^
..+....
. .
. ... O..>l "ONE" "1" 0"nullary, symmetric" 0"tautology"
. .
..+..
. .
. .
. .
s s
"b a"
0"Configurable gate"
0"You can set this to any of the 16 logic gates with the 4 control switches."
0"Enable a switch to make that input combination true, otherwise it is false."
0"E.g. enable switch '10' and '01' to make it behave like a XOR gate."
0"NOTE: in reality, the final 4 ands might be replaced by tristate buffers,"
0"and the large or would then not be needed, just combine the wires together."
l
^
.
.
o############
^ ^ ^ ^
. . . .
a<--+---+---+------------s "11"
^ a<--+---+------------s "10"
. ^ a<--+------------s "01"
. . ^ a<-----------s "00"
. . . ^
a<. a<. a[. a[.
^ . m . ^ . m .
..+...+...+.. .
. . . . .
. .............
. .
. .
s s
`, 'gates16');
registerCircuit('mux & demux', `
0"The multiplexer (mux) brings one of two signals to the output"
0"The demultiplexer (demux) brings one input to one of the two outputs"
"mux" "demux"
. .
. .
s...+>a>o..>l s...+>a..>l
. m ^ . . m
... . . ...
. v . . . v
s...+>a.. ..+>a..>l
. .
. .
s s
"select" "select"
0"8-bit mux"
l l l l l l l l
^ ^ ^ ^ ^ ^ ^ ^
. . . . . . . .
.>o<. .>o<. .>o<. .>o<. .>o<. .>o<. .>o<. .>o<.
. . . . . . . . . . . . . . . .
a[.>a a[.>a a[.>a a[.>a a[.>a a[.>a a[.>a a[.>a
^ . ^ ^ . ^ ^ . ^ ^ . ^ ^ . ^ ^ . ^ ^ . ^ ^ . ^
. . . . . . . . . . . . . . . . . . . . . . . .
...+...+.+...+.+...+.+...+.+...+.+...+.+...+.+...+....s"select"
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
. s . s . s . s . s . s . s . s
. . . . . . . .
s s s s s s s s
`, 'mux');
registerTitle('Arithmetic');
registerCircuit('half adder', `
0"The half adder adds two 1-bit values. The output can represent 0, 1 or 2. The"
0"bit output by the XOR gate has value 1, the bit output by the AND gate has"
0"value 2."
l l
^ ^
. .
a e
^^^
. .
s s
0"Chained as increment operation: this can add 1 to the 4-bit input number"
l l l l
^ ^ ^ ^
l<..a e a e a e a e ..S
^^^/^^^/^^^/^^^/
s . s . s . s .
`, 'half_adder');
registerCircuit('full adder', `
0"The full adder is made from two half adders (each pair of a+e gate is a half"
0"adder). It sums 3 1-bit numbers (or 2 bits of a 1-bit number, and the third"
0"bit being the carry, see the ripple carry circuit for that), and outputs a"
0"2-bit number"
"c s" "s"
l l l
^ ^ ^
. . .
o<a e "c"l<....o<a e .....s"c"
^ ^^^ ^ ^^^/
a e . a e .
^^^ . ^^^
. . . . .
. . . . .
s s s s s
"a b c" "a b"
0"Placing multiple in a row (ripple carry adder, more info in next circuit):"
"128" "64" "32" "16" "8" "4" "2" "1"
l l l l l l l l
^ ^ ^ ^ ^ ^ ^ ^
l<o<a e o<a e o<a e o<a e o<a e o<a e o<a e o<a e s
^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/
a e . a e . a e . a e . a e . a e . a e . a e .
^^^ ^^^ ^^^ ^^^ ^^^ ^^^ ^^^ ^^^
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
s . s . s . s . s . s . s . s .
. . . . . . . .
s s s s s s s s
`, 'full_adder');
registerCircuit('8-bit ripple carry adder', `
0"The 8-bit ripple carry has 8 full adders, configured to pass on the carry. If"
0"you add 1 to 255, you get the slowest possible ripple. The longest path is as"
0"long as the amount of bits, so this type of adder is slow and not used in"
0"practice (see carry lookahead adder next)"
"128" "64" "32" "16" "8" "4" "2" "1"
l l l l l l l l
^ ^ ^ ^ ^ ^ ^ ^
"carry"l<o<a e o<a e o<a e o<a e o<a e o<a e o<a e o<a e s"carry"
^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/
a e . a e . a e . a e . a e . a e . a e . a e .
^^^ ^^^ ^^^ ^^^ ^^^ ^^^ ^^^ ^^^
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
. ,---+-+---+-+---+-+---+-+---+-+---+-+---+-+-.
. ,---. .---+-+---+-+---+-+---+-+---+-+---+-+-+-.
. . .-------. .---+-+---+-+---+-+---+-+---+-+-+-+-.
. . . .-----------. .---+-+---+-+---+-+---+-+-+-+-+-.
. . . . .---------------. .---+-+---+-+---+-+-+-+-+-+-.
. . . . . .-------------------. .---+-+---+-+-+-+-+-+-+-.
. . . . . . .-----------------------. .---+-+-+-+-+-+-+-+-.
. . . . . . . .---------------------------. .-+-+-+-+-+-+-+-.
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
s s s s s s s s s s s s s s s s
"a" "1 6 3 1 8 4 2 1" "b" "1 6 3 1 8 4 2 1"
"2 4 2 6 " "2 4 2 6 "
"8 " "8 "
0"Note: The adder logic is in the gates at the top. The omnious looking wires"
0"at the bottom have no logic and are there only to separate the A and B inputs."
`, 'ripple_carry_adder');
registerCircuit('4-bit carry lookahead adder', `
0"The carry lookahead adder is faster than the ripple carry adder. A ripple"
0"carry adder is slow because the longest path goes through all the full"
0"adders."
0"Lookahead of the expected carry rather than letting it ripple through makes"
0"the adder faster, at the cost of more logic (especially many multi-input"
0"AND/OR gates)"
0"At the bottom are the standard full adders, except they are missing an AND"
0"and an OR (the lookahead unit has many big ones of those instead), and the"
0"outputs of their first half adder is given to the lookahead unit."
0"The left part computes things that are not needed for this 4-bit adder but"
0"can be used to chain multiple CLA's together. pg,gg to make a recursively"
0"bigger CLA, or c4 to ripple CLA's instead. Note that there is some serious"
0"redundancy in the left part, since c4 can be computed as (pg AND c0) OR gg,"
0"but that would add one more gate delay and this circuit is demonstrating the"
0"absolute max speed"
0"The one-input AND and OR gates represent buffers. Without them, some signals"
0"have different lengths of gate delay and cause some garbage flickering. They"
0"cause no slowdown since only the longest path matters."
0"CLA = carry lookahead adder: this whole circuit"
0"LCU = lookahead carry unit: the logic excluding the full adders"
0"c = carry, g = carry generator (from AND), p = carry propagator (from XOR),"
0"pg = group prop., gg = group gen."
0"carry propagate will go on if adding 1 more bit to the input would cause a"
0"carry out."
0"carry generate will go on if a carry got generated in this 4-bit sum itself,"
0"but not due to the external input carry"
2"c0"-------------------------------------------.------------------.------------.--------.-----.---s"c0"
2"p0"-------.----------------------------------.+-----------------.+-----------.+-------.+---. .
2"g0"-------+-------------.---------------.----++-------------.---++--------.--++-----.-++-. . .
2"p1"------.+------------.+--------------.+---.++------------.+--.++-------.+-.++---. . || . . .
2"g1"------++--------.---++----------.---++---+++---------.--++--+++-----.-++-+++-. . . || . . .
2"p2"-----.++-------.+--.++---------.+--.++--.+++--------.+-.++-.+++---. . || ||| . . . || . . .
2"g2"-----+++----.--++--+++------.--++--+++--++++------.-++-+++-++++-. . . || ||| . . . || . . .
2"p3"----.+++---.+-.++-.+++-----.+-.++-.+++-.++++----. . || ||| |||| . . . || ||| . . . || . . .
2"g3"----++++-.-++-+++-++++---.-++-+++-++++-+++++--. . . || ||| |||| . . . || ||| . . . || . . .
vvvv v vv vvv vvvv v vv vvv vvvv vvvvv . . v vv vvv vvvv . . v vv vvv . . v vv . . v
a### a a# a## a### a a# a## a### a#### . . a a# a## a### . . a a# a## . . a a# . . a
v v v v v v v v v v . . v v v v . . v v v . . v v . . v
o o######### o############## . . o######### . . o##### . . o## . . o
2"pg"l<--. . | . . ."c3" . . ."c2" . . ."c1". . .
2"gg"l<-------. | . . . . . . . . . . . .
2"c4"l<-----------------------. . . . . . . . . . . . .
. . ."r8" . . ."r4" . . ."r2". . ."r1"
. . . l . . . l . . . l . . . l
. . v ^ . . v ^ . . v ^ . . v ^
. .>e.. . .>e.. . .>e.. . .>e..
. . . . . . . .
a e a e a e a e
^^^ ^^^ ^^^ ^^^
. . . . . . . .
. . . . . . . .
s s s s s s s s
"a8 b8 a4 b4 a2 b2 a1 b1"
0"There are many ways to extend this adder to more than 4 bits: Keep doing the"
0"same as above with more and more and bigger and bigger AND and OR gates for"
0"every next bit. This is the fastest but most expensive. Recursively create a"
0"16-bit adder from 4 of the above CLA, and so on. This is the middle ground in"
0"cost/speed. Ripple multiple of the above CLA's. This is slower but cheaper,"
0"and still faster than rippling every single bit (which would be an even"
0"slower but even cheaper option). And then, even more tradeoffs can be made by"
0"doing any of the above with other sizes than 4-bit CLA's."
0"MODE:electron (set to electron by default to show the gate delays)"
`, 'cla_adder');
registerCircuit('half subtractor', `
3"+-----+-----+ l=loan (borrow)"
3"| a b | d l | d=difference "
3"+-----+-----+ "
3"| 0 0 | 0 0 | "
3"| 0 1 | 1 1 | "
3"| 1 0 | 1 0 | "
3"| 1 1 | 0 0 | "
3"+-----+-----+ "
"l d"
l l
^ ^
. .
a e
m^^
. .
. .
s s
"a b"
`, 'half_sub');
registerCircuit('full subtractor', `
0"Note: The full subtractor is similar to the adder, and in practice you don't"
0"need a separate circuit like this to subtract, you can also use a full adder,"
0"invert the bits of B and add 1 to B"
3"+-------+-----+ l=loan (borrow)"
3"| a b l | d l | d=difference "
3"+-------+-----+ "
3"| 0 0 0 | 0 0 | "
3"| 0 0 1 | 1 1 | "
3"| 0 1 0 | 1 1 | "
3"| 0 1 1 | 0 1 | "
3"| 1 0 0 | 1 0 | "
3"| 1 0 1 | 0 0 | "
3"| 1 1 0 | 0 0 | "
3"| 1 1 1 | 1 1 | "
3"+-------+-----+ "
"d" "d"
l l
^ ^
"l"l<--o<a e ..s"l" "l"l<--o<a e ..s"l"
^ m^^/ ^ m^^/
a e . a e .
m^^ ^mm
. . . .
| | | |
s s s s
"a b" "b a"
0"Placing multiple in a row (ripple carry subtractor, more info in next circuit):"
"128" "64" "32" "16" "8" "4" "2" "1"
l l l l l l l l
^ ^ ^ ^ ^ ^ ^ ^
l<o<a e o<a e o<a e o<a e o<a e o<a e o<a e o<a e s
^ m^^/^ m^^/^ m^^/^ m^^/^ m^^/^ m^^/^ m^^/^ m^^/
a e . a e . a e . a e . a e . a e . a e . a e .
m^^ m^^ m^^ m^^ m^^ m^^ m^^ m^^
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
s . s . s . s . s . s . s . s .
. . . . . . . .
s s s s s s s s
`, 'full_sub');
registerCircuit('8-bit comparator', `
0"Note: in practice you don't need a separate circuit like this, you can use"
0"the full adder, to subtract, and look at the carry bit of the result, see the"
0"ALU circuit for more on that."
"a < = > b" "a < = b"
l l l l l
^ ^ ^ ^ ^
. . . . .
a E a a E
m^ ^m m^^
. x . . .
.. .. . .
. . s s
s s "a b"
"a b"
0"for chaining"
"<"s....>o....>o....>o....>o....>o....>o....>o....>o.........>l "a < b"
w ^ ^ ^ ^ ^ ^ ^ ^ .
"="S.....+>a...+>a...+>a...+>a...+>a...+>a...+>a...+>a......+>l "a = b"
. . ^ . . ^ . . ^ . . ^ . . ^ . . ^ . . ^ . . ^ . w
. . . . . . . . . . . . . . . . . . . . . . . . ..]a>l "a > b"
.>a E .>a E .>a E .>a E .>a E .>a E .>a E .>a E
m^^ m^^ m^^ m^^ m^^ m^^ m^^ m^^
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
s . s . s . s . s . s . s . s .
"a128"."a64"."a32"."a16"." a8"." a4"." a2"." a1".
s s s s s s s s
"b128 b64 b32 b16 b8 b4 b2 b1"
`, 'comparator');
registerCircuit('8-bit ALU from adder', `
0"Earlier circuits demonstrated the adder, subtractor and comparator. You don't"
0"need all those three separate circuits to compute any of those however, with"
0"just an adder you can do all those operations. An ALU in a CPU, at a very"
0"basic level, does exactly that: It usually includes an adder to do various"
0"different computations."
0"In twos complement binary notation, subtracting a-b can be done by inverting"
0"the bits of b and adding 1. So before the adder inputs, put a circuit that"
0"can optionally negate b's bits (with xor gates), and adding 1 can be done"
0"with the carry input."
0"Comparing can be done by subtracting and then looking at the carry out: when"
0"subtracting a-b, it will be high when a >= b, low when a < b. To test for"
0"equality, use a many-input NOR gate to check if all out bits are zero."
0"The build below does this, and is operated as follows:"
0"The operation depends on the 3 input flags of the right side:"
0"none: ADD"
0"zb,c: INCREMENT"
0"nb,c: SUBTRACT, COMPARE: z: 'a == b', c': 'a >= b'"
0"nb,zb: DECREMENT"
"128" "64" "32" "16" "8" "4" "2" "1"
l l l l l l l l
^ ^ ^ ^ ^ ^ ^ ^
. . . . . . . .
2"z: zero"l<....O<+...o<+...o<+...o<+...o<+...o<+...o<+...o<+
^ . ^ . ^ . ^ . ^ . ^ . ^ . ^ .
... ... ... ... ... ... ... ...
. . . . . . . .
2"c: carry"l<..o<a e o<a e o<a e o<a e o<a e o<a e o<a e o<a e .............s 0"c: carry in: add 1"
2"out" ^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/^ ^^^/
a e . a e . a e . a e . a e . a e . a e . a e .
^^^ ^^^ ^^^ ^^^ ^^^ ^^^ ^^^ ^^^
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
. ,---+-+---+-+---+-+---+-+---+-+---+-+---+-+-.
. ,---. .---+-+---+-+---+-+---+-+---+-+---+-+-+---.
. . .-------. .---+-+---+-+---+-+---+-+---+-+-+---+---.
. . . .-----------. .---+-+---+-+---+-+---+-+-+---+---+---.
. . . . .---------------. .---+-+---+-+---+-+-+---+---+---+---.
. . . . . .-------------------. .---+-+---+-+-+---+---+---+---+---.
. . . . . . .-----------------------. .---+-+-+---+---+---+---+---+---.
. . . . . . . .---------------------------. .-+---+---+---+---+---+---+---.
. . . . . . . . . . . . . . . .
. . . . . . . . . ..+...+...+...+...+...+...+....s 0"nb: negate b"
. . . . . . . . . . . . . . . . . . . . . . . . 0"(bitwise not)"
. . . . . . . . e<. e<. e<. e<. e<. e<. e<. e<.
. . . . . . . . ^ ^ ^ ^ ^ ^ ^ ^
. . . . . . . . . . . . . . . .
. . . . . . . . . ..+...+...+...+...+...+...+....s 0"zb: zero b"
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . a[. a[. a[. a[. a[. a[. a[. a[.
. . . . . . . . ^ ^ ^ ^ ^ ^ ^ ^
. . . . . . . . . . . . . . . .
s s s s s s s s s s s s s s s s
"a" "1 6 3 1 8 4 2 1" "b" "1 6 3 1 8 4 2 1"
"2 4 2 6 " "2 4 2 6 "
"8 " "8 "
`, 'alu');
registerCircuit('2-bit multiplier', `
0"This circuit multiplies two 2-bit numbers"
"a1"s......>a..........>l"r1"
. ^
. ...
. .
"a2"s.. ..+>a..>e......>l"r2"
. . ^ . ^
. ..+.. . .
. . . . .
"b1"s.+.+..>a.+.. .>e..>l"r4"
. . ^ . v . ^
..+.... .>a.+..
. v . v
"b2"s......>a......>a..>l"r8"
`, 'mul2');
registerCircuit('4-bit multiplier', `
0"Multiplication can be done with the shift-and-add algorithm: To multiply"
0"number A with n-bit number B: Initialize a result value at 0. Then n times,"
0"if the n-th bit of B is 1, add A to the result, and always shift A left by 1."
0"This can be done sequentially with an algorithm, but here it is done as one"
0"entire combinational circuit in hardware, so with n layers of adders. To"
0"multiply two 4-bit numbers, that gives 4 4-bit adders, for a total of 16 full"
0"adders."
0"The main unit is the following 1-bit full adder with a few extra's. The carry"
0"c works as usual within a 4-bit adder. The bit 'b' is the bit matching the"
0"current stage from the second number we are multiplying. It ANDs the 'a'"
0"input of the adder to disable it if 0. We also output 'a' again at the top to"
0"apply the left-shift for the next stage, and pass 'b' through to the left"
0"because it must be applied to all adders of this stage. 'r' will eventually"
0"become a final result bit after it went through all stages."
"a r"
l l
^ ^
. .
"c"l<..+.o<a e%.....s"c"
. ^ ^^^|
. a e .%
. ^^^
. . .
"b"l<..+.+.+.........s"b"
. . . .
......+.. a<.
. . ^
. .....
. .
s s
"r a"
0"Note how the shifting is done: rather than physically shifting a left,"
0"instead in this implementation 'a' goes up vertically and instead r shifts to"
0"the right. That boils down to the exact same thing, but it allows the circuit"
0"to be square shaped rather than a parallellogram."
0"To operate the circuit, enter a binary a at the bottom row, and a binary b at"
0"the right column. Then read the output in the 8 output LEDs, the ones in the"
0"right column are the 4 LSBs of the output, the top ones the 4 MSBs."
0"Multiplying two 4-bit numbers can give an 8-bit result."
"r128 r64 r32 r16"
l l l l .>l"r8"
^ ^ ^ ^ /
. . . . . . . . /
. . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b8"
. . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r4"
/ . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... /
. . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b4"
. . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r2"
/ . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... /
. . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b2"
. . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r1"
/ . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... /
. . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b1"
. . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<.
/ . ^ / . ^ / . ^ / . ^
/ ..... / ..... / ..... / .....
. . . . . . . .
. . . . . . . .
s s s s
"a8 a4 a2 a1"
`, 'multiply');
registerCircuit('8-bit multiplier', `
0"8-bit multiplier: made from 8 8-bit adders"
0"See the 4-bit multiplier for the explanation. This one is simply bigger"
"r32768 r16384 r8192 r4096 r2048 r1024 r512 r256"
l l l l l l l l .>l"r128"
^ ^ ^ ^ ^ ^ ^ ^ /
. . . . . . . . . . . . . . . . /
. . . . . . . . . . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . . . . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b128"
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r64"
/ . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... / ..... / ..... / ..... / ..... /
. . . . . . . . . . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . . . . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b64"
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r32"
/ . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... / ..... / ..... / ..... / ..... /
. . . . . . . . . . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . . . . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b32"
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r16"
/ . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... / ..... / ..... / ..... / ..... /
. . . . . . . . . . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . . . . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b16"
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r8"
/ . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... / ..... / ..... / ..... / ..... /
. . . . . . . . . . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . . . . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b8"
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r4"
/ . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... / ..... / ..... / ..... / ..... /
. . . . . . . . . . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . . . . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b4"
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r2"
/ . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... / ..... / ..... / ..... / ..... /
. . . . . . . . . . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . . . . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b2"
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .>l"r1"
/ . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ /
/ ..... / ..... / ..... / ..... / ..... / ..... / ..... / ..... /
. . . . . . . . . . . . . . . . .
....+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%..+.o<a e%.
. ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^| . ^ ^^^|
. a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .% . a e .%
. ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^ . ^^^
. . . . . . . . . . . . . . . . . . . . . . . .
.+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+.....+.+.+....s"b1"
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<. .+.. a<.
/ . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^ / . ^
/ ..... / ..... / ..... / ..... / ..... / ..... / ..... / .....
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
s s s s s s s s
"a128 a64 a32 a16 a8 a4 a2 a1"
`, 'mul8');
registerCircuit('4-bit divider', `
0"Division of two binary n-bit numbers A/B to get quotient Q and remainder R"
0"can be done with the following algorithm (long division): Initialize Q and R"
0"at 0. Do n times (i=0..n-1): Left shift R by 1 bit. Set R's least significant"
0"bit to bit #i of A. If R >= B, then subtract B from R and set bit #i of Q to"
0"1."
0"This can be computed sequentially as an algorithm, but here we build a full"
0"combinational implementation with gates. Since there are n subtractions (and"
0"n is 4 for 4-bit dividers) that means there will be 4 4-bit subtractors."
0"The base unit is a subtractor with a few extras:"
"b" "r-b, r"
l l
^ ^
. o<.
. ^ .
. .]a a<.
. . ^ ^ .
"q"s.+.....+.+....>l"q"
. . .
"l"l<+.o<a e . ....s"l"
. ^ m^^ . .
. a e ..+..
. ^mm .
... .....
. .
s s
"b r"
0"This implements the algorithm as follows: the subtractor inputs are the"
0"corresponding r and b bits of the R and B inputs. The l is the loan and works"
0"as usual in the full 4-bit subtractor unit this is part of. On top, a"
0"multiplexer is added, which can choose between the subtractor output r-b, or"
0"between copying the input r. The choice is made by the q bit output by this"
0"4-bit layer, and that q bit is the loan of the leftmost (MSB) full adder of"
0"this 4-bit layer (the inverse of it will be output). This matches the"
0"algorithm as follows: this leftmost load bit is true if r < b, and by"
0"controlling the mux this implements the 'if R >= B' and outputs R itself, or"
0"R with B subtracted, as seen in the algo, as the next R. The rightmost R bit"
0"will be set to the corresponding bit of A (adding 1 to R where needed), and R"
0"is left shifted implicitely through the wiring between each layer."
0"Here is one of the 4 layers. Note how a single bit of A is input from the"
0"right as rightmost R bit, and all bits from B are used. Also note how the"
0"MUXes of all subtractors are controlled by the result of the leftmost"
0"subtractor, making this algorithm slow since this happens at every layer, so"
0"the computation has to cross every single subtractor all the time (the"
0"multiplier did not suffer from such slowness). Also note how the B inputs are"
0"passed through to the top, ready to go to the next layer. The output"
0"remainder bits will be left shifted (and r8 discarded) for the next layer."
"r8 r4 r2 r1"
l l l l
^ ^ ^ ^
. . . .
o<. o<. o<. o<.
^ . ^ . ^ . ^ .
. .]a a<. . .]a a<. . .]a a<. . .]a a<.
. . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ .
...+.....+.+....+.....+.+....+.....+.+....+.....+.+.....
. . . . . . . . . . . . .
"q"l[...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...s"l"
. ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . .
. a e ..+.. . a e ..+.. . a e ..+.. . a e ..+..
. ^mm . . ^mm . . ^mm . . ^mm .
... ..... ... ..... ... ..... ... .....
. . . . . . . .
s s s s s s s ..........s"a"
"b8 r8 b4 r4 b2 r2 b1"
0"Finally, combining all stages together, to get the full 4-bit divider. It"
0"computes a / b, and outputs the quotient on the left, and the remainder at"
0"the top, all 4-bit numbers. Look carefully which of the bits are the LSB"
0"(marked with 1) and MSB (marked with 8) of each of those 4 numbers..."
l l l l
^ ^ ^ ^
. . . .
o<. o<. o<. o<.
^ . ^ . ^ . ^ .
. .]a a<. . .]a a<. . .]a a<. . .]a a<.
. . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ .
...+.....+.+....+.....+.+....+.....+.+....+.....+.+...
. . . . . . . . . . . . .
"q1"l[...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...
. ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . .
. a e ..+.. . a e ..+.. . a e ..+.. . a e ..+..
. ^mm . . ^mm . . ^mm . . ^mm .
... ....... ... ....... ... ....... ... .........s"a1"
. . . . . . .
...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<.
. ^ . . ^ . . ^ . . ^ .
. .]a a<. . .]a a<. . .]a a<. . .]a a<.
. . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ .
...+.....+.+....+.....+.+....+.....+.+....+.....+.+...
. . . . . . . . . . . . .
"q2"l[...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...
. ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . .
. a e ..+.. . a e ..+.. . a e ..+.. . a e ..+..
. ^mm . . ^mm . . ^mm . . ^mm .
... ....... ... ....... ... ....... ... .........s"a2"
. . . . . . .
...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<.
. ^ . . ^ . . ^ . . ^ .
. .]a a<. . .]a a<. . .]a a<. . .]a a<.
. . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ .
...+.....+.+....+.....+.+....+.....+.+....+.....+.+...
. . . . . . . . . . . . .
"q4"l[...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...
. ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . .
. a e ..+.. . a e ..+.. . a e ..+.. . a e ..+..
. ^mm . . ^mm . . ^mm . . ^mm .
... ....... ... ....... ... ....... ... .........s"a4"
. . . . . . .
...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<.
. ^ . . ^ . . ^ . . ^ .
. .]a a<. . .]a a<. . .]a a<. . .]a a<.
. . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ .
...+.....+.+....+.....+.+....+.....+.+....+.....+.+...
. . . . . . . . . . . . .
"q8"l[...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...
. ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . .
. a e ..+.. . a e ..+.. . a e ..+.. . a e ..+..
. ^mm . . ^mm . . ^mm . . ^mm .
... ..... ... ..... ... ..... ... .........s"a8"
. . . .
s s s s
"b8 b4 b2 b1"
`, 'divide');
registerCircuit('8-bit divider', `
0"8-bit divider. See the 4-bit divider circuit for the explanation. This one is"
0"simply bigger."
0"Enable electron mode to see how slow it operates!"
"r128 r64 r32 r16 r8 r4 r2 r1"
l l l l l l l l
^ ^ ^ ^ ^ ^ ^ ^
. . . . . . . .
o<. o<. o<. o<. o<. o<. o<. o<.
^ . ^ . ^ . ^ . ^ . ^ . ^ . ^ .
. .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<.
. . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ .
...+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+...
. . . . . . . . . . . . . . . . . . . . . . . . .
"q1"l[...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...
. ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . .
. a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+..
. ^mm . . ^mm . . ^mm . . ^mm . . ^mm . . ^mm . . ^mm . . ^mm .
... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... .........s"a1"
. . . . . . . . . . . . . . .
...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<.
. ^ . . ^ . . ^ . . ^ . . ^ . . ^ . . ^ . . ^ .
. .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<.
. . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ .
...+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+...
. . . . . . . . . . . . . . . . . . . . . . . . .
"q2"l[...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...
. ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . .
. a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+..
. ^mm . . ^mm . . ^mm . . ^mm . . ^mm . . ^mm . . ^mm . . ^mm .
... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... .........s"a2"
. . . . . . . . . . . . . . .
...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<.
. ^ . . ^ . . ^ . . ^ . . ^ . . ^ . . ^ . . ^ .
. .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<.
. . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ .
...+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+...
. . . . . . . . . . . . . . . . . . . . . . . . .
"q4"l[...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...
. ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . .
. a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+.. . a e ..+..
. ^mm . . ^mm . . ^mm . . ^mm . . ^mm . . ^mm . . ^mm . . ^mm .
... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... .........s"a4"
. . . . . . . . . . . . . . .
...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<. ...+.....o<.
. ^ . . ^ . . ^ . . ^ . . ^ . . ^ . . ^ . . ^ .
. .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<. . .]a a<.
. . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ . . . ^ ^ .
...+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+....+.....+.+...
. . . . . . . . . . . . . . . . . . . . . . . . .
"q8"l[...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...+.o<a e . ...
. ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . . . ^ m^^ . .