I want to add a verilator-generated uart model to RISCV-TLM project, but running dhrystone gives an error. #24
Alan-19950616
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I sent an issue to systemc and verilator too. |
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Did you try to back trace by using a debugger to locate the source location in your code from where this exception is being triggered? |
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error message
code changes
├── model
│ ├── Vapb_uart_sv.a
│ └── Vapb_uart_sv.h
├── inc
│ ├── Uart.h
├── src
│ ├── Uart.cpp
├── CMakeLists.txt
├── inc
│ ├── CPU.h
├── src
│ ├── CPU.cpp
│ ├── Simulator.cpp
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