From 0128cfe497224105f4e055692169c6a06c8bde18 Mon Sep 17 00:00:00 2001 From: Meinhard Kissich Date: Wed, 3 Apr 2024 14:30:59 +0200 Subject: [PATCH] Manually instantiate buffers --- rtl/fazyrv_pc.sv | 15 ++++++++++++++- rtl/fazyrv_shftreg.sv | 14 +++++++++++++- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/rtl/fazyrv_pc.sv b/rtl/fazyrv_pc.sv index f2fe7a2..aff71a1 100644 --- a/rtl/fazyrv_pc.sv +++ b/rtl/fazyrv_pc.sv @@ -95,7 +95,20 @@ assign add_vec = {{(ADD_VEC_WIDTH-3){1'b0}}, inc_i, 2'b00}; assign carry_vec[0] = carry_r[0]; -assign pc_n = shift_i ? {din_i, pc_r[31:CHUNKSIZE]} : pc_r; + +// Insert sky130 buffers manually to achieve a higher +// placement density. Inspired by MichaelBell/tinyQV +// www.github.com/MichaelBell/tinyQV/blob/69ce898bf1122e91a3114f3f0fe8e4bdf242f7f0/cpu/register.v#L58 +// + +logic [31-CHUNKSIZE:0] pc_dlyd; +`ifdef SKY130 + sky130_fd_sc_hd__dlygate4sd3_1 i_buf[31-CHUNKSIZE:0] ( .X(pc_dlyd), .A(pc_r[31:CHUNKSIZE]) ); +`else + buf #1 i_buf[31:CHUNKSIZE] (pc_dlyd, pc_r[31:CHUNKSIZE]); +`endif + +assign pc_n = shift_i ? {din_i, pc_dlyd} : pc_r; always_ff @(posedge clk_i) begin if (~rst_in) begin diff --git a/rtl/fazyrv_shftreg.sv b/rtl/fazyrv_shftreg.sv index 7f61f89..2d97e06 100644 --- a/rtl/fazyrv_shftreg.sv +++ b/rtl/fazyrv_shftreg.sv @@ -35,11 +35,23 @@ logic [31:0] reg_r = 'b0; logic [31:0] reg_r; `endif +// Insert sky130 buffers manually to achieve a higher +// placement density. Inspired by MichaelBell/tinyQV +// www.github.com/MichaelBell/tinyQV/blob/69ce898bf1122e91a3114f3f0fe8e4bdf242f7f0/cpu/register.v#L58 +// + +logic [31-CHUNKSIZE:0] reg_dlyd; +`ifdef SKY130 + sky130_fd_sc_hd__dlygate4sd3_1 i_buf[31-CHUNKSIZE:0] ( .X(reg_dlyd), .A(reg_r[31:CHUNKSIZE]) ); +`else + buf #1 i_buf[31:CHUNKSIZE] (reg_dlyd, reg_r[31:CHUNKSIZE]); +`endif + assign dat_o = reg_r[CHUNKSIZE-1:0]; always_ff @(posedge clk_i) begin if (shft_i) begin - reg_r <= {dat_i, reg_r[31:CHUNKSIZE]}; + reg_r <= {dat_i, reg_dlyd}; end end