AES.qsf

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#
# Copyright (C) 2018  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
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# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 21:59:37  April 30, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		AES_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY AES
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:59:37  APRIL 30, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "DE1-SoC Board"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE AES.v
set_global_assignment -name VERILOG_FILE addRoundKey.v
set_global_assignment -name VERILOG_FILE mixColumns.v
set_global_assignment -name VERILOG_FILE shiftRows.v
set_global_assignment -name VERILOG_FILE keyExpansion.v
set_global_assignment -name VERILOG_FILE AES_Encrypt.v
set_global_assignment -name VERILOG_FILE AES_Decrypt.v
set_global_assignment -name VERILOG_FILE subBytes.v
set_global_assignment -name VERILOG_FILE sbox.v
set_global_assignment -name VERILOG_FILE mixColumns_tb.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH AES_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME mixColumns_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id mixColumns_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME mixColumns_tb -section_id mixColumns_tb
set_global_assignment -name EDA_TEST_BENCH_NAME subBytes_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id subBytes_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME subBytes_tb -section_id subBytes_tb
set_global_assignment -name VERILOG_FILE subBytes_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME subword_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id subword_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME subword_tb -section_id subword_tb
set_global_assignment -name VERILOG_FILE shiftRows_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME shiftRows_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id shiftRows_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME shiftRows_tb -section_id shiftRows_tb
set_global_assignment -name VERILOG_FILE keyExpansion_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME keyExpansion_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id keyExpansion_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME keyExpansion_tb -section_id keyExpansion_tb
set_global_assignment -name VERILOG_FILE addRoundKey_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME addRoundKey_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id addRoundKey_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME addRoundKey_tb -section_id addRoundKey_tb
set_global_assignment -name VERILOG_FILE AES_Encrypt_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME AES_Encrypt_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id AES_Encrypt_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME AES_Encrypt_tb -section_id AES_Encrypt_tb
set_global_assignment -name VERILOG_FILE encryptRound.v
set_global_assignment -name VERILOG_FILE inverseShiftRows.v
set_global_assignment -name VERILOG_FILE inverseShiftRows_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME inverseShiftRows_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id inverseShiftRows_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME inverseShiftRows_tb -section_id inverseShiftRows_tb
set_global_assignment -name VERILOG_FILE inverseMixColumns.v
set_global_assignment -name VERILOG_FILE inverseMixColumns_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME inverseMixColumns_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id inverseMixColumns_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME inverseMixColumns_tb -section_id inverseMixColumns_tb
set_global_assignment -name VERILOG_FILE inverseSubBytes.v
set_global_assignment -name VERILOG_FILE inverseSbox.v
set_global_assignment -name VERILOG_FILE inverseSubBytes_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME inverseSubBytes_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id inverseSubBytes_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME inverseSubBytes_tb -section_id inverseSubBytes_tb
set_global_assignment -name VERILOG_FILE decryptRound.v
set_global_assignment -name VERILOG_FILE AES_Decrypt_tb.v
set_global_assignment -name EDA_TEST_BENCH_NAME AES_Decrypt_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id AES_Decrypt_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME AES_Decrypt_tb -section_id AES_Decrypt_tb
set_global_assignment -name VERILOG_FILE AES_tb.v
set_global_assignment -name EDA_TEST_BENCH_FILE mixColumns_tb.v -section_id mixColumns_tb
set_global_assignment -name EDA_TEST_BENCH_FILE subBytes_tb.v -section_id subBytes_tb
set_global_assignment -name EDA_TEST_BENCH_FILE subword_tb.v -section_id subword_tb
set_global_assignment -name EDA_TEST_BENCH_FILE shiftRows_tb.v -section_id shiftRows_tb
set_global_assignment -name EDA_TEST_BENCH_FILE keyExpansion_tb.v -section_id keyExpansion_tb
set_global_assignment -name EDA_TEST_BENCH_FILE addRoundKey_tb.v -section_id addRoundKey_tb
set_global_assignment -name EDA_TEST_BENCH_FILE AES_Encrypt_tb.v -section_id AES_Encrypt_tb
set_global_assignment -name EDA_TEST_BENCH_FILE inverseShiftRows_tb.v -section_id inverseShiftRows_tb
set_global_assignment -name EDA_TEST_BENCH_FILE inverseMixColumns_tb.v -section_id inverseMixColumns_tb
set_global_assignment -name EDA_TEST_BENCH_FILE inverseSubBytes_tb.v -section_id inverseSubBytes_tb
set_global_assignment -name EDA_TEST_BENCH_FILE AES_Decrypt_tb.v -section_id AES_Decrypt_tb
set_global_assignment -name EDA_TEST_BENCH_NAME AES_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id AES_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME AES_tb -section_id AES_tb
set_global_assignment -name EDA_TEST_BENCH_FILE AES_tb.v -section_id AES_tb
set_location_assignment PIN_V16 -to e128
set_location_assignment PIN_W16 -to d128
set_location_assignment PIN_V17 -to e192
set_location_assignment PIN_V18 -to d192
set_location_assignment PIN_W17 -to e256
set_location_assignment PIN_W19 -to d256
set_location_assignment PIN_AB12 -to enable
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top