Pistorm32lite does not work with Amiga Micronik bus board

[xinteksik]

Pistorm32lite does not work with Amiga Micronik bus board.

When starts amiga show kickstart logo from original rom and then, after emu68 starts, reboot to no screen.

It is possible to run emu68 in some debug mode and save log to sdcard to investigate what is wrong?

https://bigbookofamigahardware.com/bboah/product.aspx?id=1386

[michalsc]

You cannot log to sdcard because Emu68 does not know about sdcard and does not use it in any way. You can however attach serial logger, either synchronous or asynchronous, to PiStorm and store data that way.

[xinteksik]

Please, it is a guide to serial log on this page correct (section Debugging)? I have HDMI output, but nothing on serial log.

https://pistorm.neocities.org/#emu68

[rondoval]

ah, I think I see the same issue. This is all new to me, so I'll start by writing down what I see.

Hardware:

• A1200 rev.2B, with a timing fix
• Sum A1200 keyboard adapter
• Micronik A1200 6860 Rev. 4.20 bus board, also known as Z-2, this one: https://amiga.resource.cx/exp/micronik1200z1
• nothing connected to the bus board, I just feed power through it
• brand spanking new pistorm32-lite with rpi 4B, and not-so-new Apollo 1240

What happens:
a) Apollo 1240 with or without the busboard - no issues
b) pistorm without the busboard - works fine, except that it doesn't properly reset on Ctrl+Amiga+Amiga - is this normal?
c) pistorm with stealth firmware forced - all is fine, keyboard reset is working (well, obviously pistorm does nothing)
d) pistorm with the busboard... the computer starts, although it appears to be using the EC020 CPU (old kickstart, FPGA LED off on pistorm) and freezes as soon as FPGA LED turns on (empty screen with just the last background color).

[xinteksik]

Just for info. With buptest it started to show points of result and freeze. When I do a reset (by button on case) then result points continue for a while (unfreeze).

[rondoval]

just tried buptest. always fails at reading $000000, always reads $FF
buptest doesn't start at power on... only after keyboard or case reset. However, consecutive resets do nothing, i.e. the process doesn't restart... doesn't sound right. I guess it's time to start looking at the source code to understand it better :)
serial debugging is on GPIO26 on the rpi?

Update: It's on GPIO5.

When it starts:

[PS32] Set REQUEST_BM
[PS32] Set DRIVE_RESET
[PS32] Clear DRIVE_RESET
[PS32] Set DRIVE_RESET
[PS32] Clear DRIVE_RESET

..and it's stuck here. Then after triggering a keyboard reset it starts and is stuck again after a while:

[BOOT] Initlializing Z2 RAM expansion
[BOOT]   Z2 expansion disabled
[BOOT] Loading ROM from 0xffffff80005f5d40, size 524288
[BOOT] Setting IRQ routing to core 0
[BOOT] Enabling PMU and Timer interrupts on core 0
[BOOT] Disabling mailbox interrupts
[CACHE] Cache setup. Cache sizeof=22016
[CACHE] Way count: 8, Set count: 128
[CACHE] ICache @ 0xffffff80005f5d40, DCache @ 0xffffff80005fb380
[ICache] Initializing caches
[ICache] Setting up LRU
[ICache] Setting up ICache
[ICache] Temporary code at 0xffffffe0000020c0
[ICache] ICache array at 0xffffff80002a2698
[JIT]
[JIT] M68K Context:
[JIT]     D0 = 0x00000000    D1 = 0x00000000    D2 = 0x00000000    D3 = 0x00000000
[JIT]     D4 = 0x00000000    D5 = 0x00000000    D6 = 0x00000000    D7 = 0x00000000
[JIT]     A0 = 0x00000000    A1 = 0x00000000    A2 = 0x00000000    A3 = 0x00000000
[JIT]     A4 = 0x00000000    A5 = 0x00000000    A6 = 0x00000000    A7 = 0x00000000
[JIT]     PC = 0x00f800d2    SR = T0|S.|IPM7|.....
[JIT]     CACR=0x00000000    VBR= 0x00000000
[JIT]     USP= 0x00000000    MSP= 0x00000000    ISP= 0x11144ef9
[JIT]     FP0 = 7fffffffffffffff (NaN)    FP1 = 7fffffffffffffff (NaN)
[JIT]     FP2 = 7fffffffffffffff (NaN)    FP3 = 7fffffffffffffff (NaN)
[JIT]     FP4 = 7fffffffffffffff (NaN)    FP5 = 7fffffffffffffff (NaN)
[JIT]     FP6 = 7fffffffffffffff (NaN)    FP7 = 7fffffffffffffff (NaN)
[JIT]     FPSR=0x00000000    FPIAR=0x00000000   FPCR=0x0000
[JIT] Let it go...
[ICache] Creating new translation unit with hash c006 (m68k code @ 0x0000000000f800d2)
[ICache]   Translated 1 M68k instructions to 6 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 4, Conditionals: 0
[ICache]   Mean epilogue size pro exit point: 4
[ICache]   Mean ARM instructions per m68k instruction: 2.00
[ICache]   Block checksum: 4ad3f574
[ICache]   ARM code at 0xfffffff000042180
-- ARM Code dump --
    52 02 02 11 26 00 80 52 c0 00 67 9e de 87 e0 4e c0 03 5f d6
[ICache] Creating new translation unit with hash c00a (m68k code @ 0x0000000000f80152)
[ICache]   Going backwards to location 00f80162
[ICache]   Translated 9 M68k instructions to 43 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 10, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 5
[ICache]   Mean ARM instructions per m68k instruction: 3.66
[ICache]   Block checksum: bd2aadcd
[ICache]   ARM code at 0xfffffff0000422c0
-- ARM Code dump --
    1d 80 80 52 0d 1f a0 52 14 00 80 12 35 00 80 52 18 00 80 52
    a4 45 40 b8 18 03 04 2b 44 d0 3b d5 05 42 3b d5 a4 7c 1c 33
    e5 37 9f 1a a4 00 1c 33 e4 00 08 37 52 5a 00 11 44 d0 1b d5
    e5 00 80 52 a0 00 67 9e de 87 e0 4e c0 03 5f d6 52 52 00 11
    18 07 00 31 05 42 3b d5 a4 7c 1c 33 e5 37 9f 1a a4 00 1c 33
    45 1a 00 11 46 12 00 51 87 3e 00 53 e7 04 00 71 f4 3c 00 33
    b2 40 86 1a c5 00 00 54 44 d0 1b d5 25 01 80 52 a0 00 67 9e
    de 87 e0 4e c0 03 5f d6 44 d0 1b d5 26 01 80 52 c0 00 67 9e
    de 87 e0 4e c0 03 5f d6
[ICache] Creating new translation unit with hash c00b (m68k code @ 0x0000000000f80168)
[ICache]   Going backwards to location 00f80162
[ICache]   Translated 1 M68k instructions to 16 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 8, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 4
[ICache]   Mean ARM instructions per m68k instruction: 8.00
[ICache]   Block checksum: 4e3fc2aa
[ICache]   ARM code at 0xfffffff000042480
-- ARM Code dump --
    44 12 00 11 45 1a 00 51 86 3e 00 53 c6 04 00 71 d4 3c 00 33
    92 40 85 1a a5 00 00 54 24 00 80 52 80 00 67 9e de 87 e0 4e
    c0 03 5f d6 26 00 80 52 c0 00 67 9e de 87 e0 4e c0 03 5f d6
[ICache] Creating new translation unit with hash c00b (m68k code @ 0x0000000000f80162)
[ICache]   Going backwards to location 00f80162
[ICache]   Creating loop within translation unit
[ICache]   Translated 4 M68k instructions to 41 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 13, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 6
[ICache]   Mean ARM instructions per m68k instruction: 7.00
[ICache]   Block checksum: 4e3fc2aa
[ICache]   ARM code at 0xfffffff0000425c0
-- ARM Code dump --
    a4 45 40 b8 18 03 04 2b 44 d0 3b d5 05 42 3b d5 a4 7c 1c 33
    e5 37 9f 1a a4 00 1c 33 e4 00 08 37 52 1a 00 11 44 d0 1b d5
    45 00 80 52 a0 00 67 9e de 87 e0 4e c0 03 5f d6 52 12 00 11
    18 07 00 31 05 42 3b d5 a4 7c 1c 33 e5 37 9f 1a a4 00 1c 33
    45 1a 00 11 46 12 00 51 87 3e 00 53 e7 04 00 71 f4 3c 00 33
    b2 40 86 1a c5 00 00 54 44 d0 1b d5 85 00 80 52 a0 00 67 9e
    de 87 e0 4e c0 03 5f d6 44 d0 1b d5 66 d0 3b d5 c5 c8 40 b9
    87 00 80 52 e0 00 67 9e de 87 e0 4e 45 fb ff 34 c0 03 5f d6
[ICache] Creating new translation unit with hash c00b (m68k code @ 0x0000000000f8016c)
[ICache]   Going backwards to location 00f80162
[ICache]   Translated 1 M68k instructions to 16 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 8, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 4
[ICache]   Mean ARM instructions per m68k instruction: 8.00
[ICache]   Block checksum: b5430df1
[ICache]   ARM code at 0xfffffff000042780
-- ARM Code dump --
    44 12 00 11 45 2a 00 51 a6 3e 00 53 c6 04 00 71 d5 3c 00 33
    92 40 85 1a a5 00 00 54 24 00 80 52 80 00 67 9e de 87 e0 4e
    c0 03 5f d6 26 00 80 52 c0 00 67 9e de 87 e0 4e c0 03 5f d6
[ICache] Creating new translation unit with hash c00b (m68k code @ 0x0000000000f80170)
[ICache]   Translated 8 M68k instructions to 37 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 5, Conditionals: 0
[ICache]   Mean epilogue size pro exit point: 5
[ICache]   Mean ARM instructions per m68k instruction: 4.00
[ICache]   Block checksum: ef5972c3
[ICache]   ARM code at 0xfffffff0000428c0
-- ARM Code dump --
    5b 92 01 11 4d c2 05 51 0e 1e a0 52 df 01 0d 6b 44 d0 3b d5
    e5 17 9f 1a a4 00 1e 33 e4 00 10 36 52 72 00 11 44 d0 1b d5
    a5 00 80 52 a0 00 67 9e de 87 e0 4e c0 03 5f d6 52 4a 00 11
    25 22 a2 52 c6 01 40 79 c7 3c 10 53 ff 00 05 6b 05 42 3b d5
    a5 00 03 52 a4 7c 1c 33 e4 00 10 37 52 2a 00 11 44 d0 1b d5
    e5 00 80 52 a0 00 67 9e de 87 e0 4e c0 03 5f d6 52 1a 00 11
    d2 09 00 11 44 d0 1b d5 06 01 80 52 c0 00 67 9e de 87 e0 4e
    c0 03 5f d6
[ICache] Creating new translation unit with hash c00c (m68k code @ 0x0000000000f8018c)
[ICache]   Translated 26 M68k instructions to 83 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 5, Conditionals: 0
[ICache]   Mean epilogue size pro exit point: 5
[ICache]   Mean ARM instructions per m68k instruction: 3.00
[ICache]   Block checksum: 26b1cd7b
[ICache]   ARM code at 0xfffffff000042a80
-- ARM Code dump --
    04 00 80 52 05 00 90 52 45 1b a0 72 a4 00 00 39 9f 3f 03 d5
    52 2a 00 11 0e 14 a0 52 04 20 b2 52 c5 01 40 39 a6 1c 08 53
    df 00 04 6b 44 d0 3b d5 e5 17 9f 1a a4 00 1e 33 e4 00 10 37
    52 fa 00 11 44 d0 1b d5 a5 00 80 52 a0 00 67 9e de 87 e0 4e
    c0 03 5f d6 52 32 00 11 ce 09 00 11 05 a0 a0 52 c6 01 40 39
    c7 1c 08 53 ff 00 05 6b e5 17 9f 1a a4 00 1e 33 e4 00 10 37
    52 ca 00 11 44 d0 1b d5 05 01 80 52 a0 00 67 9e de 87 e0 4e
    c0 03 5f d6 52 22 00 11 ce 09 00 11 05 60 a4 52 c6 01 40 39
    c7 1c 08 53 ff 00 05 6b e5 17 9f 1a a4 00 1e 33 e4 00 10 37
    52 aa 00 11 44 d0 1b d5 65 01 80 52 a0 00 67 9e de 87 e0 4e
    c0 03 5f d6 52 22 00 11 ce 09 00 11 c5 01 40 39 b3 1c 00 33
    73 22 93 13 ce 09 00 11 c5 01 40 39 b3 1c 00 33 73 22 93 13
    ce 09 00 11 c5 01 40 39 b3 1c 00 33 73 22 93 13 ce 09 00 11
    c5 01 40 39 b3 1c 00 33 73 22 93 13 ff 03 13 2b 06 42 3b d5
    c4 7c 1c 33 84 74 3e 12 65 7e 1f 33 a4 00 1f 33 0d 0c a0 52
    ad 01 13 0b f2 03 0d 2a 44 d0 1b d5 46 03 80 52 c0 00 67 9e
    de 87 e0 4e c0 03 5f d6
[ICache] Creating new translation unit with hash c00e (m68k code @ 0x0000000000f801d4)
[ICache]   Going backwards to location 00f80238
[ICache]   Translated 22 M68k instructions to 73 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 10, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 5
[ICache]   Mean ARM instructions per m68k instruction: 2.86
[ICache]   Block checksum: d2afaf7d
[ICache]   ARM code at 0xfffffff000042d00
-- ARM Code dump --
    24 00 80 52 05 00 90 52 45 1b a0 72 a4 00 00 39 24 00 94 52
    e4 17 a0 72 9f 00 00 39 24 40 94 52 e4 17 a0 72 9f 00 00 39
    24 00 9c 52 e4 17 a0 72 9f 00 00 39 64 00 80 52 25 40 9c 52
    e5 17 a0 72 a4 00 00 39 11 00 9e 52 f1 1b a0 72 e4 ff 8f 52
    93 3c 00 33 33 a2 09 78 33 c2 09 78 33 62 09 78 84 2e 80 52
    24 22 03 78 04 40 80 52 24 02 02 79 04 00 80 52 24 22 02 79
    24 22 80 52 24 02 03 79 04 e0 81 52 93 3c 00 33 f8 03 38 2a
    44 d0 3b d5 ff 03 18 2b e5 17 9f 1a a4 00 1e 33 e4 00 10 37
    52 0a 0b 11 44 d0 1b d5 25 02 80 52 a0 00 67 9e de 87 e0 4e
    c0 03 5f d6 52 6a 01 11 0d 01 80 52 b4 05 80 52 4e 92 09 11
    ff 03 0e 2b ae 45 00 b8 05 42 3b d5 a4 7c 1c 33 84 74 3e 12
    45 42 00 11 46 2a 00 11 87 3e 00 53 e7 04 00 71 f4 3c 00 33
    b2 40 86 1a c5 00 00 54 44 d0 1b d5 c5 02 80 52 a0 00 67 9e
    de 87 e0 4e c0 03 5f d6 44 d0 1b d5 c6 02 80 52 c0 00 67 9e
    de 87 e0 4e c0 03 5f d6
[JIT:SYS] OVL bit changing to 0
[ICache] Creating new translation unit with hash c011 (m68k code @ 0x0000000000f80238)
[ICache]   Going backwards to location 00f80238
[ICache]   Creating loop within translation unit
[ICache]   Translated 2 M68k instructions to 27 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 13, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 6
[ICache]   Mean ARM instructions per m68k instruction: 7.00
[ICache]   Block checksum: 1314817b
[ICache]   ARM code at 0xfffffff000042f40
-- ARM Code dump --
    ff 03 0e 2b ae 45 00 b8 44 d0 3b d5 05 42 3b d5 a4 7c 1c 33
    84 74 3e 12 45 1a 00 11 e6 03 12 2a 87 3e 00 53 e7 04 00 71
    f4 3c 00 33 b2 40 86 1a c5 00 00 54 44 d0 1b d5 45 00 80 52
    a0 00 67 9e de 87 e0 4e c0 03 5f d6 44 d0 1b d5 66 d0 3b d5
    c5 c8 40 b9 47 00 80 52 e0 00 67 9e de 87 e0 4e 05 fd ff 34
    c0 03 5f d6
[ICache] Creating new translation unit with hash c011 (m68k code @ 0x0000000000f8023e)
[ICache]   Going backwards to location 00f80244
[ICache]   Translated 5 M68k instructions to 35 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 10, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 5
[ICache]   Mean ARM instructions per m68k instruction: 5.00
[ICache]   Block checksum: 78dddbbf
[ICache]   ARM code at 0xfffffff0000430c0
-- ARM Code dump --
    04 1e 80 52 93 3c 00 33 b4 05 80 52 a4 cd 5f b8 df 01 04 6b
    44 d0 3b d5 05 42 3b d5 a5 00 03 52 a4 7c 1c 33 e4 00 10 37
    52 62 09 11 44 d0 1b d5 85 00 80 52 a0 00 67 9e de 87 e0 4e
    c0 03 5f d6 52 32 00 11 45 12 00 11 46 1a 00 51 87 3e 00 53
    e7 04 00 71 f4 3c 00 33 b2 40 86 1a c5 00 00 54 44 d0 1b d5
    a5 00 80 52 a0 00 67 9e de 87 e0 4e c0 03 5f d6 44 d0 1b d5
    a6 00 80 52 c0 00 67 9e de 87 e0 4e c0 03 5f d6
[ICache] Creating new translation unit with hash c024 (m68k code @ 0x0000000000f80496)
[ICache]   Going backwards to location 00f804b6
[ICache]   Translated 9 M68k instructions to 39 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 10, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 5
[ICache]   Mean ARM instructions per m68k instruction: 3.22
[ICache]   Block checksum: 089dc3bc
[ICache]   ARM code at 0xfffffff000043280
-- ARM Code dump --
    11 00 9e 52 f1 1b a0 72 04 40 80 52 24 02 02 79 04 00 80 52
    24 22 02 79 33 02 03 79 54 01 80 52 13 00 80 12 44 d0 3b d5
    65 01 80 52 84 00 25 0a 84 00 1d 32 2d 00 9c 52 ed 17 a0 72
    a5 01 40 39 bf 00 1f 72 a5 00 1f 32 a5 01 00 39 e0 17 9f 1a
    04 00 1e 33 45 a2 00 11 46 82 00 11 67 3e 00 53 e7 04 00 71
    f3 3c 00 33 b2 40 86 1a c5 00 00 54 44 d0 1b d5 25 01 80 52
    a0 00 67 9e de 87 e0 4e c0 03 5f d6 44 d0 1b d5 26 01 80 52
    c0 00 67 9e de 87 e0 4e c0 03 5f d6
[JIT:SYS] OVL bit changing to 1
[ICache] Creating new translation unit with hash c025 (m68k code @ 0x0000000000f804b6)
[ICache]   Going backwards to location 00f804b6
[ICache]   Creating loop within translation unit
[ICache]   Translated 2 M68k instructions to 28 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 13, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 6
[ICache]   Mean ARM instructions per m68k instruction: 7.50
[ICache]   Block checksum: cbfe9b44
[ICache]   ARM code at 0xfffffff000043440
-- ARM Code dump --
    a4 01 40 39 9f 00 1f 72 84 00 1f 32 a4 01 00 39 44 d0 3b d5
    e0 17 9f 1a 04 00 1e 33 45 22 00 11 e6 03 12 2a 67 3e 00 53
    e7 04 00 71 f3 3c 00 33 b2 40 86 1a c5 00 00 54 44 d0 1b d5
    45 00 80 52 a0 00 67 9e de 87 e0 4e c0 03 5f d6 44 d0 1b d5
    66 d0 3b d5 c5 c8 40 b9 47 00 80 52 e0 00 67 9e de 87 e0 4e
    e5 fc ff 34 c0 03 5f d6
[ICache] Creating new translation unit with hash c025 (m68k code @ 0x0000000000f804be)
[ICache]   Going backwards to location 00f804c0
[ICache]   Translated 3 M68k instructions to 37 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 10, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 5
[ICache]   Mean ARM instructions per m68k instruction: 9.00
[ICache]   Block checksum: d831ae7e
[ICache]   ARM code at 0xfffffff0000435c0
-- ARM Code dump --
    7f 02 1f 72 64 3e 00 53 84 7c 02 53 93 3c 00 33 45 d0 3b d5
    66 03 80 52 a5 00 26 0a 46 02 80 52 a6 00 06 2a a5 00 86 1a
    ff 43 04 2b a0 00 1d 32 05 40 85 1a a4 01 40 39 9f 00 1f 72
    84 78 1e 12 a4 01 00 39 e0 17 9f 1a 05 00 1e 33 44 2a 00 11
    46 0a 00 11 67 3e 00 53 e7 04 00 71 f3 3c 00 33 92 40 86 1a
    c5 00 00 54 45 d0 1b d5 64 00 80 52 80 00 67 9e de 87 e0 4e
    c0 03 5f d6 45 d0 1b d5 66 00 80 52 c0 00 67 9e de 87 e0 4e
    c0 03 5f d6
[ICache] Creating new translation unit with hash c026 (m68k code @ 0x0000000000f804c0)
[ICache]   Going backwards to location 00f804c0
[ICache]   Creating loop within translation unit
[ICache]   Translated 2 M68k instructions to 28 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 13, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 6
[ICache]   Mean ARM instructions per m68k instruction: 7.50
[ICache]   Block checksum: 30a29692
[ICache]   ARM code at 0xfffffff000043780
-- ARM Code dump --
    a4 01 40 39 9f 00 1f 72 84 78 1e 12 a4 01 00 39 44 d0 3b d5
    e0 17 9f 1a 04 00 1e 33 45 22 00 11 e6 03 12 2a 67 3e 00 53
    e7 04 00 71 f3 3c 00 33 b2 40 86 1a c5 00 00 54 44 d0 1b d5
    45 00 80 52 a0 00 67 9e de 87 e0 4e c0 03 5f d6 44 d0 1b d5
    66 d0 3b d5 c5 c8 40 b9 47 00 80 52 e0 00 67 9e de 87 e0 4e
    e5 fc ff 34 c0 03 5f d6
[ICache] Creating new translation unit with hash c026 (m68k code @ 0x0000000000f804c8)
[ICache]   Going backwards to location 00f804b6
[ICache]   Translated 1 M68k instructions to 16 ARM instructions
[ICache]   Prologue size: 0, Epilogue size: 8, Conditionals: 1
[ICache]   Mean epilogue size pro exit point: 4
[ICache]   Mean ARM instructions per m68k instruction: 8.00
[ICache]   Block checksum: fe806005
[ICache]   ARM code at 0xfffffff000043900
-- ARM Code dump --
    44 12 00 11 45 4a 00 51 86 3e 00 53 c6 04 00 71 d4 3c 00 33
    92 40 85 1a a5 00 00 54 24 00 80 52 80 00 67 9e de 87 e0 4e
    c0 03 5f d6 26 00 80 52 c0 00 67 9e de 87 e0 4e c0 03 5f d6
[HKEEP] Houskeeper will reset RasPi now...
[JIT:SYS] OVL bit changing to 0
[JIT:SYS] OVL bit changing to 1

[rondoval]

ok, so this is not a software problem.
From Emu68 perspective what happens is:

• once EMU orders gateware to assert _BR, it doesn't check whether _BG is asserted; in fact, with the Micronik board, it is not.
• Emu68 fails at first bus write, i.e. Gayle detection. Gateware never negates TXN signal.
• Gateware is aware it is not a bus master, thus I think the outputs are not driven.

Now, why this happens.
Once _BR is asserted, the voltage does not drop to low state levels. It drops, but stays above 2V. The '020 CPU remains active.

I haven't finished checking how the busboard is wired, however my hypotesis is as follows:
The _BOSS and _BR signals are separate. _BOSS is wired directly to _BOSS on the A1200 board (and also goes somewhere to the busboard), _BR and _BG are not connected to the A1200 board directly - they come somewhere "up" from the busboard.

I'm speculating that _BR is driven by one of the GAL chip outputs and that would be a reason why we can't drive it down. This could be done in order to support Zorro II bus mastering, i.e. the accelerator is supposed to sense _BR and yield the bus to Zorro II devices when requested by the busboard arbitration logic. Then a separate _BOSS line would shut down the '020 CPU.

[rondoval]

progress - got the buptest running on the other screen :)
This is a combination of two issues... will post details later today.

The details:
This applies to "Micronik A-1200 6860 Rev. 4.20" with the "Micronik 6860 Adapter Rev.6.0". Any other combination may differ.
Three points really:

1. The TURBO jumper needs to be closed for Pistorm to work. It connects the _BR line from the accelerator to the A1200 board. Without this, Pistorm will not be able to shut down the MC68EC020.
2. The _BG line from A1200 is not connected to the accelerator, hence standard Pistorm gateware will not drive the bus.
   I'm currently running a modified gateware that ignores the state of _BG, however I plan to try connecting the _BG line with a wire on the busboard soon-ish.
   For reference, _BG from A1200 is connected to one of the GAL20V8B chips (2nd from the bottom of the board, pin 10, input). _BG from accelerator is not connected anywhere.
3. _BR line... Now the thing with this one is I am not sure whether this is my busboard being faulty or just standard behavior. Would be good if someone could verify by measuring voltage on the _BR line (really between GND and the TURBO jumper on the busboard). On unmodified Pistorm, I was getting close to 3V if I recall. Should be close to 0V.

The _BR line is connected to the same GAL20V8B chip (pin 15, I/O/Q), and at least on my board, it is pulling up the line fairly strongly. Pistorm cannot sink enough to drive the line down.
Connecting _BOSS to GND is not enough, voltage drops to ca. 2.2V. This is because _BOSS is connected to _BR via a 220ohm resistor on my A1200 board (rev 2B). It seems we'd need to sink ca. 33mA.... Which is way more than the Trion can do. So in order to make it work, I had to do what the Apollo 1240 does - connect _BR straight to GND (with a jumper wire).
Now this is obviously not ideal as stealth mode will not work... so sounds like a proper solution will be to redesign the Pistorm a little... or create a small add-on board for the "spare" pins+modified gateware. If 3) is really a systemic issue and not a fried GAL on my board

The busboard with the TURBO switch and the GAL to which _BR and _BG are connected marked: https://ibb.co/y2654xY
This is where I plan to connect _BG line: https://ibb.co/mrkTWySc
This is my "temporary fix" for 3): https://ibb.co/wF0KJh3L

[rondoval]

Just to wrap things up: with the _BG line connected on the Micronik board, stock gateware works fine.

[rondoval]

so I got hold of a v5.42 busboard, with a v6.1 adapter board. This one requires only the _BG signal to be connected, same way as on the v4.20: https://ibb.co/mrkTWySc
No need to to anything to Pistorm - i.e. my v4.20 busboard has a fried GAL chip that pulls up _BR...