Proposal to contribute RISC-V support

[CNOCycle]

I am writing to express my interest in contributing to the ongoing efforts to support the RISC-V architecture within the onnxruntime framework.

I noticed an issue (# 16544) and a pull request (# 16768) concerning RISC-V support, as well as a forked project onnxruntime-riscv [1] with a similar aim, it appears that there is a latent interest in this direction. However, it seems that the latter project has not seen maintenance in quite some time.

I am pleased to share that I have undertaken an initial attemp to enable onnxruntime on RISC-V. In my implementation, all unit tests have successfully passed, except for one test that highlights a discrepancy between the IEEE 754 standard [2] and the RISC-V specification [3]. Notably, this attempt only involves the basic RISC-V ISA (rv64imafdc), without any additional accelerators or new execution providers. I believe this marks a promising starting point, and the incorporation of extensions such as V or others can potentially be facilitated by execution providers in the future.

If supporting the RISC-V architecture aligns with the current roadmap, I am enthusiastic about sharing my implementation with the community. I am open to feedback, collaboration, and further guidance in order to contribute effectively to this attempt.

References

[1] https://github.com/ucb-bar/onnxruntime-riscv

[2] Microprocessor Standards Committee. (2019). 754-2019-IEEE Standard for Floating-Point Arithmetic.

[3] The RISC-V Instruction Set Manual Volume I: Unprivileged ISA. (2019). https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf

[faxu]

Hi @CNOCycle, we're open to the contribution. A few questions:

• Is this something you'd be willing to help maintain within the community for issues and future growth?
• Have you tested your implementation on existing RISC-V hardware? And do you have ability to maintain ongoing CI-type testing?
• What is the breadth of changes required for compatibility?

[NonerKao]

Hi @faxu , Sorry for the late reply. We will send our PR in a few days.

CNOCycle and I belong to the same team in Andes Technology, one of the premier and founding members of RISC-V International. We are willing to help maintain the RISC-V port of this project.

Have you tested your implementation on existing RISC-V hardware?

No. So far, we run our basic patch on dockerized Debain-based user-space QEMU. We believe that after our patch enables the support to RISC-V in this project, people with any RISC-V hardware can try it themselves.

do you have ability to maintain ongoing CI-type testing?

Would you please elaborate more on the practice of CI testing for this project, or is there any CI porting guide that we can study first?

What is the breadth of changes required for compatibility?

Our first patch contains minimal changes to the build script and cmake files so that (cross-)compiling for RISC-V will become possible. There is no compatibility concern in this preliminary stage. For future changes, I expect that RISC-V community will have more interests in supporting different execution providers than complete the computation ability for baseline CPUs.

[faxu]

Would you please elaborate more on the practice of CI testing for this project, or is there any CI porting guide that we can study first?

For our officially supported platforms/archs, our CIs run on each PR so we're able to catch issues/breakages from new changes as they come in. Since we don't have RISC-V devices/VMs to validate the builds, we hope that you're able to set up regular runs of the current main branch to catch potential regressions as early as possible to avoid breaking things when releases are cut. This doesn't need to be on each PR, but could be nightly or weekly. At a minimum, you'd just build ORT for the architecture to run all unit tests. If there are additional tests that would be valuable to ensure functional completeness, that could be covered as well.

[CNOCycle]

Hi @faxu,

Thank you for your clarification. I believe the CIs part should be refined, but we can present the initial draft and welcome all feedback and collaboration, with the aim of making it compatible with MS CIs soon.

[CNOCycle]

Hi @faxu

I submitted a PR (#18115) to get basic RISC-V support. I hope your team has time to review this PR. Thanks.