Skip to content

Latest commit

 

History

History
21 lines (15 loc) · 982 Bytes

README.md

File metadata and controls

21 lines (15 loc) · 982 Bytes
Raw

DLX Processor Implementation

This repository contains the VHDL code for the implementation of a DLX processor, as well as scripts for simulation and synthesis.

Project Structure

  • simulation/DLX/: VHDL source code for the DLX processor
  • simulation/SCRIPTS/: Scripts for automating the simulation process
  • synthesis/: Scripts for automating the synthesis process
  • floorplan: Contains the required files for loading the design in Innovus

Tools Used

The scripts provided in this repository are designed to work with the following tools:

  • Synopsys Design Vision (for synthesis)
  • Siemens ModelSim (for simulation)
  • Cadence Innovus (for physical design)

Please note that the scripts will not function correctly without these specific tools.

Usage

Detailed instructions for using the scripts can be found in the project report. It is highly recommended to read the report to fully understand the DLX processor's architecture and how to run the provided scripts.