-
Notifications
You must be signed in to change notification settings - Fork 9
/
ssse3_priv.h
195 lines (164 loc) · 4.89 KB
/
ssse3_priv.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
#pragma once
#include "opemu.h"
#include "libudis86/extern.h"
#include "fpins.h"
#include <asm/fpu/internal.h>
// log function debug
#define LF D("%s\n", __PRETTY_FUNCTION__);
#define D printk
/**
* 128-bit Register proper for ssse3
* For 64-bit operations, use the same register type, and ignore the high values
*/
union __attribute__((__packed__)) sse_reg {
int8_t int8[16];
int16_t int16[8];
int32_t int32[4];
int64_t int64[2];
__int128_t int128;
uint8_t uint8[16];
uint16_t uint16[8];
uint32_t uint32[4];
uint64_t uint64[2];
int32_t a32[4];
int64_t a64[2];
double fa64[2];
float fa32[4];
__uint128_t uint128;
__float128 fa128;
};
typedef union sse_reg sse_reg_t;
/**
* Print said register to screen. Useful for debugging
* @param uint128
*/
#define print128(x) printk("0x%016llx%016llx", ((uint64_t*)(&(x)))[1], ((uint64_t*)(&(x)))[0] );
/**
* ssse3 object
*/
struct ssse3 {
uint8_t extended; // bool type
sse_reg_t dst, src;
sse_reg_t res;
// operands
const ud_operand_t *udo_src, *udo_dst, *udo_imm;
// objects
op_t *op_obj;
uint8_t dst64;
uint8_t dst32;
uint64_t res64;
uint32_t res32;
// legacy mmx flag
uint8_t ismmx;
};
typedef struct ssse3 ssse3_t;
static inline void _load_maddr_from_xmm (uint64_t rmaddrs, sse_reg_t *where, uint16_t rm_size, struct pt_regs *regs) {
if (is_saved_state64(regs)) {
if (rm_size == 128) {
__uint128_t M128RES = ((sse_reg_t*)where)->uint128;
*((__uint128_t*)&rmaddrs) = M128RES;
} else if (rm_size == 64) {
uint64_t M64RES = ((sse_reg_t*)where)->uint64[0];
*((uint64_t*)&rmaddrs) = M64RES;
} else if (rm_size == 32) {
uint32_t M32RES = ((sse_reg_t*)where)->uint32[0];
*((uint32_t*)&rmaddrs) = M32RES;
}
} else {
uint32_t rmaddrs32 = rmaddrs & 0xffffffff;
if (rm_size == 128) {
__uint128_t M128RES = ((sse_reg_t*)where)->uint128;
*((__uint128_t*)&rmaddrs32) = M128RES;
} else if (rm_size == 64) {
uint64_t M64RES = ((sse_reg_t*)where)->uint64[0];
*((uint64_t*)&rmaddrs32) = M64RES;
} else if (rm_size == 32) {
uint32_t M32RES = ((sse_reg_t*)where)->uint32[0];
*((uint32_t*)&rmaddrs) = M32RES;
}
}
}
/**
* Instruction emulation function type.
*/
typedef void (*ssse3_func)(ssse3_t*);
#define fstored_template(n, where) \
do { \
kernel_fpu_begin(); \
asm __volatile__ ("movss %%xmm" #n ", %0" : "=m" (*(where))); \
kernel_fpu_end(); \
} while (0);
#define floadd_template(n, where) \
do { \
kernel_fpu_begin(); \
asm __volatile__ ("movss %0, %%xmm" #n :: "m" (*(where))); \
kernel_fpu_end(); \
} while (0);
#define storedqu_template(n, where) \
do { \
asm __volatile__ ("movdqu %%xmm" #n ", %0" : "=m" (*(where))); \
} while (0);
#define loaddqu_template(n, where) \
do { \
asm __volatile__ ("movdqu %0, %%xmm" #n :: "m" (*(where))); \
} while (0);
#define storeq_template(n, where) \
do { \
asm __volatile__ ("movq %%mm" #n ", %0" : "=m" (*(where))); \
} while (0);
#define loadq_template(n, where) \
do { \
asm __volatile__ ("movq %0, %%mm" #n :: "m" (*(where))); \
} while (0);
inline int ssse3_grab_operands(ssse3_t*);
inline int ssse3_commit_results(ssse3_t*);
inline int op_sse3x_run(op_t*);
inline void psignb (ssse3_t*);
inline void psignw (ssse3_t*);
inline void psignd (ssse3_t*);
inline void pabsb (ssse3_t*);
inline void pabsw (ssse3_t*);
inline void pabsd (ssse3_t*);
inline void palignr (ssse3_t*);
inline void pshufb (ssse3_t*);
inline void pmulhrsw (ssse3_t*);
inline void pmaddubsw (ssse3_t*);
inline void phsubw (ssse3_t*);
inline void phsubd (ssse3_t*);
inline void phsubsw (ssse3_t*);
inline void phaddw (ssse3_t*);
inline void phaddd (ssse3_t*);
inline void phaddsw (ssse3_t*);
//SSE 4.1
inline void blendpd (ssse3_t*);
inline void blendps (ssse3_t*);
inline void pblendw (ssse3_t*);
inline void pextrb (ssse3_t*);
inline void pmovsxbd (ssse3_t*);
inline void pmovsxbq (ssse3_t*);
inline void pmovsxbw (ssse3_t*);
inline void pmovsxdq (ssse3_t*);
inline void pmovsxwd (ssse3_t*);
inline void pmovsxwq (ssse3_t*);
inline void pmovzxbd (ssse3_t*);
inline void pmovzxbq (ssse3_t*);
inline void pmovzxbw (ssse3_t*);
inline void pmovzxdq (ssse3_t*);
inline void pmovzxwd (ssse3_t*);
inline void pmovzxwq (ssse3_t*);
inline void roundss (ssse3_t*);
inline void pextrb (ssse3_t*);
inline void pextrd (ssse3_t*);
inline void pextrq (ssse3_t*);
inline void ptest (ssse3_t*);
inline void pinsrb (ssse3_t*);
inline void pinsrd (ssse3_t*);
inline void pinsrq (ssse3_t*);
/*** SSE4.2 TODO move this somewhere else ***/
inline void pcmpistri (ssse3_t*);
inline void pcmpestri (ssse3_t*);
inline void pcmpestrm (ssse3_t*);
inline void pcmpistrm (ssse3_t*);
inline void pcmpgtq (ssse3_t*);
inline void popcnt (ssse3_t*);
inline void crc32_op (ssse3_t*);