OTM8009A SKU:MRB3971 800*480 display support #269

chmilw · 2023-03-15T06:52:19Z

chmilw
Mar 15, 2023

Dear moononournation!
I am developing small project using Module OTM8009A SKU:MRB3971
Can You please help me how to implement it into Your library?
I don't have enough knowledge to write my own driver.

moononournation · 2023-03-15T06:57:45Z

moononournation
Mar 15, 2023
Maintainer

try this: https://github.com/moononournation/Arduino_GFX/wiki/Display-Class#nt35510-lcd-480x800

0 replies

chmilw · 2023-03-15T10:19:01Z

chmilw
Mar 15, 2023
Author

Did so does not work, stripes on the screen

#include <Arduino_GFX_Library.h>
#define GFX_BL 1
Arduino_DataBus bus = new Arduino_SWPAR8(35 /DC/, 36 /CS/, 4 / WR /, 2 / RD /,
45 / D0 /, 16 / D1 /, 15 / D2 /, 10 / D3 /, 8 / D4 /, 7 / D5 /, 6 / D6 /, 5 / D7 */);
Arduino_GFX gfx = new Arduino_NT35510(bus, 3 / RST /, 0 / rotation */);

void setup(void)
{
gfx->begin();
gfx->fillScreen(BLACK);

#ifdef GFX_BL
pinMode(GFX_BL, OUTPUT);
digitalWrite(GFX_BL, HIGH);
#endif

gfx->setCursor(10, 10);
gfx->setTextColor(RED);
gfx->println("Hello World!");

delay(5000); // 5 seconds

}

void loop()
{
gfx->setCursor(random(gfx->width()), random(gfx->height()));
gfx->setTextColor(random(0xffff), random(0xffff));
gfx->setTextSize(random(6) /* x scale /, random(6) / y scale /, random(2) / pixel_margin */);
gfx->println("Hello World!");

delay(100); // 1 second

}

Video.mp4

1 reply

moononournation Mar 15, 2023
Maintainer

not yet tried SWPAR8 with this display, what dev board are you using?

chmilw · 2023-03-15T11:12:56Z

chmilw
Mar 15, 2023
Author

https://www.aliexpress.com/item/1005004642646719.html?spm=a2g0o.order_list.order_list_main.271.4c781802L0wOeB

1 reply

moononournation Mar 15, 2023
Maintainer

try using ESP32LCD16 instead of SWPAR8

chmilw · 2023-03-15T11:16:23Z

chmilw
Mar 15, 2023
Author

on the Internet, I found information that NT35510 and OTM8009A are not initialized in the same way

0 replies

chmilw · 2023-03-15T11:30:50Z

chmilw
Mar 15, 2023
Author

tried ESPL32CD16 still doesn't work

0 replies

chmilw · 2023-03-15T11:33:54Z

chmilw
Mar 15, 2023
Author

tried it Bodmer/TFT_eSPI#672 and it worked
but this library does not work with ESP32-S3

1 reply

moononournation Mar 15, 2023
Maintainer

8bit or 16bit?

chmilw · 2023-03-15T11:56:37Z

chmilw
Mar 15, 2023
Author

8bit

0 replies

chmilw · 2023-03-15T12:00:09Z

chmilw
Mar 15, 2023
Author

I found the initialization of OTM8009 and tried to compare with HT35510 from your library and they do not match
//3.97inch OTM8009 Init
TFT_Send_Cmd(0xff00);
TFT_Write_Data(0x80);
TFT_Send_Cmd(0xff01);
TFT_Write_Data(0x09);
TFT_Send_Cmd(0xff02);
TFT_Write_Data(0x01);

TFT_Send_Cmd(0xff80);
TFT_Write_Data(0x80);
TFT_Send_Cmd(0xff81);
TFT_Write_Data(0x09);

TFT_Send_Cmd(0xff03);
TFT_Write_Data(0x01);

TFT_Send_Cmd(0xf5b6); 
TFT_Write_Data(0x06); 
TFT_Send_Cmd(0xc480); 
TFT_Write_Data(0x30); 
TFT_Send_Cmd(0xc48a); 
TFT_Write_Data(0x40); 
//===================================================//
TFT_Send_Cmd(0xc0a3);
TFT_Write_Data(0x1B);

//TFT_Send_Cmd(0xc0ba);  
//TFT_Write_Data(0x50);

TFT_Send_Cmd(0xc0ba); 
TFT_Write_Data(0x50); 

TFT_Send_Cmd(0xc181);
TFT_Write_Data(0x66);

TFT_Send_Cmd(0xc1a1);
TFT_Write_Data(0x0E);

TFT_Send_Cmd(0xc481);
TFT_Write_Data(0x83);

TFT_Send_Cmd(0xc582);
TFT_Write_Data(0x83);

TFT_Send_Cmd(0xc590);
TFT_Write_Data(0x96);

TFT_Send_Cmd(0xc591);
TFT_Write_Data(0x2B);

TFT_Send_Cmd(0xc592);
TFT_Write_Data(0x01);


TFT_Send_Cmd(0xc594);
TFT_Write_Data(0x33);

TFT_Send_Cmd(0xc595);
TFT_Write_Data(0x34);


TFT_Send_Cmd(0xc5b1);
TFT_Write_Data(0xa9);

TFT_Send_Cmd(0xce80);
TFT_Write_Data(0x86);
TFT_Send_Cmd(0xce81);
TFT_Write_Data(0x01); 
TFT_Send_Cmd(0xce82);
TFT_Write_Data(0x00); 

TFT_Send_Cmd(0xce83);
TFT_Write_Data(0x85); 
TFT_Send_Cmd(0xce84);
TFT_Write_Data(0x01); 
TFT_Send_Cmd(0xce85);
TFT_Write_Data(0x00);
TFT_Send_Cmd(0xce86);
TFT_Write_Data(0x00);
TFT_Send_Cmd(0xce87);
TFT_Write_Data(0x00);
TFT_Send_Cmd(0xce88);
TFT_Write_Data(0x00);
TFT_Send_Cmd(0xce89);
TFT_Write_Data(0x00);
TFT_Send_Cmd(0xce8A);
TFT_Write_Data(0x00);
TFT_Send_Cmd(0xce8B);
TFT_Write_Data(0x00);

TFT_Send_Cmd(0xcea0);// cea1[7:0] : clka1_width[3:0], clka1_shift[11:8]                         
TFT_Write_Data(0x18); 
TFT_Send_Cmd(0xcea1);// cea2[7:0] : clka1_shift[7:0]                                            
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcea2);// cea3[7:0] : clka1_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]   
TFT_Write_Data(0x03); 
TFT_Send_Cmd(0xcea3);// cea4[7:0] : clka1_switch[7:0]                                               
TFT_Write_Data(0x21); 
TFT_Send_Cmd(0xcea4);// cea5[7:0] : clka1_extend[7:0]                                           
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcea5);// cea6[7:0] : clka1_tchop[7:0]                                            
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcea6);// cea7[7:0] : clka1_tglue[7:0]                                            
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcea7);// cea8[7:0] : clka2_width[3:0], clka2_shift[11:8]                         
TFT_Write_Data(0x18); 
TFT_Send_Cmd(0xcea8);// cea9[7:0] : clka2_shift[7:0]                                            
TFT_Write_Data(0x03);
TFT_Send_Cmd(0xcea9);// ceaa[7:0] : clka2_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]   
TFT_Write_Data(0x03); 
TFT_Send_Cmd(0xceaa);// ceab[7:0] : clka2_switch[7:0]                                                
TFT_Write_Data(0x22);
TFT_Send_Cmd(0xceab);// ceac[7:0] : clka2_extend                                                
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xceac);// cead[7:0] : clka2_tchop                                                 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcead);// ceae[7:0] : clka2_tglue 
TFT_Write_Data(0x00);    

TFT_Send_Cmd(0xceb0);// ceb1[7:0] : clka3_width[3:0], clka3_shift[11:8]                          
TFT_Write_Data(0x18);
TFT_Send_Cmd(0xceb1);// ceb2[7:0] : clka3_shift[7:0]                                             
TFT_Write_Data(0x02); 
TFT_Send_Cmd(0xceb2);// ceb3[7:0] : clka3_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]    
TFT_Write_Data(0x03); 
TFT_Send_Cmd(0xceb3);// ceb4[7:0] : clka3_switch[7:0]                                               
TFT_Write_Data(0x23); 
TFT_Send_Cmd(0xceb4);// ceb5[7:0] : clka3_extend[7:0]                                            
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xceb5);// ceb6[7:0] : clka3_tchop[7:0]                                             
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xceb6);// ceb7[7:0] : clka3_tglue[7:0]                                             
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xceb7);// ceb8[7:0] : clka4_width[3:0], clka2_shift[11:8]                          
TFT_Write_Data(0x18);
TFT_Send_Cmd(0xceb8);// ceb9[7:0] : clka4_shift[7:0]                                             
TFT_Write_Data(0x01); 
TFT_Send_Cmd(0xceb9);// ceba[7:0] : clka4_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]    
TFT_Write_Data(0x03); 
TFT_Send_Cmd(0xceba);// cebb[7:0] : clka4_switch[7:0]                                                
TFT_Write_Data(0x24); 
TFT_Send_Cmd(0xcebb);// cebc[7:0] : clka4_extend                                                 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcebc);// cebd[7:0] : clka4_tchop                                                  
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcebd);// cebe[7:0] : clka4_tglue                                                  
TFT_Write_Data(0x00); 


TFT_Send_Cmd(0xcfc0);// cfc1[7:0] : eclk_normal_width[7:0]   
TFT_Write_Data(0x01); 
TFT_Send_Cmd(0xcfc1);// cfc2[7:0] : eclk_partial_width[7:0]                                                                                  
TFT_Write_Data(0x01); 
TFT_Send_Cmd(0xcfc2);// cfc3[7:0] : all_normal_tchop[7:0]                                                                                    
TFT_Write_Data(0x20); 
TFT_Send_Cmd(0xcfc3);// cfc4[7:0] : all_partial_tchop[7:0]                                                                                   
TFT_Write_Data(0x20); 
TFT_Send_Cmd(0xcfc4);// cfc5[7:0] : eclk1_follow[3:0], eclk2_follow[3:0]                                                                     
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcfc5);// cfc6[7:0] : eclk3_follow[3:0], eclk4_follow[3:0]                                                                     
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcfc6);// cfc7[7:0] : 00, vstmask, vendmask, 00, dir1, dir2 (0=VGL, 1=VGH)                                                     
TFT_Write_Data(0x01); 
TFT_Send_Cmd(0xcfc7);// cfc8[7:0] : reg_goa_gnd_opt, reg_goa_dpgm_tail_set, reg_goa_f_gating_en, reg_goa_f_odd_gating, toggle_mod1, 2, 3, 4  
TFT_Write_Data(0x00);    // GND OPT1 (00-->80  2011/10/28)
TFT_Send_Cmd(0xcfc8);// cfc9[7:0] : duty_block[3:0], DGPM[3:0]                                                                               
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcfc9);// cfca[7:0] : reg_goa_gnd_period[7:0]                                                                                  
TFT_Write_Data(0x00);    // Gate PCH (CLK base) (00-->0a  2011/10/28)

TFT_Send_Cmd(0xcfd0);// cfd1[7:0] : 0000000, reg_goa_frame_odd_high
TFT_Write_Data(0x00); 

TFT_Send_Cmd(0xcbc0);//cbc1[7:0] : enmode H-byte of sig1  (pwrof_0, pwrof_1, norm, pwron_4 )           
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbc1);//cbc2[7:0] : enmode H-byte of sig2  (pwrof_0, pwrof_1, norm, pwron_4 )          
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbc2);//cbc3[7:0] : enmode H-byte of sig3  (pwrof_0, pwrof_1, norm, pwron_4 )           
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbc3);//cbc4[7:0] : enmode H-byte of sig4  (pwrof_0, pwrof_1, norm, pwron_4 )        
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbc4);//cbc5[7:0] : enmode H-byte of sig5  (pwrof_0, pwrof_1, norm, pwron_4 )             
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbc5);//cbc6[7:0] : enmode H-byte of sig6  (pwrof_0, pwrof_1, norm, pwron_4 )           
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbc6);//cbc7[7:0] : enmode H-byte of sig7  (pwrof_0, pwrof_1, norm, pwron_4 )           
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbc7);//cbc8[7:0] : enmode H-byte of sig8  (pwrof_0, pwrof_1, norm, pwron_4 )           
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbc8);//cbc9[7:0] : enmode H-byte of sig9  (pwrof_0, pwrof_1, norm, pwron_4 )           
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbc9);//cbca[7:0] : enmode H-byte of sig10 (pwrof_0, pwrof_1, norm, pwron_4 )        
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbca);//cbcb[7:0] : enmode H-byte of sig11 (pwrof_0, pwrof_1, norm, pwron_4 )        
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbcb);//cbcc[7:0] : enmode H-byte of sig12 (pwrof_0, pwrof_1, norm, pwron_4 )        
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbcc);//cbcd[7:0] : enmode H-byte of sig13 (pwrof_0, pwrof_1, norm, pwron_4 )        
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbcd);//cbce[7:0] : enmode H-byte of sig14 (pwrof_0, pwrof_1, norm, pwron_4 ) 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbce);//cbcf[7:0] : enmode H-byte of sig15 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 

TFT_Send_Cmd(0xcbd0);//cbd1[7:0] : enmode H-byte of sig16 (pwrof_0, pwrof_1, norm, pwron_4 )           
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbd1);//cbd2[7:0] : enmode H-byte of sig17 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbd2);//cbd3[7:0] : enmode H-byte of sig18 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbd3);//cbd4[7:0] : enmode H-byte of sig19 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbd4);//cbd5[7:0] : enmode H-byte of sig20 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbd5);//cbd6[7:0] : enmode H-byte of sig21 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbd6);//cbd7[7:0] : enmode H-byte of sig22 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbd7);//cbd8[7:0] : enmode H-byte of sig23 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbd8);//cbd9[7:0] : enmode H-byte of sig24 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbd9);//cbda[7:0] : enmode H-byte of sig25 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbda);//cbdb[7:0] : enmode H-byte of sig26 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x04); 
TFT_Send_Cmd(0xcbdb);//cbdc[7:0] : enmode H-byte of sig27 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbdc);//cbdd[7:0] : enmode H-byte of sig28 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbdd);//cbde[7:0] : enmode H-byte of sig29 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbde);//cbdf[7:0] : enmode H-byte of sig30 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 

TFT_Send_Cmd(0xcbe0);//cbe1[7:0] : enmode H-byte of sig31 (pwrof_0, pwrof_1, norm, pwron_4 )             
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbe1);//cbe2[7:0] : enmode H-byte of sig32 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbe2);//cbe3[7:0] : enmode H-byte of sig33 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbe3);//cbe4[7:0] : enmode H-byte of sig34 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbe4);//cbe5[7:0] : enmode H-byte of sig35 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbe5);//cbe6[7:0] : enmode H-byte of sig36 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbe6);//cbe7[7:0] : enmode H-byte of sig37 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbe7);//cbe8[7:0] : enmode H-byte of sig38 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbe8);//cbe9[7:0] : enmode H-byte of sig39 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcbe9);//cbea[7:0] : enmode H-byte of sig40 (pwrof_0, pwrof_1, norm, pwron_4 )
TFT_Write_Data(0x00);

// cc8x   
TFT_Send_Cmd(0xcc80);//cc81[7:0] : reg setting for signal01 selection with u2d mode   
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc81);//cc82[7:0] : reg setting for signal02 selection with u2d mode 
TFT_Write_Data(0x26); 
TFT_Send_Cmd(0xcc82);//cc83[7:0] : reg setting for signal03 selection with u2d mode 
TFT_Write_Data(0x09); 
TFT_Send_Cmd(0xcc83);//cc84[7:0] : reg setting for signal04 selection with u2d mode 
TFT_Write_Data(0x0B); 
TFT_Send_Cmd(0xcc84);//cc85[7:0] : reg setting for signal05 selection with u2d mode 
TFT_Write_Data(0x01); 
TFT_Send_Cmd(0xcc85);//cc86[7:0] : reg setting for signal06 selection with u2d mode 
TFT_Write_Data(0x25); 
TFT_Send_Cmd(0xcc86);//cc87[7:0] : reg setting for signal07 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc87);//cc88[7:0] : reg setting for signal08 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc88);//cc89[7:0] : reg setting for signal09 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc89);//cc8a[7:0] : reg setting for signal10 selection with u2d mode 
TFT_Write_Data(0x00);  

// cc9x   
TFT_Send_Cmd(0xcc90);//cc91[7:0] : reg setting for signal11 selection with u2d mode   
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc91);//cc92[7:0] : reg setting for signal12 selection with u2d mode
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc92);//cc93[7:0] : reg setting for signal13 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc93);//cc94[7:0] : reg setting for signal14 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc94);//cc95[7:0] : reg setting for signal15 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc95);//cc96[7:0] : reg setting for signal16 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc96);//cc97[7:0] : reg setting for signal17 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc97);//cc98[7:0] : reg setting for signal18 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc98);//cc99[7:0] : reg setting for signal19 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc99);//cc9a[7:0] : reg setting for signal20 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc9a);//cc9b[7:0] : reg setting for signal21 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcc9b);//cc9c[7:0] : reg setting for signal22 selection with u2d mode 
TFT_Write_Data(0x26); 
TFT_Send_Cmd(0xcc9c);//cc9d[7:0] : reg setting for signal23 selection with u2d mode 
TFT_Write_Data(0x0A); 
TFT_Send_Cmd(0xcc9d);//cc9e[7:0] : reg setting for signal24 selection with u2d mode 
TFT_Write_Data(0x0C); 
TFT_Send_Cmd(0xcc9e);//cc9f[7:0] : reg setting for signal25 selection with u2d mode 
TFT_Write_Data(0x02);  
// ccax   
TFT_Send_Cmd(0xcca0);//cca1[7:0] : reg setting for signal26 selection with u2d mode   
TFT_Write_Data(0x25); 
TFT_Send_Cmd(0xcca1);//cca2[7:0] : reg setting for signal27 selection with u2d mode
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcca2);//cca3[7:0] : reg setting for signal28 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcca3);//cca4[7:0] : reg setting for signal29 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcca4);//cca5[7:0] : reg setting for signal20 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcca5);//cca6[7:0] : reg setting for signal31 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcca6);//cca7[7:0] : reg setting for signal32 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcca7);//cca8[7:0] : reg setting for signal33 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcca8);//cca9[7:0] : reg setting for signal34 selection with u2d mode 
TFT_Write_Data(0x00); 
TFT_Send_Cmd(0xcca9);//ccaa[7:0] : reg setting for signal35 selection with u2d mode 
TFT_Write_Data(0x00); 

    TFT_Send_Cmd(0x3A00);//ccaa[7:0] : reg setting for signal35 selection with u2d mode 
TFT_Write_Data(0x55);//0x55
	
TFT_Send_Cmd(0x1100);
delay_ms(100);
TFT_Send_Cmd(0x2900);
delay_ms(50);
TFT_Send_Cmd(0x2C00); 

TFT_Send_Cmd(0x3600);//выбираем ориентацию дисплея и порядок цветов BGR
TFT_Write_Data((1<<3)|(1<<5)|(1<<6));

delay_ms(100);	
TFT_Clear(GREEN);

}

1 reply

moononournation Mar 15, 2023
Maintainer

I do not have this display in hand, but welcome for your contribution. Make a pull request after your testing.

chmilw · 2023-03-15T12:44:13Z

chmilw
Mar 15, 2023
Author

I compared the initialization process found on the Internet with the library https://github.com/Mike120Git/TFT_eSPI they match
tell me where in the Arduino_NT35510.cpp file to insert the initialization process

If I understand correctly, then you need to replace this block
//************* NT35510**********//
_bus->beginWrite();
uint8_t ini01[] = {0x55, 0xAA, 0x52, 0x08, 0x01};
WriteRegM(0xF000, sizeof(ini01), ini01);
uint8_t ini03[] = {0x34, 0x34, 0x34};
WriteRegM(0xB600, sizeof(ini03), ini03);
uint8_t ini02[] = {0x0D, 0x0D, 0x0D};
WriteRegM(0xB000, sizeof(ini02), ini02); // AVDD Set AVDD 5.2V
uint8_t ini05[] = {0x34, 0x34, 0x34};
WriteRegM(0xB700, sizeof(ini05), ini05); // AVEE ratio
uint8_t ini04[] = {0x0D, 0x0D, 0x0D};
WriteRegM(0xB100, sizeof(ini04), ini04); // AVEE -5.2V
uint8_t ini07[] = {0x24, 0x24, 0x24};
WriteRegM(0xB800, sizeof(ini07), ini07); // VCL ratio
uint8_t ini10[] = {0x34, 0x34, 0x34};
WriteRegM(0xB900, sizeof(ini10), ini10); // VGH ratio
uint8_t ini09[] = {0x0F, 0x0F, 0x0F};
WriteRegM(0xB300, sizeof(ini09), ini09);
uint8_t ini14[] = {0x24, 0x24, 0x24};
WriteRegM(0xBA00, sizeof(ini14), ini14); // VGLX ratio
uint8_t ini12[] = {0x08, 0x08};
WriteRegM(0xB500, sizeof(ini12), ini12);
uint8_t ini15[] = {0x00, 0x78, 0x00};
WriteRegM(0xBC00, sizeof(ini15), ini15); // VGMP/VGSP 4.5V/0V
uint8_t ini16[] = {0x00, 0x78, 0x00};
WriteRegM(0xBD00, sizeof(ini16), ini16); // VGMN/VGSN -4.5V/0V
uint8_t ini17[] = {0x00, 0x89};
WriteRegM(0xBE00, sizeof(ini17), ini17); // VCOM -1.325V
// Gamma Setting
uint8_t ini20[] = {
0x00, 0x2D, 0x00, 0x2E, 0x00, 0x32, 0x00, 0x44, 0x00, 0x53, 0x00, 0x88, 0x00, 0xB6, 0x00, 0xF3, 0x01, 0x22, 0x01, 0x64,
0x01, 0x92, 0x01, 0xD4, 0x02, 0x07, 0x02, 0x08, 0x02, 0x34, 0x02, 0x5F, 0x02, 0x78, 0x02, 0x94, 0x02, 0xA6, 0x02, 0xBB,
0x02, 0xCA, 0x02, 0xDB, 0x02, 0xE8, 0x02, 0xF9, 0x03, 0x1F, 0x03, 0x7F};
WriteRegM(0xD100, sizeof(ini20), ini20);
WriteRegM(0xD400, sizeof(ini20), ini20); // R+ R-
WriteRegM(0xD200, sizeof(ini20), ini20);
WriteRegM(0xD500, sizeof(ini20), ini20); // G+ G-
WriteRegM(0xD300, sizeof(ini20), ini20);
WriteRegM(0xD600, sizeof(ini20), ini20); // B+ B-
//
uint8_t ini21[] = {0x55, 0xAA, 0x52, 0x08, 0x00};
WriteRegM(0xF000, sizeof(ini21), ini21); // #Enable Page0
uint8_t ini22[] = {0x08, 0x05, 0x02, 0x05, 0x02};
WriteRegM(0xB000, sizeof(ini22), ini22); // # RGB I/F Setting
_bus->writeCommand16(0xB600);
_bus->write16(0x08);
_bus->writeCommand16(0xB500);
_bus->write16(0x50); // ## SDT: //0x6b ?? 480x854 0x50 ?? 480x800
uint8_t ini24[] = {0x00, 0x00};
WriteRegM(0xB700, sizeof(ini24), ini24); // ## Gate EQ:
uint8_t ini25[] = {0x01, 0x05, 0x05, 0x05};
WriteRegM(0xB800, sizeof(ini25), ini25); // ## Source EQ:
uint8_t ini26[] = {0x00, 0x00, 0x00};
WriteRegM(0xBC00, sizeof(ini26), ini26); // # Inversion: Column inversion (NVT)
uint8_t ini27[] = {0x03, 0x00, 0x00};
WriteRegM(0xCC00, sizeof(ini27), ini27); // # BOE's Setting(default)
uint8_t ini28[] = {0x01, 0x84, 0x07, 0x31, 0x00, 0x01};
WriteRegM(0xBD00, sizeof(ini28), ini28); // # Display Timing:
//
uint8_t ini30[] = {0xAA, 0x55, 0x25, 0x01};
WriteRegM(0xFF00, sizeof(ini30), ini30);
_bus->writeCommand16(NT35510_TEON);
_bus->write16(0x00);
_bus->writeCommand16(NT35510_COLMOD);
_bus->write16(0x55); // 0x55=16bit Mode
_bus->writeCommand16(NT35510_SLPOUT);
_bus->endWrite();

0 replies

chmilw · 2023-03-15T17:51:14Z

chmilw
Mar 15, 2023
Author

earned

0 replies

chmilw · 2023-03-17T04:31:47Z

chmilw
Mar 17, 2023
Author

If you are interested I can send files

1 reply

moononournation Mar 17, 2023
Maintainer

simply submit a pull request

chmilw · 2023-03-17T05:14:17Z

chmilw
Mar 17, 2023
Author

tell me how

0 replies

Provide feedback

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OTM8009A SKU:MRB3971 800*480 display support #269

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