diff --git a/Documentation/devicetree/bindings/media/qcom,msm8939-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8939-camss.yaml new file mode 100644 index 00000000000000..e300b2c84971a4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,msm8939-camss.yaml @@ -0,0 +1,269 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,msm8939-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8939 Camera Subsystem (CAMSS) + +maintainers: + - Vincent Knecht + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms + +properties: + compatible: + const: qcom,msm8939-camss + + clocks: + minItems: 24 + maxItems: 24 + + clock-names: + items: + - const: top_ahb + - const: ispif_ahb + - const: csiphy0_timer + - const: csiphy1_timer + - const: csi0_ahb + - const: csi0 + - const: csi0_phy + - const: csi0_pix + - const: csi0_rdi + - const: csi1_ahb + - const: csi1 + - const: csi1_phy + - const: csi1_pix + - const: csi1_rdi + - const: csi2_ahb + - const: csi2 + - const: csi2_phy + - const: csi2_pix + - const: csi2_rdi + - const: ahb + - const: vfe0 + - const: csi_vfe0 + - const: vfe_ahb + - const: vfe_axi + + interrupts: + minItems: 7 + maxItems: 7 + + interrupt-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csid0 + - const: csid1 + - const: csid2 + - const: ispif + - const: vfe0 + + iommus: + maxItems: 1 + + power-domains: + items: + - description: VFE GDSC - Video Front End, Global Distributed Switch Controller. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + + reg: + minItems: 11 + maxItems: 11 + + reg-names: + items: + - const: csiphy0 + - const: csiphy0_clk_mux + - const: csiphy1 + - const: csiphy1_clk_mux + - const: csid0 + - const: csid1 + - const: csid2 + - const: ispif + - const: csi_clk_mux + - const: vfe0 + - const: vfe0_vbif + + vdda-supply: + description: + Definition of the regulator used as analog power supply. + +required: + - clock-names + - clocks + - compatible + - interrupt-names + - interrupts + - iommus + - power-domains + - reg + - reg-names + - vdda-supply + +additionalProperties: false + +examples: + - | + #include + #include + + camss: camss@1b0ac00 { + compatible = "qcom,msm8939-camss"; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2PHY_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>; + + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe_ahb", + "vfe_axi"; + + interrupts = , + , + , + , + , + , + ; + + interrupt-names = "csiphy0", + "csiphy1", + "csid0", + "csid1", + "csid2", + "ispif", + "vfe0"; + + iommus = <&apps_iommu 3>; + + power-domains = <&gcc VFE_GDSC>; + + reg = <0x01b0ac00 0x200>, + <0x01b00030 0x4>, + <0x01b0b000 0x200>, + <0x01b00038 0x4>, + <0x01b08000 0x100>, + <0x01b08400 0x100>, + <0x01b08800 0x100>, + <0x01b0a000 0x500>, + <0x01b00020 0x10>, + <0x01b10000 0x1000>, + <0x01b40000 0x200>; + + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csid0", + "csid1", + "csid2", + "ispif", + "csi_clk_mux", + "vfe0", + "vfe0_vbif"; + + vdda-supply = <®_2v8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + + }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts index 17d59345a00933..06153b40c17685 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -44,6 +45,37 @@ }; }; + cam_vdig_front_vreg: cam-vdig-front-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_vdig_front_vreg"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&s5k5e2_vdig_default>; + pinctrl-names = "default"; + regulator-always-on; + }; + + cam_vana_rear_vreg: cam-vana-rear-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_vana_rear_vreg"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&imx214_vana_default>; + pinctrl-names = "default"; + }; + + cam_vdig_rear_vreg: cam-vdig-rear-regulator { + compatible = "regulator-fixed"; + regulator-name = "cam_vdig_rear_vreg"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&imx214_vdig_default>; + pinctrl-names = "default"; + }; + gpio-keys { compatible = "gpio-keys"; @@ -120,6 +152,15 @@ pinctrl-names = "default"; }; + fake-reg-mclk1 { + compatible = "regulator-fixed-clock"; + regulator-name = "mclk1-force-on"; + pinctrl-names = "default"; + pinctrl-0 = <&camera_front_default>; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + regulator-always-on; + }; + }; &blsp_i2c2 { @@ -302,6 +343,56 @@ status = "okay"; }; +&camss { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csiphy0_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2 3 4>; + remote-endpoint = <&imx214_ep>; + }; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c0 { + camera-rear@10 { + compatible = "sony,imx214"; + reg = <0x10>; + + vdda-supply = <&cam_vana_rear_vreg>; + vddd-supply = <&cam_vdig_rear_vreg>; + vdddo-supply = <&pm8916_l6>; + + enable-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; + + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + assigned-clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + assigned-clock-rates = <24000000>; + + pinctrl-0 = <&camera_rear_default>; + pinctrl-names = "default"; + + orientation = <1>; + rotation = <270>; + + port { + imx214_ep: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <600000000>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; + &gpu { status = "okay"; }; @@ -464,6 +555,22 @@ bias-pull-up; }; + imx214_vana_default: imx214-vana-default-state { + pins = "gpio34"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + imx214_vdig_default: imx214-vdig-default-state { + pins = "gpio31"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + lcd_bl_en_default: lcd-bl-en-default-state { pins = "gpio98"; function = "gpio"; @@ -499,6 +606,22 @@ bias-pull-down; }; +/* s5k5e2_vana_default: s5k5e2-vana-default-state { + pins = "gpio34"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; */ + + s5k5e2_vdig_default: s5k5e2-vdig-default-state { + pins = "gpio32"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + sdc2_cd_default: sdc2-cd-default-state { pins = "gpio38"; function = "gpio"; @@ -541,3 +664,25 @@ output-high; }; }; + +&camera_front_default { + /delete-node/ rst-pins; + + rst-pins { + pins = "gpio100"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&camera_rear_default { + /delete-node/ pwdn-pins; + + pwdn-pins { + pins = "gpio101"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi index adb96cd8d643e5..659d127b1bc357 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -11,6 +11,10 @@ #include "msm8939.dtsi" #include "pm8916.dtsi" +&camss { + vdda-supply = <&pm8916_l2>; +}; + &mdss_dsi0 { vdda-supply = <&pm8916_l2>; vddio-supply = <&pm8916_l6>; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 20f6ba181f123a..53bd2fe039d36e 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1462,6 +1462,151 @@ }; }; + camss: camss@1b0ac00 { + compatible = "qcom,msm8939-camss"; + reg = <0x01b0ac00 0x200>, + <0x01b00030 0x4>, + <0x01b0b000 0x200>, + <0x01b00038 0x4>, + <0x01b08000 0x100>, + <0x01b08400 0x100>, + <0x01b08800 0x100>, + <0x01b0a000 0x500>, + <0x01b00020 0x10>, + <0x01b10000 0x1000>, + <0x01b40000 0x200>; + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csid0", + "csid1", + "csid2", + "ispif", + "csi_clk_mux", + "vfe0", + "vfe0_vbif"; + + interrupts = , + , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csid0", + "csid1", + "csid2", + "ispif", + "vfe0"; + + power-domains = <&gcc VFE_GDSC>; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2PHY_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>; + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe_ahb", + "vfe_axi"; + + iommus = <&apps_iommu 3>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + cci: cci@1b0c000 { + compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x01b0c000 0x1000>; + interrupts = ; + + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "ispif_ahb", + "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + + assigned-clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, + <19200000>; + + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: gpu@1c00000 { compatible = "qcom,adreno-405.0", "qcom,adreno"; reg = <0x01c00000 0x10000>; @@ -1526,6 +1671,13 @@ #iommu-cells = <1>; qcom,iommu-secure-id = <17>; + /* vfe */ + iommu-ctx@3000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + /* mdp_0: */ iommu-ctx@4000 { compatible = "qcom,msm-iommu-v1-ns"; diff --git a/arch/arm64/configs/msm8916_defconfig b/arch/arm64/configs/msm8916_defconfig index 77f4d31ebc3b73..26687213931047 100644 --- a/arch/arm64/configs/msm8916_defconfig +++ b/arch/arm64/configs/msm8916_defconfig @@ -274,8 +274,10 @@ CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L2_FLASH_LED_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CCS=m CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_VIDEO_IMX214=m CONFIG_DRM=y CONFIG_DRM_MSM=m # CONFIG_DRM_MSM_MDP4 is not set diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 08db8abeea2180..82de1a4d5091eb 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -707,6 +707,12 @@ config VIDEO_S5K5BAF This is a V4L2 sensor driver for Samsung S5K5BAF 2M camera sensor with an embedded SoC image signal processor. +config VIDEO_S5K5E2 + tristate "Samsung S5K5E2 sensor support" + help + This is a V4L2 sensor driver for Samsung S5K5E2 5M + camera sensor with an embedded SoC image signal processor. (TODO) + config VIDEO_S5K6A3 tristate "Samsung S5K6A3 sensor support" help diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 5873d29433ee5e..eb6c9fdd8d3761 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -122,6 +122,7 @@ obj-$(CONFIG_VIDEO_RDACM21) += rdacm21.o obj-$(CONFIG_VIDEO_RJ54N1) += rj54n1cb0c.o obj-$(CONFIG_VIDEO_S5C73M3) += s5c73m3/ obj-$(CONFIG_VIDEO_S5K5BAF) += s5k5baf.o +obj-$(CONFIG_VIDEO_S5K5E2) += s5k5e2.o obj-$(CONFIG_VIDEO_S5K6A3) += s5k6a3.o obj-$(CONFIG_VIDEO_SAA6588) += saa6588.o obj-$(CONFIG_VIDEO_SAA6752HS) += saa6752hs.o diff --git a/drivers/media/i2c/s5k5e2.c b/drivers/media/i2c/s5k5e2.c new file mode 100644 index 00000000000000..25ecbff3978fe1 --- /dev/null +++ b/drivers/media/i2c/s5k5e2.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include + +#include + +static const char * const s5k5e2_supply_name[] = { + "vdda", + "vddd", + "vdddo", +}; + +#define S5K5E2_NUM_SUPPLIES ARRAY_SIZE(s5k5e2_supply_name) + +struct s5k5e2 { + struct device *dev; + struct clk *xclk; + struct regmap *regmap; + + /* struct ccs_pll pll; */ + + /* struct v4l2_fwnode_endpoint bus_cfg; */ + + /* struct v4l2_subdev sd; */ + /* struct media_pad pad; */ + + /* struct v4l2_ctrl_handler ctrls; */ + /* struct v4l2_ctrl *pixel_rate; */ + /* struct v4l2_ctrl *link_freq; */ + /* struct v4l2_ctrl *vblank; */ + /* struct v4l2_ctrl *hblank; */ + /* struct v4l2_ctrl *exposure; */ + /* struct v4l2_ctrl *unit_size; */ + /* struct { */ + /* struct v4l2_ctrl *hflip; */ + /* struct v4l2_ctrl *vflip; */ + /* }; */ + + struct regulator_bulk_data supplies[S5K5E2_NUM_SUPPLIES]; + + struct gpio_desc *enable_gpio; +}; + +static int s5k5e2_get_regulators(struct device *dev, struct s5k5e2 *s5k5e2) +{ + unsigned int i; + + for (i = 0; i < S5K5E2_NUM_SUPPLIES; i++) + s5k5e2->supplies[i].supply = s5k5e2_supply_name[i]; + + return devm_regulator_bulk_get(dev, S5K5E2_NUM_SUPPLIES, + s5k5e2->supplies); +} + +static int __maybe_unused s5k5e2_power_on(struct s5k5e2 *s5k5e2) +{ + int ret; + + ret = regulator_bulk_enable(S5K5E2_NUM_SUPPLIES, s5k5e2->supplies); + if (ret < 0) { + dev_err(s5k5e2->dev, "failed to enable regulators: %d\n", ret); + return ret; + } + + usleep_range(2000, 3000); // TODO verify + + ret = clk_prepare_enable(s5k5e2->xclk); + if (ret < 0) { + regulator_bulk_disable(S5K5E2_NUM_SUPPLIES, s5k5e2->supplies); + dev_err(s5k5e2->dev, "clk prepare enable failed\n"); + return ret; + } + + gpiod_set_value_cansleep(s5k5e2->enable_gpio, 1); + usleep_range(12000, 15000); // TODO verify + + return 0; +} + +static int s5k5e2_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct s5k5e2 *s5k5e2; + int ret; + + s5k5e2 = devm_kzalloc(dev, sizeof(*s5k5e2), GFP_KERNEL); + if (!s5k5e2) + return -ENOMEM; + + s5k5e2->dev = dev; + + s5k5e2->xclk = devm_clk_get(dev, NULL); + if (IS_ERR(s5k5e2->xclk)) + return dev_err_probe(dev, PTR_ERR(s5k5e2->xclk), + "failed to get xclk\n"); + + ret = s5k5e2_get_regulators(dev, s5k5e2); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get regulators\n"); + + s5k5e2->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(s5k5e2->enable_gpio)) + return dev_err_probe(dev, PTR_ERR(s5k5e2->enable_gpio), + "failed to get enable gpio\n"); + + ret = s5k5e2_power_on(s5k5e2); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to power on\n"); + + // TODO read and enable power supply + // dump i2c registers + + return 0; + + +/* s5k5baf_hw_init(state);*/ +/* ret = s5k5baf_check_fw_revision(state);*/ + +/* s5k5baf_power_off(state);*/ +/* if (ret < 0)*/ +/* goto err_me;*/ + +/* ret = s5k5baf_initialize_ctrls(state);*/ +/* if (ret < 0)*/ +/* goto err_me;*/ + +/* ret = v4l2_async_register_subdev(&state->sd);*/ +/* if (ret < 0)*/ +/* goto err_ctrl;*/ + +/* return 0;*/ + +/*err_ctrl:*/ +/* v4l2_ctrl_handler_free(state->sd.ctrl_handler);*/ +/*err_me:*/ +/* media_entity_cleanup(&state->sd.entity);*/ +/* media_entity_cleanup(&state->cis_sd.entity);*/ +/* return ret;*/ +} + +static void s5k5e2_remove(struct i2c_client *c) +{ +/* struct v4l2_subdev *sd = i2c_get_clientdata(c);*/ +/* struct s5k5baf *state = to_s5k5baf(sd);*/ + +/* v4l2_async_unregister_subdev(sd);*/ +/* v4l2_ctrl_handler_free(sd->ctrl_handler);*/ +/* media_entity_cleanup(&sd->entity);*/ + +/* sd = &state->cis_sd;*/ +/* v4l2_device_unregister_subdev(sd);*/ +/* media_entity_cleanup(&sd->entity);*/ +} + +static const struct i2c_device_id s5k5e2_id[] = { + { "s5k5e2" }, + { } +}; +MODULE_DEVICE_TABLE(i2c, s5k5e2_id); + +static const struct of_device_id s5k5e2_of_match[] = { + { .compatible = "samsung,s5k5e2" }, + { } +}; +MODULE_DEVICE_TABLE(of, s5k5e2_of_match); + +static struct i2c_driver s5k5e2_i2c_driver = { + .driver = { + .of_match_table = s5k5e2_of_match, + .name = "s5k5e2" + }, + .probe = s5k5e2_probe, + .remove = s5k5e2_remove, + .id_table = s5k5e2_id, +}; + +module_i2c_driver(s5k5e2_i2c_driver); + +MODULE_DESCRIPTION("Samsung S5K5E2 camera driver"); +MODULE_AUTHOR("AndrĂ© Apitzsch"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index d26a9c24a430a8..4c66d29ae505ae 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -21,6 +21,7 @@ qcom-camss-objs += \ camss-vfe-680.o \ camss-vfe-780.o \ camss-vfe-gen1.o \ + camss-vfe-vbif.o \ camss-vfe.o \ camss-video.o \ camss-format.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index c622efcc92ff37..6311fc2975aa13 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -605,6 +605,7 @@ int msm_csiphy_subdev_init(struct camss *camss, return PTR_ERR(csiphy->base); if (camss->res->version == CAMSS_8x16 || + camss->res->version == CAMSS_8x39 || camss->res->version == CAMSS_8x53 || camss->res->version == CAMSS_8x96) { csiphy->base_clk_mux = diff --git a/drivers/media/platform/qcom/camss/camss-ispif.c b/drivers/media/platform/qcom/camss/camss-ispif.c index 2dc585c6123dd2..aaf3caa42d33dc 100644 --- a/drivers/media/platform/qcom/camss/camss-ispif.c +++ b/drivers/media/platform/qcom/camss/camss-ispif.c @@ -1112,6 +1112,8 @@ int msm_ispif_subdev_init(struct camss *camss, /* Number of ISPIF lines - same as number of CSID hardware modules */ if (camss->res->version == CAMSS_8x16) ispif->line_num = 2; + else if (camss->res->version == CAMSS_8x39) + ispif->line_num = 3; else if (camss->res->version == CAMSS_8x96 || camss->res->version == CAMSS_8x53 || camss->res->version == CAMSS_660) @@ -1128,7 +1130,8 @@ int msm_ispif_subdev_init(struct camss *camss, ispif->line[i].ispif = ispif; ispif->line[i].id = i; - if (camss->res->version == CAMSS_8x16) { + if (camss->res->version == CAMSS_8x16 || + camss->res->version == CAMSS_8x39) { ispif->line[i].formats = ispif_formats_8x16; ispif->line[i].nformats = ARRAY_SIZE(ispif_formats_8x16); @@ -1162,7 +1165,8 @@ int msm_ispif_subdev_init(struct camss *camss, ispif->irq = ret; snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s", dev_name(dev), MSM_ISPIF_NAME); - if (camss->res->version == CAMSS_8x16) + if (camss->res->version == CAMSS_8x16 || + camss->res->version == CAMSS_8x39) ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16, IRQF_TRIGGER_RISING, ispif->irq_name, ispif); else if (camss->res->version == CAMSS_8x96 || diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-1.c b/drivers/media/platform/qcom/camss/camss-vfe-4-1.c index 901677293d971c..520bc16f2a05e3 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-4-1.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-4-1.c @@ -15,6 +15,7 @@ #include "camss.h" #include "camss-vfe.h" #include "camss-vfe-gen1.h" +#include "camss-vfe-vbif.h" #define VFE_0_HW_VERSION 0x000 @@ -733,6 +734,7 @@ static void vfe_set_qos(struct vfe_device *vfe) { u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; + int ret; writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); @@ -742,6 +744,15 @@ static void vfe_set_qos(struct vfe_device *vfe) writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); + + /* SoC-specific VBIF settings */ + if (vfe->res->has_vbif) { + ret = vfe_vbif_apply_settings(vfe); + if (ret < 0) + dev_err_ratelimited(vfe->camss->dev, + "VFE: VBIF error %d\n", + ret); + } } static void vfe_set_ds(struct vfe_device *vfe) diff --git a/drivers/media/platform/qcom/camss/camss-vfe-vbif.c b/drivers/media/platform/qcom/camss/camss-vfe-vbif.c new file mode 100644 index 00000000000000..d461880e5379c2 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-vbif.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * camss-vfe-vbif.c + * + * Qualcomm MSM Camera Subsystem - VFE VBIF Module + * + * Copyright (c) 2025, The Linux Foundation. All rights reserved. + * + */ + +#include + +#include "camss.h" +#include "camss-vfe.h" +#include "camss-vfe-vbif.h" + +#define VBIF_FIXED_SORT_EN 0x30 +#define VBIF_FIXED_SORT_SEL0 0x34 + +void vfe_vbif_reg_write(struct vfe_device *vfe, u32 reg, u32 val) +{ + writel_relaxed(val, vfe->vbif_base + reg); +} + +int vfe_vbif_apply_settings(struct vfe_device *vfe) +{ + switch (vfe->camss->res->version) { + case CAMSS_8x39: + vfe_vbif_reg_write(vfe, VBIF_FIXED_SORT_EN, 0xfff); + vfe_vbif_reg_write(vfe, VBIF_FIXED_SORT_SEL0, 0x555000); + break; + default: + break; + } + + return 0; +} diff --git a/drivers/media/platform/qcom/camss/camss-vfe-vbif.h b/drivers/media/platform/qcom/camss/camss-vfe-vbif.h new file mode 100644 index 00000000000000..cef1e17dba1f23 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-vbif.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * camss-vfe-vbif.h + * + * Qualcomm MSM Camera Subsystem - VFE VBIF Module + * + * Copyright (c) 2025, The Linux Foundation. All rights reserved. + * + */ +#ifndef QC_MSM_CAMSS_VFE_VBIF_H +#define QC_MSM_CAMSS_VFE_VBIF_H + +#include "camss-vfe.h" + +void vfe_vbif_reg_write(struct vfe_device *vfe, u32 reg, u32 val); + +int vfe_vbif_apply_settings(struct vfe_device *vfe); + +#endif /* QC_MSM_CAMSS_VFE_VBIF_H */ diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 4bca6c3abaff9b..389f89c804e4d3 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -290,6 +290,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, switch (vfe->camss->res->version) { case CAMSS_8x16: + case CAMSS_8x39: case CAMSS_8x53: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: @@ -1807,6 +1808,15 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, return PTR_ERR(vfe->base); } + if (vfe->res->has_vbif) { + vfe->vbif_base = devm_platform_ioremap_resource_byname( + pdev, vfe->res->vbif_name); + if (IS_ERR(vfe->vbif_base)) { + dev_err(dev, "could not map vbif memory\n"); + return PTR_ERR(vfe->vbif_base); + } + } + /* Interrupt */ ret = platform_get_irq_byname(pdev, res->interrupt[0]); diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h index a23f666be7531e..614e932c33da78 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -136,6 +136,8 @@ struct vfe_subdev_resources { u8 line_num; bool has_pd; char *pd_name; + bool has_vbif; + char *vbif_name; const struct vfe_hw_ops *hw_ops; const struct camss_formats *formats_rdi; const struct camss_formats *formats_pix; @@ -145,6 +147,7 @@ struct vfe_device { struct camss *camss; u8 id; void __iomem *base; + void __iomem *vbif_base; u32 irq; char irq_name[30]; struct camss_clock *clock; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 06f42875702f02..6dee9360689b99 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -154,6 +154,149 @@ static const struct camss_subdev_resources vfe_res_8x16[] = { } }; +static const struct camss_subdev_resources csiphy_res_8x39[] = { + /* CSIPHY0 */ + { + .regulators = {}, + .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, + .clock_rate = { { 0 }, + { 40000000, 80000000 }, + { 0 }, + { 100000000, 200000000 } }, + .reg = { "csiphy0", "csiphy0_clk_mux" }, + .interrupt = { "csiphy0" }, + .csiphy = { + .id = 0, + .hw_ops = &csiphy_ops_2ph_1_0, + .formats = &csiphy_formats_8x16 + } + }, + + /* CSIPHY1 */ + { + .regulators = {}, + .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, + .clock_rate = { { 0 }, + { 40000000, 80000000 }, + { 0 }, + { 100000000, 200000000 } }, + .reg = { "csiphy1", "csiphy1_clk_mux" }, + .interrupt = { "csiphy1" }, + .csiphy = { + .id = 1, + .hw_ops = &csiphy_ops_2ph_1_0, + .formats = &csiphy_formats_8x16 + } + } +}; + +static const struct camss_subdev_resources csid_res_8x39[] = { + /* CSID0 */ + { + .regulators = { "vdda" }, + .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", + "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, + .clock_rate = { { 0 }, + { 40000000, 80000000 }, + { 0 }, + { 0 }, + { 100000000, 200000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .csid = { + .hw_ops = &csid_ops_4_1, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_4_1 + } + }, + + /* CSID1 */ + { + .regulators = { "vdda" }, + .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", + "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, + .clock_rate = { { 0 }, + { 40000000, 80000000 }, + { 0 }, + { 0 }, + { 100000000, 200000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .csid = { + .hw_ops = &csid_ops_4_1, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_4_1 + } + }, + + /* CSID2 */ + { + .regulators = { "vdda" }, + .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", + "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" }, + .clock_rate = { { 0 }, + { 40000000, 80000000 }, + { 0 }, + { 0 }, + { 100000000, 200000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .csid = { + .hw_ops = &csid_ops_4_1, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_4_1 + } + }, +}; + +static const struct camss_subdev_resources ispif_res_8x39 = { + /* ISPIF */ + .clock = { "top_ahb", "ispif_ahb", "ahb", + "csi0", "csi0_pix", "csi0_rdi", + "csi1", "csi1_pix", "csi1_rdi", + "csi2", "csi2_pix", "csi2_rdi" }, + .clock_for_reset = { "vfe0", "csi_vfe0" }, + .reg = { "ispif", "csi_clk_mux" }, + .interrupt = { "ispif" }, +}; + +static const struct camss_subdev_resources vfe_res_8x39[] = { + /* VFE0 */ + { + .regulators = {}, + .clock = { "top_ahb", "ispif_ahb", "vfe0", "csi_vfe0", + "vfe_ahb", "vfe_axi", "ahb" }, + .clock_rate = { { 0 }, + { 40000000, 80000000 }, + { 50000000, 80000000, 100000000, 160000000, + 177780000, 200000000, 266670000, 320000000, + 400000000, 465000000, 480000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .vfe = { + .line_num = 3, + .has_vbif = true, + .vbif_name = "vfe0_vbif", + .hw_ops = &vfe_ops_4_1, + .formats_rdi = &vfe_formats_rdi_8x16, + .formats_pix = &vfe_formats_pix_8x16 + } + } +}; + static const struct camss_subdev_resources csid_res_8x53[] = { /* CSID0 */ { @@ -3585,6 +3728,7 @@ static int camss_probe(struct platform_device *pdev) return -ENOMEM; if (camss->res->version == CAMSS_8x16 || + camss->res->version == CAMSS_8x39 || camss->res->version == CAMSS_8x53 || camss->res->version == CAMSS_8x96) { camss->ispif = devm_kcalloc(dev, 1, sizeof(*camss->ispif), GFP_KERNEL); @@ -3727,6 +3871,18 @@ static const struct camss_resources msm8916_resources = { .link_entities = camss_link_entities }; +static const struct camss_resources msm8939_resources = { + .version = CAMSS_8x39, + .csiphy_res = csiphy_res_8x39, + .csid_res = csid_res_8x39, + .ispif_res = &ispif_res_8x39, + .vfe_res = vfe_res_8x39, + .csiphy_num = ARRAY_SIZE(csiphy_res_8x39), + .csid_num = ARRAY_SIZE(csid_res_8x39), + .vfe_num = ARRAY_SIZE(vfe_res_8x39), + .link_entities = camss_link_entities +}; + static const struct camss_resources msm8953_resources = { .version = CAMSS_8x53, .icc_res = icc_res_8x53, @@ -3863,6 +4019,7 @@ static const struct camss_resources x1e80100_resources = { static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, + { .compatible = "qcom,msm8939-camss", .data = &msm8939_resources }, { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources }, { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 63c0afee154a02..be11cf3af47862 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -80,6 +80,7 @@ enum camss_version { CAMSS_660, CAMSS_7280, CAMSS_8x16, + CAMSS_8x39, CAMSS_8x53, CAMSS_8x96, CAMSS_8250,