diff --git a/data/int_group/mspm0l111x.yaml b/data/int_group/mspm0l111x.yaml new file mode 100644 index 0000000..e4b605f --- /dev/null +++ b/data/int_group/mspm0l111x.yaml @@ -0,0 +1,17 @@ +groups: + GROUP0: + - name: WWDT0 + iidx: 0 + - name: DEBUGSS + iidx: 2 + - name: FLASHCTL # NVMNW + iidx: 3 + - name: SYSCTL + iidx: 6 + GROUP1: + - name: GPIOA + iidx: 0 + - name: GPIOB + iidx: 1 + - name: TRNG + iidx: 5 diff --git a/data/parts.yaml b/data/parts.yaml index c8618ec..133cd76 100644 --- a/data/parts.yaml +++ b/data/parts.yaml @@ -532,6 +532,40 @@ families: - RHB - RTR +- family: mspm0l111x + datasheet_url: https://www.ti.com/lit/gpn/mspm0l1117 + reference_manual_url: https://www.ti.com/lit/pdf/slau847 + errata_url: https://www.ti.com/lit/pdf/slaz741 + adc_vrsel: VDD_INTREF_EXTREF + part_numbers: + - name: mspm0l1116 + memory: + - name: FLASH + length: 64 + address: 0x00000000 + - name: RAM + length: 16 + address: 0x20000000 + packages: + - PT + - RGZ + - RHB + - RGE + + - name: mspm0l1117 + memory: + - name: FLASH + length: 128 + address: 0x00000000 + - name: RAM + length: 16 + address: 0x20000000 + packages: + - PT + - RGZ + - RHB + - RGE + - family: mspm0l112x datasheet_url: https://www.ti.com/lit/gpn/mspm0l2117 reference_manual_url: https://www.ti.com/lit/pdf/slau847 diff --git a/data/registers/aes_v1.yaml b/data/registers/aes_v1.yaml new file mode 100644 index 0000000..4d4c03e --- /dev/null +++ b/data/registers/aes_v1.yaml @@ -0,0 +1,918 @@ +block/AES: + description: PERIPHERALREGION. + items: + - name: GPRCM + array: + len: 1 + stride: 24 + byte_offset: 2048 + block: GPRCM + - name: PDBGCTL + description: Peripheral Debug Control. + byte_offset: 4120 + fieldset: PDBGCTL + - name: CPU_INT + array: + len: 1 + stride: 44 + byte_offset: 4128 + block: CPU_INT + - name: DMA_TRIG0 + array: + len: 1 + stride: 44 + byte_offset: 4176 + block: DMA_TRIG0 + - name: DMA_TRIG1 + array: + len: 1 + stride: 44 + byte_offset: 4224 + block: DMA_TRIG1 + - name: DMA_TRIG2 + array: + len: 1 + stride: 44 + byte_offset: 4272 + block: DMA_TRIG2 + - name: EVT_MODE + description: Event Mode. + byte_offset: 4320 + fieldset: EVT_MODE + - name: AESACTL0 + description: AES accelerator control register 0. + byte_offset: 4352 + fieldset: AESACTL0 + - name: AESACTL1 + description: AES accelerator control register 1. + byte_offset: 4356 + fieldset: AESACTL1 + - name: AESASTAT + description: aes accelerator status register. + byte_offset: 4360 + fieldset: AESASTAT + - name: AESAKEY + description: aes accelerator key register. + byte_offset: 4364 + access: Write + fieldset: AESAKEY + - name: AESADIN + description: aes accelerator data in register. + byte_offset: 4368 + access: Write + fieldset: AESADIN + - name: AESADOUT + description: aes accelerator data out register. + byte_offset: 4372 + access: Read + fieldset: AESADOUT + - name: AESAXDIN + description: aes accelerator xored data in register. + byte_offset: 4376 + access: Write + fieldset: AESAXDIN + - name: AESAXIN + description: aes accelerator xored data in register (no trigger). + byte_offset: 4380 + access: Write + fieldset: AESAXIN +block/CPU_INT: + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 0 + access: Read + fieldset: CPU_INT_IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: CPU_INT + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: CPU_INT + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: CPU_INT + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: CPU_INT + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: CPU_INT +block/DMA_TRIG0: + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 0 + access: Read + fieldset: DMA_TRIG0_IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: DMA_TRIG0 + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: DMA_TRIG0 + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: DMA_TRIG0 + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: DMA_TRIG0 + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: DMA_TRIG0 +block/DMA_TRIG1: + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 0 + access: Read + fieldset: DMA_TRIG1_IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: DMA_TRIG1 + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: DMA_TRIG1 + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: DMA_TRIG1 + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: DMA_TRIG1 + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: DMA_TRIG1 +block/DMA_TRIG2: + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 0 + access: Read + fieldset: DMA_TRIG2_IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: DMA_TRIG2 + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: DMA_TRIG2 + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: DMA_TRIG2 + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: DMA_TRIG2 + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: DMA_TRIG2 +block/GPRCM: + items: + - name: PWREN + description: Power enable. + byte_offset: 0 + fieldset: PWREN + - name: RSTCTL + description: Reset Control. + byte_offset: 4 + access: Write + fieldset: RSTCTL + - name: STAT + description: Status Register. + byte_offset: 20 + access: Read + fieldset: STAT +fieldset/AESACTL0: + description: AES accelerator control register 0. + fields: + - name: OPx + description: AES operation. The AESOPx bits are not reset by AESSWRST = 1. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 00b = Encryption. 01b = Decryption. The provided key is the same key used for encryption. 10b = Generate first round key required for decryption. 11b = Decryption. The provided key is the first round key required for decryption. + bit_offset: 0 + bit_size: 2 + enum: OPx + - name: KLx + description: AES key length. These bits define which of the 1 AES standards is performed. The AESKLx bits are not reset by AESSWRST = 1. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. + bit_offset: 2 + bit_size: 2 + enum: KLx + - name: CMx + description: AES cipher mode select. These bits are ignored for AESCMEN = 0. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 00b = ECB 01b = CBC 10b = OFB 11b = CFB. + bit_offset: 5 + bit_size: 2 + enum: CMx + - name: SWRST + description: AES software reset. Immediately resets the complete AES accelerator module even when busy except for the AESRDYIE, the AESKLx and the AESOPx bits. It also clears the (internal) state memory. The AESSWRST bit is automatically reset and is always read as zero. 0b = No reset 1b = Reset AES accelerator module. + bit_offset: 7 + bit_size: 1 + - name: ERRFG + description: AES error flag. AESAKEY or AESADIN were written while an AES operation was in progress. The bit must be cleared by software. 0b = No error 1b = Error occurred. + bit_offset: 11 + bit_size: 1 + - name: CMEN + description: AESCMEN enables the support of the cipher modes ECB, CBC, OFB and CFB together with the DMA. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 0 = No DMA triggers are generated. 1 = DMA cipher mode support operation is enabled and the corresponding DMA triggers are generated. + bit_offset: 15 + bit_size: 1 +fieldset/AESACTL1: + description: AES accelerator control register 1. + fields: + - name: BLKCNTx + description: Cipher Block Counter. Number of blocks to be encrypted or decrypted with block cipher modes enabled (AESCMEN = 1). Ignored if AESCMEN = 0. The block counter decrements with each performed encryption or decryption. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. + bit_offset: 0 + bit_size: 8 + enum: BLKCNTx +fieldset/AESADIN: + description: aes accelerator data in register. + fields: + - name: DIN0x + description: AES data in byte n when AESADIN is written as word. AES next data in byte when AESADIN is written as byte. Do not mix word and byte access. Always reads as zero. + bit_offset: 0 + bit_size: 8 + enum: DIN0x + - name: DIN1x + description: AES data in byte n+1 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. + bit_offset: 8 + bit_size: 8 + enum: DIN1x + - name: DIN2x + description: AES data in byte n+2 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. + bit_offset: 16 + bit_size: 8 + enum: DIN2x + - name: DIN3x + description: AES data in byte n+3 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. + bit_offset: 24 + bit_size: 8 + enum: DIN3x +fieldset/AESADOUT: + description: aes accelerator data out register. + fields: + - name: DOUT0x + description: AES data out byte n when AESADOUT is read as word. AES next data out byte when AESADOUT is read as byte. Do not mix word and byte access. + bit_offset: 0 + bit_size: 8 + enum: DOUT0x + - name: DOUT1x + description: AES data out byte n+1 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access. + bit_offset: 8 + bit_size: 8 + enum: DOUT1x + - name: DOUT2x + description: AES data out byte n+2 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access. + bit_offset: 16 + bit_size: 8 + enum: DOUT2x + - name: DOUT3x + description: AES data out byte n+3 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access. + bit_offset: 24 + bit_size: 8 + enum: DOUT3x +fieldset/AESAKEY: + description: aes accelerator key register. + fields: + - name: KEY0x + description: AES key byte n when AESAKEY is written as word. AES next key byte when AESAKEY is written as byte. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1. + bit_offset: 0 + bit_size: 8 + enum: KEY0x + - name: KEY1x + description: AES key byte n+1 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1. + bit_offset: 8 + bit_size: 8 + enum: KEY1x + - name: KEY2x + description: AES key byte n+2 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1. + bit_offset: 16 + bit_size: 8 + enum: KEY2x + - name: KEY3x + description: AES key byte n+3 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1. + bit_offset: 24 + bit_size: 8 + enum: KEY3x +fieldset/AESASTAT: + description: aes accelerator status register. + fields: + - name: BUSY + description: AES accelerator module busy; encryption, decryption, or key generation in progress. 0 = Not busy 1 = Busy. + bit_offset: 0 + bit_size: 1 + enum: BUSY + - name: KEYWR + description: All bytes written to AESAKEY. This bit can be modified by software but it must not be reset by software (10) if AESCMEN=1. Changing its state by software also resets the AESKEYCNTx bits. AESKEYWR is reset by PUC, AESSWRST, an error condition, changing AESOPx, changing AESKLx, and the start to (over)write a new key. Because it is reset when AESOPx is changed it can be set by software again to indicate that the loaded key is still valid. + bit_offset: 1 + bit_size: 1 + enum: KEYWR + - name: DINWR + description: All 16 bytes written to AESADIN, AESAXDIN or AESAXIN. Changing its state by software also resets the AESDINCNTx bits. AESDINWR is reset by PUC, AESSWRST, an error condition, changing AESOPx, changing AESKLx, the start to (over)write the data, and when the AES accelerator is busy. Because it is reset when AESOPx or AESKLx is changed it can be set by software again to indicate that the current data is still valid. 0 = Not all bytes written 1 = All bytes written. + bit_offset: 2 + bit_size: 1 + enum: DINWR + - name: DOUTRD + description: All 16 bytes read from AESADOUT. AESDOUTRD is reset by PUC, AESSWRST, an error condition, changing AESOPx, changing AESKLx, when the AES accelerator is busy, and when the output data is read again. 0 = Not all bytes read 1 = All bytes read. + bit_offset: 3 + bit_size: 1 + enum: DOUTRD + - name: KEYCNTx + description: Bytes written to AESAKEY when AESKLx = 00, half-words written to AESAKEY if AESKLx = b10. Reset when AESKEYWR is reset. If AESKEYCNTx = 0 and AESKEYWR = 0, no bytes were written. If AESKEYCNTx = 0 and AESKEYWR = 1, all bytes were written. + bit_offset: 4 + bit_size: 4 + enum: KEYCNTx + - name: DINCNTx + description: Bytes written to AESADIN, AESAXDIN or AESAXIN. Reset when AESDINWR is reset. If AESDINCNTx = 0 and AESDINWR = 0, no bytes were written. If AESDINCNTx = 0 and AESDINWR = 1, all bytes were written. + bit_offset: 8 + bit_size: 4 + enum: DINCNTx + - name: DOUTCNTx + description: Bytes read from AESADOUT. Reset when AESDOUTRD is reset. If AESDOUTCNTx = 0 and AESDOUTRD = 0, no bytes were read. If AESDOUTCNTx = 0 and AESDOUTRD = 1, all bytes were read. + bit_offset: 12 + bit_size: 4 + enum: DOUTCNTx +fieldset/AESAXDIN: + description: aes accelerator xored data in register. + fields: + - name: XDIN0x + description: AES data in byte n when AESAXDIN is written as word. AES next data in byte when AESAXDIN is written as byte. Do not mix word and byte access. Always reads as zero. + bit_offset: 0 + bit_size: 8 + enum: XDIN0x + - name: XDIN1x + description: AES data in byte n+1 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. + bit_offset: 8 + bit_size: 8 + enum: XDIN1x + - name: XDIN2x + description: AES data in byte n+2 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. + bit_offset: 16 + bit_size: 8 + enum: XDIN2x + - name: XDIN3x + description: AES data in byte n+3 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. + bit_offset: 24 + bit_size: 8 + enum: XDIN3x +fieldset/AESAXIN: + description: aes accelerator xored data in register (no trigger). + fields: + - name: XIN0x + description: AES data in byte n when AESAXIN is written as word. AES next data in byte when AESAXIN is written as byte. Do not mix word and byte access. Always reads as zero. + bit_offset: 0 + bit_size: 8 + enum: XIN0x + - name: XIN1x + description: AES data in byte n+1 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. + bit_offset: 8 + bit_size: 8 + enum: XIN1x + - name: XIN2x + description: AES data in byte n+2 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. + bit_offset: 16 + bit_size: 8 + enum: XIN2x + - name: XIN3x + description: AES data in byte n+3 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. + bit_offset: 24 + bit_size: 8 + enum: XIN3x +fieldset/CPU_INT: + description: Interrupt clear. + fields: + - name: AESRDY + description: AES ready interrupt, set when the selected AES operation was completed and the result can be read from AESADOUT. + bit_offset: 0 + bit_size: 1 + - name: DMA0 + description: DMA0. + bit_offset: 1 + bit_size: 1 + - name: DMA1 + description: DMA1. + bit_offset: 2 + bit_size: 1 + - name: DMA2 + description: DMA2. + bit_offset: 3 + bit_size: 1 +fieldset/CPU_INT_IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: CPU_INT_IIDX_STAT +fieldset/DMA_TRIG0: + description: Interrupt clear. + fields: + - name: DMA0 + description: DMA0 event. + bit_offset: 1 + bit_size: 1 +fieldset/DMA_TRIG0_IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: DMA_TRIG0_IIDX_STAT +fieldset/DMA_TRIG1: + description: Interrupt clear. + fields: + - name: DMA1 + description: DMA1 event. + bit_offset: 2 + bit_size: 1 +fieldset/DMA_TRIG1_IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: DMA_TRIG1_IIDX_STAT +fieldset/DMA_TRIG2: + description: Interrupt clear. + fields: + - name: DMA2 + description: DMA2 event. + bit_offset: 3 + bit_size: 1 +fieldset/DMA_TRIG2_IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: DMA_TRIG2_IIDX_STAT +fieldset/EVT_MODE: + description: Event Mode. + fields: + - name: INT0_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]. + bit_offset: 0 + bit_size: 2 + enum: EVT_CFG + - name: EVT1_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]. + bit_offset: 2 + bit_size: 2 + enum: EVT_CFG + - name: EVT2_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]. + bit_offset: 4 + bit_size: 2 + enum: EVT_CFG + - name: EVT3_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]. + bit_offset: 6 + bit_size: 2 + enum: EVT_CFG +fieldset/PDBGCTL: + description: Peripheral Debug Control. + fields: + - name: FREE + description: Free run control. + bit_offset: 0 + bit_size: 1 + - name: SOFT + description: Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'. + bit_offset: 1 + bit_size: 1 + enum: SOFT +fieldset/PWREN: + description: Power enable. + fields: + - name: ENABLE + description: Enable the power. + bit_offset: 0 + bit_size: 1 + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY +fieldset/RSTCTL: + description: Reset Control. + fields: + - name: RESETASSERT + description: Assert reset to the peripheral. + bit_offset: 0 + bit_size: 1 + - name: RESETSTKYCLR + description: Clear the RESETSTKY bit in the STAT register. + bit_offset: 1 + bit_size: 1 + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY +fieldset/STAT: + description: Status Register. + fields: + - name: RESETSTKY + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + bit_offset: 16 + bit_size: 1 +enum/BLKCNTx: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest value. + value: 0 + - name: ENABLE + description: Highest possible value. + value: 255 +enum/BUSY: + bit_size: 1 + variants: + - name: IDLE + description: Not busy. + value: 0 + - name: BUSY + description: Busy. + value: 1 +enum/CMx: + bit_size: 2 + variants: + - name: ECB + description: ECB. + value: 0 + - name: CBC + description: CBC. + value: 1 + - name: OFB + description: OFB. + value: 2 + - name: CFB + description: CFB. + value: 3 +enum/CPU_INT_IIDX_STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: AESRDY + description: AES ready interrupt, set when the selected AES operation was completed and the result can be read from AESADOUT. + value: 1 + - name: DMA0 + description: AES trigger 0 DMA. + value: 2 + - name: DMA1 + description: AES trigger 1 DMA. + value: 3 + - name: DMA2 + description: AES trigger 2 DMA. + value: 4 +enum/DIN0x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/DIN1x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/DIN2x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/DIN3x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/DINCNTx: + bit_size: 4 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 15 +enum/DINWR: + bit_size: 1 + variants: + - name: NALL + description: Not all bytes written. + value: 0 + - name: ALL + description: All bytes written. + value: 1 +enum/DMA_TRIG0_IIDX_STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: DMA0 + description: AES trigger 0 DMA. + value: 2 +enum/DMA_TRIG1_IIDX_STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: DMA1 + description: AES trigger 1 DMA. + value: 3 +enum/DMA_TRIG2_IIDX_STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: DMA2 + description: AES trigger 2 DMA. + value: 4 +enum/DOUT0x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/DOUT1x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/DOUT2x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/DOUT3x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/DOUTCNTx: + bit_size: 4 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 15 +enum/DOUTRD: + bit_size: 1 + variants: + - name: NALL + description: Not all bytes read. + value: 0 + - name: ALL + description: All bytes read. + value: 1 +enum/EVT_CFG: + bit_size: 2 + variants: + - name: DISABLE + description: The interrupt or event line is disabled. + value: 0 + - name: SOFTWARE + description: The interrupt or event line is in software mode. Software must clear the RIS. + value: 1 + - name: HARDWARE + description: The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. + value: 2 +enum/KEY0x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/KEY1x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/KEY2x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/KEY3x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/KEYCNTx: + bit_size: 4 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 15 +enum/KEYWR: + bit_size: 1 + variants: + - name: NALL + description: Not all bytes written. + value: 0 + - name: ALL + description: All bytes written. + value: 1 +enum/KLx: + bit_size: 2 + variants: + - name: AES128 + description: The key size is 128 bit. + value: 0 + - name: AES256 + description: The key size is 256 bit. + value: 2 +enum/OPx: + bit_size: 2 + variants: + - name: OP0 + description: Encryption. + value: 0 + - name: OP1 + description: Decryption. The provided key is the same key used for encryption. + value: 1 + - name: OP2 + description: Generate first round key required for decryption. + value: 2 + - name: OP3 + description: Decryption. The provided key is the first round key required for decryption. + value: 3 +enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 +enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 +enum/SOFT: + bit_size: 1 + variants: + - name: IMMEDIATE + description: The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted. + value: 0 + - name: DELAYED + description: The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption. + value: 1 +enum/XDIN0x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/XDIN1x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/XDIN2x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/XDIN3x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/XIN0x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/XIN1x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/XIN2x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 +enum/XIN3x: + bit_size: 8 + variants: + - name: MINNUM + description: Smallest possible value. + value: 0 + - name: MAXNUM + description: Highest possible value. + value: 255 diff --git a/data/registers/canfd_v1.yaml b/data/registers/canfd_v1.yaml index 25826de..f790937 100644 --- a/data/registers/canfd_v1.yaml +++ b/data/registers/canfd_v1.yaml @@ -37,121 +37,119 @@ block/CPU_INT: - name: IMASK description: Interrupt mask. byte_offset: 8 - fieldset: CPU_INT + fieldset: IMASK - name: RIS description: Raw interrupt status. byte_offset: 16 access: Read - fieldset: CPU_INT + fieldset: RIS - name: MIS description: Masked interrupt status. byte_offset: 24 access: Read - fieldset: CPU_INT + fieldset: MIS - name: ISET description: Interrupt set. byte_offset: 32 access: Write - fieldset: CPU_INT + fieldset: ISET - name: ICLR description: Interrupt clear. byte_offset: 40 access: Write - fieldset: CPU_INT -block/ECC: + fieldset: ICLR +block/ECC_REGS: items: - - name: ERR_REV + - name: MCANERR_REV description: MCAN Error Aggregator Revision Register. byte_offset: 0 access: Read - fieldset: ERR_REV - - name: ERR_VECTOR + fieldset: MCANERR_REV + - name: MCANERR_VECTOR description: MCAN ECC Vector Register. byte_offset: 8 - fieldset: ERR_VECTOR - - name: ERR_STAT + fieldset: MCANERR_VECTOR + - name: MCANERR_STAT description: MCAN Error Misc Status. byte_offset: 12 access: Read - fieldset: ERR_STAT - - name: ERR_WRAP_REV + fieldset: MCANERR_STAT + - name: MCANERR_WRAP_REV description: MCAN ECC Wrapper Revision Register. byte_offset: 16 access: Read - fieldset: ERR_WRAP_REV - - name: ERR_CTRL + fieldset: MCANERR_WRAP_REV + - name: MCANERR_CTRL description: MCAN ECC Control. byte_offset: 20 - fieldset: ERR_CTRL - - name: ERR_ERR_CTRL1 + fieldset: MCANERR_CTRL + - name: MCANERR_ERR_CTRL1 description: MCAN ECC Error Control 1 Register. byte_offset: 24 - fieldset: ERR_ERR_CTRL1 - - name: ERR_ERR_CTRL2 + - name: MCANERR_ERR_CTRL2 description: MCAN ECC Error Control 2 Register. byte_offset: 28 - fieldset: ERR_ERR_CTRL2 - - name: ERR_ERR_STAT1 + fieldset: MCANERR_ERR_CTRL2 + - name: MCANERR_ERR_STAT1 description: MCAN ECC Error Status 1 Register. byte_offset: 32 - fieldset: ERR_ERR_STAT1 - - name: ERR_ERR_STAT2 + fieldset: MCANERR_ERR_STAT1 + - name: MCANERR_ERR_STAT2 description: MCAN ECC Error Status 2 Register. byte_offset: 36 access: Read - fieldset: ERR_ERR_STAT2 - - name: ERR_ERR_STAT3 + - name: MCANERR_ERR_STAT3 description: MCAN ECC Error Status 3 Register. byte_offset: 40 - fieldset: ERR_ERR_STAT3 - - name: ERR_SEC_EOI + fieldset: MCANERR_ERR_STAT3 + - name: MCANERR_SEC_EOI description: MCAN Single Error Corrected End of Interrupt Register. byte_offset: 60 - fieldset: ERR_SEC_EOI - - name: ERR_SEC_STATUS + fieldset: MCANERR_SEC_EOI + - name: MCANERR_SEC_STATUS description: MCAN Single Error Corrected Interrupt Status Register. byte_offset: 64 - fieldset: ERR_SEC_STATUS - - name: ERR_SEC_ENABLE_SET + fieldset: MCANERR_SEC_STATUS + - name: MCANERR_SEC_ENABLE_SET description: MCAN Single Error Corrected Interrupt Enable Set Register. byte_offset: 128 - fieldset: ERR_SEC_ENABLE_SET - - name: ERR_SEC_ENABLE_CLR + fieldset: MCANERR_SEC_ENABLE_SET + - name: MCANERR_SEC_ENABLE_CLR description: MCAN Single Error Corrected Interrupt Enable Clear Register. byte_offset: 192 - fieldset: ERR_SEC_ENABLE_CLR - - name: ERR_DED_EOI + fieldset: MCANERR_SEC_ENABLE_CLR + - name: MCANERR_DED_EOI description: MCAN Double Error Detected End of Interrupt Register. byte_offset: 316 - fieldset: ERR_DED_EOI - - name: ERR_DED_STATUS + fieldset: MCANERR_DED_EOI + - name: MCANERR_DED_STATUS description: MCAN Double Error Detected Interrupt Status Register. byte_offset: 320 - fieldset: ERR_DED_STATUS - - name: ERR_DED_ENABLE_SET + fieldset: MCANERR_DED_STATUS + - name: MCANERR_DED_ENABLE_SET description: MCAN Double Error Detected Interrupt Enable Set Register. byte_offset: 384 - fieldset: ERR_DED_ENABLE_SET - - name: ERR_DED_ENABLE_CLR + fieldset: MCANERR_DED_ENABLE_SET + - name: MCANERR_DED_ENABLE_CLR description: MCAN Double Error Detected Interrupt Enable Clear Register. byte_offset: 448 - fieldset: ERR_DED_ENABLE_CLR - - name: ERR_AGGR_ENABLE_SET + fieldset: MCANERR_DED_ENABLE_CLR + - name: MCANERR_AGGR_ENABLE_SET description: MCAN Error Aggregator Enable Set Register. byte_offset: 512 - fieldset: ERR_AGGR_ENABLE_SET - - name: ERR_AGGR_ENABLE_CLR + fieldset: MCANERR_AGGR_ENABLE_SET + - name: MCANERR_AGGR_ENABLE_CLR description: MCAN Error Aggregator Enable Clear Register. byte_offset: 516 - fieldset: ERR_AGGR_ENABLE_CLR - - name: ERR_AGGR_STATUS_SET + fieldset: MCANERR_AGGR_ENABLE_CLR + - name: MCANERR_AGGR_STATUS_SET description: MCAN Error Aggregator Status Set Register. byte_offset: 520 - fieldset: ERR_AGGR_STATUS_SET - - name: ERR_AGGR_STATUS_CLR + fieldset: MCANERR_AGGR_STATUS_SET + - name: MCANERR_AGGR_STATUS_CLR description: MCAN Error Aggregator Status Clear Register. byte_offset: 524 - fieldset: ERR_AGGR_STATUS_CLR + fieldset: MCANERR_AGGR_STATUS_CLR block/MCAN: items: - name: CREL @@ -163,7 +161,6 @@ block/MCAN: description: MCAN Endian Register. byte_offset: 4 access: Read - fieldset: ENDN - name: DBTP description: MCAN Data Bit Timing and Prescaler Register. byte_offset: 12 @@ -254,11 +251,11 @@ block/MCAN: - name: NDAT1 description: MCAN New Data 1. byte_offset: 152 - fieldset: NDAT + fieldset: NDAT1 - name: NDAT2 description: MCAN New Data 2. byte_offset: 156 - fieldset: NDAT + fieldset: NDAT2 - name: RXF0C description: MCAN Rx FIFO 0 Configuration. byte_offset: 160 @@ -350,6 +347,56 @@ block/MCAN: description: MCAN Tx Event FIFO Acknowledge. byte_offset: 248 fieldset: TXEFA +block/MCANSS_REGS: + items: + - name: MCANSS_PID + description: MCAN Subsystem Revision Register. + byte_offset: 0 + access: Read + fieldset: MCANSS_PID + - name: MCANSS_CTRL + description: MCAN Subsystem Control Register. + byte_offset: 4 + fieldset: MCANSS_CTRL + - name: MCANSS_STAT + description: MCAN Subsystem Status Register. + byte_offset: 8 + access: Read + fieldset: MCANSS_STAT + - name: MCANSS_ICS + description: MCAN Subsystem Interrupt Clear Shadow Register. + byte_offset: 12 + fieldset: MCANSS_ICS + - name: MCANSS_IRS + description: MCAN Subsystem Interrupt Raw Satus Register. + byte_offset: 16 + fieldset: MCANSS_IRS + - name: MCANSS_IECS + description: MCAN Subsystem Interrupt Enable Clear Shadow Register. + byte_offset: 20 + fieldset: MCANSS_IECS + - name: MCANSS_IE + description: MCAN Subsystem Interrupt Enable Register. + byte_offset: 24 + fieldset: MCANSS_IE + - name: MCANSS_IES + description: MCAN Subsystem Interrupt Enable Status. + byte_offset: 28 + access: Read + fieldset: MCANSS_IES + - name: MCANSS_EOI + description: MCAN Subsystem End of Interrupt. + byte_offset: 32 + fieldset: MCANSS_EOI + - name: MCANSS_EXT_TS_PRESCALER + description: MCAN Subsystem External Timestamp Prescaler 0. + byte_offset: 36 + fieldset: MCANSS_EXT_TS_PRESCALER + - name: MCANSS_EXT_TS_UNSERVICED_INTR_CNTR + description: MCAN Subsystem External Timestamp Unserviced Interrupts Counter. + byte_offset: 40 + access: Read + fieldset: MCANSS_EXT_TS_UNSERVICED_INTR_CNTR block/MSP: items: - name: CPU_INT @@ -367,87 +414,37 @@ block/MSP: byte_offset: 252 access: Read fieldset: DESC - - name: SUBSYS_CLKEN + - name: MCANSS_CLKEN description: MCAN module clock enable. byte_offset: 256 - fieldset: SUBSYS_CLKEN - - name: SUBSYS_CLKDIV + fieldset: MCANSS_CLKEN + - name: MCANSS_CLKDIV description: Clock divider. byte_offset: 260 - fieldset: SUBSYS_CLKDIV - - name: SUBSYS_CLKCTL + fieldset: MCANSS_CLKDIV + - name: MCANSS_CLKCTL description: MCAN-SS clock stop control register. byte_offset: 264 - fieldset: SUBSYS_CLKCTL - - name: SUBSYS_CLKSTS + fieldset: MCANSS_CLKCTL + - name: MCANSS_CLKSTS description: MCANSS clock stop status register. byte_offset: 268 access: Read - fieldset: SUBSYS_CLKSTS + fieldset: MCANSS_CLKSTS block/PROCESSORS: items: - - name: SUBSYS_REGS + - name: MCANSS_REGS array: len: 1 stride: 44 byte_offset: 0 - block: SUBSYS - - name: ECC_REGS + block: MCANSS_REGS + - name: MCAN_ECC_REGS array: len: 1 stride: 528 byte_offset: 512 - block: ECC -block/SUBSYS: - items: - - name: SUBSYS_PID - description: MCAN Subsystem Revision Register. - byte_offset: 0 - access: Read - fieldset: SUBSYS_PID - - name: SUBSYS_CTRL - description: MCAN Subsystem Control Register. - byte_offset: 4 - fieldset: SUBSYS_CTRL - - name: SUBSYS_STAT - description: MCAN Subsystem Status Register. - byte_offset: 8 - access: Read - fieldset: SUBSYS_STAT - - name: SUBSYS_ICS - description: MCAN Subsystem Interrupt Clear Shadow Register. - byte_offset: 12 - fieldset: SUBSYS_ICS - - name: SUBSYS_IRS - description: MCAN Subsystem Interrupt Raw Satus Register. - byte_offset: 16 - fieldset: SUBSYS_IRS - - name: SUBSYS_IECS - description: MCAN Subsystem Interrupt Enable Clear Shadow Register. - byte_offset: 20 - fieldset: SUBSYS_IECS - - name: SUBSYS_IE - description: MCAN Subsystem Interrupt Enable Register. - byte_offset: 24 - fieldset: SUBSYS_IE - - name: SUBSYS_IES - description: MCAN Subsystem Interrupt Enable Status. - byte_offset: 28 - access: Read - fieldset: SUBSYS_IES - - name: SUBSYS_EOI - description: MCAN Subsystem End of Interrupt. - byte_offset: 32 - fieldset: SUBSYS_EOI - - name: SUBSYS_EXT_TS_PRESCALER - description: MCAN Subsystem External Timestamp Prescaler 0. - byte_offset: 36 - fieldset: SUBSYS_EXT_TS_PRESCALER - - name: SUBSYS_EXT_TS_UNSERVICED_INTR_CNTR - description: MCAN Subsystem External Timestamp Unserviced Interrupts Counter. - byte_offset: 40 - access: Read - fieldset: SUBSYS_EXT_TS_UNSERVICED_INTR_CNTR + block: ECC_REGS block/TI_WRAPPER: items: - name: PROCESSORS @@ -521,33 +518,6 @@ fieldset/CCCR: description: Non ISO Operation. If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0 CAN FD frame format according to ISO 11898-1:2015 1 CAN FD frame format according to Bosch CAN FD Specification V1.0. bit_offset: 15 bit_size: 1 -fieldset/CPU_INT: - description: Interrupt clear. - fields: - - name: INTL0 - description: Clear MCAN Interrupt Line 0. - bit_offset: 0 - bit_size: 1 - - name: INTL1 - description: Clear MCAN Interrupt Line 1. - bit_offset: 1 - bit_size: 1 - - name: SEC - description: Clear Message RAM SEC interrupt. - bit_offset: 2 - bit_size: 1 - - name: DED - description: Clear Message RAM DED interrupt. - bit_offset: 3 - bit_size: 1 - - name: EXT_TS_CNTR_OVFL - description: Clear External Timestamp Counter Overflow interrupt. - bit_offset: 4 - bit_size: 1 - - name: WAKEUP - description: Clear Clock Stop Wake Up interrupt. - bit_offset: 5 - bit_size: 1 fieldset/CREL: description: MCAN Core Release Register. fields: @@ -637,362 +607,116 @@ fieldset/ECR: description: 'CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.' bit_offset: 16 bit_size: 8 -fieldset/ENDN: - description: MCAN Endian Register. - fields: [] -fieldset/ERR_AGGR_ENABLE_CLR: - description: MCAN Error Aggregator Enable Clear Register. +fieldset/EVT_MODE: + description: Event Mode. fields: - - name: ENABLE_PARITY_CLR - description: Write 1 to disable parity errors. Reads return the corresponding enable bit's current value. + - name: INT0_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]. bit_offset: 0 - bit_size: 1 - - name: ENABLE_TIMEOUT_CLR - description: Write 1 to disable timeout errors. Reads return the corresponding enable bit's current value. - bit_offset: 1 - bit_size: 1 -fieldset/ERR_AGGR_ENABLE_SET: - description: MCAN Error Aggregator Enable Set Register. + bit_size: 2 + enum: INT0_CFG +fieldset/GFC: + description: MCAN Global Filter Configuration. fields: - - name: ENABLE_PARITY_SET - description: Write 1 to enable parity errors. Reads return the corresponding enable bit's current value. + - name: RRFE + description: Reject Remote Frames Extended 0 Filter remote frames with 29-bit extended IDs 1 Reject all remote frames with 29-bit extended IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. bit_offset: 0 bit_size: 1 - - name: ENABLE_TIMEOUT_SET - description: Write 1 to enable timeout errors. Reads return the corresponding enable bit's current value. + - name: RRFS + description: Reject Remote Frames Standard 0 Filter remote frames with 11-bit standard IDs 1 Reject all remote frames with 11-bit standard IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. bit_offset: 1 bit_size: 1 -fieldset/ERR_AGGR_STATUS_CLR: - description: MCAN Error Aggregator Status Clear Register. - fields: - - name: AGGR_PARITY_ERR - description: Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. - bit_offset: 0 - bit_size: 2 - - name: SVBUS_TIMEOUT - description: Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. + - name: ANFE + description: Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. bit_offset: 2 bit_size: 2 -fieldset/ERR_AGGR_STATUS_SET: - description: MCAN Error Aggregator Status Set Register. + - name: ANFS + description: Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 4 + bit_size: 2 +fieldset/HPMS: + description: MCAN High Priority Message Status. fields: - - name: AGGR_PARITY_ERR - description: Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field increments it by the value provided. + - name: BIDX + description: Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'. bit_offset: 0 + bit_size: 6 + - name: MSI + description: Message Storage Indicator 00 No FIFO selected 01 FIFO message lost 10 Message stored in FIFO 0 11 Message stored in FIFO 1. + bit_offset: 6 bit_size: 2 - - name: SVBUS_TIMEOUT - description: Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field increments it by the value provided. - bit_offset: 2 - bit_size: 2 -fieldset/ERR_CTRL: - description: MCAN ECC Control. + - name: FIDX + description: Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + bit_offset: 8 + bit_size: 7 + - name: FLST + description: Filter List. Indicates the filter list of the matching filter element. 0 Standard Filter List 1 Extended Filter List. + bit_offset: 15 + bit_size: 1 +fieldset/ICLR: + description: Interrupt clear. fields: - - name: ECC_ENABLE - description: Enable ECC Generation. + - name: INTL0 + description: Clear MCAN Interrupt Line 0. bit_offset: 0 bit_size: 1 - - name: ECC_CHECK - description: Enable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'. + - name: INTL1 + description: Clear MCAN Interrupt Line 1. bit_offset: 1 bit_size: 1 - - name: ENABLE_RMW - description: Enable read-modify-write on partial word writes. + - name: SEC + description: Clear Message RAM SEC interrupt. bit_offset: 2 bit_size: 1 - - name: FORCE_SEC - description: Force single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. + - name: DED + description: Clear Message RAM DED interrupt. bit_offset: 3 bit_size: 1 - - name: FORCE_DED - description: Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. + - name: EXT_TS_CNTR_OVFL + description: Clear External Timestamp Counter Overflow interrupt. bit_offset: 4 bit_size: 1 - - name: FORCE_N_ROW - description: Enable single/double-bit error on the next RAM read, regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode, this applies to writes as well as reads. + - name: WAKEUP + description: Clear Clock Stop Wake Up interrupt. bit_offset: 5 bit_size: 1 - - name: ERROR_ONCE - description: If this bit is set, the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled, this error will be cleared the cycle following the read when the data is corrected. For double-bit errors, the FORCE_DED bit will be cleared the cycle following the double-bit error. Any subsequent reads will not force an error. - bit_offset: 6 - bit_size: 1 - - name: CHECK_SVBUS_TIMEOUT - description: Enables Serial VBUS timeout mechanism. - bit_offset: 8 - bit_size: 1 -fieldset/ERR_DED_ENABLE_CLR: - description: MCAN Double Error Detected Interrupt Enable Clear Register. +fieldset/IE: + description: MCAN Interrupt Enable. fields: - - name: MSGMEM_ENABLE_CLR - description: Message RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. + - name: RF0NE + description: Rx FIFO 0 New Message Enable. bit_offset: 0 bit_size: 1 -fieldset/ERR_DED_ENABLE_SET: - description: MCAN Double Error Detected Interrupt Enable Set Register. - fields: - - name: MSGMEM_ENABLE_SET - description: Message RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. - bit_offset: 0 + - name: RF0WE + description: Rx FIFO 0 Watermark Reached Enable. + bit_offset: 1 bit_size: 1 -fieldset/ERR_DED_EOI: - description: MCAN Double Error Detected End of Interrupt Register. - fields: - - name: EOI_WR - description: Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_DED goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. - bit_offset: 0 + - name: RF0FE + description: Rx FIFO 0 Full Enable. + bit_offset: 2 bit_size: 1 -fieldset/ERR_DED_STATUS: - description: MCAN Double Error Detected Interrupt Status Register. - fields: - - name: MSGMEM_PEND - description: Message RAM DED Interrupt Pending 0 No DED interrupt is pending 1 DED interrupt is pending. - bit_offset: 0 + - name: RF0LE + description: Rx FIFO 0 Message Lost Enable. + bit_offset: 3 bit_size: 1 -fieldset/ERR_ERR_CTRL1: - description: MCAN ECC Error Control 1 Register. - fields: [] -fieldset/ERR_ERR_CTRL2: - description: MCAN ECC Error Control 2 Register. - fields: - - name: ECC_BIT1 - description: Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set. - bit_offset: 0 - bit_size: 16 - - name: ECC_BIT2 - description: Second column/data bit that needs to be flipped when FORCE_DED is set. - bit_offset: 16 - bit_size: 16 -fieldset/ERR_ERR_STAT1: - description: MCAN ECC Error Status 1 Register. - fields: - - name: ECC_SEC - description: Single Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared. 0 No single-bit error detected 1 One single-bit error was detected and corrected 2 Two single-bit errors were detected and corrected 3 Three single-bit errors were detected and corrected A write of a non-zero value to this bit field increments it by the value provided. - bit_offset: 0 - bit_size: 2 - - name: ECC_DED - description: Double Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared. 0 No double-bit error detected 1 One double-bit error was detected 2 Two double-bit errors were detected 3 Three double-bit errors were detected A write of a non-zero value to this bit field increments it by the value provided. - bit_offset: 2 - bit_size: 2 - - name: ECC_OTHER - description: SEC While Writeback Error Status 0 No SEC error while writeback pending 1 Indicates that successive single-bit errors have occurred while a writeback is still pending. + - name: RF1NE + description: Rx FIFO 1 New Message Enable. bit_offset: 4 bit_size: 1 - - name: CTRL_REG_ERROR - description: Control Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to re-write these registers to a known state. A write of 1 will set this interrupt flag. + - name: RF1WE + description: Rx FIFO 1 Watermark Reached Enable. + bit_offset: 5 + bit_size: 1 + - name: RF1FE + description: Rx FIFO 1 Full Enable. + bit_offset: 6 + bit_size: 1 + - name: RF1LE + description: Rx FIFO 1 Message Lost Enable. bit_offset: 7 bit_size: 1 - - name: CLR_ECC_SEC - description: Clear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided. - bit_offset: 8 - bit_size: 2 - - name: CLR_ECC_DED - description: Clear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided. - bit_offset: 10 - bit_size: 2 - - name: CLR_ECC_OTHER - description: Writing a '1' clears the ECC_OTHER bit. - bit_offset: 12 - bit_size: 1 - - name: CLR_CTRL_REG_ERROR - description: Writing a '1' clears the CTRL_REG_ERROR bit. - bit_offset: 15 - bit_size: 1 - - name: ECC_BIT1 - description: ECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error. 0 Bit 0 is in error 1 Bit 1 is in error 2 Bit 2 is in error 3 Bit 3 is in error ... 31 Bit 31 is in error >32 Invalid. - bit_offset: 16 - bit_size: 16 -fieldset/ERR_ERR_STAT2: - description: MCAN ECC Error Status 2 Register. - fields: [] -fieldset/ERR_ERR_STAT3: - description: MCAN ECC Error Status 3 Register. - fields: - - name: WB_PEND - description: Delayed Write Back Pending Status 0 No write back pending 1 An ECC data correction write back is pending. - bit_offset: 0 - bit_size: 1 - - name: SVBUS_TIMEOUT - description: Serial VBUS Timeout Flag. Write 1 to set. - bit_offset: 1 - bit_size: 1 - - name: CLR_SVBUS_TIMEOUT - description: Write 1 to clear the Serial VBUS Timeout Flag. - bit_offset: 9 - bit_size: 1 -fieldset/ERR_REV: - description: MCAN Error Aggregator Revision Register. - fields: - - name: REVMIN - description: Minor Revision of the Error Aggregator. - bit_offset: 0 - bit_size: 6 - - name: REVMAJ - description: Major Revision of the Error Aggregator. - bit_offset: 8 - bit_size: 3 - - name: MODULE_ID - description: Module Identification Number. - bit_offset: 16 - bit_size: 12 - - name: SCHEME - description: PID Register Scheme. - bit_offset: 30 - bit_size: 2 -fieldset/ERR_SEC_ENABLE_CLR: - description: MCAN Single Error Corrected Interrupt Enable Clear Register. - fields: - - name: MSGMEM_ENABLE_CLR - description: Message RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. - bit_offset: 0 - bit_size: 1 -fieldset/ERR_SEC_ENABLE_SET: - description: MCAN Single Error Corrected Interrupt Enable Set Register. - fields: - - name: MSGMEM_ENABLE_SET - description: Message RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. - bit_offset: 0 - bit_size: 1 -fieldset/ERR_SEC_EOI: - description: MCAN Single Error Corrected End of Interrupt Register. - fields: - - name: EOI_WR - description: Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_SEC goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. - bit_offset: 0 - bit_size: 1 -fieldset/ERR_SEC_STATUS: - description: MCAN Single Error Corrected Interrupt Status Register. - fields: - - name: MSGMEM_PEND - description: Message RAM SEC Interrupt Pending 0 No SEC interrupt is pending 1 SEC interrupt is pending. - bit_offset: 0 - bit_size: 1 -fieldset/ERR_STAT: - description: MCAN Error Misc Status. - fields: - - name: NUM_RAMS - description: Number of RAMs. Number of ECC RAMs serviced by the aggregator. - bit_offset: 0 - bit_size: 11 -fieldset/ERR_VECTOR: - description: MCAN ECC Vector Register. - fields: - - name: ECC_VECTOR - description: ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address. 0x000 Message RAM ECC controller is selected Others Reserved (do not use) Subsequent writes through the SVBUS (offsets 0x10 - 0x3B) have a delayed completion. To avoid conflicts, perform a read back of a register within this range after writing. - bit_offset: 0 - bit_size: 11 - - name: RD_SVBUS - description: Read Trigger. - bit_offset: 15 - bit_size: 1 - - name: RD_SVBUS_ADDRESS - description: Read Address Offset. - bit_offset: 16 - bit_size: 8 - - name: RD_SVBUS_DONE - description: Read Completion Flag. - bit_offset: 24 - bit_size: 1 -fieldset/ERR_WRAP_REV: - description: MCAN ECC Wrapper Revision Register. - fields: - - name: REVMIN - description: Minor Revision of the Error Aggregator. - bit_offset: 0 - bit_size: 6 - - name: REVMAJ - description: Major Revision of the Error Aggregator. - bit_offset: 8 - bit_size: 3 - - name: MODULE_ID - description: Module Identification Number. - bit_offset: 16 - bit_size: 12 - - name: SCHEME - description: PID Register Scheme. - bit_offset: 30 - bit_size: 2 -fieldset/EVT_MODE: - description: Event Mode. - fields: - - name: INT0_CFG - description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]. - bit_offset: 0 - bit_size: 2 - enum: INT0_CFG -fieldset/GFC: - description: MCAN Global Filter Configuration. - fields: - - name: RRFE - description: Reject Remote Frames Extended 0 Filter remote frames with 29-bit extended IDs 1 Reject all remote frames with 29-bit extended IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 0 - bit_size: 1 - - name: RRFS - description: Reject Remote Frames Standard 0 Filter remote frames with 11-bit standard IDs 1 Reject all remote frames with 11-bit standard IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 1 - bit_size: 1 - - name: ANFE - description: Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 2 - bit_size: 2 - - name: ANFS - description: Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 4 - bit_size: 2 -fieldset/HPMS: - description: MCAN High Priority Message Status. - fields: - - name: BIDX - description: Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'. - bit_offset: 0 - bit_size: 6 - - name: MSI - description: Message Storage Indicator 00 No FIFO selected 01 FIFO message lost 10 Message stored in FIFO 0 11 Message stored in FIFO 1. - bit_offset: 6 - bit_size: 2 - - name: FIDX - description: Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. - bit_offset: 8 - bit_size: 7 - - name: FLST - description: Filter List. Indicates the filter list of the matching filter element. 0 Standard Filter List 1 Extended Filter List. - bit_offset: 15 - bit_size: 1 -fieldset/IE: - description: MCAN Interrupt Enable. - fields: - - name: RF0NE - description: Rx FIFO 0 New Message Enable. - bit_offset: 0 - bit_size: 1 - - name: RF0WE - description: Rx FIFO 0 Watermark Reached Enable. - bit_offset: 1 - bit_size: 1 - - name: RF0FE - description: Rx FIFO 0 Full Enable. - bit_offset: 2 - bit_size: 1 - - name: RF0LE - description: Rx FIFO 0 Message Lost Enable. - bit_offset: 3 - bit_size: 1 - - name: RF1NE - description: Rx FIFO 1 New Message Enable. - bit_offset: 4 - bit_size: 1 - - name: RF1WE - description: Rx FIFO 1 Watermark Reached Enable. - bit_offset: 5 - bit_size: 1 - - name: RF1FE - description: Rx FIFO 1 Full Enable. - bit_offset: 6 - bit_size: 1 - - name: RF1LE - description: Rx FIFO 1 Message Lost Enable. - bit_offset: 7 - bit_size: 1 - - name: HPME - description: High Priority Message Enable. + - name: HPME + description: High Priority Message Enable. bit_offset: 8 bit_size: 1 - name: TCE @@ -1221,6 +945,33 @@ fieldset/ILS: description: Access to Reserved Address Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1. bit_offset: 29 bit_size: 1 +fieldset/IMASK: + description: Interrupt mask. + fields: + - name: INTL0 + description: MCAN Interrupt Line 0 mask. + bit_offset: 0 + bit_size: 1 + - name: INTL1 + description: MCAN Interrupt Line 1 mask. + bit_offset: 1 + bit_size: 1 + - name: SEC + description: Message RAM SEC interrupt mask. + bit_offset: 2 + bit_size: 1 + - name: DED + description: Massage RAM DED interrupt mask. + bit_offset: 3 + bit_size: 1 + - name: EXT_TS_CNTR_OVFL + description: External Timestamp Counter Overflow interrupt mask. + bit_offset: 4 + bit_size: 1 + - name: WAKEUP + description: Clock Stop Wake Up interrupt mask. + bit_offset: 5 + bit_size: 1 fieldset/IR: description: MCAN Interrupt Register. fields: @@ -1340,264 +1091,298 @@ fieldset/IR: description: Access to Reserved Address 0 No access to reserved address occurred 1 Access to reserved address occurred. bit_offset: 29 bit_size: 1 -fieldset/NBTP: - description: MCAN Nominal Bit Timing and Prescaler Register. - fields: - - name: NTSEG2 - description: Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 0 - bit_size: 7 - - name: NTSEG1 - description: Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 8 - bit_size: 8 - - name: NBRP - description: Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 16 - bit_size: 9 - - name: NSJW - description: Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 25 - bit_size: 7 -fieldset/NDAT: - description: MCAN New Data 1. +fieldset/ISET: + description: Interrupt set. fields: - - name: ND - description: New Data RX Buffer 0 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + - name: INTL0 + description: Set MCAN Interrupt Line 0. bit_offset: 0 bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/PSR: - description: MCAN Protocol Status Register. - fields: - - name: LEC - description: 'Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ''0'' when a message has been transferred (reception or transmission) without error. 0 No Error: No error occurred since LEC has been reset by successful reception or transmission. 1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2 Form Error: A fixed format part of a received frame has the wrong format. 3 AckError: The message transmitted by the MCAN was not acknowledged by another node. 4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ''1''), but the monitored bus value was dominant. 5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ''0''), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ''7''. When the LEC shows the value ''7'', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.' - bit_offset: 0 - bit_size: 3 - - name: ACT - description: 'Node Activity. Monitors the module''s CAN communication state. 00 Synchronizing - node is synchronizing on CAN communication 01 Idle - node is neither receiver nor transmitter 10 Receiver - node is operating as receiver 11 Transmitter - node is operating as transmitter Note: ACT is set to "00" by a Protocol Exception Event.' + - name: INTL1 + description: Set MCAN Interrupt Line 1. + bit_offset: 1 + bit_size: 1 + - name: SEC + description: Set Message RAM SEC interrupt. + bit_offset: 2 + bit_size: 1 + - name: DED + description: Set Message RAM DED interrupt. bit_offset: 3 - bit_size: 2 - - name: EP - description: Error Passive 0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1 The M_CAN is in the Error_Passive state. + bit_size: 1 + - name: EXT_TS_CNTR_OVFL + description: Set External Timestamp Counter Overflow interrupt. + bit_offset: 4 + bit_size: 1 + - name: WAKEUP + description: Set Clock Stop Wake Up interrupt. bit_offset: 5 bit_size: 1 - - name: EW - description: Warning Status 0 Both error counters are below the Error_Warning limit of 96 1 At least one of error counter has reached the Error_Warning limit of 96. - bit_offset: 6 - bit_size: 1 - - name: BO - description: Bus_Off Status 0 The M_CAN is not Bus_Off 1 The M_CAN is in Bus_Off state. - bit_offset: 7 - bit_size: 1 - - name: DLEC - description: Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. - bit_offset: 8 - bit_size: 3 - - name: RESI - description: ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its ESI flag set 1 Last received CAN FD message had its ESI flag set. - bit_offset: 11 - bit_size: 1 - - name: RBRS - description: BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its BRS flag set 1 Last received CAN FD message had its BRS flag set. - bit_offset: 12 - bit_size: 1 - - name: RFDF - description: Received a CAN FD Message. This bit is set independent of acceptance filtering. 0 Since this bit was reset by the CPU, no CAN FD message has been received 1 Message in CAN FD format with FDF flag set has been received. - bit_offset: 13 - bit_size: 1 - - name: PXE - description: Protocol Exception Event 0 No protocol exception event occurred since last read access 1 Protocol exception event occurred. - bit_offset: 14 - bit_size: 1 - - name: TDCV - description: Transmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. - bit_offset: 16 - bit_size: 7 -fieldset/PWREN: - description: Power enable. +fieldset/MCANERR_AGGR_ENABLE_CLR: + description: MCAN Error Aggregator Enable Clear Register. fields: - - name: ENABLE - description: Enable the power. + - name: ENABLE_PARITY_CLR + description: Write 1 to disable parity errors. Reads return the corresponding enable bit's current value. bit_offset: 0 bit_size: 1 - - name: KEY - description: KEY to allow Power State Change 26h = KEY to allow write access to this register - bit_offset: 24 - bit_size: 8 - enum: PWREN_KEY -fieldset/RSTCTL: - description: Reset Control. + - name: ENABLE_TIMEOUT_CLR + description: Write 1 to disable timeout errors. Reads return the corresponding enable bit's current value. + bit_offset: 1 + bit_size: 1 +fieldset/MCANERR_AGGR_ENABLE_SET: + description: MCAN Error Aggregator Enable Set Register. fields: - - name: RESETASSERT - description: Assert reset to the peripheral. + - name: ENABLE_PARITY_SET + description: Write 1 to enable parity errors. Reads return the corresponding enable bit's current value. bit_offset: 0 bit_size: 1 - - name: RESETSTKYCLR - description: Clear the RESETSTKY bit in the STAT register. + - name: ENABLE_TIMEOUT_SET + description: Write 1 to enable timeout errors. Reads return the corresponding enable bit's current value. bit_offset: 1 bit_size: 1 - - name: KEY - description: Unlock key B1h = KEY to allow write access to this register - bit_offset: 24 - bit_size: 8 - enum: RESET_KEY -fieldset/RWD: - description: MCAN RAM Watchdog. +fieldset/MCANERR_AGGR_STATUS_CLR: + description: MCAN Error Aggregator Status Clear Register. fields: - - name: WDC - description: Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + - name: AGGR_PARITY_ERR + description: Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. bit_offset: 0 - bit_size: 8 - - name: WDV - description: Watchdog Value. Acutal Message RAM Watchdog Counter Value. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Master Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock. - bit_offset: 8 - bit_size: 8 -fieldset/RXBC: - description: MCAN Rx Buffer Configuration. + bit_size: 2 + - name: SVBUS_TIMEOUT + description: Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. + bit_offset: 2 + bit_size: 2 +fieldset/MCANERR_AGGR_STATUS_SET: + description: MCAN Error Aggregator Status Set Register. fields: - - name: RBSA - description: Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +I466. + - name: AGGR_PARITY_ERR + description: Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field increments it by the value provided. + bit_offset: 0 + bit_size: 2 + - name: SVBUS_TIMEOUT + description: Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field increments it by the value provided. bit_offset: 2 - bit_size: 14 -fieldset/RXESC: - description: MCAN Rx Buffer / FIFO Element Size Configuration. + bit_size: 2 +fieldset/MCANERR_CTRL: + description: MCAN ECC Control. fields: - - name: F0DS - description: 'Rx FIFO 0 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame''s data field is ignored. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + - name: ECC_ENABLE + description: Enable ECC Generation. bit_offset: 0 - bit_size: 3 - - name: F1DS - description: 'Rx FIFO 1 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame''s data field is ignored. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + bit_size: 1 + - name: ECC_CHECK + description: Enable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'. + bit_offset: 1 + bit_size: 1 + - name: ENABLE_RMW + description: Enable read-modify-write on partial word writes. + bit_offset: 2 + bit_size: 1 + - name: FORCE_SEC + description: Force single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. + bit_offset: 3 + bit_size: 1 + - name: FORCE_DED + description: Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. bit_offset: 4 - bit_size: 3 - - name: RBDS - description: 'Rx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame''s data field is ignored. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + bit_size: 1 + - name: FORCE_N_ROW + description: Enable single/double-bit error on the next RAM read, regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode, this applies to writes as well as reads. + bit_offset: 5 + bit_size: 1 + - name: ERROR_ONCE + description: If this bit is set, the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled, this error will be cleared the cycle following the read when the data is corrected. For double-bit errors, the FORCE_DED bit will be cleared the cycle following the double-bit error. Any subsequent reads will not force an error. + bit_offset: 6 + bit_size: 1 + - name: CHECK_SVBUS_TIMEOUT + description: Enables Serial VBUS timeout mechanism. bit_offset: 8 - bit_size: 3 -fieldset/RXF0A: - description: MCAN Rx FIFO 0 Acknowledge. + bit_size: 1 +fieldset/MCANERR_DED_ENABLE_CLR: + description: MCAN Double Error Detected Interrupt Enable Clear Register. fields: - - name: F0AI - description: Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + - name: MSGMEM_ENABLE_CLR + description: Message RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. bit_offset: 0 - bit_size: 6 -fieldset/RXF0C: - description: MCAN Rx FIFO 0 Configuration. - fields: - - name: F0SA - description: Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 2 - bit_size: 14 - - name: F0S - description: Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1. 0 No Rx FIFO 0 1-64 Number of Rx FIFO 0 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 16 - bit_size: 7 - - name: F0WM - description: Rx FIFO 0 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 24 - bit_size: 7 - - name: F0OM - description: FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode. 0 FIFO 0 blocking mode 1 FIFO 0 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 31 bit_size: 1 -fieldset/RXF0S: - description: MCAN Rx FIFO 0 Status. +fieldset/MCANERR_DED_ENABLE_SET: + description: MCAN Double Error Detected Interrupt Enable Set Register. fields: - - name: F0FL - description: Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64. + - name: MSGMEM_ENABLE_SET + description: Message RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. bit_offset: 0 - bit_size: 7 - - name: F0GI - description: Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63. - bit_offset: 8 - bit_size: 6 - - name: F0PI - description: Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63. - bit_offset: 16 - bit_size: 6 - - name: F0F - description: Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full. - bit_offset: 24 - bit_size: 1 - - name: RF0L - description: 'Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when RXF0C.F0OM = ''1'' will not set this flag.' - bit_offset: 25 bit_size: 1 -fieldset/RXF1A: - description: MCAN Rx FIFO 1 Acknowledge. +fieldset/MCANERR_DED_EOI: + description: MCAN Double Error Detected End of Interrupt Register. fields: - - name: F1AI - description: Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + - name: EOI_WR + description: Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_DED goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. bit_offset: 0 - bit_size: 6 -fieldset/RXF1C: - description: MCAN Rx FIFO 1 Configuration. + bit_size: 1 +fieldset/MCANERR_DED_STATUS: + description: MCAN Double Error Detected Interrupt Status Register. fields: - - name: F1SA - description: Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address). - bit_offset: 2 - bit_size: 14 - - name: F1S - description: Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1. 0 No Rx FIFO 1 1-64 Number of Rx FIFO 1 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 16 - bit_size: 7 - - name: F1WM - description: Rx FIFO 1 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 24 - bit_size: 7 - - name: F1OM - description: FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode. 0 FIFO 1 blocking mode 1 FIFO 1 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 31 + - name: MSGMEM_PEND + description: Message RAM DED Interrupt Pending 0 No DED interrupt is pending 1 DED interrupt is pending. + bit_offset: 0 bit_size: 1 -fieldset/RXF1S: - description: MCAN Rx FIFO 1 Status. +fieldset/MCANERR_ERR_CTRL2: + description: MCAN ECC Error Control 2 Register. fields: - - name: F1FL - description: Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64. + - name: ECC_BIT1 + description: Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set. bit_offset: 0 - bit_size: 7 - - name: F1GI - description: Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63. - bit_offset: 8 - bit_size: 6 - - name: F1PI - description: Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63. + bit_size: 16 + - name: ECC_BIT2 + description: Second column/data bit that needs to be flipped when FORCE_DED is set. bit_offset: 16 - bit_size: 6 - - name: F1F - description: Rx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full. - bit_offset: 24 - bit_size: 1 - - name: RF1L - description: 'Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = ''1'' will not set this flag.' - bit_offset: 25 - bit_size: 1 - - name: DMS - description: Debug Message Status 00 Idle state, wait for reception of debug messages 01 Debug message A received 10 Debug messages A, B received 11 Debug messages A, B, C received. - bit_offset: 30 - bit_size: 2 -fieldset/SIDFC: - description: MCAN Standard ID Filter Configuration. + bit_size: 16 +fieldset/MCANERR_ERR_STAT1: + description: MCAN ECC Error Status 1 Register. fields: - - name: FLSSA - description: Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address). + - name: ECC_SEC + description: Single Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared. 0 No single-bit error detected 1 One single-bit error was detected and corrected 2 Two single-bit errors were detected and corrected 3 Three single-bit errors were detected and corrected A write of a non-zero value to this bit field increments it by the value provided. + bit_offset: 0 + bit_size: 2 + - name: ECC_DED + description: Double Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared. 0 No double-bit error detected 1 One double-bit error was detected 2 Two double-bit errors were detected 3 Three double-bit errors were detected A write of a non-zero value to this bit field increments it by the value provided. bit_offset: 2 - bit_size: 14 - - name: LSS - description: List Size Standard 0 No standard Message ID filter 1-128 Number of standard Message ID filter elements >128 Values greater than 128 are interpreted as 128. + bit_size: 2 + - name: ECC_OTHER + description: SEC While Writeback Error Status 0 No SEC error while writeback pending 1 Indicates that successive single-bit errors have occurred while a writeback is still pending. + bit_offset: 4 + bit_size: 1 + - name: CTRL_REG_ERROR + description: Control Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to re-write these registers to a known state. A write of 1 will set this interrupt flag. + bit_offset: 7 + bit_size: 1 + - name: CLR_ECC_SEC + description: Clear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided. + bit_offset: 8 + bit_size: 2 + - name: CLR_ECC_DED + description: Clear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided. + bit_offset: 10 + bit_size: 2 + - name: CLR_ECC_OTHER + description: Writing a '1' clears the ECC_OTHER bit. + bit_offset: 12 + bit_size: 1 + - name: CLR_CTRL_REG_ERROR + description: Writing a '1' clears the CTRL_REG_ERROR bit. + bit_offset: 15 + bit_size: 1 + - name: ECC_BIT1 + description: ECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error. 0 Bit 0 is in error 1 Bit 1 is in error 2 Bit 2 is in error 3 Bit 3 is in error ... 31 Bit 31 is in error >32 Invalid. bit_offset: 16 - bit_size: 8 -fieldset/STAT: - description: Status Register. + bit_size: 16 +fieldset/MCANERR_ERR_STAT3: + description: MCAN ECC Error Status 3 Register. fields: - - name: RESETSTKY - description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + - name: WB_PEND + description: Delayed Write Back Pending Status 0 No write back pending 1 An ECC data correction write back is pending. + bit_offset: 0 + bit_size: 1 + - name: SVBUS_TIMEOUT + description: Serial VBUS Timeout Flag. Write 1 to set. + bit_offset: 1 + bit_size: 1 + - name: CLR_SVBUS_TIMEOUT + description: Write 1 to clear the Serial VBUS Timeout Flag. + bit_offset: 9 + bit_size: 1 +fieldset/MCANERR_REV: + description: MCAN Error Aggregator Revision Register. + fields: + - name: REVMIN + description: Minor Revision of the Error Aggregator. + bit_offset: 0 + bit_size: 6 + - name: REVMAJ + description: Major Revision of the Error Aggregator. + bit_offset: 8 + bit_size: 3 + - name: MODULE_ID + description: Module Identification Number. + bit_offset: 16 + bit_size: 12 + - name: SCHEME + description: PID Register Scheme. + bit_offset: 30 + bit_size: 2 +fieldset/MCANERR_SEC_ENABLE_CLR: + description: MCAN Single Error Corrected Interrupt Enable Clear Register. + fields: + - name: MSGMEM_ENABLE_CLR + description: Message RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. + bit_offset: 0 + bit_size: 1 +fieldset/MCANERR_SEC_ENABLE_SET: + description: MCAN Single Error Corrected Interrupt Enable Set Register. + fields: + - name: MSGMEM_ENABLE_SET + description: Message RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. + bit_offset: 0 + bit_size: 1 +fieldset/MCANERR_SEC_EOI: + description: MCAN Single Error Corrected End of Interrupt Register. + fields: + - name: EOI_WR + description: Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_SEC goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. + bit_offset: 0 + bit_size: 1 +fieldset/MCANERR_SEC_STATUS: + description: MCAN Single Error Corrected Interrupt Status Register. + fields: + - name: MSGMEM_PEND + description: Message RAM SEC Interrupt Pending 0 No SEC interrupt is pending 1 SEC interrupt is pending. + bit_offset: 0 + bit_size: 1 +fieldset/MCANERR_STAT: + description: MCAN Error Misc Status. + fields: + - name: NUM_RAMS + description: Number of RAMs. Number of ECC RAMs serviced by the aggregator. + bit_offset: 0 + bit_size: 11 +fieldset/MCANERR_VECTOR: + description: MCAN ECC Vector Register. + fields: + - name: ECC_VECTOR + description: ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address. 0x000 Message RAM ECC controller is selected Others Reserved (do not use) Subsequent writes through the SVBUS (offsets 0x10 - 0x3B) have a delayed completion. To avoid conflicts, perform a read back of a register within this range after writing. + bit_offset: 0 + bit_size: 11 + - name: RD_SVBUS + description: Read Trigger. + bit_offset: 15 + bit_size: 1 + - name: RD_SVBUS_ADDRESS + description: Read Address Offset. bit_offset: 16 + bit_size: 8 + - name: RD_SVBUS_DONE + description: Read Completion Flag. + bit_offset: 24 bit_size: 1 -fieldset/SUBSYS_CLKCTL: +fieldset/MCANERR_WRAP_REV: + description: MCAN ECC Wrapper Revision Register. + fields: + - name: REVMIN + description: Minor Revision of the Error Aggregator. + bit_offset: 0 + bit_size: 6 + - name: REVMAJ + description: Major Revision of the Error Aggregator. + bit_offset: 8 + bit_size: 3 + - name: MODULE_ID + description: Module Identification Number. + bit_offset: 16 + bit_size: 12 + - name: SCHEME + description: PID Register Scheme. + bit_offset: 30 + bit_size: 2 +fieldset/MCANSS_CLKCTL: description: MCAN-SS clock stop control register. fields: - name: STOPREQ @@ -1612,7 +1397,7 @@ fieldset/SUBSYS_CLKCTL: description: Setting this bit enables the glitch filter on MCAN RXD input, which wakes up the MCAN controller to exit clock gating. bit_offset: 8 bit_size: 1 -fieldset/SUBSYS_CLKDIV: +fieldset/MCANSS_CLKDIV: description: Clock divider. fields: - name: RATIO @@ -1620,292 +1405,1705 @@ fieldset/SUBSYS_CLKDIV: bit_offset: 0 bit_size: 2 enum: RATIO -fieldset/SUBSYS_CLKEN: +fieldset/MCANSS_CLKEN: description: MCAN module clock enable. fields: - name: CLK_REQEN description: MCAN functional and MCAN/MCANSS MMR clock request enable bit. bit_offset: 0 bit_size: 1 -fieldset/SUBSYS_CLKSTS: +fieldset/MCANSS_CLKSTS: description: MCANSS clock stop status register. fields: - - name: CLKSTOP_ACKSTS - description: Clock stop acknowledge status from MCAN IP. + - name: CLKSTOP_ACKSTS + description: Clock stop acknowledge status from MCAN IP. + bit_offset: 0 + bit_size: 1 + enum: CLKSTOP_ACKSTS + - name: STOPREQ_HW_OVR + description: MCANSS clock stop HW override status bit. This bit indicates when the MCANSS_CLKCTL.STOPREQ bit has been cleared by HW when a clock-stop wake-up event via CAN RX activity is trigged. + bit_offset: 4 + bit_size: 1 + enum: STOPREQ_HW_OVR + - name: CCLKDONE + description: This bit indicates the status of MCAN contoller clock request from GPRCM. + bit_offset: 8 + bit_size: 1 + enum: CCLKDONE +fieldset/MCANSS_CTRL: + description: MCAN Subsystem Control Register. + fields: + - name: DBGSUSP_FREE + description: Debug Suspend Free Bit. Enables debug suspend. 0 Disable debug suspend 1 Enable debug suspend. + bit_offset: 3 + bit_size: 1 + - name: WAKEUPREQEN + description: Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity. 0 Disable wakeup request 1 Enables wakeup request. + bit_offset: 4 + bit_size: 1 + - name: AUTOWAKEUP + description: Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up, on an enabled wakeup request. 0 Disable the automatic write to CCCR.INIT 1 Enable the automatic write to CCCR.INIT. + bit_offset: 5 + bit_size: 1 + - name: EXT_TS_CNTR_EN + description: External Timestamp Counter Enable. 0 External timestamp counter disabled 1 External timestamp counter enabled. + bit_offset: 6 + bit_size: 1 +fieldset/MCANSS_EOI: + description: MCAN Subsystem End of Interrupt. + fields: + - name: EOI + description: End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1, another interrupt is generated. 0x00 External TS Interrupt is cleared 0x01 MCAN(0) interrupt is cleared 0x02 MCAN(1) interrupt is cleared Other writes are ignored. + bit_offset: 0 + bit_size: 8 +fieldset/MCANSS_EXT_TS_PRESCALER: + description: MCAN Subsystem External Timestamp Prescaler 0. + fields: + - name: PRESCALER + description: External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value, except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001. + bit_offset: 0 + bit_size: 24 +fieldset/MCANSS_EXT_TS_UNSERVICED_INTR_CNTR: + description: MCAN Subsystem External Timestamp Unserviced Interrupts Counter. + fields: + - name: EXT_TS_INTR_CNTR + description: External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1, an MCANSS_EOI write of '1' to bit 0 will issue another interrupt. The status of this bit field is affected by the MCANSS_IRS.EXT_TS_CNTR_OVFL bit field. + bit_offset: 0 + bit_size: 5 +fieldset/MCANSS_ICS: + description: MCAN Subsystem Interrupt Clear Shadow Register. + fields: + - name: EXT_TS_CNTR_OVFL + description: External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IRS.EXT_TS_CNTR_OVFL bit. + bit_offset: 0 + bit_size: 1 +fieldset/MCANSS_IE: + description: MCAN Subsystem Interrupt Enable Register. + fields: + - name: EXT_TS_CNTR_OVFL + description: External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit. + bit_offset: 0 + bit_size: 1 +fieldset/MCANSS_IECS: + description: MCAN Subsystem Interrupt Enable Clear Shadow Register. + fields: + - name: EXT_TS_CNTR_OVFL + description: External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IES.EXT_TS_CNTR_OVFL bit. + bit_offset: 0 + bit_size: 1 +fieldset/MCANSS_IES: + description: MCAN Subsystem Interrupt Enable Status. + fields: + - name: EXT_TS_CNTR_OVFL + description: External Timestamp Counter Overflow Interrupt Enable Status. To set, use the CANSS_IE.EXT_TS_CNTR_OVFL bit. To clear, use the MCANSS_IECS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter overflow interrupt is not enabled 1 External timestamp counter overflow interrupt is enabled. + bit_offset: 0 + bit_size: 1 +fieldset/MCANSS_IRS: + description: MCAN Subsystem Interrupt Raw Satus Register. + fields: + - name: EXT_TS_CNTR_OVFL + description: External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear, use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter has not overflowed 1 External timestamp counter has overflowed When this bit is set to '1' by HW or SW, the MCANSS_EXT_TS_UNSERVICED_INTR_CNTR.EXT_TS_INTR_CNTR bit field will increment by 1. + bit_offset: 0 + bit_size: 1 +fieldset/MCANSS_PID: + description: MCAN Subsystem Revision Register. + fields: + - name: MINOR + description: Minor Revision of the MCAN Subsystem. + bit_offset: 0 + bit_size: 6 + - name: MAJOR + description: Major Revision of the MCAN Subsystem. + bit_offset: 8 + bit_size: 3 + - name: MODULE_ID + description: Module Identification Number. + bit_offset: 16 + bit_size: 12 + - name: SCHEME + description: PID Register Scheme. + bit_offset: 30 + bit_size: 2 +fieldset/MCANSS_STAT: + description: MCAN Subsystem Status Register. + fields: + - name: RESET + description: Soft Reset Status. 0 Not in reset 1 Reset is in progress. + bit_offset: 0 + bit_size: 1 + - name: MEM_INIT_DONE + description: Memory Initialization Done. 0 Message RAM initialization is in progress 1 Message RAM is initialized for use. + bit_offset: 1 + bit_size: 1 + - name: ENABLE_FDOE + description: Flexible Datarate Operation Enable. Determines whether CAN FD operation may be enabled via the MCAN core CCCR.FDOE bit (bit 8) or if only standard CAN operation is possible with this instance of the MCAN. 0 MCAN is only capable of standard CAN communication 1 MCAN may be configured to perform CAN FD communication. + bit_offset: 2 + bit_size: 1 +fieldset/MIS: + description: Masked interrupt status. + fields: + - name: INTL0 + description: Masked MCAN Interrupt Line 0. + bit_offset: 0 + bit_size: 1 + - name: INTL1 + description: Masked MCAN Interrupt Line 1. + bit_offset: 1 + bit_size: 1 + - name: SEC + description: Masked Message RAM SEC interrupt. + bit_offset: 2 + bit_size: 1 + - name: DED + description: Masked Message RAM DED interrupt. + bit_offset: 3 + bit_size: 1 + - name: EXT_TS_CNTR_OVFL + description: Masked External Timestamp Counter Overflow interrupt. + bit_offset: 4 + bit_size: 1 + - name: WAKEUP + description: Masked Clock Stop Wake Up interrupt. + bit_offset: 5 + bit_size: 1 +fieldset/NBTP: + description: MCAN Nominal Bit Timing and Prescaler Register. + fields: + - name: NTSEG2 + description: Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 0 + bit_size: 7 + - name: NTSEG1 + description: Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 8 + bit_size: 8 + - name: NBRP + description: Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 16 + bit_size: 9 + - name: NSJW + description: Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 25 + bit_size: 7 +fieldset/NDAT1: + description: MCAN New Data 1. + fields: + - name: ND0 + description: New Data RX Buffer 0 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 0 + bit_size: 1 + - name: ND1 + description: New Data RX Buffer 1 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 1 + bit_size: 1 + - name: ND2 + description: New Data RX Buffer 2 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 2 + bit_size: 1 + - name: ND3 + description: New Data RX Buffer 3 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 3 + bit_size: 1 + - name: ND4 + description: New Data RX Buffer 4 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 4 + bit_size: 1 + - name: ND5 + description: New Data RX Buffer 5 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 5 + bit_size: 1 + - name: ND6 + description: New Data RX Buffer 6 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 6 + bit_size: 1 + - name: ND7 + description: New Data RX Buffer 7 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 7 + bit_size: 1 + - name: ND8 + description: New Data RX Buffer 8 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 8 + bit_size: 1 + - name: ND9 + description: New Data RX Buffer 9 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 9 + bit_size: 1 + - name: ND10 + description: New Data RX Buffer 10 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 10 + bit_size: 1 + - name: ND11 + description: New Data RX Buffer 11 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 11 + bit_size: 1 + - name: ND12 + description: New Data RX Buffer 12 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 12 + bit_size: 1 + - name: ND13 + description: New Data RX Buffer 13 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 13 + bit_size: 1 + - name: ND14 + description: New Data RX Buffer 14 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 14 + bit_size: 1 + - name: ND15 + description: New Data RX Buffer 15 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 15 + bit_size: 1 + - name: ND16 + description: New Data RX Buffer 16 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 16 + bit_size: 1 + - name: ND17 + description: New Data RX Buffer 17 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 17 + bit_size: 1 + - name: ND18 + description: New Data RX Buffer 18 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 18 + bit_size: 1 + - name: ND19 + description: New Data RX Buffer 19 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 19 + bit_size: 1 + - name: ND20 + description: New Data RX Buffer 20 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 20 + bit_size: 1 + - name: ND21 + description: New Data RX Buffer 21 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 21 + bit_size: 1 + - name: ND22 + description: New Data RX Buffer 22 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 22 + bit_size: 1 + - name: ND23 + description: New Data RX Buffer 23 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 23 + bit_size: 1 + - name: ND24 + description: New Data RX Buffer 24 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 24 + bit_size: 1 + - name: ND25 + description: New Data RX Buffer 25 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 25 + bit_size: 1 + - name: ND26 + description: New Data RX Buffer 26 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 26 + bit_size: 1 + - name: ND27 + description: New Data RX Buffer 27 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 27 + bit_size: 1 + - name: ND28 + description: New Data RX Buffer 28 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 28 + bit_size: 1 + - name: ND29 + description: New Data RX Buffer 29 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 29 + bit_size: 1 + - name: ND30 + description: New Data RX Buffer 30 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 30 + bit_size: 1 + - name: ND31 + description: New Data RX Buffer 31 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 31 + bit_size: 1 +fieldset/NDAT2: + description: MCAN New Data 2. + fields: + - name: ND32 + description: New Data RX Buffer 32 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 0 + bit_size: 1 + - name: ND33 + description: New Data RX Buffer 33 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 1 + bit_size: 1 + - name: ND34 + description: New Data RX Buffer 34 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 2 + bit_size: 1 + - name: ND35 + description: New Data RX Buffer 35 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 3 + bit_size: 1 + - name: ND36 + description: New Data RX Buffer 36 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 4 + bit_size: 1 + - name: ND37 + description: New Data RX Buffer 37 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 5 + bit_size: 1 + - name: ND38 + description: New Data RX Buffer 38 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 6 + bit_size: 1 + - name: ND39 + description: New Data RX Buffer 39 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 7 + bit_size: 1 + - name: ND40 + description: New Data RX Buffer 40 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 8 + bit_size: 1 + - name: ND41 + description: New Data RX Buffer 41 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 9 + bit_size: 1 + - name: ND42 + description: New Data RX Buffer 42 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 10 + bit_size: 1 + - name: ND43 + description: New Data RX Buffer 43 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 11 + bit_size: 1 + - name: ND44 + description: New Data RX Buffer 44 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 12 + bit_size: 1 + - name: ND45 + description: New Data RX Buffer 45 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 13 + bit_size: 1 + - name: ND46 + description: New Data RX Buffer 46 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 14 + bit_size: 1 + - name: ND47 + description: New Data RX Buffer 47 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 15 + bit_size: 1 + - name: ND48 + description: New Data RX Buffer 48 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 16 + bit_size: 1 + - name: ND49 + description: New Data RX Buffer 49 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 17 + bit_size: 1 + - name: ND50 + description: New Data RX Buffer 50 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 18 + bit_size: 1 + - name: ND51 + description: New Data RX Buffer 51 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 19 + bit_size: 1 + - name: ND52 + description: New Data RX Buffer 52 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 20 + bit_size: 1 + - name: ND53 + description: New Data RX Buffer 53 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 21 + bit_size: 1 + - name: ND54 + description: New Data RX Buffer 54 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 22 + bit_size: 1 + - name: ND55 + description: New Data RX Buffer 55 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 23 + bit_size: 1 + - name: ND56 + description: New Data RX Buffer 56 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 24 + bit_size: 1 + - name: ND57 + description: New Data RX Buffer 57 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 25 + bit_size: 1 + - name: ND58 + description: New Data RX Buffer 58 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 26 + bit_size: 1 + - name: ND59 + description: New Data RX Buffer 59 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 27 + bit_size: 1 + - name: ND60 + description: New Data RX Buffer 60 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 28 + bit_size: 1 + - name: ND61 + description: New Data RX Buffer 61 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 29 + bit_size: 1 + - name: ND62 + description: New Data RX Buffer 62 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 30 + bit_size: 1 + - name: ND63 + description: New Data RX Buffer 63 0 Rx Buffer not updated 1 Rx Buffer updated from new message. + bit_offset: 31 + bit_size: 1 +fieldset/PSR: + description: MCAN Protocol Status Register. + fields: + - name: LEC + description: 'Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ''0'' when a message has been transferred (reception or transmission) without error. 0 No Error: No error occurred since LEC has been reset by successful reception or transmission. 1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2 Form Error: A fixed format part of a received frame has the wrong format. 3 AckError: The message transmitted by the MCAN was not acknowledged by another node. 4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ''1''), but the monitored bus value was dominant. 5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ''0''), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ''7''. When the LEC shows the value ''7'', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.' + bit_offset: 0 + bit_size: 3 + - name: ACT + description: 'Node Activity. Monitors the module''s CAN communication state. 00 Synchronizing - node is synchronizing on CAN communication 01 Idle - node is neither receiver nor transmitter 10 Receiver - node is operating as receiver 11 Transmitter - node is operating as transmitter Note: ACT is set to "00" by a Protocol Exception Event.' + bit_offset: 3 + bit_size: 2 + - name: EP + description: Error Passive 0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1 The M_CAN is in the Error_Passive state. + bit_offset: 5 + bit_size: 1 + - name: EW + description: Warning Status 0 Both error counters are below the Error_Warning limit of 96 1 At least one of error counter has reached the Error_Warning limit of 96. + bit_offset: 6 + bit_size: 1 + - name: BO + description: Bus_Off Status 0 The M_CAN is not Bus_Off 1 The M_CAN is in Bus_Off state. + bit_offset: 7 + bit_size: 1 + - name: DLEC + description: Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. + bit_offset: 8 + bit_size: 3 + - name: RESI + description: ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its ESI flag set 1 Last received CAN FD message had its ESI flag set. + bit_offset: 11 + bit_size: 1 + - name: RBRS + description: BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its BRS flag set 1 Last received CAN FD message had its BRS flag set. + bit_offset: 12 + bit_size: 1 + - name: RFDF + description: Received a CAN FD Message. This bit is set independent of acceptance filtering. 0 Since this bit was reset by the CPU, no CAN FD message has been received 1 Message in CAN FD format with FDF flag set has been received. + bit_offset: 13 + bit_size: 1 + - name: PXE + description: Protocol Exception Event 0 No protocol exception event occurred since last read access 1 Protocol exception event occurred. + bit_offset: 14 + bit_size: 1 + - name: TDCV + description: Transmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + bit_offset: 16 + bit_size: 7 +fieldset/PWREN: + description: Power enable. + fields: + - name: ENABLE + description: Enable the power. + bit_offset: 0 + bit_size: 1 + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY +fieldset/RIS: + description: Raw interrupt status. + fields: + - name: INTL0 + description: MCAN Interrupt Line 0. + bit_offset: 0 + bit_size: 1 + - name: INTL1 + description: MCAN Interrupt Line 1. + bit_offset: 1 + bit_size: 1 + - name: SEC + description: Message RAM SEC interrupt. + bit_offset: 2 + bit_size: 1 + - name: DED + description: Message RAM DED interrupt. + bit_offset: 3 + bit_size: 1 + - name: EXT_TS_CNTR_OVFL + description: External Timestamp Counter Overflow interrupt. + bit_offset: 4 + bit_size: 1 + - name: WAKEUP + description: Clock Stop Wake Up interrupt. + bit_offset: 5 + bit_size: 1 +fieldset/RSTCTL: + description: Reset Control. + fields: + - name: RESETASSERT + description: Assert reset to the peripheral. + bit_offset: 0 + bit_size: 1 + - name: RESETSTKYCLR + description: Clear the RESETSTKY bit in the STAT register. + bit_offset: 1 + bit_size: 1 + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY +fieldset/RWD: + description: MCAN RAM Watchdog. + fields: + - name: WDC + description: Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 0 + bit_size: 8 + - name: WDV + description: Watchdog Value. Acutal Message RAM Watchdog Counter Value. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Master Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock. + bit_offset: 8 + bit_size: 8 +fieldset/RXBC: + description: MCAN Rx Buffer Configuration. + fields: + - name: RBSA + description: Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +I466. + bit_offset: 2 + bit_size: 14 +fieldset/RXESC: + description: MCAN Rx Buffer / FIFO Element Size Configuration. + fields: + - name: F0DS + description: 'Rx FIFO 0 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame''s data field is ignored. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + bit_offset: 0 + bit_size: 3 + - name: F1DS + description: 'Rx FIFO 1 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame''s data field is ignored. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + bit_offset: 4 + bit_size: 3 + - name: RBDS + description: 'Rx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame''s data field is ignored. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + bit_offset: 8 + bit_size: 3 +fieldset/RXF0A: + description: MCAN Rx FIFO 0 Acknowledge. + fields: + - name: F0AI + description: Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + bit_offset: 0 + bit_size: 6 +fieldset/RXF0C: + description: MCAN Rx FIFO 0 Configuration. + fields: + - name: F0SA + description: Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 2 + bit_size: 14 + - name: F0S + description: Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1. 0 No Rx FIFO 0 1-64 Number of Rx FIFO 0 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 16 + bit_size: 7 + - name: F0WM + description: Rx FIFO 0 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 24 + bit_size: 7 + - name: F0OM + description: FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode. 0 FIFO 0 blocking mode 1 FIFO 0 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 31 + bit_size: 1 +fieldset/RXF0S: + description: MCAN Rx FIFO 0 Status. + fields: + - name: F0FL + description: Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64. + bit_offset: 0 + bit_size: 7 + - name: F0GI + description: Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63. + bit_offset: 8 + bit_size: 6 + - name: F0PI + description: Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63. + bit_offset: 16 + bit_size: 6 + - name: F0F + description: Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full. + bit_offset: 24 + bit_size: 1 + - name: RF0L + description: 'Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when RXF0C.F0OM = ''1'' will not set this flag.' + bit_offset: 25 + bit_size: 1 +fieldset/RXF1A: + description: MCAN Rx FIFO 1 Acknowledge. + fields: + - name: F1AI + description: Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + bit_offset: 0 + bit_size: 6 +fieldset/RXF1C: + description: MCAN Rx FIFO 1 Configuration. + fields: + - name: F1SA + description: Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address). + bit_offset: 2 + bit_size: 14 + - name: F1S + description: Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1. 0 No Rx FIFO 1 1-64 Number of Rx FIFO 1 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 16 + bit_size: 7 + - name: F1WM + description: Rx FIFO 1 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 24 + bit_size: 7 + - name: F1OM + description: FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode. 0 FIFO 1 blocking mode 1 FIFO 1 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 31 + bit_size: 1 +fieldset/RXF1S: + description: MCAN Rx FIFO 1 Status. + fields: + - name: F1FL + description: Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64. + bit_offset: 0 + bit_size: 7 + - name: F1GI + description: Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63. + bit_offset: 8 + bit_size: 6 + - name: F1PI + description: Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63. + bit_offset: 16 + bit_size: 6 + - name: F1F + description: Rx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full. + bit_offset: 24 + bit_size: 1 + - name: RF1L + description: 'Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = ''1'' will not set this flag.' + bit_offset: 25 + bit_size: 1 + - name: DMS + description: Debug Message Status 00 Idle state, wait for reception of debug messages 01 Debug message A received 10 Debug messages A, B received 11 Debug messages A, B, C received. + bit_offset: 30 + bit_size: 2 +fieldset/SIDFC: + description: MCAN Standard ID Filter Configuration. + fields: + - name: FLSSA + description: Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address). + bit_offset: 2 + bit_size: 14 + - name: LSS + description: List Size Standard 0 No standard Message ID filter 1-128 Number of standard Message ID filter elements >128 Values greater than 128 are interpreted as 128. + bit_offset: 16 + bit_size: 8 +fieldset/STAT: + description: Status Register. + fields: + - name: RESETSTKY + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + bit_offset: 16 + bit_size: 1 +fieldset/TDCR: + description: MCAN Transmitter Delay Compensation Register. + fields: + - name: TDCF + description: Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 0 + bit_size: 7 + - name: TDCO + description: Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 8 + bit_size: 7 +fieldset/TEST: + description: MCAN Test Register. + fields: + - name: LBCK + description: Loop Back Mode 0 Reset value, Loop Back Mode is disabled 1 Loop Back Mode is enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 4 + bit_size: 1 + - name: TX + description: Control of Transmit Pin 00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at CAN TX pin 10 Dominant ('0') level at CAN TX pin 11 Recessive ('1') at CAN TX pin Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 5 + bit_size: 2 + - name: RX + description: Receive Pin. Monitors the actual value of the CAN receive pin. 0 The CAN bus is dominant (CAN RX pin = '0') 1 The CAN bus is recessive (CAN RX pin = '1'). + bit_offset: 7 + bit_size: 1 +fieldset/TOCC: + description: MCAN Timeout Counter Configuration. + fields: + - name: ETOC + description: Enable Timeout Counter 0 Timeout Counter disabled 1 Timeout Counter enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 0 + bit_size: 1 + - name: TOS + description: Timeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00 Continuous operation 01 Timeout controlled by Tx Event FIFO 10 Timeout controlled by Rx FIFO 0 11 Timeout controlled by Rx FIFO 1 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 1 + bit_size: 2 + - name: TOP + description: Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 16 + bit_size: 16 +fieldset/TOCV: + description: MCAN Timeout Counter Value. + fields: + - name: TOC + description: Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. + bit_offset: 0 + bit_size: 16 +fieldset/TSCC: + description: MCAN Timestamp Counter Configuration. + fields: + - name: TSS + description: Timestamp Select 00 Timestamp counter value always 0x0000 01 Timestamp counter value incremented according to TCP 10 External timestamp counter value used 11 Same as "00" Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 0 + bit_size: 2 + - name: TCP + description: 'Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With CAN FD an external counter is required for timestamp generation (TSS = "10"). Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + bit_offset: 16 + bit_size: 4 +fieldset/TSCV: + description: MCAN Timestamp Counter Value. + fields: + - name: TSC + description: 'Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01", the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = "10", TSC reflects the External Timestamp Counter value, and a write access has no impact. Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not caused by write access to MCAN_TSCV.' + bit_offset: 0 + bit_size: 16 +fieldset/TXBAR: + description: MCAN Tx Buffer Add Request. + fields: + - name: AR0 + description: 'Add Request 0. Each Tx Buffer has its own Add Request bit. Writing a ''1'' will set the corresponding Add Request bit; writing a ''0'' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0 No transmission request added 1 Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. Qualified Write is possible only with CCCR.CCE=''0''.' + bit_offset: 0 + bit_size: 1 + - name: AR1 + description: Add Request 1. See description for bit 0. + bit_offset: 1 + bit_size: 1 + - name: AR2 + description: Add Request 2. See description for bit 0. + bit_offset: 2 + bit_size: 1 + - name: AR3 + description: Add Request 3. See description for bit 0. + bit_offset: 3 + bit_size: 1 + - name: AR4 + description: Add Request 4. See description for bit 0. + bit_offset: 4 + bit_size: 1 + - name: AR5 + description: Add Request 5. See description for bit 0. + bit_offset: 5 + bit_size: 1 + - name: AR6 + description: Add Request 6. See description for bit 0. + bit_offset: 6 + bit_size: 1 + - name: AR7 + description: Add Request 7. See description for bit 0. + bit_offset: 7 + bit_size: 1 + - name: AR8 + description: Add Request 8. See description for bit 0. + bit_offset: 8 + bit_size: 1 + - name: AR9 + description: Add Request 9. See description for bit 0. + bit_offset: 9 + bit_size: 1 + - name: AR10 + description: Add Request 10. See description for bit 0. + bit_offset: 10 + bit_size: 1 + - name: AR11 + description: Add Request 11. See description for bit 0. + bit_offset: 11 + bit_size: 1 + - name: AR12 + description: Add Request 12. See description for bit 0. + bit_offset: 12 + bit_size: 1 + - name: AR13 + description: Add Request 13. See description for bit 0. + bit_offset: 13 + bit_size: 1 + - name: AR14 + description: Add Request 14. See description for bit 0. + bit_offset: 14 + bit_size: 1 + - name: AR15 + description: Add Request 15. See description for bit 0. + bit_offset: 15 + bit_size: 1 + - name: AR16 + description: Add Request 16. See description for bit 0. + bit_offset: 16 + bit_size: 1 + - name: AR17 + description: Add Request 17. See description for bit 0. + bit_offset: 17 + bit_size: 1 + - name: AR18 + description: Add Request 18. See description for bit 0. + bit_offset: 18 + bit_size: 1 + - name: AR19 + description: Add Request 19. See description for bit 0. + bit_offset: 19 + bit_size: 1 + - name: AR20 + description: Add Request 20. See description for bit 0. + bit_offset: 20 + bit_size: 1 + - name: AR21 + description: Add Request 21. See description for bit 0. + bit_offset: 21 + bit_size: 1 + - name: AR22 + description: Add Request 22. See description for bit 0. + bit_offset: 22 + bit_size: 1 + - name: AR23 + description: Add Request 23. See description for bit 0. + bit_offset: 23 + bit_size: 1 + - name: AR24 + description: Add Request 24. See description for bit 0. + bit_offset: 24 + bit_size: 1 + - name: AR25 + description: Add Request 25. See description for bit 0. + bit_offset: 25 + bit_size: 1 + - name: AR26 + description: Add Request 26. See description for bit 0. + bit_offset: 26 + bit_size: 1 + - name: AR27 + description: Add Request 27. See description for bit 0. + bit_offset: 27 + bit_size: 1 + - name: AR28 + description: Add Request 28. See description for bit 0. + bit_offset: 28 + bit_size: 1 + - name: AR29 + description: Add Request 29. See description for bit 0. + bit_offset: 29 + bit_size: 1 + - name: AR30 + description: Add Request 30. See description for bit 0. + bit_offset: 30 + bit_size: 1 + - name: AR31 + description: Add Request 31. See description for bit 0. + bit_offset: 31 + bit_size: 1 +fieldset/TXBC: + description: MCAN Tx Buffer Configuration. + fields: + - name: TBSA + description: Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 2 + bit_size: 14 + - name: NDTB + description: 'Number of Dedicated Transmit Buffers 0 No Dedicated Tx Buffers 1-32 Number of Dedicated Tx Buffers >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + bit_offset: 16 + bit_size: 6 + - name: TFQS + description: 'Transmit FIFO/Queue Size 0 No Tx FIFO/Queue 1-32 Number of Tx Buffers used for Tx FIFO/Queue >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + bit_offset: 24 + bit_size: 6 + - name: TFQM + description: Tx FIFO/Queue Mode 0 Tx FIFO operation 1 Tx Queue operation Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. + bit_offset: 30 + bit_size: 1 +fieldset/TXBCF: + description: MCAN Tx Buffer Cancellation Finished. + fields: + - name: CF0 + description: Cancellation Finished 0. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmit buffer cancellation 1 Transmit buffer cancellation finished. + bit_offset: 0 + bit_size: 1 + - name: CF1 + description: Cancellation Finished 1. See description for bit 0. + bit_offset: 1 + bit_size: 1 + - name: CF2 + description: Cancellation Finished 2. See description for bit 0. + bit_offset: 2 + bit_size: 1 + - name: CF3 + description: Cancellation Finished 3. See description for bit 0. + bit_offset: 3 + bit_size: 1 + - name: CF4 + description: Cancellation Finished 4. See description for bit 0. + bit_offset: 4 + bit_size: 1 + - name: CF5 + description: Cancellation Finished 5. See description for bit 0. + bit_offset: 5 + bit_size: 1 + - name: CF6 + description: Cancellation Finished 6. See description for bit 0. + bit_offset: 6 + bit_size: 1 + - name: CF7 + description: Cancellation Finished 7. See description for bit 0. + bit_offset: 7 + bit_size: 1 + - name: CF8 + description: Cancellation Finished 8. See description for bit 0. + bit_offset: 8 + bit_size: 1 + - name: CF9 + description: Cancellation Finished 9. See description for bit 0. + bit_offset: 9 + bit_size: 1 + - name: CF10 + description: Cancellation Finished 10. See description for bit 0. + bit_offset: 10 + bit_size: 1 + - name: CF11 + description: Cancellation Finished 11. See description for bit 0. + bit_offset: 11 + bit_size: 1 + - name: CF12 + description: Cancellation Finished 12. See description for bit 0. + bit_offset: 12 + bit_size: 1 + - name: CF13 + description: Cancellation Finished 13. See description for bit 0. + bit_offset: 13 + bit_size: 1 + - name: CF14 + description: Cancellation Finished 14. See description for bit 0. + bit_offset: 14 + bit_size: 1 + - name: CF15 + description: Cancellation Finished 15. See description for bit 0. + bit_offset: 15 + bit_size: 1 + - name: CF16 + description: Cancellation Finished 16. See description for bit 0. + bit_offset: 16 + bit_size: 1 + - name: CF17 + description: Cancellation Finished 17. See description for bit 0. + bit_offset: 17 + bit_size: 1 + - name: CF18 + description: Cancellation Finished 18. See description for bit 0. + bit_offset: 18 + bit_size: 1 + - name: CF19 + description: Cancellation Finished 19. See description for bit 0. + bit_offset: 19 + bit_size: 1 + - name: CF20 + description: Cancellation Finished 20. See description for bit 0. + bit_offset: 20 + bit_size: 1 + - name: CF21 + description: Cancellation Finished 21. See description for bit 0. + bit_offset: 21 + bit_size: 1 + - name: CF22 + description: Cancellation Finished 22. See description for bit 0. + bit_offset: 22 + bit_size: 1 + - name: CF23 + description: Cancellation Finished 23. See description for bit 0. + bit_offset: 23 + bit_size: 1 + - name: CF24 + description: Cancellation Finished 24. See description for bit 0. + bit_offset: 24 + bit_size: 1 + - name: CF25 + description: Cancellation Finished 25. See description for bit 0. + bit_offset: 25 + bit_size: 1 + - name: CF26 + description: Cancellation Finished 26. See description for bit 0. + bit_offset: 26 + bit_size: 1 + - name: CF27 + description: Cancellation Finished 27. See description for bit 0. + bit_offset: 27 + bit_size: 1 + - name: CF28 + description: Cancellation Finished 28. See description for bit 0. + bit_offset: 28 + bit_size: 1 + - name: CF29 + description: Cancellation Finished 29. See description for bit 0. + bit_offset: 29 + bit_size: 1 + - name: CF30 + description: Cancellation Finished 30. See description for bit 0. + bit_offset: 30 + bit_size: 1 + - name: CF31 + description: Cancellation Finished 31. See description for bit 0. + bit_offset: 31 + bit_size: 1 +fieldset/TXBCIE: + description: MCAN Tx Buffer Cancellation Finished Interrupt Enable. + fields: + - name: CFIE0 + description: Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 0 + bit_size: 1 + - name: CFIE1 + description: Cancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 1 + bit_size: 1 + - name: CFIE2 + description: Cancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 2 + bit_size: 1 + - name: CFIE3 + description: Cancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 3 + bit_size: 1 + - name: CFIE4 + description: Cancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 4 + bit_size: 1 + - name: CFIE5 + description: Cancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 5 + bit_size: 1 + - name: CFIE6 + description: Cancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 6 + bit_size: 1 + - name: CFIE7 + description: Cancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 7 + bit_size: 1 + - name: CFIE8 + description: Cancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 8 + bit_size: 1 + - name: CFIE9 + description: Cancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 9 + bit_size: 1 + - name: CFIE10 + description: Cancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 10 + bit_size: 1 + - name: CFIE11 + description: Cancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 11 + bit_size: 1 + - name: CFIE12 + description: Cancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 12 + bit_size: 1 + - name: CFIE13 + description: Cancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 13 + bit_size: 1 + - name: CFIE14 + description: Cancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 14 + bit_size: 1 + - name: CFIE15 + description: Cancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 15 + bit_size: 1 + - name: CFIE16 + description: Cancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 16 + bit_size: 1 + - name: CFIE17 + description: Cancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 17 + bit_size: 1 + - name: CFIE18 + description: Cancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 18 + bit_size: 1 + - name: CFIE19 + description: Cancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 19 + bit_size: 1 + - name: CFIE20 + description: Cancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 20 + bit_size: 1 + - name: CFIE21 + description: Cancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 21 + bit_size: 1 + - name: CFIE22 + description: Cancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 22 + bit_size: 1 + - name: CFIE23 + description: Cancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 23 + bit_size: 1 + - name: CFIE24 + description: Cancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 24 + bit_size: 1 + - name: CFIE25 + description: Cancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 25 + bit_size: 1 + - name: CFIE26 + description: Cancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 26 + bit_size: 1 + - name: CFIE27 + description: Cancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 27 + bit_size: 1 + - name: CFIE28 + description: Cancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 28 + bit_size: 1 + - name: CFIE29 + description: Cancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 29 + bit_size: 1 + - name: CFIE30 + description: Cancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 30 + bit_size: 1 + - name: CFIE31 + description: Cancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. + bit_offset: 31 + bit_size: 1 +fieldset/TXBCR: + description: MCAN Tx Buffer Cancellation Request. + fields: + - name: CR0 + description: Cancellation Request 0. Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0 No cancellation pending 1 Cancellation pending Qualified Write is possible only with CCCR.CCE='0'. + bit_offset: 0 + bit_size: 1 + - name: CR1 + description: Cancellation Request 1. See description for bit 0. + bit_offset: 1 + bit_size: 1 + - name: CR2 + description: Cancellation Request 2. See description for bit 0. + bit_offset: 2 + bit_size: 1 + - name: CR3 + description: Cancellation Request 3. See description for bit 0. + bit_offset: 3 + bit_size: 1 + - name: CR4 + description: Cancellation Request 4. See description for bit 0. + bit_offset: 4 + bit_size: 1 + - name: CR5 + description: Cancellation Request 5. See description for bit 0. + bit_offset: 5 + bit_size: 1 + - name: CR6 + description: Cancellation Request 6. See description for bit 0. + bit_offset: 6 + bit_size: 1 + - name: CR7 + description: Cancellation Request 7. See description for bit 0. + bit_offset: 7 + bit_size: 1 + - name: CR8 + description: Cancellation Request 8. See description for bit 0. + bit_offset: 8 + bit_size: 1 + - name: CR9 + description: Cancellation Request 9. See description for bit 0. + bit_offset: 9 + bit_size: 1 + - name: CR10 + description: Cancellation Request 10. See description for bit 0. + bit_offset: 10 + bit_size: 1 + - name: CR11 + description: Cancellation Request 11. See description for bit 0. + bit_offset: 11 + bit_size: 1 + - name: CR12 + description: Cancellation Request 12. See description for bit 0. + bit_offset: 12 + bit_size: 1 + - name: CR13 + description: Cancellation Request 13. See description for bit 0. + bit_offset: 13 + bit_size: 1 + - name: CR14 + description: Cancellation Request 14. See description for bit 0. + bit_offset: 14 + bit_size: 1 + - name: CR15 + description: Cancellation Request 15. See description for bit 0. + bit_offset: 15 + bit_size: 1 + - name: CR16 + description: Cancellation Request 16. See description for bit 0. + bit_offset: 16 + bit_size: 1 + - name: CR17 + description: Cancellation Request 17. See description for bit 0. + bit_offset: 17 + bit_size: 1 + - name: CR18 + description: Cancellation Request 18. See description for bit 0. + bit_offset: 18 + bit_size: 1 + - name: CR19 + description: Cancellation Request 19. See description for bit 0. + bit_offset: 19 + bit_size: 1 + - name: CR20 + description: Cancellation Request 20. See description for bit 0. + bit_offset: 20 + bit_size: 1 + - name: CR21 + description: Cancellation Request 21. See description for bit 0. + bit_offset: 21 + bit_size: 1 + - name: CR22 + description: Cancellation Request 22. See description for bit 0. + bit_offset: 22 + bit_size: 1 + - name: CR23 + description: Cancellation Request 23. See description for bit 0. + bit_offset: 23 + bit_size: 1 + - name: CR24 + description: Cancellation Request 24. See description for bit 0. + bit_offset: 24 + bit_size: 1 + - name: CR25 + description: Cancellation Request 25. See description for bit 0. + bit_offset: 25 + bit_size: 1 + - name: CR26 + description: Cancellation Request 26. See description for bit 0. + bit_offset: 26 + bit_size: 1 + - name: CR27 + description: Cancellation Request 27. See description for bit 0. + bit_offset: 27 + bit_size: 1 + - name: CR28 + description: Cancellation Request 28. See description for bit 0. + bit_offset: 28 + bit_size: 1 + - name: CR29 + description: Cancellation Request 29. See description for bit 0. + bit_offset: 29 + bit_size: 1 + - name: CR30 + description: Cancellation Request 30. See description for bit 0. + bit_offset: 30 + bit_size: 1 + - name: CR31 + description: Cancellation Request 31. See description for bit 0. + bit_offset: 31 + bit_size: 1 +fieldset/TXBRP: + description: MCAN Tx Buffer Request Pending. + fields: + - name: TRP0 + description: 'Transmission Request Pending 0. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF - after successful transmission together with the corresponding TXBTO bit - when the transmission has not yet been started at the point of cancellation - when the transmission has been aborted due to lost arbitration - when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0 No transmission request pending 1 Transmission request pending Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset.' + bit_offset: 0 + bit_size: 1 + - name: TRP1 + description: Transmission Request Pending 1. See description for bit 0. + bit_offset: 1 + bit_size: 1 + - name: TRP2 + description: Transmission Request Pending 2. See description for bit 0. + bit_offset: 2 + bit_size: 1 + - name: TRP3 + description: Transmission Request Pending 3. See description for bit 0. + bit_offset: 3 + bit_size: 1 + - name: TRP4 + description: Transmission Request Pending 4. See description for bit 0. + bit_offset: 4 + bit_size: 1 + - name: TRP5 + description: Transmission Request Pending 5. See description for bit 0. + bit_offset: 5 + bit_size: 1 + - name: TRP6 + description: Transmission Request Pending 6. See description for bit 0. + bit_offset: 6 + bit_size: 1 + - name: TRP7 + description: Transmission Request Pending 7. See description for bit 0. + bit_offset: 7 + bit_size: 1 + - name: TRP8 + description: Transmission Request Pending 8. See description for bit 0. + bit_offset: 8 + bit_size: 1 + - name: TRP9 + description: Transmission Request Pending 9. See description for bit 0. + bit_offset: 9 + bit_size: 1 + - name: TRP10 + description: Transmission Request Pending 10. See description for bit 0. + bit_offset: 10 + bit_size: 1 + - name: TRP11 + description: Transmission Request Pending 11. See description for bit 0. + bit_offset: 11 + bit_size: 1 + - name: TRP12 + description: Transmission Request Pending 12. See description for bit 0. + bit_offset: 12 + bit_size: 1 + - name: TRP13 + description: Transmission Request Pending 13. See description for bit 0. + bit_offset: 13 + bit_size: 1 + - name: TRP14 + description: Transmission Request Pending 14. See description for bit 0. + bit_offset: 14 + bit_size: 1 + - name: TRP15 + description: Transmission Request Pending 15. See description for bit 0. + bit_offset: 15 + bit_size: 1 + - name: TRP16 + description: Transmission Request Pending 16. See description for bit 0. + bit_offset: 16 + bit_size: 1 + - name: TRP17 + description: Transmission Request Pending 17. See description for bit 0. + bit_offset: 17 + bit_size: 1 + - name: TRP18 + description: Transmission Request Pending 18. See description for bit 0. + bit_offset: 18 + bit_size: 1 + - name: TRP19 + description: Transmission Request Pending 19. See description for bit 0. + bit_offset: 19 + bit_size: 1 + - name: TRP20 + description: Transmission Request Pending 20. See description for bit 0. + bit_offset: 20 + bit_size: 1 + - name: TRP21 + description: Transmission Request Pending 21. See description for bit 0. + bit_offset: 21 + bit_size: 1 + - name: TRP22 + description: Transmission Request Pending 22. See description for bit 0. + bit_offset: 22 + bit_size: 1 + - name: TRP23 + description: Transmission Request Pending 23. See description for bit 0. + bit_offset: 23 + bit_size: 1 + - name: TRP24 + description: Transmission Request Pending 24. See description for bit 0. + bit_offset: 24 + bit_size: 1 + - name: TRP25 + description: Transmission Request Pending 25. See description for bit 0. + bit_offset: 25 + bit_size: 1 + - name: TRP26 + description: Transmission Request Pending 26. See description for bit 0. + bit_offset: 26 + bit_size: 1 + - name: TRP27 + description: Transmission Request Pending 27. See description for bit 0. + bit_offset: 27 + bit_size: 1 + - name: TRP28 + description: Transmission Request Pending 28. See description for bit 0. + bit_offset: 28 + bit_size: 1 + - name: TRP29 + description: Transmission Request Pending 29. See description for bit 0. + bit_offset: 29 + bit_size: 1 + - name: TRP30 + description: Transmission Request Pending 30. See description for bit 0. + bit_offset: 30 + bit_size: 1 + - name: TRP31 + description: Transmission Request Pending 31. See description for bit 0. + bit_offset: 31 + bit_size: 1 +fieldset/TXBTIE: + description: MCAN Tx Buffer Transmission Interrupt Enable. + fields: + - name: TIE0 + description: Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: TIE1 + description: Transmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 1 + bit_size: 1 + - name: TIE2 + description: Transmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 2 + bit_size: 1 + - name: TIE3 + description: Transmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 3 + bit_size: 1 + - name: TIE4 + description: Transmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 4 + bit_size: 1 + - name: TIE5 + description: Transmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 5 + bit_size: 1 + - name: TIE6 + description: Transmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 6 + bit_size: 1 + - name: TIE7 + description: Transmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: TIE8 + description: Transmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 8 + bit_size: 1 + - name: TIE9 + description: Transmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 9 + bit_size: 1 + - name: TIE10 + description: Transmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 10 + bit_size: 1 + - name: TIE11 + description: Transmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 11 + bit_size: 1 + - name: TIE12 + description: Transmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 12 + bit_size: 1 + - name: TIE13 + description: Transmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 13 + bit_size: 1 + - name: TIE14 + description: Transmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 14 + bit_size: 1 + - name: TIE15 + description: Transmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 15 + bit_size: 1 + - name: TIE16 + description: Transmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 16 + bit_size: 1 + - name: TIE17 + description: Transmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 17 + bit_size: 1 + - name: TIE18 + description: Transmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 18 + bit_size: 1 + - name: TIE19 + description: Transmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 19 + bit_size: 1 + - name: TIE20 + description: Transmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 20 + bit_size: 1 + - name: TIE21 + description: Transmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 21 + bit_size: 1 + - name: TIE22 + description: Transmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 22 + bit_size: 1 + - name: TIE23 + description: Transmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 23 + bit_size: 1 + - name: TIE24 + description: Transmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 24 + bit_size: 1 + - name: TIE25 + description: Transmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 25 + bit_size: 1 + - name: TIE26 + description: Transmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 26 + bit_size: 1 + - name: TIE27 + description: Transmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 27 + bit_size: 1 + - name: TIE28 + description: Transmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 28 + bit_size: 1 + - name: TIE29 + description: Transmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 29 + bit_size: 1 + - name: TIE30 + description: Transmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 30 + bit_size: 1 + - name: TIE31 + description: Transmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. + bit_offset: 31 + bit_size: 1 +fieldset/TXBTO: + description: MCAN Tx Buffer Transmission Occurred. + fields: + - name: TO0 + description: Transmission Occurred 0. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmission occurred 1 Transmission occurred. bit_offset: 0 bit_size: 1 - - name: STOPREQ_HW_OVR - description: MCANSS clock stop HW override status bit. This bit indicates when the MCANSS_CLKCTL.STOPREQ bit has been cleared by HW when a clock-stop wake-up event via CAN RX activity is trigged. - bit_offset: 4 + - name: TO1 + description: Transmission Occurred 1. See description for bit 0. + bit_offset: 1 bit_size: 1 - - name: CCLKDONE - description: This bit indicates the status of MCAN contoller clock request from GPRCM. - bit_offset: 8 + - name: TO2 + description: Transmission Occurred 2. See description for bit 0. + bit_offset: 2 bit_size: 1 -fieldset/SUBSYS_CTRL: - description: MCAN Subsystem Control Register. - fields: - - name: DBGSUSP_FREE - description: Debug Suspend Free Bit. Enables debug suspend. 0 Disable debug suspend 1 Enable debug suspend. + - name: TO3 + description: Transmission Occurred 3. See description for bit 0. bit_offset: 3 bit_size: 1 - - name: WAKEUPREQEN - description: Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity. 0 Disable wakeup request 1 Enables wakeup request. + - name: TO4 + description: Transmission Occurred 4. See description for bit 0. bit_offset: 4 bit_size: 1 - - name: AUTOWAKEUP - description: Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up, on an enabled wakeup request. 0 Disable the automatic write to CCCR.INIT 1 Enable the automatic write to CCCR.INIT. + - name: TO5 + description: Transmission Occurred 5. See description for bit 0. bit_offset: 5 bit_size: 1 - - name: EXT_TS_CNTR_EN - description: External Timestamp Counter Enable. 0 External timestamp counter disabled 1 External timestamp counter enabled. + - name: TO6 + description: Transmission Occurred 6. See description for bit 0. bit_offset: 6 bit_size: 1 -fieldset/SUBSYS_EOI: - description: MCAN Subsystem End of Interrupt. - fields: - - name: EOI - description: End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1, another interrupt is generated. 0x00 External TS Interrupt is cleared 0x01 MCAN(0) interrupt is cleared 0x02 MCAN(1) interrupt is cleared Other writes are ignored. - bit_offset: 0 - bit_size: 8 -fieldset/SUBSYS_EXT_TS_PRESCALER: - description: MCAN Subsystem External Timestamp Prescaler 0. - fields: - - name: PRESCALER - description: External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value, except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001. - bit_offset: 0 - bit_size: 24 -fieldset/SUBSYS_EXT_TS_UNSERVICED_INTR_CNTR: - description: MCAN Subsystem External Timestamp Unserviced Interrupts Counter. - fields: - - name: EXT_TS_INTR_CNTR - description: External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1, an MCANSS_EOI write of '1' to bit 0 will issue another interrupt. The status of this bit field is affected by the MCANSS_IRS.EXT_TS_CNTR_OVFL bit field. - bit_offset: 0 - bit_size: 5 -fieldset/SUBSYS_ICS: - description: MCAN Subsystem Interrupt Clear Shadow Register. - fields: - - name: EXT_TS_CNTR_OVFL - description: External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IRS.EXT_TS_CNTR_OVFL bit. - bit_offset: 0 + - name: TO7 + description: Transmission Occurred 7. See description for bit 0. + bit_offset: 7 bit_size: 1 -fieldset/SUBSYS_IE: - description: MCAN Subsystem Interrupt Enable Register. - fields: - - name: EXT_TS_CNTR_OVFL - description: External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit. - bit_offset: 0 + - name: TO8 + description: Transmission Occurred 8. See description for bit 0. + bit_offset: 8 bit_size: 1 -fieldset/SUBSYS_IECS: - description: MCAN Subsystem Interrupt Enable Clear Shadow Register. - fields: - - name: EXT_TS_CNTR_OVFL - description: External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IES.EXT_TS_CNTR_OVFL bit. - bit_offset: 0 + - name: TO9 + description: Transmission Occurred 9. See description for bit 0. + bit_offset: 9 bit_size: 1 -fieldset/SUBSYS_IES: - description: MCAN Subsystem Interrupt Enable Status. - fields: - - name: EXT_TS_CNTR_OVFL - description: External Timestamp Counter Overflow Interrupt Enable Status. To set, use the CANSS_IE.EXT_TS_CNTR_OVFL bit. To clear, use the MCANSS_IECS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter overflow interrupt is not enabled 1 External timestamp counter overflow interrupt is enabled. - bit_offset: 0 + - name: TO10 + description: Transmission Occurred 10. See description for bit 0. + bit_offset: 10 bit_size: 1 -fieldset/SUBSYS_IRS: - description: MCAN Subsystem Interrupt Raw Satus Register. - fields: - - name: EXT_TS_CNTR_OVFL - description: External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear, use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter has not overflowed 1 External timestamp counter has overflowed When this bit is set to '1' by HW or SW, the MCANSS_EXT_TS_UNSERVICED_INTR_CNTR.EXT_TS_INTR_CNTR bit field will increment by 1. - bit_offset: 0 + - name: TO11 + description: Transmission Occurred 11. See description for bit 0. + bit_offset: 11 bit_size: 1 -fieldset/SUBSYS_PID: - description: MCAN Subsystem Revision Register. - fields: - - name: MINOR - description: Minor Revision of the MCAN Subsystem. - bit_offset: 0 - bit_size: 6 - - name: MAJOR - description: Major Revision of the MCAN Subsystem. - bit_offset: 8 - bit_size: 3 - - name: MODULE_ID - description: Module Identification Number. + - name: TO12 + description: Transmission Occurred 12. See description for bit 0. + bit_offset: 12 + bit_size: 1 + - name: TO13 + description: Transmission Occurred 13. See description for bit 0. + bit_offset: 13 + bit_size: 1 + - name: TO14 + description: Transmission Occurred 14. See description for bit 0. + bit_offset: 14 + bit_size: 1 + - name: TO15 + description: Transmission Occurred 15. See description for bit 0. + bit_offset: 15 + bit_size: 1 + - name: TO16 + description: Transmission Occurred 16. See description for bit 0. bit_offset: 16 - bit_size: 12 - - name: SCHEME - description: PID Register Scheme. - bit_offset: 30 - bit_size: 2 -fieldset/SUBSYS_STAT: - description: MCAN Subsystem Status Register. - fields: - - name: RESET - description: Soft Reset Status. 0 Not in reset 1 Reset is in progress. - bit_offset: 0 bit_size: 1 - - name: MEM_INIT_DONE - description: Memory Initialization Done. 0 Message RAM initialization is in progress 1 Message RAM is initialized for use. - bit_offset: 1 + - name: TO17 + description: Transmission Occurred 17. See description for bit 0. + bit_offset: 17 bit_size: 1 - - name: ENABLE_FDOE - description: Flexible Datarate Operation Enable. Determines whether CAN FD operation may be enabled via the MCAN core CCCR.FDOE bit (bit 8) or if only standard CAN operation is possible with this instance of the MCAN. 0 MCAN is only capable of standard CAN communication 1 MCAN may be configured to perform CAN FD communication. - bit_offset: 2 + - name: TO18 + description: Transmission Occurred 18. See description for bit 0. + bit_offset: 18 bit_size: 1 -fieldset/TDCR: - description: MCAN Transmitter Delay Compensation Register. - fields: - - name: TDCF - description: Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 0 - bit_size: 7 - - name: TDCO - description: Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 8 - bit_size: 7 -fieldset/TEST: - description: MCAN Test Register. - fields: - - name: LBCK - description: Loop Back Mode 0 Reset value, Loop Back Mode is disabled 1 Loop Back Mode is enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 4 + - name: TO19 + description: Transmission Occurred 19. See description for bit 0. + bit_offset: 19 bit_size: 1 - - name: TX - description: Control of Transmit Pin 00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at CAN TX pin 10 Dominant ('0') level at CAN TX pin 11 Recessive ('1') at CAN TX pin Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 5 - bit_size: 2 - - name: RX - description: Receive Pin. Monitors the actual value of the CAN receive pin. 0 The CAN bus is dominant (CAN RX pin = '0') 1 The CAN bus is recessive (CAN RX pin = '1'). - bit_offset: 7 + - name: TO20 + description: Transmission Occurred 20. See description for bit 0. + bit_offset: 20 bit_size: 1 -fieldset/TOCC: - description: MCAN Timeout Counter Configuration. - fields: - - name: ETOC - description: Enable Timeout Counter 0 Timeout Counter disabled 1 Timeout Counter enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 0 + - name: TO21 + description: Transmission Occurred 21. See description for bit 0. + bit_offset: 21 bit_size: 1 - - name: TOS - description: Timeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00 Continuous operation 01 Timeout controlled by Tx Event FIFO 10 Timeout controlled by Rx FIFO 0 11 Timeout controlled by Rx FIFO 1 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 1 - bit_size: 2 - - name: TOP - description: Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 16 - bit_size: 16 -fieldset/TOCV: - description: MCAN Timeout Counter Value. - fields: - - name: TOC - description: Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. - bit_offset: 0 - bit_size: 16 -fieldset/TSCC: - description: MCAN Timestamp Counter Configuration. - fields: - - name: TSS - description: Timestamp Select 00 Timestamp counter value always 0x0000 01 Timestamp counter value incremented according to TCP 10 External timestamp counter value used 11 Same as "00" Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 0 - bit_size: 2 - - name: TCP - description: 'Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With CAN FD an external counter is required for timestamp generation (TSS = "10"). Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' - bit_offset: 16 - bit_size: 4 -fieldset/TSCV: - description: MCAN Timestamp Counter Value. - fields: - - name: TSC - description: 'Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01", the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = "10", TSC reflects the External Timestamp Counter value, and a write access has no impact. Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not caused by write access to MCAN_TSCV.' - bit_offset: 0 - bit_size: 16 -fieldset/TXBAR: - description: MCAN Tx Buffer Add Request. - fields: - - name: AR - description: 'Add Request 0. Each Tx Buffer has its own Add Request bit. Writing a ''1'' will set the corresponding Add Request bit; writing a ''0'' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0 No transmission request added 1 Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. Qualified Write is possible only with CCCR.CCE=''0''.' - bit_offset: 0 + - name: TO22 + description: Transmission Occurred 22. See description for bit 0. + bit_offset: 22 bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/TXBC: - description: MCAN Tx Buffer Configuration. - fields: - - name: TBSA - description: Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 2 - bit_size: 14 - - name: NDTB - description: 'Number of Dedicated Transmit Buffers 0 No Dedicated Tx Buffers 1-32 Number of Dedicated Tx Buffers >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' - bit_offset: 16 - bit_size: 6 - - name: TFQS - description: 'Transmit FIFO/Queue Size 0 No Tx FIFO/Queue 1-32 Number of Tx Buffers used for Tx FIFO/Queue >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE=''1'' and CCCR.INIT=''1''.' + - name: TO23 + description: Transmission Occurred 23. See description for bit 0. + bit_offset: 23 + bit_size: 1 + - name: TO24 + description: Transmission Occurred 24. See description for bit 0. bit_offset: 24 - bit_size: 6 - - name: TFQM - description: Tx FIFO/Queue Mode 0 Tx FIFO operation 1 Tx Queue operation Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. - bit_offset: 30 bit_size: 1 -fieldset/TXBCF: - description: MCAN Tx Buffer Cancellation Finished. - fields: - - name: CF - description: Cancellation Finished 0. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmit buffer cancellation 1 Transmit buffer cancellation finished. - bit_offset: 0 + - name: TO25 + description: Transmission Occurred 25. See description for bit 0. + bit_offset: 25 bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/TXBCIE: - description: MCAN Tx Buffer Cancellation Finished Interrupt Enable. - fields: - - name: CFIE - description: Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled. - bit_offset: 0 + - name: TO26 + description: Transmission Occurred 26. See description for bit 0. + bit_offset: 26 bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/TXBCR: - description: MCAN Tx Buffer Cancellation Request. - fields: - - name: CR - description: Cancellation Request 0. Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0 No cancellation pending 1 Cancellation pending Qualified Write is possible only with CCCR.CCE='0'. - bit_offset: 0 + - name: TO27 + description: Transmission Occurred 27. See description for bit 0. + bit_offset: 27 bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/TXBRP: - description: MCAN Tx Buffer Request Pending. - fields: - - name: TRP - description: 'Transmission Request Pending 0. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF - after successful transmission together with the corresponding TXBTO bit - when the transmission has not yet been started at the point of cancellation - when the transmission has been aborted due to lost arbitration - when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0 No transmission request pending 1 Transmission request pending Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset.' - bit_offset: 0 + - name: TO28 + description: Transmission Occurred 28. See description for bit 0. + bit_offset: 28 bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/TXBTIE: - description: MCAN Tx Buffer Transmission Interrupt Enable. - fields: - - name: TIE - description: Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable. - bit_offset: 0 + - name: TO29 + description: Transmission Occurred 29. See description for bit 0. + bit_offset: 29 bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/TXBTO: - description: MCAN Tx Buffer Transmission Occurred. - fields: - - name: TO - description: Transmission Occurred 0. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmission occurred 1 Transmission occurred. - bit_offset: 0 + - name: TO30 + description: Transmission Occurred 30. See description for bit 0. + bit_offset: 30 + bit_size: 1 + - name: TO31 + description: Transmission Occurred 31. See description for bit 0. + bit_offset: 31 bit_size: 1 - array: - len: 32 - stride: 1 fieldset/TXEFA: description: MCAN Tx Event FIFO Acknowledge. fields: @@ -1995,6 +3193,24 @@ fieldset/XIDFC: description: Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. bit_offset: 16 bit_size: 7 +enum/CCLKDONE: + bit_size: 1 + variants: + - name: RESET + description: MCAN controller clock is not available to the MCAN IP. + value: 0 + - name: SET + description: MCAN controller clock is enabled and available to the MCAN IP. + value: 1 +enum/CLKSTOP_ACKSTS: + bit_size: 1 + variants: + - name: RESET + description: No clock stop acknowledged. + value: 0 + - name: SET + description: MCAN-SS may be clock gated by stopping both the CAN host and functional clocks. + value: 1 enum/FEATUREVER: bit_size: 4 variants: @@ -2062,3 +3278,12 @@ enum/STAT: - name: WAKEUP description: Clock Stop Wake Up interrupt pending. value: 6 +enum/STOPREQ_HW_OVR: + bit_size: 1 + variants: + - name: RESET + description: MCANSS_CLKCTL.STOPREQ bit has not been cleared by HW. + value: 0 + - name: SET + description: MCANSS_CLKCTL.STOPREQ bit has been cleared by HW. + value: 1 diff --git a/data/registers/comp_v1.yaml b/data/registers/comp_v1.yaml new file mode 100644 index 0000000..c98c78a --- /dev/null +++ b/data/registers/comp_v1.yaml @@ -0,0 +1,568 @@ +block/COMP: + description: PERIPHERALREGION. + items: + - name: FSUB + description: Subscriber Port 0. + array: + len: 2 + stride: 4 + byte_offset: 1024 + fieldset: FPORT + - name: FPUB_1 + description: Publisher port 1. + byte_offset: 1092 + fieldset: FPORT + - name: GPRCM + array: + len: 1 + stride: 24 + byte_offset: 2048 + block: GPRCM + - name: INT_EVENT + array: + len: 2 + stride: 44 + byte_offset: 4128 + block: INT_EVENT + - name: EVT_MODE + description: Event Mode. + byte_offset: 4320 + fieldset: EVT_MODE + - name: DESC + description: Module Description. + byte_offset: 4348 + access: Read + fieldset: DESC + - name: CTL0 + description: Control 0. + byte_offset: 4352 + fieldset: CTL0 + - name: CTL1 + description: Control 1. + byte_offset: 4356 + fieldset: CTL1 + - name: CTL2 + description: Control 2. + byte_offset: 4360 + fieldset: CTL2 + - name: CTL3 + description: Control 3. + byte_offset: 4364 + fieldset: CTL3 + - name: STAT + description: Status. + byte_offset: 4384 + access: Read + fieldset: STAT +block/GPRCM: + items: + - name: PWREN + description: Power enable. + byte_offset: 0 + fieldset: PWREN + - name: RSTCTL + description: Reset Control. + byte_offset: 4 + access: Write + fieldset: RSTCTL + - name: CLKCFG + description: Peripheral Clock Configuration Register. + byte_offset: 8 + fieldset: CLKCFG + - name: GPRCM_STAT + description: Status Register. + byte_offset: 20 + access: Read + fieldset: GPRCM_STAT +block/INT_EVENT: + items: + - name: IIDX + description: Interrupt index. + byte_offset: 0 + access: Read + fieldset: IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: INT + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: INT + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: INT + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: INT + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: INT +fieldset/CLKCFG: + description: Peripheral Clock Configuration Register. + fields: + - name: BLOCKASYNC + description: Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz. + bit_offset: 8 + bit_size: 1 +fieldset/CTL0: + description: Control 0. + fields: + - name: IPSEL + description: Channel input selected for the positive terminal of the comparator if IPEN is set to 1. + bit_offset: 0 + bit_size: 3 + enum: IPSEL + - name: IPEN + description: Channel input enable for the positive terminal of the comparator. + bit_offset: 15 + bit_size: 1 + - name: IMSEL + description: Channel input selected for the negative terminal of the comparator if IMEN is set to 1. + bit_offset: 16 + bit_size: 3 + enum: IMSEL + - name: IMEN + description: Channel input enable for the negative terminal of the comparator. + bit_offset: 31 + bit_size: 1 +fieldset/CTL1: + description: Control 1. + fields: + - name: ENABLE + description: This bit turns on the comparator. When the comparator is turned off it consumes no power. + bit_offset: 0 + bit_size: 1 + - name: MODE + description: This bit selects the comparator operating mode. + bit_offset: 1 + bit_size: 1 + enum: MODE + - name: EXCH + description: This bit exchanges the comparator inputs and inverts the comparator output. + bit_offset: 2 + bit_size: 1 + - name: SHORT + description: This bit shorts the positive and negative input terminals of the comparator. + bit_offset: 3 + bit_size: 1 + - name: IES + description: This bit selected the interrupt edge for COMPIFG and COMPINVIFG. + bit_offset: 4 + bit_size: 1 + enum: IES + - name: HYST + description: These bits select the hysteresis setting of the comparator. + bit_offset: 5 + bit_size: 2 + enum: HYST + - name: OUTPOL + description: This bit selects the comparator output polarity. + bit_offset: 7 + bit_size: 1 + enum: OUTPOL + - name: FLTEN + description: This bit enables the analog filter at comparator output. + bit_offset: 8 + bit_size: 1 + - name: FLTDLY + description: These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings. + bit_offset: 9 + bit_size: 2 + enum: FLTDLY + - name: WINCOMPEN + description: This bit enables window comparator operation of comparator. + bit_offset: 12 + bit_size: 1 +fieldset/CTL2: + description: Control 2. + fields: + - name: REFMODE + description: This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Static mode operation offers higher accuracy but consumes higher current. Sampled mode operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL > 0. + bit_offset: 0 + bit_size: 1 + enum: REFMODE + - name: REFSRC + description: These bits select the reference source for the comparator. + bit_offset: 3 + bit_size: 2 + enum: REFSRC + - name: REFSEL + description: This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator. + bit_offset: 7 + bit_size: 1 + enum: REFSEL + - name: BLANKSRC + description: These bits select the blanking source for the comparator. + bit_offset: 8 + bit_size: 3 + enum: BLANKSRC + - name: DACCTL + description: This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1. + bit_offset: 16 + bit_size: 1 + enum: DACCTL + - name: DACSW + description: This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1. + bit_offset: 17 + bit_size: 1 + enum: DACSW + - name: SAMPMODE + description: Enable sampled mode of comparator. + bit_offset: 24 + bit_size: 1 +fieldset/CTL3: + description: Control 3. + fields: + - name: DACCODE0 + description: This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. + bit_offset: 0 + bit_size: 8 + - name: DACCODE1 + description: This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. + bit_offset: 16 + bit_size: 8 +fieldset/DESC: + description: Module Description. + fields: + - name: MINREV + description: Minor rev of the IP. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major rev of the IP. + bit_offset: 4 + bit_size: 4 + - name: FEATUREVER + description: Feature Set for the module *instance*. + bit_offset: 12 + bit_size: 4 + - name: MODULEID + description: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. + bit_offset: 16 + bit_size: 16 +fieldset/EVT_MODE: + description: Event Mode. + fields: + - name: INT0_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]. + bit_offset: 0 + bit_size: 2 + enum: EVT_CFG + - name: EVT1_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]. + bit_offset: 2 + bit_size: 2 + enum: EVT_CFG +fieldset/FPORT: + description: Publisher port 1. + fields: + - name: CHANID + description: 0 = disconnected. 1-15 = connected to channelID = CHANID. + bit_offset: 0 + bit_size: 4 +fieldset/GPRCM_STAT: + description: Status Register. + fields: + - name: RESETSTKY + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + bit_offset: 16 + bit_size: 1 +fieldset/IIDX: + description: Interrupt index. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 2 + enum: STAT +fieldset/INT: + description: Interrupt clear. + fields: + - name: COMPIFG + description: Clears COMPIFG in RIS register. + bit_offset: 1 + bit_size: 1 + - name: COMPINVIFG + description: Clears COMPINVIFG in RIS register. + bit_offset: 2 + bit_size: 1 + - name: OUTRDYIFG + description: Clears OUTRDYIFG in RIS register. + bit_offset: 3 + bit_size: 1 +fieldset/PWREN: + description: Power enable. + fields: + - name: ENABLE + description: Enable the power. + bit_offset: 0 + bit_size: 1 + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY +fieldset/RSTCTL: + description: Reset Control. + fields: + - name: RESETASSERT + description: Assert reset to the peripheral. + bit_offset: 0 + bit_size: 1 + - name: RESETSTKYCLR + description: Clear the RESETSTKY bit in the STAT register. + bit_offset: 1 + bit_size: 1 + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY +fieldset/STAT: + description: Status. + fields: + - name: OUT + description: This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output. + bit_offset: 0 + bit_size: 1 + enum: OUT +enum/BLANKSRC: + bit_size: 3 + variants: + - name: DISABLE + description: Blanking source disabled. + value: 0 + - name: BLANKSRC1 + description: Select Blanking Source 1. + value: 1 + - name: BLANKSRC2 + description: Select Blanking Source 2. + value: 2 + - name: BLANKSRC3 + description: Select Blanking Source 3. + value: 3 + - name: BLANKSRC4 + description: Select Blanking Source 4. + value: 4 + - name: BLANKSRC5 + description: Select Blanking Source 5. + value: 5 + - name: BLANKSRC6 + description: Select Blanking Source 6. + value: 6 +enum/DACCTL: + bit_size: 1 + variants: + - name: COMPOUT_SEL + description: Comparator output controls selection between DACCODE0 and DACCODE1. + value: 0 + - name: DACSW_SEL + description: DACSW bit controls selection between DACCODE0 and DACCODE1. + value: 1 +enum/DACSW: + bit_size: 1 + variants: + - name: DACCODE0_SEL + description: DACCODE0 selected for 8-bit DAC. + value: 0 + - name: DACCODE1_SEL + description: DACCODE1 selected for 8-bit DAC. + value: 1 +enum/EVT_CFG: + bit_size: 2 + variants: + - name: DISABLE + description: The interrupt or event line is disabled. + value: 0 + - name: SOFTWARE + description: Event handled by software. Software must clear the associated RIS flag. + value: 1 + - name: HARDWARE + description: Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. + value: 2 +enum/FLTDLY: + bit_size: 2 + variants: + - name: DLY_0 + description: Typical filter delay of 70 ns. + value: 0 + - name: DLY_1 + description: Typical filter delay of 500 ns. + value: 1 + - name: DLY_2 + description: Typical filter delay of 1200 ns. + value: 2 + - name: DLY_3 + description: Typical filter delay of 2700 ns. + value: 3 +enum/HYST: + bit_size: 2 + variants: + - name: NO_HYS + description: No hysteresis. + value: 0 + - name: LOW_HYS + description: Low hysteresis, typical 10mV. + value: 1 + - name: MED_HYS + description: Medium hysteresis, typical 20mV. + value: 2 + - name: HIGH_HYS + description: High hysteresis, typical 30mV. + value: 3 +enum/IES: + bit_size: 1 + variants: + - name: RISING + description: Rising edge sets COMPIFG and falling edge sets COMPINVIFG. + value: 0 + - name: FALLING + description: Falling edge sets COMPIFG and rising edge sets COMPINVIFG. + value: 1 +enum/IMSEL: + bit_size: 3 + variants: + - name: CH_0 + description: Channel 0 selected. + value: 0 + - name: CH_1 + description: Channel 1 selected. + value: 1 + - name: CH_2 + description: Channel 2 selected. + value: 2 + - name: CH_3 + description: Channel 3 selected. + value: 3 + - name: CH_4 + description: Channel 4 selected. + value: 4 + - name: CH_5 + description: Channel 5 selected. + value: 5 + - name: CH_6 + description: Channel 6 selected. + value: 6 + - name: CH_7 + description: Channel 7 selected. + value: 7 +enum/IPSEL: + bit_size: 3 + variants: + - name: CH_0 + description: Channel 0 selected. + value: 0 + - name: CH_1 + description: Channel 1 selected. + value: 1 + - name: CH_2 + description: Channel 2 selected. + value: 2 + - name: CH_3 + description: Channel 3 selected. + value: 3 + - name: CH_4 + description: Channel 4 selected. + value: 4 + - name: CH_5 + description: Channel 5 selected. + value: 5 + - name: CH_6 + description: Channel 6 selected. + value: 6 + - name: CH_7 + description: Channel 7 selected. + value: 7 +enum/MODE: + bit_size: 1 + variants: + - name: FAST + description: Comparator is in fast mode. + value: 0 + - name: ULP + description: Comparator is in ultra-low power mode. + value: 1 +enum/OUT: + bit_size: 1 + variants: + - name: LOW + description: Comparator output is low. + value: 0 + - name: HIGH + description: Comparator output is high. + value: 1 +enum/OUTPOL: + bit_size: 1 + variants: + - name: NON_INV + description: Comparator output is non-inverted. + value: 0 + - name: INV + description: Comparator output is inverted. + value: 1 +enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 +enum/REFMODE: + bit_size: 1 + variants: + - name: STATIC + description: ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in static mode. + value: 0 + - name: SAMPLED + description: ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in sampled mode. + value: 1 +enum/REFSEL: + bit_size: 1 + variants: + - name: POSITIVE + description: If EXCH bit is 0, the selected reference is applied to positive terminal. If EXCH bit is 1, the selected reference is applied to negative terminal. + value: 0 + - name: NEGATIVE + description: If EXCH bit is 0, the selected reference is applied to negative terminal. If EXCH bit is 1, the selected reference is applied to positive terminal. + value: 1 +enum/REFSRC: + bit_size: 2 + variants: + - name: OFF + description: Reference voltage generator is disabled (local reference buffer as well as DAC). + value: 0 + - name: VDDA_DAC + description: VDDA selected as the reference source to DAC and DAC output applied as reference to comparator. + value: 1 + - name: VREF_DAC + description: VREF selected as reference to DAC and DAC output applied as reference to comparator. + value: 2 + - name: VREF + description: VREF applied as reference to comparator. DAC is switched off. + value: 3 +enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 +enum/STAT: + bit_size: 2 + variants: + - name: NO_INTR + description: No pending interrupt. + value: 0 + - name: OUTRDYIFG + description: Comparator output ready interrupt. + value: 1 + - name: COMPIFG + description: Comparator output interrupt. + value: 2 + - name: COMPINVIFG + description: Comparator output inverted interrupt. + value: 3 diff --git a/data/registers/crc_v1.yaml b/data/registers/crc_v1.yaml new file mode 100644 index 0000000..7730814 --- /dev/null +++ b/data/registers/crc_v1.yaml @@ -0,0 +1,160 @@ +block/CRC: + description: PERIPHERALREGION. + items: + - name: GPRCM + array: + len: 1 + stride: 24 + byte_offset: 2048 + block: GPRCM + - name: DESC + description: Module Description. + byte_offset: 4348 + access: Read + fieldset: DESC + - name: CRCCTRL + description: CRC Control Register. + byte_offset: 4352 + fieldset: CRCCTRL + - name: CRCSEED + description: CRC Seed Register. + byte_offset: 4356 + access: Write + - name: CRCIN + description: CRC Input Data Register. + byte_offset: 4360 + access: Write + - name: CRCOUT + description: CRC Output Result Register. + byte_offset: 4364 + access: Read + - name: CRCIN_IDX + description: CRC Input Data Array Register. + array: + len: 512 + stride: 4 + byte_offset: 6144 + access: Write +block/GPRCM: + items: + - name: PWREN + description: Power enable. + byte_offset: 0 + fieldset: PWREN + - name: RSTCTL + description: Reset Control. + byte_offset: 4 + access: Write + fieldset: RSTCTL + - name: STAT + description: Status Register. + byte_offset: 20 + access: Read + fieldset: STAT +fieldset/CRCCTRL: + description: CRC Control Register. + fields: + - name: POLYSIZE + description: This bit indicates which CRC calculation is performed by the generator. + bit_offset: 0 + bit_size: 1 + enum: POLYSIZE + - name: BITREVERSE + description: CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT. + bit_offset: 1 + bit_size: 1 + - name: INPUT_ENDIANNESS + description: CRC Endian. This bit indicates the byte order within a word or half word of input data. + bit_offset: 2 + bit_size: 1 + enum: INPUT_ENDIANNESS + - name: OUTPUT_BYTESWAP + description: 'CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0.' + bit_offset: 4 + bit_size: 1 +fieldset/DESC: + description: Module Description. + fields: + - name: MINREV + description: Minor rev of the IP. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major rev of the IP. + bit_offset: 4 + bit_size: 4 + - name: INSTNUM + description: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances. + bit_offset: 8 + bit_size: 4 + - name: FEATUREVER + description: Feature Set for the module *instance*. + bit_offset: 12 + bit_size: 4 + - name: MODULEID + description: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. + bit_offset: 16 + bit_size: 16 +fieldset/PWREN: + description: Power enable. + fields: + - name: ENABLE + description: Enable the power. + bit_offset: 0 + bit_size: 1 + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY +fieldset/RSTCTL: + description: Reset Control. + fields: + - name: RESETASSERT + description: Assert reset to the peripheral. + bit_offset: 0 + bit_size: 1 + - name: RESETSTKYCLR + description: Clear the RESETSTKY bit in the STAT register. + bit_offset: 1 + bit_size: 1 + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY +fieldset/STAT: + description: Status Register. + fields: + - name: RESETSTKY + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + bit_offset: 16 + bit_size: 1 +enum/INPUT_ENDIANNESS: + bit_size: 1 + variants: + - name: LITTLE_ENDIAN + description: LSB is lowest memory address and first to be processed. + value: 0 + - name: BIG_ENDIAN + description: LSB is highest memory address and last to be processed. + value: 1 +enum/POLYSIZE: + bit_size: 1 + variants: + - name: CRC32 + description: CRC-32 ISO-3309 calulation is performed. + value: 0 + - name: CRC16 + description: CRC-16 CCITT is performed. + value: 1 +enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 +enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 diff --git a/data/registers/dac_v1.yaml b/data/registers/dac_v1.yaml new file mode 100644 index 0000000..2a2dbe8 --- /dev/null +++ b/data/registers/dac_v1.yaml @@ -0,0 +1,509 @@ +block/DAC: + description: PERIPHERALREGION. + items: + - name: FSUB + description: Subscriber Port 0. + array: + len: 2 + stride: 4 + byte_offset: 1024 + fieldset: FPORT + - name: FPUB_1 + description: Publisher port 1. + byte_offset: 1092 + fieldset: FPORT + - name: GPRCM + array: + len: 1 + stride: 24 + byte_offset: 2048 + block: GPRCM + - name: INT_EVENT + array: + len: 2 + stride: 44 + byte_offset: 4128 + block: INT_EVENT + - name: EVT_MODE + description: Event Mode. + byte_offset: 4320 + fieldset: EVT_MODE + - name: DESC + description: Module Description. + byte_offset: 4348 + access: Read + fieldset: DESC + - name: CTL0 + description: Control 0. + byte_offset: 4352 + fieldset: CTL0 + - name: CTL1 + description: Control 1. + byte_offset: 4368 + fieldset: CTL1 + - name: CTL2 + description: Control 2. + byte_offset: 4384 + fieldset: CTL2 + - name: CTL3 + description: Control 3. + byte_offset: 4400 + fieldset: CTL3 + - name: CALCTL + description: Calibration control. + byte_offset: 4416 + fieldset: CALCTL + - name: CALDATA + description: Calibration data. + byte_offset: 4448 + access: Read + fieldset: CALDATA + - name: DATA0 + description: Data 0. + byte_offset: 4608 + fieldset: DATA0 +block/GPRCM: + items: + - name: PWREN + description: Power enable. + byte_offset: 0 + fieldset: PWREN + - name: RSTCTL + description: Reset Control. + byte_offset: 4 + access: Write + fieldset: RSTCTL + - name: STAT + description: Status Register. + byte_offset: 20 + access: Read + fieldset: STAT +block/INT_EVENT: + items: + - name: IIDX + description: Interrupt index. + byte_offset: 0 + access: Read + fieldset: IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: INT + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: INT + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: INT + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: INT + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: INT +fieldset/CALCTL: + description: Calibration control. + fields: + - name: CALON + description: This bit when set initiates the DAC offset error calibration sequence and is automatically reset when the offset error calibration completes. + bit_offset: 0 + bit_size: 1 + - name: CALSEL + description: This bit is used to select between factory trim or self calibration trim. + bit_offset: 1 + bit_size: 1 + enum: CALSEL +fieldset/CALDATA: + description: Calibration data. + fields: + - name: DATA + description: DAC offset error calibration data. The DAC offset error calibration data is represented in twos complement format providing a range of 64 to +63. This is read-only bit, reflecting the calibration data. Writing to this register will have no effect, it will not change the calibration value. + bit_offset: 0 + bit_size: 7 +fieldset/CTL0: + description: Control 0. + fields: + - name: ENABLE + description: This bit enables the DAC module. + bit_offset: 0 + bit_size: 1 + - name: RES + description: These bits define the DAC output voltage resolution. + bit_offset: 8 + bit_size: 1 + enum: RES + - name: DFM + description: This bit defines the DAC input data format. + bit_offset: 16 + bit_size: 1 + enum: DFM +fieldset/CTL1: + description: Control 1. + fields: + - name: AMPEN + description: 'AMP_EN - output amplifier enabled or disabled 0 : disabled 1 : enabled.' + bit_offset: 0 + bit_size: 1 + - name: AMPHIZ + description: 'AMPHIZ - amplifier output value 0 : amplifier output is high impedance 1 : amplifier output is pulled down to ground.' + bit_offset: 1 + bit_size: 1 + enum: AMPHIZ + - name: REFSP + description: This bit selects the DAC voltage reference source + input. + bit_offset: 8 + bit_size: 1 + enum: REFSP + - name: REFSN + description: This bit selects the DAC voltage reference source + input. + bit_offset: 9 + bit_size: 1 + enum: REFSN + - name: OPS + description: These bits select the DAC output on device pin. + bit_offset: 24 + bit_size: 1 + enum: OPS +fieldset/CTL2: + description: Control 2. + fields: + - name: FIFOEN + description: This bit enables the FIFO and the FIFO hardware control state machine. + bit_offset: 0 + bit_size: 1 + - name: FIFOTH + description: These bits determine the FIFO threshold. In case of DMA based operation, DAC generates new DMA trigger when the number of empty locations in FIFO match the selected FIFO threshold level. In case of CPU based operation, the FIFO threshold bits are don't care and FIFO level is directly indicated through the respective bits in the RIS register. + bit_offset: 8 + bit_size: 2 + enum: FIFOTH + - name: FIFOTRIGSEL + description: These bits select the source for FIFO read trigger. When the selected FIFO read trigger is asserted, the data from FIFO (as indicated by read pointer) is moved into internal DAC data register. + bit_offset: 16 + bit_size: 2 + enum: FIFOTRIGSEL + - name: DMATRIGEN + description: This bit enables the DMA trigger generation mechanism. When this bit is set along with FIFOEN, the DMA trigger is generated based on the empty FIFO locations qualified by FIFOTH settings. This bit needs to be cleared by SW to stop further DMA triggers. + bit_offset: 24 + bit_size: 1 +fieldset/CTL3: + description: Control 3. + fields: + - name: STIMEN + description: This bit enables the sample time generator. + bit_offset: 0 + bit_size: 1 + - name: STIMCONFIG + description: These bits are used to configure the trigger rate from the sample time generator. The STIMCONFIG values 10 to 15 are reserved and default to same effect as value 0 (500SPS). + bit_offset: 8 + bit_size: 4 + enum: STIMCONFIG +fieldset/DATA0: + description: Data 0. + fields: + - name: DATA_VALUE + description: This is the data written for digital to analog conversion. + bit_offset: 0 + bit_size: 12 +fieldset/DESC: + description: Module Description. + fields: + - name: MINREV + description: Minor rev of the IP. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major rev of the IP. + bit_offset: 4 + bit_size: 4 + - name: FEATUREVER + description: Feature Set for the module *instance*. + bit_offset: 12 + bit_size: 4 + - name: MODULEID + description: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. + bit_offset: 16 + bit_size: 16 +fieldset/EVT_MODE: + description: Event Mode. + fields: + - name: INT0_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]. + bit_offset: 0 + bit_size: 2 + enum: EVT_CFG + - name: EVT1_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]. + bit_offset: 2 + bit_size: 2 + enum: EVT_CFG +fieldset/FPORT: + description: Publisher port 1. + fields: + - name: CHANID + description: 0 = disconnected. others = connected to channel_ID = CHANID. + bit_offset: 0 + bit_size: 4 +fieldset/IIDX: + description: Interrupt index. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 4 + enum: STAT +fieldset/INT: + description: Interrupt clear. + fields: + - name: MODRDYIFG + description: Clears MODRDYIFG in RIS register. + bit_offset: 1 + bit_size: 1 + - name: FIFOFULLIFG + description: Clears FIFOFULLIFG in RIS register. + bit_offset: 8 + bit_size: 1 + - name: FIFO1B4IFG + description: Clears FIFO1B4IFG in RIS register. + bit_offset: 9 + bit_size: 1 + - name: FIFO1B2IFG + description: Clears FIFO1B2IFG in RIS register. + bit_offset: 10 + bit_size: 1 + - name: FIFO3B4IFG + description: Clears FIFO3B4IFG in RIS register. + bit_offset: 11 + bit_size: 1 + - name: FIFOEMPTYIFG + description: Clears FIFOEMPTYIFG in RIS register. + bit_offset: 12 + bit_size: 1 + - name: FIFOURUNIFG + description: Clears FIFOURUNIFG in RIS register. + bit_offset: 13 + bit_size: 1 + - name: DMADONEIFG + description: Clears DMADONEIFG in RIS register. + bit_offset: 14 + bit_size: 1 +fieldset/PWREN: + description: Power enable. + fields: + - name: ENABLE + description: Enable the power. + bit_offset: 0 + bit_size: 1 + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY +fieldset/RSTCTL: + description: Reset Control. + fields: + - name: RESETASSERT + description: Assert reset to the peripheral. + bit_offset: 0 + bit_size: 1 + - name: RESETSTKYCLR + description: Clear the RESETSTKY bit in the STAT register. + bit_offset: 1 + bit_size: 1 + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY +fieldset/STAT: + description: Status Register. + fields: + - name: RESETSTKY + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + bit_offset: 16 + bit_size: 1 +enum/AMPHIZ: + bit_size: 1 + variants: + - name: HIZ + description: HiZ when disable. + value: 0 + - name: PULLDOWN + description: dacout pulldown when disable. + value: 1 +enum/CALSEL: + bit_size: 1 + variants: + - name: FACTORYTRIM + description: Factory Trim Calibration Values are used when calibration is enabled. + value: 0 + - name: SELFCALIBRATIONTRIM + description: Self Calibration Trim Values are used when calibration is enabled. + value: 1 +enum/DFM: + bit_size: 1 + variants: + - name: BINARY + description: Straight binary. + value: 0 + - name: TWOS_COMP + description: Twos complement. + value: 1 +enum/EVT_CFG: + bit_size: 2 + variants: + - name: DISABLE + description: The interrupt or event line is disabled. + value: 0 + - name: SOFTWARE + description: Event handled by software. Software must clear the associated RIS flag. + value: 1 + - name: HARDWARE + description: Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. + value: 2 +enum/FIFOTH: + bit_size: 2 + variants: + - name: LOW + description: One fourth of the FIFO locations are empty. + value: 0 + - name: MED + description: Half of the FIFO locations are empty. + value: 1 + - name: HIGH + description: Three fourth of the FIFO locations are empty. + value: 2 + - name: SPARE + description: Reserved value. Defaults to same effect as FIFOTH = 0 (One fourth of the FIFO locations are empty). + value: 3 +enum/FIFOTRIGSEL: + bit_size: 2 + variants: + - name: STIM + description: Sample time generator output. + value: 0 + - name: TRIG0 + description: Hardware trigger-0 from event fabric. + value: 1 + - name: TRIG1 + description: Hardware trigger-1 from event fabric. + value: 2 + - name: SPARE + description: Reserved - unimplemented. + value: 3 +enum/OPS: + bit_size: 1 + variants: + - name: NOC0 + description: No connect. Both DAC output switches are open. + value: 0 + - name: OUT0 + description: OUT0 output is selected. + value: 1 +enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 +enum/REFSN: + bit_size: 1 + variants: + - name: VEREFN + description: VEREFN pin as VR-. + value: 0 + - name: VSSA + description: Analog supply (VSSA) as VR-. + value: 1 +enum/REFSP: + bit_size: 1 + variants: + - name: VDDA + description: Analog supply (VDDA) as VR+. + value: 0 + - name: VEREFP + description: VEREFP pin as VR+. + value: 1 +enum/RES: + bit_size: 1 + variants: + - name: _8BITS + description: 8-bits resolution. + value: 0 + - name: _12BITS + description: 12-bit resolution. + value: 1 +enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 +enum/STAT: + bit_size: 4 + variants: + - name: NO_INTR + description: No pending interrupt. + value: 0 + - name: MODRDYIFG + description: Module ready interrupt. + value: 2 + - name: FIFOFULLIFG + description: FIFO full interrupt. + value: 9 + - name: FIFO1B4IFG + description: FIFO one fourth empty interrupt. + value: 10 + - name: FIFO1B2IFG + description: FIFO half empty interrupt. + value: 11 + - name: FIFO3B4IFG + description: FIFO three fourth empty interrupt. + value: 12 + - name: FIFOEMPTYIFG + description: FIFO empty interrupt. + value: 13 + - name: FIFOURUNIFG + description: FIFO underrun interrupt. + value: 14 + - name: DMADONEIFG + description: DMA done interrupt. + value: 15 +enum/STIMCONFIG: + bit_size: 4 + variants: + - name: _500SPS + description: Trigger rate is 500 sps (clock divide value is 4000). + value: 0 + - name: _1KSPS + description: Trigger rate is 1 ksps (clock divide value is 2000). + value: 1 + - name: _2KSPS + description: Trigger rate is 2 ksps (clock divide value is 1000). + value: 2 + - name: _4KSPS + description: Trigger rate is 4 ksps (clock divide value is 500). + value: 3 + - name: _8KSPS + description: Trigger rate is 8 ksps (clock divide value is 250). + value: 4 + - name: _16KSPS + description: Trigger rate is 16 ksps (clock divide value is 125). + value: 5 + - name: _100KSPS + description: Trigger rate is 100 ksps (clock divide value is 20). + value: 6 + - name: _200KSPS + description: Trigger rate is 200 ksps (clock divide value is 10). + value: 7 + - name: _500KSPS + description: Trigger rate is 500 ksps (clock divide value is 4). + value: 8 + - name: _1MSPS + description: Trigger rate is 1 Msps (clock divide value is 2). + value: 9 diff --git a/data/registers/debugss_v1.yaml b/data/registers/debugss_v1.yaml new file mode 100644 index 0000000..858f6f4 --- /dev/null +++ b/data/registers/debugss_v1.yaml @@ -0,0 +1,248 @@ +block/DEBUGSS: + description: DSSM. + items: + - name: IIDX + description: Interrupt index. + byte_offset: 4128 + access: Read + fieldset: IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 4136 + fieldset: INT + - name: RIS + description: Raw interrupt status. + byte_offset: 4144 + access: Read + fieldset: INT + - name: MIS + description: Masked interrupt status. + byte_offset: 4152 + access: Read + fieldset: INT + - name: ISET + description: Interrupt set. + byte_offset: 4160 + access: Write + fieldset: INT + - name: ICLR + description: Interrupt clear. + byte_offset: 4168 + access: Write + fieldset: INT + - name: EVT_MODE + description: Event Mode. + byte_offset: 4320 + access: Read + fieldset: EVT_MODE + - name: DESC + description: Module Description. + byte_offset: 4348 + access: Read + fieldset: DESC + - name: TXD + description: Transmit data register. + byte_offset: 4352 + access: Read + - name: TXCTL + description: Transmit control register. + byte_offset: 4356 + access: Read + fieldset: TXCTL + - name: RXD + description: Receive data register. + byte_offset: 4360 + - name: RXCTL + description: Receive control register. + byte_offset: 4364 + fieldset: RXCTL + - name: SPECIAL_AUTH + description: Special enable authorization register. + byte_offset: 4608 + access: Read + fieldset: SPECIAL_AUTH + - name: APP_AUTH + description: Application CPU0 authorization register. + byte_offset: 4624 + access: Read + fieldset: APP_AUTH +fieldset/APP_AUTH: + description: Application CPU0 authorization register. + fields: + - name: DBGEN + description: Controls invasive debug enable. + bit_offset: 0 + bit_size: 1 + - name: NIDEN + description: Controls non-invasive debug enable. + bit_offset: 1 + bit_size: 1 + - name: SPIDEN + description: Secure invasive debug enable. + bit_offset: 2 + bit_size: 1 + - name: SPNIDEN + description: Secure non-invasive debug enable. + bit_offset: 3 + bit_size: 1 +fieldset/DESC: + description: Module Description. + fields: + - name: MINREV + description: Minor rev of the IP. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major rev of the IP. + bit_offset: 4 + bit_size: 4 + - name: INSTNUM + description: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances. + bit_offset: 8 + bit_size: 4 + - name: FEATUREVER + description: Feature Set for the module *instance*. + bit_offset: 12 + bit_size: 4 + - name: MODULEID + description: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. + bit_offset: 16 + bit_size: 16 +fieldset/EVT_MODE: + description: Event Mode. + fields: + - name: INT0_CFG + description: Event line mode select for peripheral events. + bit_offset: 0 + bit_size: 2 + enum: INT0_CFG +fieldset/IIDX: + description: Interrupt index. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: STAT +fieldset/INT: + description: Interrupt clear. + fields: + - name: TXIFG + description: Clears TXIFG in RIS register. + bit_offset: 0 + bit_size: 1 + - name: RXIFG + description: Clears RXIFG in RIS register. + bit_offset: 1 + bit_size: 1 + - name: PWRUPIFG + description: Clears PWRUPIFG in RIS register. + bit_offset: 2 + bit_size: 1 + - name: PWRDWNIFG + description: Clears PWRDWNIFG in RIS register. + bit_offset: 3 + bit_size: 1 +fieldset/RXCTL: + description: Receive control register. + fields: + - name: RECEIVE + description: Indicates SW write to the DSSM.RXD register. A read of the DSSM.RXD register by SWD Access Port will clear the RX field. + bit_offset: 0 + bit_size: 1 + enum: RECEIVE + - name: RECEIVE_FLAGS + description: Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW. + bit_offset: 1 + bit_size: 7 +fieldset/SPECIAL_AUTH: + description: Special enable authorization register. + fields: + - name: SECAPEN + description: An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Security-AP to communicate with security control logic. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Security-AP. + bit_offset: 0 + bit_size: 1 + - name: SWDPORTEN + description: When asserted, the SW-DP functions normally. When deasserted, the SW-DP effectively disables all external debug access. + bit_offset: 1 + bit_size: 1 + - name: DFTAPEN + description: An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access. + bit_offset: 2 + bit_size: 1 + - name: ETAPEN + description: An active high input. When asserted (and SWD access is also permitted), the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access. + bit_offset: 3 + bit_size: 1 + - name: CFGAPEN + description: An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Config-AP to read device configuration information. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Config-AP. + bit_offset: 4 + bit_size: 1 + - name: AHBAPEN + description: Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation. + bit_offset: 5 + bit_size: 1 + - name: PWRAPEN + description: An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted, a DAPBUS firewall will isolate the AP and prevent access. + bit_offset: 6 + bit_size: 1 +fieldset/TXCTL: + description: Transmit control register. + fields: + - name: TRANSMIT + description: Indicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD. A read of the DSSM.TXD register by SW will clear the TX field. The tool can check that TXD is empty by reading this field. + bit_offset: 0 + bit_size: 1 + enum: TRANSMIT + - name: TRANSMIT_FLAGS + description: Generic TX flags that can be set by external debug tool. Functionality is defined by SW. + bit_offset: 1 + bit_size: 31 +enum/INT0_CFG: + bit_size: 2 + variants: + - name: DISABLE + description: The interrupt or event line is disabled. + value: 0 + - name: SOFTWARE + description: The interrupt or event line is in software mode. Software must clear the RIS. + value: 1 + - name: HARDWARE + description: The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. + value: 2 +enum/RECEIVE: + bit_size: 1 + variants: + - name: EMPTY + description: RXD empty. + value: 0 + - name: FULL + description: RXD full. + value: 1 +enum/STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No pending interrupt request. + value: 0 + - name: TXIFG + description: TX interrupt. + value: 1 + - name: RXIFG + description: RX interrupt. + value: 2 + - name: PWRUP + description: Power-up interrupt. A debug session has started. + value: 3 + - name: PWRDWN + description: Power-up interrupt. A debug session has started. + value: 4 +enum/TRANSMIT: + bit_size: 1 + variants: + - name: EMPTY + description: TXD is empty. + value: 0 + - name: FULL + description: TXD is full. + value: 1 diff --git a/data/registers/eventlp_v1.yaml b/data/registers/eventlp_v1.yaml new file mode 100644 index 0000000..8748dae --- /dev/null +++ b/data/registers/eventlp_v1.yaml @@ -0,0 +1,2737 @@ +block/EVENTLP: + description: PERIPHERALREGION. + items: + - name: PUBCFG_DESC_EX + description: Extended Module Description. + byte_offset: 248 + access: Read + fieldset: PUBCFG_DESC_EX + - name: PUBCFG_DESC + description: Module Description. + byte_offset: 252 + access: Read + fieldset: PUBCFG_DESC + - name: PUBCFG_FSUB + array: + len: 1 + stride: 128 + byte_offset: 256 + block: PUBCFG_FSUB + - name: PUBCFG_FPUB + array: + len: 1 + stride: 104 + byte_offset: 768 + block: PUBCFG_FPUB + - name: PUBCFG_EXPORT + array: + len: 1 + stride: 4 + byte_offset: 1280 + block: PUBCFG_EXPORT + - name: PUBCFG_IMPORT + array: + len: 1 + stride: 4 + byte_offset: 1792 + block: PUBCFG_IMPORT + - name: PUBCFG_CPU_CONNECT + array: + len: 1 + stride: 128 + byte_offset: 2304 + block: PUBCFG_CPU_CONNECT + - name: SECCFG_DESC_EX + description: Extended Module Description. + byte_offset: 4344 + access: Read + fieldset: SECCFG_DESC_EX + - name: SECCFG_DESC + description: Module Description. + byte_offset: 4348 + access: Read + fieldset: SECCFG_DESC + - name: SECCFG_FSUB + array: + len: 1 + stride: 32 + byte_offset: 4352 + block: SECCFG_FSUB + - name: SECCFG_FPUB + array: + len: 1 + stride: 26 + byte_offset: 4480 + block: SECCFG_FPUB + - name: SECCFG_EXPORT + array: + len: 1 + stride: 1 + byte_offset: 4608 + block: SECCFG_EXPORT + - name: SECCFG_IMPORT + array: + len: 1 + stride: 1 + byte_offset: 4736 + block: SECCFG_IMPORT + - name: SECCFG_CPU_CONNECT + array: + len: 1 + stride: 32 + byte_offset: 4864 + block: SECCFG_CPU_CONNECT + - name: CTL + description: Event Manager control register. + byte_offset: 5120 + bit_size: 8 + fieldset: CTL + - name: LMGMT_SFTYDIAG + array: + len: 1 + stride: 1024 + byte_offset: 7168 + block: LMGMT_SFTYDIAG + - name: IMPEXPCFG_EXPORT + array: + len: 1 + stride: 4 + byte_offset: 8192 + block: IMPEXPCFG_EXPORT + - name: IMPEXPCFG_IMPORT + array: + len: 1 + stride: 4 + byte_offset: 8704 + block: IMPEXPCFG_IMPORT +block/IMPEXPCFG_EXPORT: + items: + - name: IMPEXPCFG_EXPORT_PORT + description: Export channel ID register. + byte_offset: 0 + fieldset: IMPEXPCFG_EXPORT_PORT +block/IMPEXPCFG_IMPORT: + items: + - name: IMPEXPCFG_IMPORT_PORT + description: Import channel ID registe. + byte_offset: 0 + fieldset: IMPEXPCFG_IMPORT_PORT +block/LMGMT_SFTYDIAG: + items: + - name: DIAGPAR192 + description: Diagnostic Parity Register 768. + byte_offset: 236 + access: Write + fieldset: DIAGPAR192 + - name: DIAGPAR191 + description: Diagnostic Parity Register 191. + byte_offset: 240 + access: Write + fieldset: DIAGPAR191 + - name: DIAGPAR190 + description: Diagnostic Parity Register 190. + byte_offset: 244 + access: Write + fieldset: DIAGPAR190 + - name: DIAGPAR189 + description: Diagnostic Parity Register 189. + byte_offset: 248 + access: Write + fieldset: DIAGPAR189 + - name: DIAGPAR188 + description: Diagnostic Parity Register 188. + byte_offset: 252 + access: Write + fieldset: DIAGPAR188 + - name: DIAGPAR187 + description: Diagnostic Parity Register 187. + byte_offset: 256 + access: Write + fieldset: DIAGPAR187 + - name: DIAGPAR186 + description: Diagnostic Parity Register 186. + byte_offset: 260 + access: Write + fieldset: DIAGPAR186 + - name: DIAGPAR185 + description: Diagnostic Parity Register 185. + byte_offset: 264 + access: Write + fieldset: DIAGPAR185 + - name: DIAGPAR184 + description: Diagnostic Parity Register 184. + byte_offset: 268 + access: Write + fieldset: DIAGPAR184 + - name: DIAGPAR183 + description: Diagnostic Parity Register 183. + byte_offset: 272 + access: Write + fieldset: DIAGPAR183 + - name: DIAGPAR182 + description: Diagnostic Parity Register 182. + byte_offset: 276 + access: Write + fieldset: DIAGPAR182 + - name: DIAGPAR181 + description: Diagnostic Parity Register 181. + byte_offset: 280 + access: Write + fieldset: DIAGPAR181 + - name: DIAGPAR180 + description: Diagnostic Parity Register 180. + byte_offset: 284 + access: Write + fieldset: DIAGPAR180 + - name: DIAGPAR179 + description: Diagnostic Parity Register 179. + byte_offset: 288 + access: Write + fieldset: DIAGPAR179 + - name: DIAGPAR178 + description: Diagnostic Parity Register 178. + byte_offset: 292 + access: Write + fieldset: DIAGPAR178 + - name: DIAGPAR177 + description: Diagnostic Parity Register 177. + byte_offset: 296 + access: Write + fieldset: DIAGPAR177 + - name: DIAGPAR176 + description: Diagnostic Parity Register 176. + byte_offset: 300 + access: Write + fieldset: DIAGPAR176 + - name: DIAGPAR175 + description: Diagnostic Parity Register 175. + byte_offset: 304 + access: Write + fieldset: DIAGPAR175 + - name: DIAGPAR174 + description: Diagnostic Parity Register 174. + byte_offset: 308 + access: Write + fieldset: DIAGPAR174 + - name: DIAGPAR173 + description: Diagnostic Parity Register 173. + byte_offset: 312 + access: Write + fieldset: DIAGPAR173 + - name: DIAGPAR172 + description: Diagnostic Parity Register 172. + byte_offset: 316 + access: Write + fieldset: DIAGPAR172 + - name: DIAGPAR171 + description: Diagnostic Parity Register 171. + byte_offset: 320 + access: Write + fieldset: DIAGPAR171 + - name: DIAGPAR170 + description: Diagnostic Parity Register 170. + byte_offset: 324 + access: Write + fieldset: DIAGPAR170 + - name: DIAGPAR169 + description: Diagnostic Parity Register 169. + byte_offset: 328 + access: Write + fieldset: DIAGPAR169 + - name: DIAGPAR168 + description: Diagnostic Parity Register 168. + byte_offset: 332 + access: Write + fieldset: DIAGPAR168 + - name: DIAGPAR167 + description: Diagnostic Parity Register 167. + byte_offset: 336 + access: Write + fieldset: DIAGPAR167 + - name: DIAGPAR166 + description: Diagnostic Parity Register 166. + byte_offset: 340 + access: Write + fieldset: DIAGPAR166 + - name: DIAGPAR165 + description: Diagnostic Parity Register 165. + byte_offset: 344 + access: Write + fieldset: DIAGPAR165 + - name: DIAGPAR164 + description: Diagnostic Parity Register 164. + byte_offset: 348 + access: Write + fieldset: DIAGPAR164 + - name: DIAGPAR163 + description: Diagnostic Parity Register 163. + byte_offset: 352 + access: Write + fieldset: DIAGPAR163 + - name: DIAGPAR162 + description: Diagnostic Parity Register 162. + byte_offset: 356 + access: Write + fieldset: DIAGPAR162 + - name: DIAGPAR161 + description: Diagnostic Parity Register 161. + byte_offset: 360 + access: Write + fieldset: DIAGPAR161 + - name: DIAGPAR160 + description: Diagnostic Parity Register 160. + byte_offset: 364 + access: Write + fieldset: DIAGPAR160 + - name: DIAGPAR159 + description: Diagnostic Parity Register 159. + byte_offset: 368 + access: Write + fieldset: DIAGPAR159 + - name: DIAGPAR158 + description: Diagnostic Parity Register 158. + byte_offset: 372 + access: Write + fieldset: DIAGPAR158 + - name: DIAGPAR157 + description: Diagnostic Parity Register 157. + byte_offset: 376 + access: Write + fieldset: DIAGPAR157 + - name: DIAGPAR156 + description: Diagnostic Parity Register 156. + byte_offset: 380 + access: Write + fieldset: DIAGPAR156 + - name: DIAGPAR155 + description: Diagnostic Parity Register 155. + byte_offset: 384 + access: Write + fieldset: DIAGPAR155 + - name: DIAGPAR154 + description: Diagnostic Parity Register 154. + byte_offset: 388 + access: Write + fieldset: DIAGPAR154 + - name: DIAGPAR153 + description: Diagnostic Parity Register 153. + byte_offset: 392 + access: Write + fieldset: DIAGPAR153 + - name: DIAGPAR152 + description: Diagnostic Parity Register 152. + byte_offset: 396 + access: Write + fieldset: DIAGPAR152 + - name: DIAGPAR151 + description: Diagnostic Parity Register 151. + byte_offset: 400 + access: Write + fieldset: DIAGPAR151 + - name: DIAGPAR150 + description: Diagnostic Parity Register 150. + byte_offset: 404 + access: Write + fieldset: DIAGPAR150 + - name: DIAGPAR149 + description: Diagnostic Parity Register 149. + byte_offset: 408 + access: Write + fieldset: DIAGPAR149 + - name: DIAGPAR148 + description: Diagnostic Parity Register 148. + byte_offset: 412 + access: Write + fieldset: DIAGPAR148 + - name: DIAGPAR147 + description: Diagnostic Parity Register 147. + byte_offset: 416 + access: Write + fieldset: DIAGPAR147 + - name: DIAGPAR146 + description: Diagnostic Parity Register 146. + byte_offset: 420 + access: Write + fieldset: DIAGPAR146 + - name: DIAGPAR145 + description: Diagnostic Parity Register 145. + byte_offset: 424 + access: Write + fieldset: DIAGPAR145 + - name: DIAGPAR144 + description: Diagnostic Parity Register 144. + byte_offset: 428 + access: Write + fieldset: DIAGPAR144 + - name: DIAGPAR143 + description: Diagnostic Parity Register 143. + byte_offset: 432 + access: Write + fieldset: DIAGPAR143 + - name: DIAGPAR142 + description: Diagnostic Parity Register 142. + byte_offset: 436 + access: Write + fieldset: DIAGPAR142 + - name: DIAGPAR141 + description: Diagnostic Parity Register 141. + byte_offset: 440 + access: Write + fieldset: DIAGPAR141 + - name: DIAGPAR140 + description: Diagnostic Parity Register 140. + byte_offset: 444 + access: Write + fieldset: DIAGPAR140 + - name: DIAGPAR139 + description: Diagnostic Parity Register 139. + byte_offset: 448 + access: Write + fieldset: DIAGPAR139 + - name: DIAGPAR138 + description: Diagnostic Parity Register 138. + byte_offset: 452 + access: Write + fieldset: DIAGPAR138 + - name: DIAGPAR137 + description: Diagnostic Parity Register 137. + byte_offset: 456 + access: Write + fieldset: DIAGPAR137 + - name: DIAGPAR136 + description: Diagnostic Parity Register 136. + byte_offset: 460 + access: Write + fieldset: DIAGPAR136 + - name: DIAGPAR135 + description: Diagnostic Parity Register 135. + byte_offset: 464 + access: Write + fieldset: DIAGPAR135 + - name: DIAGPAR134 + description: Diagnostic Parity Register 134. + byte_offset: 468 + access: Write + fieldset: DIAGPAR134 + - name: DIAGPAR133 + description: Diagnostic Parity Register 133. + byte_offset: 472 + access: Write + fieldset: DIAGPAR133 + - name: DIAGPAR132 + description: Diagnostic Parity Register 132. + byte_offset: 476 + access: Write + fieldset: DIAGPAR132 + - name: DIAGPAR131 + description: Diagnostic Parity Register 131. + byte_offset: 480 + access: Write + fieldset: DIAGPAR131 + - name: DIAGPAR130 + description: Diagnostic Parity Register 130. + byte_offset: 484 + access: Write + fieldset: DIAGPAR130 + - name: DIAGPAR129 + description: Diagnostic Parity Register 129. + byte_offset: 488 + access: Write + fieldset: DIAGPAR129 + - name: DIAGPAR128 + description: Diagnostic Parity Register 128. + byte_offset: 492 + access: Write + fieldset: DIAGPAR128 + - name: DIAGPAR127 + description: Diagnostic Parity Register 127. + byte_offset: 496 + access: Write + fieldset: DIAGPAR127 + - name: DIAGPAR126 + description: Diagnostic Parity Register 126. + byte_offset: 500 + access: Write + fieldset: DIAGPAR126 + - name: DIAGPAR125 + description: Diagnostic Parity Register 125. + byte_offset: 504 + access: Write + fieldset: DIAGPAR125 + - name: DIAGPAR124 + description: Diagnostic Parity Register 124. + byte_offset: 508 + access: Write + fieldset: DIAGPAR124 + - name: DIAGPAR123 + description: Diagnostic Parity Register 123. + byte_offset: 512 + access: Write + fieldset: DIAGPAR123 + - name: DIAGPAR122 + description: Diagnostic Parity Register 122. + byte_offset: 516 + access: Write + fieldset: DIAGPAR122 + - name: DIAGPAR121 + description: Diagnostic Parity Register 121. + byte_offset: 520 + access: Write + fieldset: DIAGPAR121 + - name: DIAGPAR120 + description: Diagnostic Parity Register 120. + byte_offset: 524 + access: Write + fieldset: DIAGPAR120 + - name: DIAGPAR119 + description: Diagnostic Parity Register 119. + byte_offset: 528 + access: Write + fieldset: DIAGPAR119 + - name: DIAGPAR118 + description: Diagnostic Parity Register 118. + byte_offset: 532 + access: Write + fieldset: DIAGPAR118 + - name: DIAGPAR117 + description: Diagnostic Parity Register 117. + byte_offset: 536 + access: Write + fieldset: DIAGPAR117 + - name: DIAGPAR116 + description: Diagnostic Parity Register 116. + byte_offset: 540 + access: Write + fieldset: DIAGPAR116 + - name: DIAGPAR115 + description: Diagnostic Parity Register 115. + byte_offset: 544 + access: Write + fieldset: DIAGPAR115 + - name: DIAGPAR114 + description: Diagnostic Parity Register 114. + byte_offset: 548 + access: Write + fieldset: DIAGPAR114 + - name: DIAGPAR113 + description: Diagnostic Parity Register 113. + byte_offset: 552 + access: Write + fieldset: DIAGPAR113 + - name: DIAGPAR112 + description: Diagnostic Parity Register 112. + byte_offset: 556 + access: Write + fieldset: DIAGPAR112 + - name: DIAGPAR111 + description: Diagnostic Parity Register 111. + byte_offset: 560 + access: Write + fieldset: DIAGPAR111 + - name: DIAGPAR110 + description: Diagnostic Parity Register 110. + byte_offset: 564 + access: Write + fieldset: DIAGPAR110 + - name: DIAGPAR109 + description: Diagnostic Parity Register 109. + byte_offset: 568 + access: Write + fieldset: DIAGPAR109 + - name: DIAGPAR108 + description: Diagnostic Parity Register 108. + byte_offset: 572 + access: Write + fieldset: DIAGPAR108 + - name: DIAGPAR107 + description: Diagnostic Parity Register 107. + byte_offset: 576 + access: Write + fieldset: DIAGPAR107 + - name: DIAGPAR106 + description: Diagnostic Parity Register 106. + byte_offset: 580 + access: Write + fieldset: DIAGPAR106 + - name: DIAGPAR105 + description: Diagnostic Parity Register 105. + byte_offset: 584 + access: Write + fieldset: DIAGPAR105 + - name: DIAGPAR104 + description: Diagnostic Parity Register 104. + byte_offset: 588 + access: Write + fieldset: DIAGPAR104 + - name: DIAGPAR103 + description: Diagnostic Parity Register 103. + byte_offset: 592 + access: Write + fieldset: DIAGPAR103 + - name: DIAGPAR102 + description: Diagnostic Parity Register 102. + byte_offset: 596 + access: Write + fieldset: DIAGPAR102 + - name: DIAGPAR101 + description: Diagnostic Parity Register 101. + byte_offset: 600 + access: Write + fieldset: DIAGPAR101 + - name: DIAGPAR100 + description: Diagnostic Parity Register 100. + byte_offset: 604 + access: Write + fieldset: DIAGPAR100 + - name: DIAGPAR99 + description: Diagnostic Parity Register 99. + byte_offset: 608 + access: Write + fieldset: DIAGPAR99 + - name: DIAGPAR98 + description: Diagnostic Parity Register 98. + byte_offset: 612 + access: Write + fieldset: DIAGPAR98 + - name: DIAGPAR97 + description: Diagnostic Parity Register 97. + byte_offset: 616 + access: Write + fieldset: DIAGPAR97 + - name: DIAGPAR96 + description: Diagnostic Parity Register 96. + byte_offset: 620 + access: Write + fieldset: DIAGPAR96 + - name: DIAGPAR95 + description: Diagnostic Parity Register 95. + byte_offset: 624 + access: Write + fieldset: DIAGPAR95 + - name: DIAGPAR94 + description: Diagnostic Parity Register 94. + byte_offset: 628 + access: Write + fieldset: DIAGPAR94 + - name: DIAGPAR93 + description: Diagnostic Parity Register 93. + byte_offset: 632 + access: Write + fieldset: DIAGPAR93 + - name: DIAGPAR92 + description: Diagnostic Parity Register 92. + byte_offset: 636 + access: Write + fieldset: DIAGPAR92 + - name: DIAGPAR91 + description: Diagnostic Parity Register 91. + byte_offset: 640 + access: Write + fieldset: DIAGPAR91 + - name: DIAGPAR90 + description: Diagnostic Parity Register 90. + byte_offset: 644 + access: Write + fieldset: DIAGPAR90 + - name: DIAGPAR89 + description: Diagnostic Parity Register 89. + byte_offset: 648 + access: Write + fieldset: DIAGPAR89 + - name: DIAGPAR88 + description: Diagnostic Parity Register 88. + byte_offset: 652 + access: Write + fieldset: DIAGPAR88 + - name: DIAGPAR87 + description: Diagnostic Parity Register 87. + byte_offset: 656 + access: Write + fieldset: DIAGPAR87 + - name: DIAGPAR86 + description: Diagnostic Parity Register 86. + byte_offset: 660 + access: Write + fieldset: DIAGPAR86 + - name: DIAGPAR85 + description: Diagnostic Parity Register 85. + byte_offset: 664 + access: Write + fieldset: DIAGPAR85 + - name: DIAGPAR84 + description: Diagnostic Parity Register 84. + byte_offset: 668 + access: Write + fieldset: DIAGPAR84 + - name: DIAGPAR83 + description: Diagnostic Parity Register 83. + byte_offset: 672 + access: Write + fieldset: DIAGPAR83 + - name: DIAGPAR82 + description: Diagnostic Parity Register 82. + byte_offset: 676 + access: Write + fieldset: DIAGPAR82 + - name: DIAGPAR81 + description: Diagnostic Parity Register 81. + byte_offset: 680 + access: Write + fieldset: DIAGPAR81 + - name: DIAGPAR80 + description: Diagnostic Parity Register 80. + byte_offset: 684 + access: Write + fieldset: DIAGPAR80 + - name: DIAGPAR79 + description: Diagnostic Parity Register 79. + byte_offset: 688 + access: Write + fieldset: DIAGPAR79 + - name: DIAGPAR78 + description: Diagnostic Parity Register 78. + byte_offset: 692 + access: Write + fieldset: DIAGPAR78 + - name: DIAGPAR77 + description: Diagnostic Parity Register 77. + byte_offset: 696 + access: Write + fieldset: DIAGPAR77 + - name: DIAGPAR76 + description: Diagnostic Parity Register 76. + byte_offset: 700 + access: Write + fieldset: DIAGPAR76 + - name: DIAGPAR75 + description: Diagnostic Parity Register 75. + byte_offset: 704 + access: Write + fieldset: DIAGPAR75 + - name: DIAGPAR74 + description: Diagnostic Parity Register 74. + byte_offset: 708 + access: Write + fieldset: DIAGPAR74 + - name: DIAGPAR73 + description: Diagnostic Parity Register 73. + byte_offset: 712 + access: Write + fieldset: DIAGPAR73 + - name: DIAGPAR72 + description: Diagnostic Parity Register 72. + byte_offset: 716 + access: Write + fieldset: DIAGPAR72 + - name: DIAGPAR71 + description: Diagnostic Parity Register 71. + byte_offset: 720 + access: Write + fieldset: DIAGPAR71 + - name: DIAGPAR70 + description: Diagnostic Parity Register 70. + byte_offset: 724 + access: Write + fieldset: DIAGPAR70 + - name: DIAGPAR69 + description: Diagnostic Parity Register 69. + byte_offset: 728 + access: Write + fieldset: DIAGPAR69 + - name: DIAGPAR68 + description: Diagnostic Parity Register 68. + byte_offset: 732 + access: Write + fieldset: DIAGPAR68 + - name: DIAGPAR67 + description: Diagnostic Parity Register 67. + byte_offset: 736 + access: Write + fieldset: DIAGPAR67 + - name: DIAGPAR66 + description: Diagnostic Parity Register 66. + byte_offset: 740 + access: Write + fieldset: DIAGPAR66 + - name: DIAGPAR65 + description: Diagnostic Parity Register 65. + byte_offset: 744 + access: Write + fieldset: DIAGPAR65 + - name: DIAGPAR64 + description: Diagnostic Parity Register 64. + byte_offset: 748 + access: Write + fieldset: DIAGPAR64 + - name: DIAGPAR63 + description: Diagnostic Parity Register 63. + byte_offset: 752 + access: Write + fieldset: DIAGPAR63 + - name: DIAGPAR62 + description: Diagnostic Parity Register 62. + byte_offset: 756 + access: Write + fieldset: DIAGPAR62 + - name: DIAGPAR61 + description: Diagnostic Parity Register 61. + byte_offset: 760 + access: Write + fieldset: DIAGPAR61 + - name: DIAGPAR60 + description: Diagnostic Parity Register 60. + byte_offset: 764 + access: Write + fieldset: DIAGPAR60 + - name: DIAGPAR59 + description: Diagnostic Parity Register 59. + byte_offset: 768 + access: Write + fieldset: DIAGPAR59 + - name: DIAGPAR58 + description: Diagnostic Parity Register 58. + byte_offset: 772 + access: Write + fieldset: DIAGPAR58 + - name: DIAGPAR57 + description: Diagnostic Parity Register 57. + byte_offset: 776 + access: Write + fieldset: DIAGPAR57 + - name: DIAGPAR56 + description: Diagnostic Parity Register 56. + byte_offset: 780 + access: Write + fieldset: DIAGPAR56 + - name: DIAGPAR55 + description: Diagnostic Parity Register 55. + byte_offset: 784 + access: Write + fieldset: DIAGPAR55 + - name: DIAGPAR54 + description: Diagnostic Parity Register 54. + byte_offset: 788 + access: Write + fieldset: DIAGPAR54 + - name: DIAGPAR53 + description: Diagnostic Parity Register 53. + byte_offset: 792 + access: Write + fieldset: DIAGPAR53 + - name: DIAGPAR52 + description: Diagnostic Parity Register 52. + byte_offset: 796 + access: Write + fieldset: DIAGPAR52 + - name: DIAGPAR51 + description: Diagnostic Parity Register 51. + byte_offset: 800 + access: Write + fieldset: DIAGPAR51 + - name: DIAGPAR50 + description: Diagnostic Parity Register 50. + byte_offset: 804 + access: Write + fieldset: DIAGPAR50 + - name: DIAGPAR49 + description: Diagnostic Parity Register 49. + byte_offset: 808 + access: Write + fieldset: DIAGPAR49 + - name: DIAGPAR48 + description: Diagnostic Parity Register 48. + byte_offset: 812 + access: Write + fieldset: DIAGPAR48 + - name: DIAGPAR47 + description: Diagnostic Parity Register 47. + byte_offset: 816 + access: Write + fieldset: DIAGPAR47 + - name: DIAGPAR46 + description: Diagnostic Parity Register 46. + byte_offset: 820 + access: Write + fieldset: DIAGPAR46 + - name: DIAGPAR45 + description: Diagnostic Parity Register 45. + byte_offset: 824 + access: Write + fieldset: DIAGPAR45 + - name: DIAGPAR44 + description: Diagnostic Parity Register 44. + byte_offset: 828 + access: Write + fieldset: DIAGPAR44 + - name: DIAGPAR43 + description: Diagnostic Parity Register 43. + byte_offset: 832 + access: Write + fieldset: DIAGPAR43 + - name: DIAGPAR42 + description: Diagnostic Parity Register 42. + byte_offset: 836 + access: Write + fieldset: DIAGPAR42 + - name: DIAGPAR41 + description: Diagnostic Parity Register 41. + byte_offset: 840 + access: Write + fieldset: DIAGPAR41 + - name: DIAGPAR40 + description: Diagnostic Parity Register 40. + byte_offset: 844 + access: Write + fieldset: DIAGPAR40 + - name: DIAGPAR39 + description: Diagnostic Parity Register 39. + byte_offset: 848 + access: Write + fieldset: DIAGPAR39 + - name: DIAGPAR38 + description: Diagnostic Parity Register 38. + byte_offset: 852 + access: Write + fieldset: DIAGPAR38 + - name: DIAGPAR37 + description: Diagnostic Parity Register 37. + byte_offset: 856 + access: Write + fieldset: DIAGPAR37 + - name: DIAGPAR36 + description: Diagnostic Parity Register 36. + byte_offset: 860 + access: Write + fieldset: DIAGPAR36 + - name: DIAGPAR35 + description: Diagnostic Parity Register 35. + byte_offset: 864 + access: Write + fieldset: DIAGPAR35 + - name: DIAGPAR34 + description: Diagnostic Parity Register 34. + byte_offset: 868 + access: Write + fieldset: DIAGPAR34 + - name: DIAGPAR33 + description: Diagnostic Parity Register 33. + byte_offset: 872 + access: Write + fieldset: DIAGPAR33 + - name: DIAGPAR32 + description: Diagnostic Parity Register 32. + byte_offset: 876 + access: Write + fieldset: DIAGPAR32 + - name: DIAGPAR31 + description: Diagnostic Parity Register 31. + byte_offset: 880 + access: Write + fieldset: DIAGPAR31 + - name: DIAGPAR30 + description: Diagnostic Parity Register 30. + byte_offset: 884 + access: Write + fieldset: DIAGPAR30 + - name: DIAGPAR29 + description: Diagnostic Parity Register 29. + byte_offset: 888 + access: Write + fieldset: DIAGPAR29 + - name: DIAGPAR28 + description: Diagnostic Parity Register 28. + byte_offset: 892 + access: Write + fieldset: DIAGPAR28 + - name: DIAGPAR27 + description: Diagnostic Parity Register 27. + byte_offset: 896 + access: Write + fieldset: DIAGPAR27 + - name: DIAGPAR26 + description: Diagnostic Parity Register 26. + byte_offset: 900 + access: Write + fieldset: DIAGPAR26 + - name: DIAGPAR25 + description: Diagnostic Parity Register 25. + byte_offset: 904 + access: Write + fieldset: DIAGPAR25 + - name: DIAGPAR24 + description: Diagnostic Parity Register 24. + byte_offset: 908 + access: Write + fieldset: DIAGPAR24 + - name: DIAGPAR23 + description: Diagnostic Parity Register 23. + byte_offset: 912 + access: Write + fieldset: DIAGPAR23 + - name: DIAGPAR22 + description: Diagnostic Parity Register 22. + byte_offset: 916 + access: Write + fieldset: DIAGPAR22 + - name: DIAGPAR21 + description: Diagnostic Parity Register 21. + byte_offset: 920 + access: Write + fieldset: DIAGPAR21 + - name: DIAGPAR20 + description: Diagnostic Parity Register 20. + byte_offset: 924 + access: Write + fieldset: DIAGPAR20 + - name: DIAGPAR19 + description: Diagnostic Parity Register 19. + byte_offset: 928 + access: Write + fieldset: DIAGPAR19 + - name: DIAGPAR18 + description: Diagnostic Parity Register 18. + byte_offset: 932 + access: Write + fieldset: DIAGPAR18 + - name: DIAGPAR17 + description: Diagnostic Parity Register 17. + byte_offset: 936 + access: Write + fieldset: DIAGPAR17 + - name: DIAGPAR16 + description: Diagnostic Parity Register 16. + byte_offset: 940 + access: Write + fieldset: DIAGPAR16 + - name: DIAGPAR15 + description: Diagnostic Parity Register 15. + byte_offset: 944 + access: Write + fieldset: DIAGPAR15 + - name: DIAGPAR14 + description: Diagnostic Parity Register 14. + byte_offset: 948 + access: Write + fieldset: DIAGPAR14 + - name: DIAGPAR13 + description: Diagnostic Parity Register 13. + byte_offset: 952 + access: Write + fieldset: DIAGPAR13 + - name: DIAGPAR12 + description: Diagnostic Parity Register 12. + byte_offset: 956 + access: Write + fieldset: DIAGPAR12 + - name: DIAGPAR11 + description: Diagnostic Parity Register 11. + byte_offset: 960 + access: Write + fieldset: DIAGPAR11 + - name: DIAGPAR10 + description: Diagnostic Parity Register 10. + byte_offset: 964 + access: Write + fieldset: DIAGPAR10 + - name: DIAGPAR9 + description: Diagnostic Parity Register 9. + byte_offset: 968 + access: Write + fieldset: DIAGPAR9 + - name: DIAGPAR8 + description: Diagnostic Parity Register 8. + byte_offset: 972 + access: Write + fieldset: DIAGPAR8 + - name: DIAGPAR7 + description: Diagnostic Parity Register 7. + byte_offset: 976 + access: Write + fieldset: DIAGPAR7 + - name: DIAGPAR6 + description: Diagnostic Parity Register 6. + byte_offset: 980 + access: Write + fieldset: DIAGPAR6 + - name: DIAGPAR5 + description: Diagnostic Parity Register 5. + byte_offset: 984 + access: Write + fieldset: DIAGPAR5 + - name: DIAGPAR4 + description: Diagnostic Parity Register 4. + byte_offset: 988 + access: Write + fieldset: DIAGPAR4 + - name: DIAGPAR3 + description: Diagnostic Parity Register 3. + byte_offset: 992 + access: Write + fieldset: DIAGPAR3 + - name: DIAGPAR2 + description: Diagnostic Parity Register 2. + byte_offset: 996 + access: Write + fieldset: DIAGPAR2 + - name: DIAGPAR1 + description: Diagnostic Parity Register 1. + byte_offset: 1000 + access: Write + fieldset: DIAGPAR1 + - name: DIAGPAR0 + description: Diagnostic Parity Register 0. + byte_offset: 1004 + access: Write + fieldset: DIAGPAR0 + - name: DIAGIFRST + description: Diagnostic Interface Reset Register. + byte_offset: 1012 + fieldset: DIAGIFRST + - name: DIAGPARFV + description: Diagnostic Parity Fail Vector Register. + byte_offset: 1016 + access: Read + fieldset: DIAGPARFV + - name: DIAGSTAT + description: Diagnostic Status Register. + byte_offset: 1020 + access: Read + fieldset: DIAGSTAT +block/PUBCFG_CPU_CONNECT: + items: + - name: PUBCFG_CPU_NUM + description: CPU connect register. + array: + len: 32 + stride: 4 + byte_offset: 0 + fieldset: PUBCFG_CPU_NUM +block/PUBCFG_EXPORT: + items: + - name: PUBCFG_EXPORT_PORT + description: Export channel ID register. + byte_offset: 0 + fieldset: PUBCFG_EXPORT_PORT +block/PUBCFG_FPUB: + items: + - name: PUBCFG_FPUB_PORT + description: Publisher channel ID register. + array: + len: 26 + stride: 4 + byte_offset: 0 + fieldset: PUBCFG_FPUB_PORT +block/PUBCFG_FSUB: + items: + - name: PUBCFG_FSUB_PORT + description: Subscriber channel ID register. + array: + len: 32 + stride: 4 + byte_offset: 0 + fieldset: PUBCFG_FSUB_PORT +block/PUBCFG_IMPORT: + items: + - name: PUBCFG_IMPORT_PORT + description: Import channel ID registe. + byte_offset: 0 + fieldset: PUBCFG_IMPORT_PORT +block/SECCFG_CPU_CONNECT: + items: + - name: SECCFG_CPU_NUM + description: CPU connect register. + array: + len: 32 + stride: 1 + byte_offset: 0 + bit_size: 8 + fieldset: SECCFG_CPU_NUM +block/SECCFG_EXPORT: + items: + - name: SECCFG_EXPORT_PORT + description: Export channel ID register. + byte_offset: 0 + bit_size: 8 +block/SECCFG_FPUB: + items: + - name: SECCFG_FPUB_PORT + description: Publisher channel ID register. + array: + len: 26 + stride: 1 + byte_offset: 0 + bit_size: 8 +block/SECCFG_FSUB: + items: + - name: SECCFG_FSUB_PORT + description: Subscriber channel ID register. + array: + len: 32 + stride: 1 + byte_offset: 0 + bit_size: 8 +block/SECCFG_IMPORT: + items: + - name: SECCFG_IMPORT_PORT + description: Import channel ID registe. + byte_offset: 0 + bit_size: 8 +fieldset/CTL: + description: Event Manager control register. + bit_size: 8 + fields: + - name: OVRWR_EN + description: Enable overwrite of config even if resources are already configured. By default, a configuration cannot be overwritten. + bit_offset: 0 + bit_size: 4 + enum: OVRWR_EN +fieldset/DIAGIFRST: + description: Diagnostic Interface Reset Register. + fields: + - name: ASSERTIFRST + description: Writing a 1 will synchronously clear the Diagnostic Interface. The STICKY bits for status and well as the PARFV will be cleared. If a true functional failure still exists, the interface will re-assert FUNCFAIL on the cycle following the interface reset. + bit_offset: 0 + bit_size: 1 + - name: DIAGPASSCLR + description: Writing a 1 will synchronously clear the PARFV MMR DPINDEX field. The STICKY bit for DIAGPASS status will be cleared as well. + bit_offset: 1 + bit_size: 1 +fieldset/DIAGPAR0: + description: Diagnostic Parity Register 0. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR1: + description: Diagnostic Parity Register 1. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR10: + description: Diagnostic Parity Register 10. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR100: + description: Diagnostic Parity Register 100. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR101: + description: Diagnostic Parity Register 101. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR102: + description: Diagnostic Parity Register 102. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR103: + description: Diagnostic Parity Register 103. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR104: + description: Diagnostic Parity Register 104. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR105: + description: Diagnostic Parity Register 105. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR106: + description: Diagnostic Parity Register 106. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR107: + description: Diagnostic Parity Register 107. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR108: + description: Diagnostic Parity Register 108. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR109: + description: Diagnostic Parity Register 109. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR11: + description: Diagnostic Parity Register 11. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR110: + description: Diagnostic Parity Register 110. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR111: + description: Diagnostic Parity Register 111. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR112: + description: Diagnostic Parity Register 112. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR113: + description: Diagnostic Parity Register 113. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR114: + description: Diagnostic Parity Register 114. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR115: + description: Diagnostic Parity Register 115. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR116: + description: Diagnostic Parity Register 116. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR117: + description: Diagnostic Parity Register 117. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR118: + description: Diagnostic Parity Register 118. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR119: + description: Diagnostic Parity Register 119. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR12: + description: Diagnostic Parity Register 12. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR120: + description: Diagnostic Parity Register 120. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR121: + description: Diagnostic Parity Register 121. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR122: + description: Diagnostic Parity Register 122. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR123: + description: Diagnostic Parity Register 123. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR124: + description: Diagnostic Parity Register 124. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR125: + description: Diagnostic Parity Register 125. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR126: + description: Diagnostic Parity Register 126. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR127: + description: Diagnostic Parity Register 127. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR128: + description: Diagnostic Parity Register 128. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR129: + description: Diagnostic Parity Register 129. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR13: + description: Diagnostic Parity Register 13. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR130: + description: Diagnostic Parity Register 130. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR131: + description: Diagnostic Parity Register 131. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR132: + description: Diagnostic Parity Register 132. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR133: + description: Diagnostic Parity Register 133. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR134: + description: Diagnostic Parity Register 134. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR135: + description: Diagnostic Parity Register 135. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR136: + description: Diagnostic Parity Register 136. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR137: + description: Diagnostic Parity Register 137. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR138: + description: Diagnostic Parity Register 138. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR139: + description: Diagnostic Parity Register 139. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR14: + description: Diagnostic Parity Register 14. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR140: + description: Diagnostic Parity Register 140. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR141: + description: Diagnostic Parity Register 141. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR142: + description: Diagnostic Parity Register 142. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR143: + description: Diagnostic Parity Register 143. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR144: + description: Diagnostic Parity Register 144. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR145: + description: Diagnostic Parity Register 145. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR146: + description: Diagnostic Parity Register 146. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR147: + description: Diagnostic Parity Register 147. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR148: + description: Diagnostic Parity Register 148. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR149: + description: Diagnostic Parity Register 149. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR15: + description: Diagnostic Parity Register 15. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR150: + description: Diagnostic Parity Register 150. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR151: + description: Diagnostic Parity Register 151. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR152: + description: Diagnostic Parity Register 152. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR153: + description: Diagnostic Parity Register 153. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR154: + description: Diagnostic Parity Register 154. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR155: + description: Diagnostic Parity Register 155. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR156: + description: Diagnostic Parity Register 156. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR157: + description: Diagnostic Parity Register 157. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR158: + description: Diagnostic Parity Register 158. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR159: + description: Diagnostic Parity Register 159. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR16: + description: Diagnostic Parity Register 16. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR160: + description: Diagnostic Parity Register 160. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR161: + description: Diagnostic Parity Register 161. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR162: + description: Diagnostic Parity Register 162. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR163: + description: Diagnostic Parity Register 163. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR164: + description: Diagnostic Parity Register 164. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR165: + description: Diagnostic Parity Register 165. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR166: + description: Diagnostic Parity Register 166. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR167: + description: Diagnostic Parity Register 167. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR168: + description: Diagnostic Parity Register 168. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR169: + description: Diagnostic Parity Register 169. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR17: + description: Diagnostic Parity Register 17. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR170: + description: Diagnostic Parity Register 170. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR171: + description: Diagnostic Parity Register 171. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR172: + description: Diagnostic Parity Register 172. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR173: + description: Diagnostic Parity Register 173. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR174: + description: Diagnostic Parity Register 174. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR175: + description: Diagnostic Parity Register 175. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR176: + description: Diagnostic Parity Register 176. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR177: + description: Diagnostic Parity Register 177. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR178: + description: Diagnostic Parity Register 178. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR179: + description: Diagnostic Parity Register 179. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR18: + description: Diagnostic Parity Register 18. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR180: + description: Diagnostic Parity Register 180. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR181: + description: Diagnostic Parity Register 181. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR182: + description: Diagnostic Parity Register 182. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR183: + description: Diagnostic Parity Register 183. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR184: + description: Diagnostic Parity Register 184. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR185: + description: Diagnostic Parity Register 185. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR186: + description: Diagnostic Parity Register 186. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR187: + description: Diagnostic Parity Register 187. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR188: + description: Diagnostic Parity Register 188. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR189: + description: Diagnostic Parity Register 189. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR19: + description: Diagnostic Parity Register 19. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR190: + description: Diagnostic Parity Register 190. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR191: + description: Diagnostic Parity Register 191. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR192: + description: Diagnostic Parity Register 768. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR2: + description: Diagnostic Parity Register 2. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR20: + description: Diagnostic Parity Register 20. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR21: + description: Diagnostic Parity Register 21. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR22: + description: Diagnostic Parity Register 22. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR23: + description: Diagnostic Parity Register 23. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR24: + description: Diagnostic Parity Register 24. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR25: + description: Diagnostic Parity Register 25. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR26: + description: Diagnostic Parity Register 26. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR27: + description: Diagnostic Parity Register 27. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR28: + description: Diagnostic Parity Register 28. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR29: + description: Diagnostic Parity Register 29. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR3: + description: Diagnostic Parity Register 3. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR30: + description: Diagnostic Parity Register 30. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR31: + description: Diagnostic Parity Register 31. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR32: + description: Diagnostic Parity Register 32. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR33: + description: Diagnostic Parity Register 33. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR34: + description: Diagnostic Parity Register 34. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR35: + description: Diagnostic Parity Register 35. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR36: + description: Diagnostic Parity Register 36. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR37: + description: Diagnostic Parity Register 37. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR38: + description: Diagnostic Parity Register 38. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR39: + description: Diagnostic Parity Register 39. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR4: + description: Diagnostic Parity Register 4. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR40: + description: Diagnostic Parity Register 40. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR41: + description: Diagnostic Parity Register 41. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR42: + description: Diagnostic Parity Register 42. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR43: + description: Diagnostic Parity Register 43. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR44: + description: Diagnostic Parity Register 44. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR45: + description: Diagnostic Parity Register 45. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR46: + description: Diagnostic Parity Register 46. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR47: + description: Diagnostic Parity Register 47. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR48: + description: Diagnostic Parity Register 48. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR49: + description: Diagnostic Parity Register 49. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR5: + description: Diagnostic Parity Register 5. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR50: + description: Diagnostic Parity Register 50. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR51: + description: Diagnostic Parity Register 51. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR52: + description: Diagnostic Parity Register 52. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR53: + description: Diagnostic Parity Register 53. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR54: + description: Diagnostic Parity Register 54. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR55: + description: Diagnostic Parity Register 55. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR56: + description: Diagnostic Parity Register 56. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR57: + description: Diagnostic Parity Register 57. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR58: + description: Diagnostic Parity Register 58. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR59: + description: Diagnostic Parity Register 59. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR6: + description: Diagnostic Parity Register 6. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR60: + description: Diagnostic Parity Register 60. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR61: + description: Diagnostic Parity Register 61. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR62: + description: Diagnostic Parity Register 62. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR63: + description: Diagnostic Parity Register 63. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR64: + description: Diagnostic Parity Register 64. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR65: + description: Diagnostic Parity Register 65. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR66: + description: Diagnostic Parity Register 66. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR67: + description: Diagnostic Parity Register 67. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR68: + description: Diagnostic Parity Register 68. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR69: + description: Diagnostic Parity Register 69. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR7: + description: Diagnostic Parity Register 7. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR70: + description: Diagnostic Parity Register 70. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR71: + description: Diagnostic Parity Register 71. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR72: + description: Diagnostic Parity Register 72. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR73: + description: Diagnostic Parity Register 73. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR74: + description: Diagnostic Parity Register 74. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR75: + description: Diagnostic Parity Register 75. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR76: + description: Diagnostic Parity Register 76. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR77: + description: Diagnostic Parity Register 77. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR78: + description: Diagnostic Parity Register 78. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR79: + description: Diagnostic Parity Register 79. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR8: + description: Diagnostic Parity Register 8. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR80: + description: Diagnostic Parity Register 80. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR81: + description: Diagnostic Parity Register 81. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR82: + description: Diagnostic Parity Register 82. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR83: + description: Diagnostic Parity Register 83. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR84: + description: Diagnostic Parity Register 84. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR85: + description: Diagnostic Parity Register 85. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR86: + description: Diagnostic Parity Register 86. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR87: + description: Diagnostic Parity Register 87. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR88: + description: Diagnostic Parity Register 88. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR89: + description: Diagnostic Parity Register 89. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR9: + description: Diagnostic Parity Register 9. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR90: + description: Diagnostic Parity Register 90. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR91: + description: Diagnostic Parity Register 91. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR92: + description: Diagnostic Parity Register 92. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR93: + description: Diagnostic Parity Register 93. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR94: + description: Diagnostic Parity Register 94. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR95: + description: Diagnostic Parity Register 95. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR96: + description: Diagnostic Parity Register 96. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR97: + description: Diagnostic Parity Register 97. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR98: + description: Diagnostic Parity Register 98. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPAR99: + description: Diagnostic Parity Register 99. + fields: + - name: ASSERTDIAG + description: Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. + bit_offset: 0 + bit_size: 1 +fieldset/DIAGPARFV: + description: Diagnostic Parity Fail Vector Register. + fields: + - name: INDEX + description: 'Index of DIAG MMR creating the failure. NOTE: INDEX value of 1 corresponds to DIAGPAR0, 2 corresponds to DIAGPAR1 and so on.' + bit_offset: 0 + bit_size: 10 + - name: DPINDEX + description: 'Index of DIAG PASS MMR. NOTE: DPINDEX value of 1 corresponds to DIAGPAR0, 2 corresponds to DIAGPAR1 and so on.' + bit_offset: 16 + bit_size: 10 +fieldset/DIAGSTAT: + description: Diagnostic Status Register. + fields: + - name: STATE + description: Current diagnostic state. + bit_offset: 0 + bit_size: 3 + enum: STATE + - name: NUMDIAG + description: This is a hardware constant that indicates how many DIAGPAR registers are included in this SFTYDIAG sub-region. + bit_offset: 16 + bit_size: 10 +fieldset/IMPEXPCFG_EXPORT_PORT: + description: Export channel ID register. + fields: + - name: CHANID + description: Channel ID for import side to connect to. + bit_offset: 0 + bit_size: 8 +fieldset/IMPEXPCFG_IMPORT_PORT: + description: Import channel ID registe. + fields: + - name: CHANID + description: Channel ID for import side to connect to. + bit_offset: 0 + bit_size: 8 +fieldset/PUBCFG_CPU_NUM: + description: CPU connect register. + fields: + - name: CPUSS0_CONN + description: CPUSS0 connect bit. + bit_offset: 1 + bit_size: 1 +fieldset/PUBCFG_DESC: + description: Module Description. + fields: + - name: MINREV + description: Minor rev of the IP. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major rev of the IP. + bit_offset: 4 + bit_size: 4 + - name: INSTNUM + description: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances. + bit_offset: 8 + bit_size: 4 + - name: FEATUREVER + description: Feature Set for the module *instance*. + bit_offset: 12 + bit_size: 4 + - name: MODULEID + description: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. + bit_offset: 16 + bit_size: 16 +fieldset/PUBCFG_DESC_EX: + description: Extended Module Description. + fields: + - name: NUM_SINGLE_CHANNEL + description: Number of single channels contained in this instance of event manager. + bit_offset: 0 + bit_size: 8 + - name: NUM_DUAL_CHANNEL + description: Number of dual channels contained in this instance of event manager. + bit_offset: 8 + bit_size: 8 + - name: NUM_IMPORT + description: Number of import ports available in this EventManager instantiation. + bit_offset: 16 + bit_size: 8 + - name: NUM_EXPORT + description: Number of export ports available in this EventManager instantiation. + bit_offset: 24 + bit_size: 8 +fieldset/PUBCFG_EXPORT_PORT: + description: Export channel ID register. + fields: + - name: CHANID + description: Channel ID for export side to connect to. + bit_offset: 0 + bit_size: 8 +fieldset/PUBCFG_FPUB_PORT: + description: Publisher channel ID register. + fields: + - name: CHANID + description: Channel ID for publisher to connect to. + bit_offset: 0 + bit_size: 8 +fieldset/PUBCFG_FSUB_PORT: + description: Subscriber channel ID register. + fields: + - name: CHANID + description: Channel ID for subscriber to connect to. + bit_offset: 0 + bit_size: 8 +fieldset/PUBCFG_IMPORT_PORT: + description: Import channel ID registe. + fields: + - name: CHANID + description: Channel ID for import side to connect to. + bit_offset: 0 + bit_size: 8 +fieldset/SECCFG_CPU_NUM: + description: CPU connect register. + bit_size: 8 + fields: + - name: CPUSS0_CONN + description: CPUSS0 connect bit. + bit_offset: 1 + bit_size: 1 +fieldset/SECCFG_DESC: + description: Module Description. + fields: + - name: MINREV + description: Minor rev of the IP. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major rev of the IP. + bit_offset: 4 + bit_size: 4 + - name: INSTNUM + description: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances. + bit_offset: 8 + bit_size: 4 + - name: FEATUREVER + description: Feature Set for the module *instance*. + bit_offset: 12 + bit_size: 4 + - name: MODULEID + description: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. + bit_offset: 16 + bit_size: 16 +fieldset/SECCFG_DESC_EX: + description: Extended Module Description. + fields: + - name: NUM_SINGLE_CHANNEL + description: Number of single channels contained in this instance of event manager. + bit_offset: 0 + bit_size: 8 + - name: NUM_DUAL_CHANNEL + description: Number of dual channels contained in this instance of event manager. + bit_offset: 8 + bit_size: 8 + - name: NUM_IMPORT + description: Number of import ports available in this EventManager instantiation. + bit_offset: 16 + bit_size: 8 + - name: NUM_EXPORT + description: Number of export ports available in this EventManager instantiation. + bit_offset: 24 + bit_size: 8 +enum/OVRWR_EN: + bit_size: 4 + variants: + - name: DISABLE + description: Overwrite is disabled. Mode is same as in UNASG aperture. + value: 5 + - name: ENABLED + description: Ovewrite is enabled. + value: 10 +enum/STATE: + bit_size: 3 + variants: + - name: NONE + description: No failures and no diagnostic. + value: 0 + - name: FUNC_FAIL + description: Functional Failure. + value: 1 + - name: DIAG_FAIL + description: Diagnostic Failure. + value: 2 + - name: DIAG_PASS + description: Diagnostic Pass. + value: 4 diff --git a/data/registers/flashctl_v1.yaml b/data/registers/flashctl_v1.yaml new file mode 100644 index 0000000..1d07d9f --- /dev/null +++ b/data/registers/flashctl_v1.yaml @@ -0,0 +1,818 @@ +block/FLASHCTL: + description: F65NW. + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 4128 + access: Read + fieldset: IIDX + - name: IMASK + description: Interrupt Mask Register. + byte_offset: 4136 + fieldset: INT + - name: RIS + description: Raw Interrupt Status Register. + byte_offset: 4144 + access: Read + fieldset: INT + - name: MIS + description: Masked Interrupt Status Register. + byte_offset: 4152 + access: Read + fieldset: INT + - name: ISET + description: Interrupt Set Register. + byte_offset: 4160 + access: Write + fieldset: INT + - name: ICLR + description: Interrupt Clear Register. + byte_offset: 4168 + access: Write + fieldset: INT + - name: EVT_MODE + description: Event Mode. + byte_offset: 4320 + access: Read + fieldset: EVT_MODE + - name: DESC + description: Hardware Version Description Register. + byte_offset: 4348 + access: Read + fieldset: DESC + - name: CMDEXEC + description: Command Execute Register. + byte_offset: 4352 + fieldset: CMDEXEC + - name: CMDTYPE + description: Command Type Register. + byte_offset: 4356 + fieldset: CMDTYPE + - name: CMDCTL + description: Command Control Register. + byte_offset: 4360 + fieldset: CMDCTL + - name: CMDADDR + description: Command Address Register. + byte_offset: 4384 + - name: CMDBYTEN + description: Command Program Byte Enable Register. + byte_offset: 4388 + fieldset: CMDBYTEN + - name: CMDDATA0 + description: Command Data Register 0. + byte_offset: 4400 + - name: CMDDATA1 + description: Command Data Register 1. + byte_offset: 4404 + - name: CMDDATAECC0 + description: Command Data Register ECC 0. + byte_offset: 4528 + fieldset: CMDDATAECC0 + - name: CMDWEPROTA + description: Command Write Erase Protect A Register. + byte_offset: 4560 + - name: CMDWEPROTB + description: Command Write Erase Protect B Register. + byte_offset: 4564 + fieldset: CMDWEPROTB + - name: CMDWEPROTNM + description: Command Write Erase Protect Non-Main Register. + byte_offset: 4624 + fieldset: CMDWEPROTNM + - name: CMDWEPROTTR + description: Command Write Erase Protect Trim Register. + byte_offset: 4628 + fieldset: CMDWEPROTTR + - name: CMDWEPROTEN + description: Command Write Erase Protect Engr Register. + byte_offset: 4632 + fieldset: CMDWEPROTEN + - name: CFGCMD + description: Command Configuration Register. + byte_offset: 5040 + fieldset: CFGCMD + - name: CFGPCNT + description: Pulse Counter Configuration Register. + byte_offset: 5044 + fieldset: CFGPCNT + - name: STATCMD + description: Command Status Register. + byte_offset: 5072 + access: Read + fieldset: STATCMD + - name: STATADDR + description: Address Status Register. + byte_offset: 5076 + access: Read + fieldset: STATADDR + - name: STATPCNT + description: Pulse Count Status Register. + byte_offset: 5080 + access: Read + fieldset: STATPCNT + - name: STATMODE + description: Mode Status Register. + byte_offset: 5084 + access: Read + fieldset: STATMODE + - name: GBLINFO0 + description: Global Information Register 0. + byte_offset: 5104 + access: Read + fieldset: GBLINFO0 + - name: GBLINFO1 + description: Global Information Register 1. + byte_offset: 5108 + access: Read + fieldset: GBLINFO1 + - name: GBLINFO2 + description: Global Information Register 2. + byte_offset: 5112 + access: Read + fieldset: GBLINFO2 + - name: BANK0INFO0 + description: Bank Information Register 0 for Bank 0. + byte_offset: 5120 + access: Read + fieldset: BANK0INFO0 + - name: BANK0INFO1 + description: Bank Information Register 1 for Bank 0. + byte_offset: 5124 + access: Read + fieldset: BANK0INFO1 +fieldset/BANK0INFO0: + description: Bank Information Register 0 for Bank 0. + fields: + - name: MAINSIZE + description: 'Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512).' + bit_offset: 0 + bit_size: 12 + enum: MAINSIZE +fieldset/BANK0INFO1: + description: Bank Information Register 1 for Bank 0. + fields: + - name: NONMAINSIZE + description: 'Non-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16).' + bit_offset: 0 + bit_size: 8 + enum: NONMAINSIZE + - name: TRIMSIZE + description: 'Trim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16).' + bit_offset: 8 + bit_size: 8 + enum: TRIMSIZE + - name: ENGRSIZE + description: 'Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16).' + bit_offset: 16 + bit_size: 8 + enum: ENGRSIZE +fieldset/CFGCMD: + description: Command Configuration Register. + fields: + - name: WAITSTATE + description: Wait State setting for program verify, erase verify and read verify. + bit_offset: 0 + bit_size: 4 +fieldset/CFGPCNT: + description: Pulse Counter Configuration Register. + fields: + - name: MAXPCNTOVR + description: Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used. + bit_offset: 0 + bit_size: 1 + enum: MAXPCNTOVR + - name: MAXPCNTVAL + description: Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}. + bit_offset: 4 + bit_size: 8 +fieldset/CMDBYTEN: + description: Command Program Byte Enable Register. + fields: + - name: VAL + description: Command Byte Enable value. A 1-bit per flash word byte value is placed in this register. + bit_offset: 0 + bit_size: 9 +fieldset/CMDCTL: + description: Command Control Register. + fields: + - name: MODESEL + description: Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware. + bit_offset: 0 + bit_size: 4 + enum: MODESEL + - name: REGIONSEL + description: Bank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set. + bit_offset: 9 + bit_size: 4 + enum: REGIONSEL + - name: ADDRXLATEOVR + description: Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID. + bit_offset: 16 + bit_size: 1 + - name: ECCGENOVR + description: Override hardware generation of ECC data for program. Use data written to CMDDATAECC*. + bit_offset: 17 + bit_size: 1 + - name: SSERASEDIS + description: Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired. + bit_offset: 20 + bit_size: 1 + enum: SSERASEDIS + - name: DATAVEREN + description: Enable invalid data verify. This checks for 0->1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming. + bit_offset: 21 + bit_size: 1 +fieldset/CMDDATAECC0: + description: Command Data Register ECC 0. + fields: + - name: VAL0 + description: ECC data for bits 63:0 of the data is placed here. + bit_offset: 0 + bit_size: 8 +fieldset/CMDEXEC: + description: Command Execute Register. + fields: + - name: VAL + description: Command Execute value Initiates execution of the command specified in the CMDTYPE register. + bit_offset: 0 + bit_size: 1 +fieldset/CMDTYPE: + description: Command Type Register. + fields: + - name: COMMAND + description: Command type. + bit_offset: 0 + bit_size: 3 + enum: COMMAND + - name: SIZE + description: Command size. + bit_offset: 4 + bit_size: 3 + enum: SIZE +fieldset/CMDWEPROTB: + description: Command Write Erase Protect B Register. + fields: + - name: VAL + description: Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register. + bit_offset: 0 + bit_size: 12 +fieldset/CMDWEPROTEN: + description: Command Write Erase Protect Engr Register. + fields: + - name: VAL + description: 'Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program. and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase.' + bit_offset: 0 + bit_size: 2 +fieldset/CMDWEPROTNM: + description: Command Write Erase Protect Non-Main Register. + fields: + - name: VAL + description: 'Each bit protects 1 sector. bit [0]: When 1, sector 0 of the non-main region will be protected from program. and erase. bit [1]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the non-main will be protected from program and erase.' + bit_offset: 0 + bit_size: 1 +fieldset/CMDWEPROTTR: + description: Command Write Erase Protect Trim Register. + fields: + - name: VAL + description: 'Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program. and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase.' + bit_offset: 0 + bit_size: 1 +fieldset/DESC: + description: Hardware Version Description Register. + fields: + - name: MINREV + description: Minor Revision. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major Revision. + bit_offset: 4 + bit_size: 4 + - name: INSTNUM + description: Instance number. + bit_offset: 8 + bit_size: 4 + - name: FEATUREVER + description: Feature set. + bit_offset: 12 + bit_size: 4 + - name: MODULEID + description: Module ID. + bit_offset: 16 + bit_size: 16 +fieldset/EVT_MODE: + description: Event Mode. + fields: + - name: INT0_CFG + description: Event line mode select for peripheral event. + bit_offset: 0 + bit_size: 2 + enum: EVT_CFG +fieldset/GBLINFO0: + description: Global Information Register 0. + fields: + - name: SECTORSIZE + description: Sector size in bytes. + bit_offset: 0 + bit_size: 16 + enum: SECTORSIZE + - name: NUMBANKS + description: 'Number of banks instantiated Minimum: 1 Maximum: 5.' + bit_offset: 16 + bit_size: 3 +fieldset/GBLINFO1: + description: Global Information Register 1. + fields: + - name: DATAWIDTH + description: Data width in bits. + bit_offset: 0 + bit_size: 8 + enum: DATAWIDTH + - name: ECCWIDTH + description: ECC data width in bits. + bit_offset: 8 + bit_size: 5 + enum: ECCWIDTH + - name: REDWIDTH + description: Redundant data width in bits. + bit_offset: 16 + bit_size: 3 + enum: REDWIDTH +fieldset/GBLINFO2: + description: Global Information Register 2. + fields: + - name: DATAREGISTERS + description: Number of data registers present. + bit_offset: 0 + bit_size: 4 +fieldset/IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt. + bit_offset: 0 + bit_size: 1 + enum: STAT +fieldset/INT: + description: Interrupt Clear Register. + fields: + - name: DONE + description: '0: No effect 1: Clear the DONE interrupt in the RIS register.' + bit_offset: 0 + bit_size: 1 +fieldset/STATADDR: + description: Address Status Register. + fields: + - name: BANKADDR + description: Current Bank Address A bank offset address is stored in this register. + bit_offset: 0 + bit_size: 16 + - name: REGIONID + description: Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating. + bit_offset: 16 + bit_size: 5 + enum: REGIONID + - name: BANKID + description: Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank. + bit_offset: 21 + bit_size: 5 + enum: BANKID +fieldset/STATCMD: + description: Command Status Register. + fields: + - name: CMDDONE + description: Command Done. + bit_offset: 0 + bit_size: 1 + enum: CMDDONE + - name: CMDPASS + description: Command Pass - valid when CMD_DONE field is 1. + bit_offset: 1 + bit_size: 1 + enum: CMDPASS + - name: CMDINPROGRESS + description: Command In Progress. + bit_offset: 2 + bit_size: 1 + enum: CMDINPROGRESS + - name: FAILWEPROT + description: Command failed due to Write/Erase Protect Sector Violation. + bit_offset: 4 + bit_size: 1 + enum: FAILWEPROT + - name: FAILVERIFY + description: Command failed due to verify error. + bit_offset: 5 + bit_size: 1 + enum: FAILVERIFY + - name: FAILILLADDR + description: Command failed due to the use of an illegal address. + bit_offset: 6 + bit_size: 1 + enum: FAILILLADDR + - name: FAILMODE + description: Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode. + bit_offset: 7 + bit_size: 1 + enum: FAILMODE + - name: FAILINVDATA + description: Program command failed because an attempt was made to program a stored 0 value to a 1. + bit_offset: 8 + bit_size: 1 + enum: FAILINVDATA + - name: FAILMISC + description: Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit. + bit_offset: 12 + bit_size: 1 + enum: FAILMISC +fieldset/STATMODE: + description: Mode Status Register. + fields: + - name: BANKNOTINRD + description: Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank. + bit_offset: 0 + bit_size: 1 + - name: BANKMODE + description: Indicates mode of bank(s) that are not in READ mode. + bit_offset: 8 + bit_size: 4 + enum: BANKMODE + - name: BANK2TRDY + description: Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s). + bit_offset: 16 + bit_size: 1 + - name: BANK1TRDY + description: Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed. + bit_offset: 17 + bit_size: 1 +fieldset/STATPCNT: + description: Pulse Count Status Register. + fields: + - name: PULSECNT + description: Current Pulse Counter Value. + bit_offset: 0 + bit_size: 12 +enum/BANKID: + bit_size: 5 + variants: + - name: BANK0 + description: Bank 0. + value: 1 + - name: BANK1 + description: Bank 1. + value: 2 + - name: BANK2 + description: Bank 2. + value: 4 + - name: BANK3 + description: Bank 3. + value: 8 + - name: BANK4 + description: Bank 4. + value: 16 +enum/BANKMODE: + bit_size: 4 + variants: + - name: READ + description: Read Mode. + value: 0 + - name: RDMARG0 + description: Read Margin 0 Mode. + value: 2 + - name: RDMARG1 + description: Read Margin 1 Mode. + value: 4 + - name: RDMARG0B + description: Read Margin 0B Mode. + value: 6 + - name: RDMARG1B + description: Read Margin 1B Mode. + value: 7 + - name: PGMVER + description: Program Verify Mode. + value: 9 + - name: PGMSW + description: Program Single Word. + value: 10 + - name: ERASEVER + description: Erase Verify Mode. + value: 11 + - name: ERASESECT + description: Erase Sector. + value: 12 + - name: PGMMW + description: Program Multiple Word. + value: 14 + - name: ERASEBNK + description: Erase Bank. + value: 15 +enum/CMDDONE: + bit_size: 1 + variants: + - name: STATNOTDONE + description: Not Done. + value: 0 + - name: STATDONE + description: Done. + value: 1 +enum/CMDINPROGRESS: + bit_size: 1 + variants: + - name: STATCOMPLETE + description: Complete. + value: 0 + - name: STATINPROGRESS + description: In Progress. + value: 1 +enum/CMDPASS: + bit_size: 1 + variants: + - name: STATFAIL + description: Fail. + value: 0 + - name: STATPASS + description: Pass. + value: 1 +enum/COMMAND: + bit_size: 3 + variants: + - name: NOOP + description: No Operation. + value: 0 + - name: PROGRAM + description: Program. + value: 1 + - name: ERASE + description: Erase. + value: 2 + - name: READVERIFY + description: Read Verify - Perform a standalone read verify operation. + value: 3 + - name: MODECHANGE + description: Mode Change - Perform a mode change only, no other operation. + value: 4 + - name: CLEARSTATUS + description: Clear Status - Clear status bits in FW_SMSTAT only. + value: 5 + - name: BLANKVERIFY + description: Blank Verify - Check whether a flash word is in the erased state. This command may only be used with CMDTYPE.SIZE = ONEWORD. + value: 6 +enum/DATAWIDTH: + bit_size: 8 + variants: + - name: W64BIT + description: Data width is 64 bits. + value: 64 + - name: W128BIT + description: Data width is 128 bits. + value: 128 +enum/ECCWIDTH: + bit_size: 5 + variants: + - name: W0BIT + description: ECC data width is 0. ECC not used. + value: 0 + - name: W8BIT + description: ECC data width is 8 bits. + value: 8 + - name: W16BIT + description: ECC data width is 16 bits. + value: 16 +enum/ENGRSIZE: + bit_size: 8 + variants: + - name: MINSECTORS + description: Minimum value of [ENGRSIZE]. + value: 0 + - name: MAXSECTORS + description: Maximum value of [ENGRSIZE]. + value: 32 +enum/EVT_CFG: + bit_size: 2 + variants: + - name: DISABLE + description: The interrupt or event line is disabled. + value: 0 + - name: SOFTWARE + description: The interrupt or event line is in software mode. Software must clear the RIS. + value: 1 + - name: HARDWARE + description: The interrupt or event line is in hardware mode. Hardware should clear the RIS. + value: 2 +enum/FAILILLADDR: + bit_size: 1 + variants: + - name: STATNOFAIL + description: No Fail. + value: 0 + - name: STATFAIL + description: Fail. + value: 1 +enum/FAILINVDATA: + bit_size: 1 + variants: + - name: STATNOFAIL + description: No Fail. + value: 0 + - name: STATFAIL + description: Fail. + value: 1 +enum/FAILMISC: + bit_size: 1 + variants: + - name: STATNOFAIL + description: No Fail. + value: 0 + - name: STATFAIL + description: Fail. + value: 1 +enum/FAILMODE: + bit_size: 1 + variants: + - name: STATNOFAIL + description: No Fail. + value: 0 + - name: STATFAIL + description: Fail. + value: 1 +enum/FAILVERIFY: + bit_size: 1 + variants: + - name: STATNOFAIL + description: No Fail. + value: 0 + - name: STATFAIL + description: Fail. + value: 1 +enum/FAILWEPROT: + bit_size: 1 + variants: + - name: STATNOFAIL + description: No Fail. + value: 0 + - name: STATFAIL + description: Fail. + value: 1 +enum/MAINSIZE: + bit_size: 12 + variants: + - name: MINSECTORS + description: Minimum value of [MAINSIZE]. + value: 8 + - name: MAXSECTORS + description: Maximum value of [MAINSIZE]. + value: 512 +enum/MAXPCNTOVR: + bit_size: 1 + variants: + - name: DEFAULT + description: Use hard-wired (default) value for maximum pulse count. + value: 0 + - name: OVERRIDE + description: Use value from MAXPCNTVAL field as maximum puse count. + value: 1 +enum/MODESEL: + bit_size: 4 + variants: + - name: READ + description: Read Mode. + value: 0 + - name: RDMARG0 + description: Read Margin 0 Mode. + value: 2 + - name: RDMARG1 + description: Read Margin 1 Mode. + value: 4 + - name: RDMARG0B + description: Read Margin 0B Mode. + value: 6 + - name: RDMARG1B + description: Read Margin 1B Mode. + value: 7 + - name: PGMVER + description: Program Verify Mode. + value: 9 + - name: PGMSW + description: Program Single Word. + value: 10 + - name: ERASEVER + description: Erase Verify Mode. + value: 11 + - name: ERASESECT + description: Erase Sector. + value: 12 + - name: PGMMW + description: Program Multiple Word. + value: 14 + - name: ERASEBNK + description: Erase Bank. + value: 15 +enum/NONMAINSIZE: + bit_size: 8 + variants: + - name: MINSECTORS + description: Minimum value of [NONMAINSIZE]. + value: 0 + - name: MAXSECTORS + description: Maximum value of [NONMAINSIZE]. + value: 32 +enum/REDWIDTH: + bit_size: 3 + variants: + - name: W0BIT + description: Redundant data width is 0. Redundancy/Repair not present. + value: 0 + - name: W2BIT + description: Redundant data width is 2 bits. + value: 2 + - name: W4BIT + description: Redundant data width is 4 bits. + value: 4 +enum/REGIONID: + bit_size: 5 + variants: + - name: MAIN + description: Main Region. + value: 1 + - name: NONMAIN + description: Non-Main Region. + value: 2 + - name: TRIM + description: Trim Region. + value: 4 + - name: ENGR + description: Engr Region. + value: 8 +enum/REGIONSEL: + bit_size: 4 + variants: + - name: MAIN + description: Main Region. + value: 1 + - name: NONMAIN + description: Non-Main Region. + value: 2 + - name: TRIM + description: Trim Region. + value: 4 + - name: ENGR + description: Engr Region. + value: 8 +enum/SECTORSIZE: + bit_size: 16 + variants: + - name: ONEKB + description: Sector size is ONEKB. + value: 1024 + - name: TWOKB + description: Sector size is TWOKB. + value: 2048 +enum/SIZE: + bit_size: 3 + variants: + - name: ONEWORD + description: Operate on 1 flash word. + value: 0 + - name: TWOWORD + description: Operate on 2 flash words. + value: 1 + - name: FOURWORD + description: Operate on 4 flash words. + value: 2 + - name: EIGHTWORD + description: Operate on 8 flash words. + value: 3 + - name: SECTOR + description: Operate on a flash sector. + value: 4 + - name: BANK + description: Operate on an entire flash bank. + value: 5 +enum/SSERASEDIS: + bit_size: 1 + variants: + - name: ENABLE + description: Enable. + value: 0 + - name: DISABLE + description: Disable. + value: 1 +enum/STAT: + bit_size: 1 + variants: + - name: NO_INTR + description: No Interrupt Pending. + value: 0 + - name: DONE + description: DONE Interrupt Pending. + value: 1 +enum/TRIMSIZE: + bit_size: 8 + variants: + - name: MINSECTORS + description: Minimum value of [TRIMSIZE]. + value: 0 + - name: MAXSECTORS + description: Maximum value of [TRIMSIZE]. + value: 32 diff --git a/data/registers/opa_v1.yaml b/data/registers/opa_v1.yaml new file mode 100644 index 0000000..2318cb8 --- /dev/null +++ b/data/registers/opa_v1.yaml @@ -0,0 +1,273 @@ +block/GPRCM: + items: + - name: PWREN + description: Power enable. + byte_offset: 0 + fieldset: PWREN + - name: RSTCTL + description: Reset Control. + byte_offset: 4 + access: Write + fieldset: RSTCTL + - name: GPRCM_STAT + description: Status Register. + byte_offset: 20 + access: Read + fieldset: GPRCM_STAT +block/OPA: + description: PERIPHERALREGION. + items: + - name: GPRCM + array: + len: 1 + stride: 24 + byte_offset: 2048 + block: GPRCM + - name: CLKOVR + description: Clock Override. + byte_offset: 4112 + fieldset: CLKOVR + - name: PWRCTL + description: Power Control. + byte_offset: 4124 + fieldset: PWRCTL + - name: CTL + description: Control Register. + byte_offset: 4352 + fieldset: CTL + - name: CFGBASE + description: Configuration Base Register. + byte_offset: 4356 + fieldset: CFGBASE + - name: CFG + description: Configuration Register. + byte_offset: 4360 + fieldset: CFG + - name: STAT + description: Status Register. + byte_offset: 4376 + access: Read + fieldset: STAT +fieldset/CFG: + description: Configuration Register. + fields: + - name: CHOP + description: Chopping enable. + bit_offset: 0 + bit_size: 2 + enum: CHOP + - name: OUTPIN + description: Enable output pin. + bit_offset: 2 + bit_size: 1 + - name: PSEL + description: Positive OA input selection. Please refer to the device specific datasheet for exact channels available. + bit_offset: 3 + bit_size: 4 + enum: PSEL + - name: NSEL + description: Negative OA input selection. Please refer to the device specific datasheet for exact channels available. + bit_offset: 7 + bit_size: 3 + enum: NSEL + - name: MSEL + description: MSEL Mux selection. Please refer to the device specific datasheet for exact channels available. + bit_offset: 10 + bit_size: 3 + enum: MSEL + - name: GAIN + description: Gain setting. Refer to TRM for enumeration information. + bit_offset: 13 + bit_size: 3 +fieldset/CFGBASE: + description: Configuration Base Register. + fields: + - name: GBW + description: Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0. + bit_offset: 0 + bit_size: 1 + enum: GBW + - name: RRI + description: Rail-to-rail input enable. Can only be modified when STAT.BUSY=0. + bit_offset: 2 + bit_size: 1 +fieldset/CLKOVR: + description: Clock Override. + fields: + - name: OVERRIDE + description: Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request. + bit_offset: 0 + bit_size: 1 + - name: RUN_STOP + description: If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system. + bit_offset: 1 + bit_size: 1 + enum: RUN_STOP +fieldset/CTL: + description: Control Register. + fields: + - name: ENABLE + description: OAxn Enable. + bit_offset: 0 + bit_size: 1 +fieldset/GPRCM_STAT: + description: Status Register. + fields: + - name: RESETSTKY + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + bit_offset: 16 + bit_size: 1 +fieldset/PWRCTL: + description: Power Control. + fields: + - name: AUTO_OFF + description: When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled. + bit_offset: 0 + bit_size: 1 +fieldset/PWREN: + description: Power enable. + fields: + - name: ENABLE + description: Enable the power. + bit_offset: 0 + bit_size: 1 + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY +fieldset/RSTCTL: + description: Reset Control. + fields: + - name: RESETASSERT + description: Assert reset to the peripheral. + bit_offset: 0 + bit_size: 1 + - name: RESETSTKYCLR + description: Clear the RESETSTKY bit in the STAT register. + bit_offset: 1 + bit_size: 1 + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY +fieldset/STAT: + description: Status Register. + fields: + - name: RDY + description: OA ready status. + bit_offset: 0 + bit_size: 1 +enum/CHOP: + bit_size: 2 + variants: + - name: OFF + description: Chopping disable. + value: 0 + - name: ON + description: Standard chopping enable. + value: 1 + - name: AVGON + description: Chop with post average on. Requires output to be connect to ADC in average mode. + value: 2 +enum/GBW: + bit_size: 1 + variants: + - name: LOWGAIN + description: Low gain bandwidth. See device specific datasheet for gain bandwidth. + value: 0 + - name: HIGHGAIN + description: High gain bandwidth. See device specific datasheet for gain bandwidth. + value: 1 +enum/MSEL: + bit_size: 3 + variants: + - name: NC + description: no connect. + value: 0 + - name: EXTNPIN1 + description: external pin OAn-1. + value: 1 + - name: VSS + description: VSS. + value: 2 + - name: DAC12OUT + description: DAC12 Output. + value: 3 + - name: OANM1RTOP + description: OA[n-1]Rtop. + value: 4 +enum/NSEL: + bit_size: 3 + variants: + - name: NC + description: no connect. + value: 0 + - name: EXTPIN0 + description: external pin OAn-0. + value: 1 + - name: EXTPIN1 + description: external pin OAn-1. + value: 2 + - name: OANP1RBOT + description: OA[n+1]Rbot. + value: 3 + - name: OANRTAP + description: OA[n]Rtap. + value: 4 + - name: OANRTOP + description: OA[n]Rtop. + value: 5 + - name: SPARE + description: Spare input. + value: 6 +enum/PSEL: + bit_size: 4 + variants: + - name: NC + description: No connect. + value: 0 + - name: EXTPIN0 + description: external pin OA+0. + value: 1 + - name: EXTPIN1 + description: external pin OAn+1. + value: 2 + - name: DAC12OUT + description: DAC12OUT. + value: 3 + - name: DAC8OUT + description: DAC8OUT. + value: 4 + - name: VREF + description: VREF Channel. + value: 5 + - name: OANM1RTOP + description: OA[n-1]Rtop. + value: 6 + - name: GPAMP_OUT_INT + description: GPAMP_OUT_INT Input. + value: 7 + - name: VSS + description: Internal Grouund Connection. + value: 8 +enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 +enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 +enum/RUN_STOP: + bit_size: 1 + variants: + - name: RUN + description: Run/ungate functional clock. + value: 0 + - name: STOP + description: Stop/gate functional clock. + value: 1 diff --git a/data/registers/rtc_v1.yaml b/data/registers/rtc_v1.yaml new file mode 100644 index 0000000..2d9481d --- /dev/null +++ b/data/registers/rtc_v1.yaml @@ -0,0 +1,900 @@ +block/CPU_INT: + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 0 + access: Read + fieldset: CPU_INT_IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: CPU_INT + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: CPU_INT + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: CPU_INT + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: CPU_INT + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: CPU_INT +block/EVT_OUT: + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 0 + access: Read + fieldset: EVT_OUT_IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: EVT_OUT + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: EVT_OUT + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: EVT_OUT + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: EVT_OUT + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: EVT_OUT +block/GPRCM: + items: + - name: PWREN + description: Power enable. + byte_offset: 0 + fieldset: PWREN + - name: RSTCTL + description: Reset Control. + byte_offset: 4 + access: Write + fieldset: RSTCTL + - name: CLKCFG + description: Peripheral Clock Configuration Register. + byte_offset: 8 + fieldset: CLKCFG + - name: STAT + description: Status Register. + byte_offset: 20 + access: Read + fieldset: STAT +block/RTC: + description: PERIPHERALREGION. + items: + - name: FPUB_0 + description: Publisher Port 0. + byte_offset: 1092 + fieldset: FPUB_0 + - name: GPRCM + array: + len: 1 + stride: 24 + byte_offset: 2048 + block: GPRCM + - name: CLKSEL + description: Clock Select for Ultra Low Power peripherals. + byte_offset: 4100 + access: Read + fieldset: CLKSEL + - name: CPU_INT + array: + len: 1 + stride: 44 + byte_offset: 4128 + block: CPU_INT + - name: EVT_OUT + array: + len: 1 + stride: 44 + byte_offset: 4176 + block: EVT_OUT + - name: EVT_MODE + description: Event Mode. + byte_offset: 4320 + fieldset: EVT_MODE + - name: DESC + description: RTC Descriptor Register. + byte_offset: 4348 + access: Read + fieldset: DESC + - name: CLKCTL + description: RTC Clock Control Register. + byte_offset: 4352 + fieldset: CLKCTL + - name: DBGCTL + description: RTC Module Debug Control Register. + byte_offset: 4356 + fieldset: DBGCTL + - name: CTL + description: RTC Control Register. + byte_offset: 4360 + fieldset: CTL + - name: STA + description: RTC Status Register. + byte_offset: 4364 + access: Read + fieldset: STA + - name: CAL + description: RTC Clock Offset Calibration Register. + byte_offset: 4368 + fieldset: CAL + - name: TCMP + description: RTC Temperature Compensation Register. + byte_offset: 4372 + fieldset: TCMP + - name: SEC + description: RTC Seconds Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4376 + fieldset: SEC + - name: MIN + description: RTC Minutes Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4380 + fieldset: MIN + - name: HOUR + description: RTC Hours Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4384 + fieldset: HOUR + - name: DAY + description: RTC Day Of Week / Month Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4388 + fieldset: DAY + - name: MON + description: RTC Month Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4392 + fieldset: MON + - name: YEAR + description: RTC Year Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4396 + fieldset: YEAR + - name: A1MIN + description: RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4400 + fieldset: A1MIN + - name: A1HOUR + description: RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4404 + fieldset: A1HOUR + - name: A1DAY + description: RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4408 + fieldset: A1DAY + - name: A2MIN + description: RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4412 + fieldset: A2MIN + - name: A2HOUR + description: RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4416 + fieldset: A2HOUR + - name: A2DAY + description: RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format. + byte_offset: 4420 + fieldset: A2DAY + - name: PSCTL + description: RTC Prescale Timer 0/1 Control Register. + byte_offset: 4424 + fieldset: PSCTL +fieldset/A1DAY: + description: RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format. + fields: + - name: ADOW + description: Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0. + bit_offset: 0 + bit_size: 3 + - name: ADOWAE + description: Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0. + bit_offset: 7 + bit_size: 1 + - name: ADOMBIN + description: Alarm Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 5 + - name: ADOMAEBIN + description: Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. + bit_offset: 15 + bit_size: 1 + - name: ADOMLOWBCD + description: Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 16 + bit_size: 4 + - name: ADOMHIGHBCD + description: Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 20 + bit_size: 2 + - name: ADOMAEBCD + description: Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. + bit_offset: 23 + bit_size: 1 +fieldset/A1HOUR: + description: RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format. + fields: + - name: AHOURBIN + description: Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 0 + bit_size: 5 + - name: AHOURAEBIN + description: Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. + bit_offset: 7 + bit_size: 1 + - name: AHOURLOWBCD + description: Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 4 + - name: AHOURHIGHBCD + description: Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.. + bit_offset: 12 + bit_size: 2 + - name: AHOURAEBCD + description: Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. + bit_offset: 15 + bit_size: 1 +fieldset/A1MIN: + description: RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format. + fields: + - name: AMINBIN + description: Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 0 + bit_size: 6 + - name: AMINAEBIN + description: Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. + bit_offset: 7 + bit_size: 1 + - name: AMINLOWBCD + description: Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 4 + - name: AMINHIGHBCD + description: Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 12 + bit_size: 3 + - name: AMINAEBCD + description: Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. + bit_offset: 15 + bit_size: 1 +fieldset/A2DAY: + description: RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format. + fields: + - name: ADOW + description: Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0. + bit_offset: 0 + bit_size: 3 + - name: ADOWAE + description: Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0. + bit_offset: 7 + bit_size: 1 + - name: ADOMBIN + description: Alarm Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 5 + - name: ADOMAEBIN + description: Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. + bit_offset: 15 + bit_size: 1 + - name: ADOMLOWBCD + description: Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 16 + bit_size: 4 + - name: ADOMHIGHBCD + description: Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 20 + bit_size: 2 + - name: ADOMAEBCD + description: Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. + bit_offset: 23 + bit_size: 1 +fieldset/A2HOUR: + description: RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format. + fields: + - name: AHOURBIN + description: Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 0 + bit_size: 5 + - name: AHOURAEBIN + description: Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. + bit_offset: 7 + bit_size: 1 + - name: AHOURLOWBCD + description: Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 4 + - name: AHOURHIGHBCD + description: Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.. + bit_offset: 12 + bit_size: 2 + - name: AHOURAEBCD + description: Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. + bit_offset: 15 + bit_size: 1 +fieldset/A2MIN: + description: RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format. + fields: + - name: AMINBIN + description: Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 0 + bit_size: 6 + - name: AMINAEBIN + description: Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. + bit_offset: 7 + bit_size: 1 + - name: AMINLOWBCD + description: Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 4 + - name: AMINHIGHBCD + description: Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 12 + bit_size: 3 + - name: AMINAEBCD + description: Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. + bit_offset: 15 + bit_size: 1 +fieldset/CAL: + description: RTC Clock Offset Calibration Register. + fields: + - name: RTCOCALX + description: Real-time clock offset error calibration. Each LSB represents approximately +1ppm (RTCOCALXS = 1) or -1ppm (RTCOCALXS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm will be ignored by hardware. + bit_offset: 0 + bit_size: 8 + - name: RTCOCALS + description: Real-time clock offset error calibration sign. This bit decides the sign of offset error calibration. + bit_offset: 15 + bit_size: 1 + enum: RTCOCALS + - name: RTCCALFX + description: Real-time clock calibration frequency. Selects frequency output to RTC_OUT pin for calibration measurement. The corresponding port must be configured for the peripheral module function. + bit_offset: 16 + bit_size: 2 + enum: RTCCALFX +fieldset/CLKCFG: + description: Peripheral Clock Configuration Register. + fields: + - name: BLOCKASYNC + description: Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz. + bit_offset: 8 + bit_size: 1 +fieldset/CLKCTL: + description: RTC Clock Control Register. + fields: + - name: MODCLKEN + description: This bit enables the supply of the 32kHz clock to the RTC. It will not power-up the 32kHz crystal oscillator this needs to be done in the Clock System Module. + bit_offset: 31 + bit_size: 1 +fieldset/CLKSEL: + description: Clock Select for Ultra Low Power peripherals. + fields: + - name: LFCLK_SEL + description: Selects LFCLK as clock source if enabled. + bit_offset: 1 + bit_size: 1 +fieldset/CPU_INT: + description: Interrupt clear. + fields: + - name: RTCRDY + description: Clear RTC-Ready interrupt. + bit_offset: 0 + bit_size: 1 + - name: RTCTEV + description: Clear Time-Event interrupt. + bit_offset: 1 + bit_size: 1 + - name: RTCA1 + description: Clear Alarm-1 interrupt. + bit_offset: 2 + bit_size: 1 + - name: RTCA2 + description: Clear Alarm-2 interrupt. + bit_offset: 3 + bit_size: 1 + - name: RT0PS + description: Clear Prescaler-0 interrupt. + bit_offset: 4 + bit_size: 1 + - name: RT1PS + description: Clear Prescaler-1 interrupt. + bit_offset: 5 + bit_size: 1 +fieldset/CPU_INT_IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: CPU_INT_IIDX_STAT +fieldset/CTL: + description: RTC Control Register. + fields: + - name: RTCTEVTX + description: Real-time clock time event. + bit_offset: 0 + bit_size: 2 + enum: RTCTEVTX + - name: RTCBCD + description: Real-time clock BCD select. Selects BCD counting for real-time clock. + bit_offset: 7 + bit_size: 1 + enum: RTCBCD +fieldset/DAY: + description: RTC Day Of Week / Month Register - Calendar Mode With Binary / BCD Format. + fields: + - name: DOW + description: Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0. + bit_offset: 0 + bit_size: 3 + - name: DOMBIN + description: Day of month Binary (1 to 28, 29, 30, 31). If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 5 + - name: DOMLOWBCD + description: Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 16 + bit_size: 4 + - name: DOMHIGHBCD + description: Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 20 + bit_size: 2 +fieldset/DBGCTL: + description: RTC Module Debug Control Register. + fields: + - name: DBGRUN + description: Debug Run. + bit_offset: 0 + bit_size: 1 + enum: DBGRUN + - name: DBGINT + description: Debug Interrupt Enable. + bit_offset: 1 + bit_size: 1 +fieldset/DESC: + description: RTC Descriptor Register. + fields: + - name: MINREV + description: Minor revision. This number holds the module revision and is incremented by the module developers. n = Minor module revision (see device-specific data sheet). + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major revision. This number holds the module revision and is incremented by the module developers. n = Major version (see device-specific data sheet). + bit_offset: 4 + bit_size: 4 + - name: INSTNUM + description: Instantiated version. Describes which instance of the module accessed. + bit_offset: 8 + bit_size: 4 + enum: INSTNUM + - name: FEATUREVER + description: Feature set of this module. Differentiates the complexity of the actually instantiated module if there are differences. + bit_offset: 12 + bit_size: 4 + - name: MODULEID + description: Module identifier. This ID is unique for each module. 0x0911 = Module ID of the RTC Module. + bit_offset: 16 + bit_size: 16 +fieldset/EVT_MODE: + description: Event Mode. + fields: + - name: EVT0_CFG + description: Event line mode 0 select. + bit_offset: 0 + bit_size: 2 + enum: EVT_CFG + - name: EVT_OUT + description: Event line mode 1 select. + bit_offset: 2 + bit_size: 2 + enum: EVT_CFG +fieldset/EVT_OUT: + description: Interrupt clear. + fields: + - name: RTCRDY + description: Clear RTC-Ready interrupt. + bit_offset: 0 + bit_size: 1 + - name: RTCTEV + description: Clear Time-Event interrupt. + bit_offset: 1 + bit_size: 1 + - name: RTCA1 + description: Clear Alarm-1 interrupt. + bit_offset: 2 + bit_size: 1 + - name: RTCA2 + description: Clear Alarm-2 interrupt. + bit_offset: 3 + bit_size: 1 + - name: RT0PS + description: Clear Prescaler-0 interrupt. + bit_offset: 4 + bit_size: 1 + - name: RT1PS + description: Clear Prescaler-1 interrupt. + bit_offset: 5 + bit_size: 1 +fieldset/EVT_OUT_IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: EVT_OUT_IIDX_STAT +fieldset/FPUB_0: + description: Publisher Port 0. + fields: + - name: CHANID + description: 0 = disconnected. 1-15 = connected to channelID = CHANID. + bit_offset: 0 + bit_size: 4 +fieldset/HOUR: + description: RTC Hours Register - Calendar Mode With Binary / BCD Format. + fields: + - name: HOURBIN + description: Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 0 + bit_size: 5 + - name: HOURLOWBCD + description: Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 4 + - name: HOURHIGHBCD + description: Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 12 + bit_size: 2 +fieldset/MIN: + description: RTC Minutes Register - Calendar Mode With Binary / BCD Format. + fields: + - name: MINBIN + description: Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 0 + bit_size: 6 + - name: MINLOWBCD + description: Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 4 + - name: MINHIGHBCD + description: Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 12 + bit_size: 3 +fieldset/MON: + description: RTC Month Register - Calendar Mode With Binary / BCD Format. + fields: + - name: MONBIN + description: Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 0 + bit_size: 4 + - name: MONLOWBCD + description: Month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 4 + - name: MONHIGHBCD + description: Month BCD high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 12 + bit_size: 1 +fieldset/PSCTL: + description: RTC Prescale Timer 0/1 Control Register. + fields: + - name: RT0IP + description: Prescale timer 0 interrupt interval. + bit_offset: 2 + bit_size: 3 + enum: RT0IP + - name: RT1IP + description: Prescale timer 1 interrupt interval. + bit_offset: 18 + bit_size: 3 + enum: RT1IP +fieldset/PWREN: + description: Power enable. + fields: + - name: ENABLE + description: Enable the power. + bit_offset: 0 + bit_size: 1 + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY +fieldset/RSTCTL: + description: Reset Control. + fields: + - name: RESETASSERT + description: Assert reset to the peripheral. + bit_offset: 0 + bit_size: 1 + - name: RESETSTKYCLR + description: Clear the RESETSTKY bit in the STAT register. + bit_offset: 1 + bit_size: 1 + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY +fieldset/SEC: + description: RTC Seconds Register - Calendar Mode With Binary / BCD Format. + fields: + - name: SECBIN + description: Seconds Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 0 + bit_size: 6 + - name: SECLOWBCD + description: Seconds BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 4 + - name: SECHIGHBCD + description: Seconds BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 12 + bit_size: 3 +fieldset/STA: + description: RTC Status Register. + fields: + - name: RTCRDY + description: Real-time clock ready. This bit indicates when the real-time clock time values are safe for reading. + bit_offset: 0 + bit_size: 1 + - name: RTCTCRDY + description: Real-time clock temperature compensation ready. This is a read only bit that indicates when the RTCTCMPx can be written. Write to RTCTCMPx should be avoided when RTCTCRDY is reset. + bit_offset: 1 + bit_size: 1 + - name: RTCTCOK + description: Real-time clock temperature compensation write OK. This is a read-only bit that indicates if the write to RTCTCMP is successful or not. + bit_offset: 2 + bit_size: 1 +fieldset/STAT: + description: Status Register. + fields: + - name: RESETSTKY + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + bit_offset: 16 + bit_size: 1 +fieldset/TCMP: + description: RTC Temperature Compensation Register. + fields: + - name: RTCTCMPX + description: Real-time clock temperature compensation. Value written into this register is used for temperature compensation of RTC. Each LSB represents approximately +1ppm (RTCTCMPS = 1) or -1ppm (RTCTCMPS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm are ignored by hardware. Reading from RTCTCMP register at any time returns the cumulative value which is the signed addition of RTCOCALx and RTCTCMPX values, and the updated sign bit (RTCTCMPS) of the addition result. + bit_offset: 0 + bit_size: 8 + - name: RTCTCMPS + description: Real-time clock temperature compensation sign. This bit decides the sign of temperature compensation. + bit_offset: 15 + bit_size: 1 + enum: RTCTCMPS +fieldset/YEAR: + description: RTC Year Register - Calendar Mode With Binary / BCD Format. + fields: + - name: YEARLOWBIN + description: Year Binary low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 0 + bit_size: 8 + - name: YEARHIGHBIN + description: Year Binary high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0. + bit_offset: 8 + bit_size: 4 + - name: YEARLOWESTBCD + description: Year BCD lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 16 + bit_size: 4 + - name: DECADEBCD + description: Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 20 + bit_size: 4 + - name: CENTLOWBCD + description: Century BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 24 + bit_size: 4 + - name: CENTHIGHBCD + description: Century BCD high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0. + bit_offset: 28 + bit_size: 3 +enum/CPU_INT_IIDX_STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: RTCRDY + description: 'RTC-Ready interrupt; Interrupt flag: RTCRDY.' + value: 1 + - name: RTCTEV + description: 'Time-Event interrupt; Interrupt flag: RTCTEV.' + value: 2 + - name: RTCA1 + description: 'Alarm-1 interrupt; Interrupt flag: RTCA1.' + value: 3 + - name: RTCA2 + description: 'Alarm-2 interrupt; Interrupt flag: RTCA2.' + value: 4 + - name: RT0PS + description: 'Prescaler-0 interrupt; Interrupt flag: RT0PS.' + value: 5 + - name: RT1PS + description: 'Prescaler-1 interrupt; Interrupt flag: RT1PS.' + value: 6 +enum/DBGRUN: + bit_size: 1 + variants: + - name: HALT + description: Counter is halted if CPU is in debug state. + value: 0 + - name: RUN + description: Continue to operate normally ignoring the debug state of the CPU. + value: 1 +enum/EVT_CFG: + bit_size: 2 + variants: + - name: DISABLE + description: The interrupt or event line is disabled. + value: 0 + - name: SOFTWARE + description: The interrupt or event line is in software mode. The software ISR clears the associated RIS flag. + value: 1 + - name: HARDWARE + description: The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. + value: 2 +enum/EVT_OUT_IIDX_STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: RTCRDY + description: 'RTC-Ready interrupt; Interrupt flag: RTCRDY.' + value: 1 + - name: RTCTEV + description: 'Time-Event interrupt; Interrupt flag: RTCTEV.' + value: 2 + - name: RTCA1 + description: 'Alarm-1 interrupt; Interrupt flag: RTCA1.' + value: 3 + - name: RTCA2 + description: 'Alarm-2 interrupt; Interrupt flag: RTCA2.' + value: 4 + - name: RT0PS + description: 'Prescaler-0 interrupt; Interrupt flag: RT0PS.' + value: 5 + - name: RT1PS + description: 'Prescaler-1 interrupt; Interrupt flag: RT1PS.' + value: 6 +enum/INSTNUM: + bit_size: 4 + variants: + - name: INST0 + description: This is the default, if there is only one instance - like for SSIM. + value: 0 +enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 +enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 +enum/RT0IP: + bit_size: 3 + variants: + - name: DIV8 + description: Divide by 8 - 244 microsecond interval. + value: 2 + - name: DIV16 + description: Divide by 16 - 488 microsecond interval. + value: 3 + - name: DIV32 + description: Divide by 32 - 976 microsecond interval. + value: 4 + - name: DIV64 + description: Divide by 64 - 1.95 millisecond interval. + value: 5 + - name: DIV128 + description: Divide by 128 - 3.90 millisecond interval. + value: 6 + - name: DIV256 + description: Divide by 256 - 7.81 millisecond interval. + value: 7 +enum/RT1IP: + bit_size: 3 + variants: + - name: DIV2 + description: Divide by 2 - 15.6 millisecond interval. + value: 0 + - name: DIV4 + description: Divide by 4 - 31.2 millisecond interval. + value: 1 + - name: DIV8 + description: Divide by 8 - 62.5 millisecond interval. + value: 2 + - name: DIV16 + description: Divide by 16 - 125 millisecond interval. + value: 3 + - name: DIV32 + description: Divide by 32 - 250 millisecond interval. + value: 4 + - name: DIV64 + description: Divide by 64 - 500 millisecond interval. + value: 5 + - name: DIV128 + description: Divide by 128 - 1 second interval. + value: 6 + - name: DIV256 + description: Divide by 256 - 2 second interval. + value: 7 +enum/RTCBCD: + bit_size: 1 + variants: + - name: BINARY + description: Binary code selected. + value: 0 + - name: BCD + description: Binary coded decimal (BCD) code selected. + value: 1 +enum/RTCCALFX: + bit_size: 2 + variants: + - name: OFF + description: No frequency output to RTC_OUT pin. + value: 0 + - name: F512HZ + description: 512 Hz. + value: 1 + - name: F256HZ + description: 256 Hz. + value: 2 + - name: F1HZ + description: 1 Hz. + value: 3 +enum/RTCOCALS: + bit_size: 1 + variants: + - name: DOWN + description: Down calibration. Frequency adjusted down. + value: 0 + - name: UP + description: Up calibration. Frequency adjusted up. + value: 1 +enum/RTCTCMPS: + bit_size: 1 + variants: + - name: DOWN + description: Down calibration. Frequency adjusted down. + value: 0 + - name: UP + description: Up calibration. Frequency adjusted up. + value: 1 +enum/RTCTEVTX: + bit_size: 2 + variants: + - name: MINUTE + description: Minute changed. + value: 0 + - name: HOUR + description: Hour changed. + value: 1 + - name: MIDNIGHT + description: Every day at midnight (00:00). + value: 2 + - name: NOON + description: Every day at noon (12:00). + value: 3 diff --git a/data/registers/spi_v1.yaml b/data/registers/spi_v1.yaml new file mode 100644 index 0000000..bbe90e3 --- /dev/null +++ b/data/registers/spi_v1.yaml @@ -0,0 +1,855 @@ +block/CPU_INT: + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 0 + access: Read + fieldset: CPU_INT_IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: CPU_INT + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: CPU_INT + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: CPU_INT + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: CPU_INT + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: CPU_INT +block/DMA_TRIG_RX: + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 0 + access: Read + fieldset: DMA_TRIG_RX_IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: DMA_TRIG_RX + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: DMA_TRIG_RX + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: DMA_TRIG_RX + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: DMA_TRIG_RX + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: DMA_TRIG_RX +block/DMA_TRIG_TX: + items: + - name: IIDX + description: Interrupt Index Register. + byte_offset: 0 + access: Read + fieldset: DMA_TRIG_TX_IIDX + - name: IMASK + description: Interrupt mask. + byte_offset: 8 + fieldset: DMA_TRIG_TX + - name: RIS + description: Raw interrupt status. + byte_offset: 16 + access: Read + fieldset: DMA_TRIG_TX + - name: MIS + description: Masked interrupt status. + byte_offset: 24 + access: Read + fieldset: DMA_TRIG_TX + - name: ISET + description: Interrupt set. + byte_offset: 32 + access: Write + fieldset: DMA_TRIG_TX + - name: ICLR + description: Interrupt clear. + byte_offset: 40 + access: Write + fieldset: DMA_TRIG_TX +block/GPRCM: + items: + - name: PWREN + description: Power enable. + byte_offset: 0 + fieldset: PWREN + - name: RSTCTL + description: Reset Control. + byte_offset: 4 + access: Write + fieldset: RSTCTL + - name: CLKCFG + description: Peripheral Clock Configuration Register. + byte_offset: 8 + fieldset: CLKCFG + - name: GPRCM_STAT + description: Status Register. + byte_offset: 20 + access: Read + fieldset: GPRCM_STAT +block/SPI: + description: PERIPHERALREGION. + items: + - name: GPRCM + array: + len: 1 + stride: 24 + byte_offset: 2048 + block: GPRCM + - name: CLKDIV + description: Clock Divider. + byte_offset: 4096 + fieldset: CLKDIV + - name: CLKSEL + description: Clock Select for Ultra Low Power peripherals. + byte_offset: 4100 + fieldset: CLKSEL + - name: PDBGCTL + description: Peripheral Debug Control. + byte_offset: 4120 + fieldset: PDBGCTL + - name: CPU_INT + array: + len: 1 + stride: 44 + byte_offset: 4128 + block: CPU_INT + - name: DMA_TRIG_RX + array: + len: 1 + stride: 44 + byte_offset: 4176 + block: DMA_TRIG_RX + - name: DMA_TRIG_TX + array: + len: 1 + stride: 44 + byte_offset: 4224 + block: DMA_TRIG_TX + - name: EVT_MODE + description: Event Mode. + byte_offset: 4320 + fieldset: EVT_MODE + - name: INTCTL + description: Interrupt control register. + byte_offset: 4324 + fieldset: INTCTL + - name: CTL0 + description: SPI control register 0. + byte_offset: 4352 + fieldset: CTL0 + - name: CTL1 + description: SPI control register 1. + byte_offset: 4356 + fieldset: CTL1 + - name: CLKCTL + description: Clock prescaler and divider register. + byte_offset: 4360 + fieldset: CLKCTL + - name: IFLS + description: UART Interrupt FIFO Level Select Register. + byte_offset: 4364 + fieldset: IFLS + - name: STAT + description: Status Register. + byte_offset: 4368 + access: Read + fieldset: STAT + - name: RXDATA + description: RXDATA Register. + byte_offset: 4400 + access: Read + fieldset: RXDATA + - name: TXDATA + description: TXDATA Register. + byte_offset: 4416 + fieldset: TXDATA +fieldset/CLKCFG: + description: Peripheral Clock Configuration Register. + fields: + - name: BLOCKASYNC + description: Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz. + bit_offset: 8 + bit_size: 1 + - name: KEY + description: KEY to Allow State Change A9h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: CLKCFG_KEY +fieldset/CLKCTL: + description: Clock prescaler and divider register. + fields: + - name: SCR + description: 'Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI''s functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023.' + bit_offset: 0 + bit_size: 10 + - name: DSAMPLE + description: 'Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations.' + bit_offset: 28 + bit_size: 4 +fieldset/CLKDIV: + description: Clock Divider. + fields: + - name: RATIO + description: Selects divide ratio of module clock. + bit_offset: 0 + bit_size: 3 + enum: RATIO +fieldset/CLKSEL: + description: Clock Select for Ultra Low Power peripherals. + fields: + - name: LFCLK_SEL + description: Selects LFCLK as clock source if enabled. + bit_offset: 1 + bit_size: 1 + - name: MFCLK_SEL + description: Selects MFCLK as clock source if enabled. + bit_offset: 2 + bit_size: 1 + - name: SYSCLK_SEL + description: Selects SYSCLK as clock source if enabled. + bit_offset: 3 + bit_size: 1 +fieldset/CPU_INT: + description: Interrupt clear. + fields: + - name: RXFIFO_OVF + description: Clear RXFIFO overflow event. + bit_offset: 0 + bit_size: 1 + - name: PER + description: Clear Parity error event. + bit_offset: 1 + bit_size: 1 + - name: RTOUT + description: Clear SPI Receive Time-Out Event. + bit_offset: 2 + bit_size: 1 + - name: RX + description: Clear Receive FIFO event. + bit_offset: 3 + bit_size: 1 + - name: TX + description: Clear Transmit FIFO event. + bit_offset: 4 + bit_size: 1 + - name: TXEMPTY + description: Clear Transmit FIFO Empty event. + bit_offset: 5 + bit_size: 1 + - name: IDLE + description: Clear SPI IDLE mode event. + bit_offset: 6 + bit_size: 1 + - name: DMA_DONE_RX + description: Clear DMA Done 1 event for RX. + bit_offset: 7 + bit_size: 1 + - name: DMA_DONE_TX + description: Clear DMA Done 1 event for TX. + bit_offset: 8 + bit_size: 1 + - name: TXFIFO_UNF + description: Clear TXFIFO underflow event. + bit_offset: 9 + bit_size: 1 + - name: RXFULL + description: Clear RX FIFO underflow event. + bit_offset: 10 + bit_size: 1 +fieldset/CPU_INT_IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: CPU_INT_IIDX_STAT +fieldset/CTL0: + description: SPI control register 0. + fields: + - name: DSS + description: 'Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit.' + bit_offset: 0 + bit_size: 5 + enum: DSS + - name: FRF + description: Frame format Select. + bit_offset: 5 + bit_size: 2 + enum: FRF + - name: PACKEN + description: Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP. + bit_offset: 7 + bit_size: 1 + - name: SPO + description: CLKOUT polarity (Motorola SPI frame format only). + bit_offset: 8 + bit_size: 1 + enum: SPO + - name: SPH + description: CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. + bit_offset: 9 + bit_size: 1 + enum: SPH + - name: CSSEL + description: Select the CS line to control on data transfer This bit is for controller mode only. + bit_offset: 12 + bit_size: 2 + enum: CSSEL + - name: CSCLR + description: Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.MS=0. + bit_offset: 14 + bit_size: 1 +fieldset/CTL1: + description: SPI control register 1. + fields: + - name: ENABLE + description: SPI enable. + bit_offset: 0 + bit_size: 1 + - name: LBM + description: Loop back mode. + bit_offset: 1 + bit_size: 1 + - name: MS + description: Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0. + bit_offset: 2 + bit_size: 1 + - name: SOD + description: 'Peripheral-mode: Data output disabled This bit is relevant only in the peripheral mode, CTL1.MS=1. In multiple-peripheral systems, it is possible for an SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the MISO lines from multiple peripherals could be tied together. To operate in such systems, this bitfield can be set if the SPI peripheral is not supposed to drive the MISO line:.' + bit_offset: 3 + bit_size: 1 + - name: MSB + description: MSB first select. Controls the direction of the receive and transmit shift register. + bit_offset: 4 + bit_size: 1 + - name: PREN + description: Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set. + bit_offset: 5 + bit_size: 1 + - name: PES + description: Even Parity Select. + bit_offset: 6 + bit_size: 1 + - name: PBS + description: Parity Bit Select. + bit_offset: 7 + bit_size: 1 + - name: PTEN + description: Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes. + bit_offset: 8 + bit_size: 1 + - name: CDENABLE + description: Command/Data Mode enable. + bit_offset: 11 + bit_size: 1 + - name: CDMODE + description: 'Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low.' + bit_offset: 12 + bit_size: 4 + enum: CDMODE + - name: REPEATTX + description: 'Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral.' + bit_offset: 16 + bit_size: 8 + enum: REPEATTX + - name: RXTIMEOUT + description: Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function. + bit_offset: 24 + bit_size: 6 +fieldset/DMA_TRIG_RX: + description: Interrupt clear. + fields: + - name: RTOUT + description: Clear SPI Receive Time-Out event. + bit_offset: 2 + bit_size: 1 + - name: RX + description: Clear Receive FIFO event. + bit_offset: 3 + bit_size: 1 +fieldset/DMA_TRIG_RX_IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: DMA_TRIG_RX_IIDX_STAT +fieldset/DMA_TRIG_TX: + description: Interrupt clear. + fields: + - name: TX + description: Clear Transmit FIFO event. + bit_offset: 4 + bit_size: 1 +fieldset/DMA_TRIG_TX_IIDX: + description: Interrupt Index Register. + fields: + - name: STAT + description: Interrupt index status. + bit_offset: 0 + bit_size: 8 + enum: DMA_TRIG_TX_IIDX_STAT +fieldset/EVT_MODE: + description: Event Mode. + fields: + - name: CPU + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]. + bit_offset: 0 + bit_size: 2 + enum: EVT_CFG + - name: DMA_TRIG_RX + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]. + bit_offset: 2 + bit_size: 2 + enum: EVT_CFG + - name: INT2_CFG + description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]. + bit_offset: 4 + bit_size: 2 + enum: EVT_CFG +fieldset/GPRCM_STAT: + description: Status Register. + fields: + - name: RESETSTKY + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + bit_offset: 16 + bit_size: 1 +fieldset/IFLS: + description: UART Interrupt FIFO Level Select Register. + fields: + - name: TXIFLSEL + description: SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:. + bit_offset: 0 + bit_size: 3 + enum: TXIFLSEL + - name: RXIFLSEL + description: SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:. + bit_offset: 3 + bit_size: 3 + enum: RXIFLSEL +fieldset/INTCTL: + description: Interrupt control register. + fields: + - name: INTEVAL + description: Writing a 1 to this field re-evaluates the interrupt sources. + bit_offset: 0 + bit_size: 1 +fieldset/PDBGCTL: + description: Peripheral Debug Control. + fields: + - name: FREE + description: Free run control. + bit_offset: 0 + bit_size: 1 + - name: SOFT + description: Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'. + bit_offset: 1 + bit_size: 1 + enum: SOFT +fieldset/PWREN: + description: Power enable. + fields: + - name: ENABLE + description: Enable the power. + bit_offset: 0 + bit_size: 1 + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY +fieldset/RSTCTL: + description: Reset Control. + fields: + - name: RESETASSERT + description: Assert reset to the peripheral. + bit_offset: 0 + bit_size: 1 + - name: RESETSTKYCLR + description: Clear the RESETSTKY bit in the STAT register. + bit_offset: 1 + bit_size: 1 + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY +fieldset/RXDATA: + description: RXDATA Register. + fields: + - name: DATA + description: Received Data When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer. + bit_offset: 0 + bit_size: 16 +fieldset/STAT: + description: Status Register. + fields: + - name: TFE + description: Transmit FIFO empty. + bit_offset: 0 + bit_size: 1 + - name: TNF + description: Transmit FIFO not full. + bit_offset: 1 + bit_size: 1 + enum: TNF + - name: RFE + description: Receive FIFO empty. + bit_offset: 2 + bit_size: 1 + - name: RNF + description: Receive FIFO not full. + bit_offset: 3 + bit_size: 1 + enum: RNF + - name: BUSY + description: Busy. + bit_offset: 4 + bit_size: 1 + enum: BUSY +fieldset/TXDATA: + description: TXDATA Register. + fields: + - name: DATA + description: Transmit Data WWhen read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. + bit_offset: 0 + bit_size: 16 +enum/BUSY: + bit_size: 1 + variants: + - name: IDLE + description: SPI is in idle mode. + value: 0 + - name: ACTIVE + description: SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty. + value: 1 +enum/CDMODE: + bit_size: 4 + variants: + - name: DATA + description: 'Manual mode: Data.' + value: 0 + - name: COMMAND + description: 'Manual mode: Command.' + value: 15 +enum/CLKCFG_KEY: + bit_size: 8 + variants: + - name: KEY + value: 169 +enum/CPU_INT_IIDX_STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: RXFIFO_OFV_EVT + description: RX FIFO Overflow Event/interrupt pending. + value: 1 + - name: PER_EVT + description: Transmit Parity Event/interrupt pending. + value: 2 + - name: RTOUT_EVT + description: SPI receive time-out interrupt. + value: 3 + - name: RX_EVT + description: Receive Event/interrupt pending. + value: 4 + - name: TX_EVT + description: Transmit Event/interrupt pending. + value: 5 + - name: TX_EMPTY + description: Transmit Buffer Empty Event/interrupt pending. + value: 6 + - name: IDLE_EVT + description: End of Transmit Event/interrupt pending. + value: 7 + - name: DMA_DONE_RX_EVT + description: DMA Done for Recevive Event/interrupt pending. + value: 8 + - name: DMA_DONE_TX_EVT + description: DMA Done for Transmit Event/interrupt pending. + value: 9 + - name: TXFIFO_UNF_EVT + description: TX FIFO underflow interrupt. + value: 10 + - name: RXFULL_EVT + description: RX FIFO Full Interrupt. + value: 11 +enum/CSSEL: + bit_size: 2 + variants: + - name: CSSEL_0 + description: 'CS line select: 0.' + value: 0 + - name: CSSEL_1 + description: 'CS line select: 1.' + value: 1 + - name: CSSEL_2 + description: 'CS line select: 2.' + value: 2 + - name: CSSEL_3 + description: 'CS line select: 3.' + value: 3 +enum/DMA_TRIG_RX_IIDX_STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: RTOUT_EVT + description: SPI receive time-out interrupt. + value: 3 + - name: RX_EVT + description: Receive Event/interrupt pending. + value: 4 +enum/DMA_TRIG_TX_IIDX_STAT: + bit_size: 8 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: TX_EVT + description: Transmit Event/interrupt pending. + value: 5 +enum/DSS: + bit_size: 5 + variants: + - name: DSS_4 + description: 'Data Size Select bits: 4.' + value: 3 + - name: DSS_5 + description: 'Data Size Select bits: 5.' + value: 4 + - name: DSS_6 + description: 'Data Size Select bits: 6.' + value: 5 + - name: DSS_7 + description: 'Data Size Select bits: 7.' + value: 6 + - name: DSS_8 + description: 'Data Size Select bits: 8.' + value: 7 + - name: DSS_9 + description: 'Data Size Select bits: 9.' + value: 8 + - name: DSS_10 + description: 'Data Size Select bits: 10.' + value: 9 + - name: DSS_11 + description: 'Data Size Select bits: 11.' + value: 10 + - name: DSS_12 + description: 'Data Size Select bits: 12.' + value: 11 + - name: DSS_13 + description: 'Data Size Select bits: 13.' + value: 12 + - name: DSS_14 + description: 'Data Size Select bits: 14.' + value: 13 + - name: DSS_15 + description: 'Data Size Select bits: 15.' + value: 14 + - name: DSS_16 + description: 'Data Size Select bits: 16.' + value: 15 + - name: DSS_32 + description: 'Data Size Select bits: 32.' + value: 31 +enum/EVT_CFG: + bit_size: 2 + variants: + - name: DISABLE + description: The interrupt or event line is disabled. + value: 0 + - name: SOFTWARE + description: The interrupt or event line is in software mode. Software must clear the RIS. + value: 1 + - name: HARDWARE + description: The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. + value: 2 +enum/FRF: + bit_size: 2 + variants: + - name: MOTOROLA_3WIRE + description: Motorola SPI frame format (3 wire mode). + value: 0 + - name: MOTOROLA_4WIRE + description: Motorola SPI frame format (4 wire mode). + value: 1 + - name: TI_SYNC + description: TI synchronous serial frame format. + value: 2 + - name: MIRCOWIRE + description: National Microwire frame format. + value: 3 +enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 +enum/RATIO: + bit_size: 3 + variants: + - name: DIV_BY_1 + description: Do not divide clock source. + value: 0 + - name: DIV_BY_2 + description: Divide clock source by 2. + value: 1 + - name: DIV_BY_3 + description: Divide clock source by 3. + value: 2 + - name: DIV_BY_4 + description: Divide clock source by 4. + value: 3 + - name: DIV_BY_5 + description: Divide clock source by 5. + value: 4 + - name: DIV_BY_6 + description: Divide clock source by 6. + value: 5 + - name: DIV_BY_7 + description: Divide clock source by 7. + value: 6 + - name: DIV_BY_8 + description: Divide clock source by 8. + value: 7 +enum/REPEATTX: + bit_size: 8 + variants: + - name: DISABLE + description: REPEATTX disable. + value: 0 +enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 +enum/RNF: + bit_size: 1 + variants: + - name: FULL + description: Receive FIFO is full. + value: 0 + - name: NOT_FULL + description: Receive FIFO is not full. + value: 1 +enum/RXIFLSEL: + bit_size: 3 + variants: + - name: LVL_OFF + description: Reserved. + value: 0 + - name: LVL_1_4 + description: RX FIFO >= 1/4 full. + value: 1 + - name: LVL_1_2 + description: RX FIFO >= 1/2 full (default). + value: 2 + - name: LVL_3_4 + description: RX FIFO >= 3/4 full. + value: 3 + - name: LVL_RES4 + description: Reserved. + value: 4 + - name: LVL_FULL + description: RX FIFO is full. + value: 5 + - name: LVL_RES6 + description: Reserved. + value: 6 + - name: LEVEL_1 + description: Trigger when RX FIFO contains >= 1 frame. + value: 7 +enum/SOFT: + bit_size: 1 + variants: + - name: IMMEDIATE + description: The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted. + value: 0 + - name: DELAYED + description: The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption. + value: 1 +enum/SPH: + bit_size: 1 + variants: + - name: FIRST + description: Data is captured on the first clock edge transition. + value: 0 + - name: SECOND + description: Data is captured on the second clock edge transition. + value: 1 +enum/SPO: + bit_size: 1 + variants: + - name: LOW + description: SPI produces a steady state LOW value on the CLKOUT. + value: 0 + - name: HIGH + description: SPI produces a steady state HIGH value on the CLKOUT. + value: 1 +enum/TNF: + bit_size: 1 + variants: + - name: FULL + description: Transmit FIFO is full. + value: 0 + - name: NOT_FULL + description: Transmit FIFO is not full. + value: 1 +enum/TXIFLSEL: + bit_size: 3 + variants: + - name: LVL_OFF + description: Reserved. + value: 0 + - name: LVL_3_4 + description: TX FIFO <= 3/4 empty. + value: 1 + - name: LVL_1_2 + description: TX FIFO <= 1/2 empty (default). + value: 2 + - name: LVL_1_4 + description: TX FIFO <= 1/4 empty. + value: 3 + - name: LVL_RES4 + description: Reserved. + value: 4 + - name: LVL_EMPTY + description: TX FIFO is empty. + value: 5 + - name: LVL_RES6 + description: Reserved. + value: 6 + - name: LEVEL_1 + description: Trigger when TX FIFO has >= 1 frame free Should be used with DMA. + value: 7 diff --git a/data/registers/sysctl_l111x.yaml b/data/registers/sysctl_l111x.yaml new file mode 100644 index 0000000..63323d3 --- /dev/null +++ b/data/registers/sysctl_l111x.yaml @@ -0,0 +1,1257 @@ +block/SYSCTL: + description: mem_map. + items: + - name: IIDX + description: SYSCTL interrupt index. + byte_offset: 4128 + access: Read + fieldset: IIDX + - name: IMASK + description: SYSCTL interrupt mask. + byte_offset: 4136 + fieldset: INT + - name: RIS + description: SYSCTL raw interrupt status. + byte_offset: 4144 + access: Read + fieldset: INT + - name: MIS + description: SYSCTL masked interrupt status. + byte_offset: 4152 + access: Read + fieldset: INT + - name: ISET + description: SYSCTL interrupt set. + byte_offset: 4160 + access: Write + fieldset: INT + - name: ICLR + description: SYSCTL interrupt clear. + byte_offset: 4168 + access: Write + fieldset: INT + - name: NMIIIDX + description: NMI interrupt index. + byte_offset: 4176 + access: Read + fieldset: NMIIIDX + - name: NMIRIS + description: NMI raw interrupt status. + byte_offset: 4192 + access: Read + fieldset: NMI + - name: NMIISET + description: NMI interrupt set. + byte_offset: 4208 + access: Write + fieldset: NMI + - name: NMIICLR + description: NMI interrupt clear. + byte_offset: 4216 + access: Write + fieldset: NMI + - name: SYSOSCCFG + description: SYSOSC configuration. + byte_offset: 4352 + fieldset: SYSOSCCFG + - name: MCLKCFG + description: Main clock (MCLK) configuration. + byte_offset: 4356 + fieldset: MCLKCFG + - name: HSCLKEN + description: High-speed clock (HSCLK) source enable/disable. + byte_offset: 4360 + fieldset: HSCLKEN + - name: LFCLKCFG + description: Low frequency crystal oscillator (LFXT) configuration. + byte_offset: 4372 + fieldset: LFCLKCFG + - name: GENCLKCFG + description: General clock configuration. + byte_offset: 4408 + fieldset: GENCLKCFG + - name: GENCLKEN + description: General clock enable control. + byte_offset: 4412 + fieldset: GENCLKEN + - name: PMODECFG + description: Power mode configuration. + byte_offset: 4416 + fieldset: PMODECFG + - name: FCC + description: Frequency clock counter (FCC) count. + byte_offset: 4432 + access: Read + fieldset: FCC + - name: SYSOSCTRIMUSER + description: SYSOSC user-specified trim. + byte_offset: 4464 + fieldset: SYSOSCTRIMUSER + - name: SRAMBOUNDARY + description: SRAM Write Boundary. + byte_offset: 4472 + fieldset: SRAMBOUNDARY + - name: SYSTEMCFG + description: System configuration. + byte_offset: 4480 + fieldset: SYSTEMCFG + - name: WRITELOCK + description: SYSCTL register write lockout. + byte_offset: 4608 + fieldset: WRITELOCK + - name: CLKSTATUS + description: Clock module (CKM) status. + byte_offset: 4612 + access: Read + fieldset: CLKSTATUS + - name: SYSSTATUS + description: System status information. + byte_offset: 4616 + access: Read + fieldset: SYSSTATUS + - name: DEDERRADDR + description: Memory DED Address. + byte_offset: 4620 + access: Read + - name: RSTCAUSE + description: Reset cause. + byte_offset: 4640 + access: Read + fieldset: RSTCAUSE + - name: RESETLEVEL + description: Reset level for application-triggered reset command. + byte_offset: 4864 + fieldset: RESETLEVEL + - name: RESETCMD + description: Execute an application-triggered reset command. + byte_offset: 4868 + access: Write + fieldset: RESETCMD + - name: BORTHRESHOLD + description: BOR threshold selection. + byte_offset: 4872 + fieldset: BORTHRESHOLD + - name: BORCLRCMD + description: Set the BOR threshold. + byte_offset: 4876 + access: Write + fieldset: BORCLRCMD + - name: SYSOSCFCLCTL + description: SYSOSC frequency correction loop (FCL) ROSC enable. + byte_offset: 4880 + access: Write + fieldset: SYSOSCFCLCTL + - name: LFXTCTL + description: LFXT and LFCLK control. + byte_offset: 4884 + access: Write + fieldset: LFXTCTL + - name: EXLFCTL + description: LFCLK_IN and LFCLK control. + byte_offset: 4888 + access: Write + fieldset: EXLFCTL + - name: SHDNIOREL + description: SHUTDOWN IO release control. + byte_offset: 4892 + access: Write + fieldset: SHDNIOREL + - name: EXRSTPIN + description: Disable the reset function of the NRST pin. + byte_offset: 4896 + access: Write + fieldset: EXRSTPIN + - name: SYSSTATUSCLR + description: Clear sticky bits of SYSSTATUS. + byte_offset: 4900 + access: Write + fieldset: SYSSTATUSCLR + - name: SWDCFG + description: Disable the SWD function on the SWD pins. + byte_offset: 4904 + access: Write + fieldset: SWDCFG + - name: FCCCMD + description: Frequency clock counter start capture. + byte_offset: 4908 + access: Write + fieldset: FCCCMD + - name: SHUTDNSTORE + description: Shutdown storage memory (byte 0). + array: + len: 4 + stride: 4 + byte_offset: 5120 + fieldset: SHUTDNSTORE + - name: FWEPROTMAIN + description: 1 Sector Write-Erase per bit starting at address 0x0 of flash. + byte_offset: 12288 + - name: FRXPROTMAINSTART + description: Flash RX Protection Start Address. + byte_offset: 12312 + fieldset: FRXPROTMAINSTART + - name: FRXPROTMAINEND + description: Flash RX Protection End Address. + byte_offset: 12316 + fieldset: FRXPROTMAINEND + - name: FIPPROTMAINSTART + description: Flash IP Protection Start Address. + byte_offset: 12320 + fieldset: FIPPROTMAINSTART + - name: FIPPROTMAINEND + description: Flash IP Protection End Address. + byte_offset: 12324 + fieldset: FIPPROTMAINEND + - name: FLBANKSWPPOLICY + description: Flash Bank Swap Policy. + byte_offset: 12344 + access: Write + fieldset: FLBANKSWPPOLICY + - name: FLBANKSWP + description: Flash MAIN bank address swap. + byte_offset: 12348 + access: Write + fieldset: FLBANKSWP + - name: FWENABLE + description: Security Firewall Enable Register. + byte_offset: 12356 + access: Write + fieldset: FWENABLE + - name: SECSTATUS + description: Security Configuration status. + byte_offset: 12360 + access: Read + fieldset: SECSTATUS + - name: INITDONE + description: INITCODE PASS. + byte_offset: 12384 + access: Write + fieldset: INITDONE +fieldset/BORCLRCMD: + description: Set the BOR threshold. + fields: + - name: GO + description: GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register. + bit_offset: 0 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: BORCLRCMD_KEY +fieldset/BORTHRESHOLD: + description: BOR threshold selection. + fields: + - name: LEVEL + description: LEVEL specifies the desired BOR threshold and BOR mode. + bit_offset: 0 + bit_size: 2 +fieldset/CLKSTATUS: + description: Clock module (CKM) status. + fields: + - name: SYSOSCFREQ + description: SYSOSCFREQ indicates the current SYSOSC operating frequency. + bit_offset: 0 + bit_size: 2 + enum: SYSOSCFREQ + - name: HSCLKMUX + description: HSCLKMUX indicates if MCLK is currently sourced from the high-speed clock (HSCLK). + bit_offset: 4 + bit_size: 1 + enum: HSCLKMUX + - name: LFCLKMUX + description: LFCLKMUX indicates if LFCLK is sourced from the internal LFOSC, the low frequency crystal (LFXT), or the LFCLK_IN digital clock input. + bit_offset: 6 + bit_size: 2 + enum: LFCLKMUX + - name: LFXTGOOD + description: LFXTGOOD indicates if the LFXT started correctly. When the LFXT is started, LFXTGOOD is cleared by hardware. After the startup settling time has expired, the LFXT status is tested. If the LFXT started successfully the LFXTGOOD bit is set, else it is left cleared. + bit_offset: 10 + bit_size: 1 + - name: LFOSCGOOD + description: LFOSCGOOD indicates when the LFOSC startup has completed and the LFOSC is ready for use. + bit_offset: 11 + bit_size: 1 + - name: CURMCLKSEL + description: CURMCLKSEL indicates if MCLK is currently sourced from LFCLK. + bit_offset: 17 + bit_size: 1 + - name: LFCLKFAIL + description: LFCLKFAIL indicates when the continous LFCLK monitor detects a LFXT or LFCLK_IN clock stuck failure. + bit_offset: 23 + bit_size: 1 + - name: FCLMODE + description: FCLMODE indicates if the SYSOSC frequency correction loop (FCL) is enabled. + bit_offset: 24 + bit_size: 1 + - name: FCCDONE + description: FCCDONE indicates when a frequency clock counter capture is complete. + bit_offset: 25 + bit_size: 1 + - name: ANACLKERR + description: ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected. + bit_offset: 31 + bit_size: 1 +fieldset/EXLFCTL: + description: LFCLK_IN and LFCLK control. + fields: + - name: SETUSEEXLF + description: Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set, SETUSEEXLF remains set until the next BOOTRST. + bit_offset: 0 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: EXLFCTL_KEY +fieldset/EXRSTPIN: + description: Disable the reset function of the NRST pin. + fields: + - name: DISABLE + description: Set DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR. + bit_offset: 0 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: EXRSTPIN_KEY +fieldset/FCC: + description: Frequency clock counter (FCC) count. + fields: + - name: DATA + description: Frequency clock counter (FCC) count value. + bit_offset: 0 + bit_size: 22 +fieldset/FCCCMD: + description: Frequency clock counter start capture. + fields: + - name: GO + description: Set GO to start a capture with the frequency clock counter (FCC). + bit_offset: 0 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: FCCCMD_KEY +fieldset/FIPPROTMAINEND: + description: Flash IP Protection End Address. + fields: + - name: ADDR + description: Flash IP Protection End Address 64B granularity. + bit_offset: 6 + bit_size: 16 +fieldset/FIPPROTMAINSTART: + description: Flash IP Protection Start Address. + fields: + - name: ADDR + description: Flash IP Protection Start Address 64B granularity. + bit_offset: 6 + bit_size: 16 +fieldset/FLBANKSWP: + description: Flash MAIN bank address swap. + fields: + - name: USEUPPER + description: '1: Use Upper Bank as Logical 0.' + bit_offset: 0 + bit_size: 1 +fieldset/FLBANKSWPPOLICY: + description: Flash Bank Swap Policy. + fields: + - name: DISABLE + description: '1: Disables Policy To Allow Flash Bank Swapping.' + bit_offset: 0 + bit_size: 1 +fieldset/FRXPROTMAINEND: + description: Flash RX Protection End Address. + fields: + - name: ADDR + description: Flash RX Protection End Address 64B granularity. + bit_offset: 6 + bit_size: 16 +fieldset/FRXPROTMAINSTART: + description: Flash RX Protection Start Address. + fields: + - name: ADDR + description: Flash RX Protection Start Address 64B granularity. + bit_offset: 6 + bit_size: 16 +fieldset/FWENABLE: + description: Security Firewall Enable Register. + fields: + - name: FLRXPROT + description: '1: Flash Read Execute Protection Active.' + bit_offset: 4 + bit_size: 1 + - name: FLIPPROT + description: '1: Flash Read IP ProtectionActive.' + bit_offset: 6 + bit_size: 1 + - name: SRAMBOUNDARYLOCK + description: '1: Blocks Writes from Changing SRAMBOUNDARY MMR.' + bit_offset: 8 + bit_size: 1 +fieldset/GENCLKCFG: + description: General clock configuration. + fields: + - name: EXCLKSRC + description: EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled. + bit_offset: 0 + bit_size: 3 + enum: EXCLKSRC + - name: EXCLKDIVVAL + description: EXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block. + bit_offset: 4 + bit_size: 3 + enum: EXCLKDIVVAL + - name: EXCLKDIVEN + description: EXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block. + bit_offset: 7 + bit_size: 1 + - name: MFPCLKSRC + description: MFPCLKSRC selects the MFPCLK (middle frequency precision clock) source. + bit_offset: 9 + bit_size: 1 + enum: MFPCLKSRC + - name: HFCLK4MFPCLKDIV + description: HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected. + bit_offset: 12 + bit_size: 4 + enum: HFCLK4MFPCLKDIV + - name: FCCSELCLK + description: FCCSELCLK selectes the frequency clock counter (FCC) clock source. + bit_offset: 16 + bit_size: 4 + enum: FCCSELCLK + - name: FCCTRIGSRC + description: FCCTRIGSRC selects the frequency clock counter (FCC) trigger source. + bit_offset: 20 + bit_size: 1 + enum: FCCTRIGSRC + - name: FCCLVLTRIG + description: FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode. + bit_offset: 21 + bit_size: 1 + enum: FCCLVLTRIG + - name: ANACPUMPCFG + description: ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method. + bit_offset: 22 + bit_size: 2 + enum: ANACPUMPCFG + - name: FCCTRIGCNT + description: FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified. + bit_offset: 24 + bit_size: 5 + - name: FCCLFCLKSRC + description: FCCLFCLKSRC selects between SYSTEM LFCLK and EXTERNAL SOURCED LFCLK. + bit_offset: 29 + bit_size: 1 +fieldset/GENCLKEN: + description: General clock enable control. + fields: + - name: EXCLKEN + description: EXCLKEN enables the CLK_OUT external clock output block. + bit_offset: 0 + bit_size: 1 + - name: MFPCLKEN + description: MFPCLKEN enables the middle frequency precision clock (MFPCLK). + bit_offset: 4 + bit_size: 1 +fieldset/HSCLKEN: + description: High-speed clock (HSCLK) source enable/disable. + fields: + - name: USEEXTHFCLK + description: USEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled, HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously. + bit_offset: 16 + bit_size: 1 +fieldset/IIDX: + description: SYSCTL interrupt index. + fields: + - name: STAT + description: The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers. + bit_offset: 0 + bit_size: 3 + enum: IIDX_STAT +fieldset/INITDONE: + description: INITCODE PASS. + fields: + - name: PASS + description: INITCODE writes 1 for PASS, left unwritten a timeout will occur if not blocked. + bit_offset: 0 + bit_size: 1 +fieldset/INT: + description: SYSCTL interrupt clear. + fields: + - name: LFOSCGOOD + description: Clear the LFOSCGOOD interrupt. + bit_offset: 0 + bit_size: 1 + - name: ANACLKERR + description: Analog Clocking Consistency Error. + bit_offset: 1 + bit_size: 1 + - name: FLASHSEC + description: Flash Single Error Correct. + bit_offset: 2 + bit_size: 1 + - name: LFXTGOOD + description: LFXT GOOD. + bit_offset: 3 + bit_size: 1 +fieldset/LFCLKCFG: + description: Low frequency crystal oscillator (LFXT) configuration. + fields: + - name: XT1DRIVE + description: XT1DRIVE selects the low frequency crystal oscillator (LFXT) drive strength. + bit_offset: 0 + bit_size: 2 + enum: XT1DRIVE + - name: MONITOR + description: MONITOR enables or disables the LFCLK monitor, which continuously checks LFXT or LFCLK_IN for a clock stuck fault. + bit_offset: 4 + bit_size: 1 + - name: LOWCAP + description: LOWCAP controls the low-power LFXT mode. When the LFXT load capacitance is less than 3pf, LOWCAP may be set for reduced power consumption. + bit_offset: 8 + bit_size: 1 +fieldset/LFXTCTL: + description: LFXT and LFCLK control. + fields: + - name: STARTLFXT + description: Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set, STARTLFXT remains set until the next BOOTRST. + bit_offset: 0 + bit_size: 1 + - name: SETUSELFXT + description: Set SETUSELFXT to switch LFCLK to LFXT. Once set, SETUSELFXT remains set until the next BOOTRST. + bit_offset: 1 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: LFXTCTL_KEY +fieldset/MCLKCFG: + description: Main clock (MCLK) configuration. + fields: + - name: MDIV + description: MDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC. MDIV=0h corresponds to /1 (no divider). MDIV=1h corresponds to /2 (divide-by-2). MDIV=Fh corresponds to /16 (divide-by-16). MDIV may be set between /1 and /16 on an integer basis. + bit_offset: 0 + bit_size: 4 + - name: FLASHWAIT + description: FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK. + bit_offset: 8 + bit_size: 4 + enum: FLASHWAIT + - name: USEMFTICK + description: USEMFTICK specifies whether the 4MHz constant-rate clock (MFCLK) to peripherals is enabled or disabled. When enabled, MDIV must be disabled (set to 0h=/1). + bit_offset: 12 + bit_size: 1 + - name: USEHSCLK + description: USEHSCLK, together with USELFCLK, sets the MCLK source policy. Set USEHSCLK to use HSCLK (HFCLK or SYSPLL) as the MCLK source in RUN and SLEEP modes. + bit_offset: 16 + bit_size: 1 + - name: USELFCLK + description: USELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source. Note that setting USELFCLK does not disable SYSOSC, and SYSOSC remains available for direct use by analog modules. + bit_offset: 20 + bit_size: 1 + - name: STOPCLKSTBY + description: STOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1). When set, ULPCLK and LFCLK are disabled to all peripherals in STANDBY mode, with the exception of TIMG0 and TIMG1 which continue to run. Wake-up is only possible via an asynchronous fast clock request. + bit_offset: 21 + bit_size: 1 + - name: MCLKDEADCHK + description: MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled. + bit_offset: 22 + bit_size: 1 +fieldset/NMI: + description: NMI interrupt clear. + fields: + - name: BORLVL + description: Clr the BORLVL NMI. + bit_offset: 0 + bit_size: 1 + - name: WWDT0 + description: Watch Dog 0 Fault. + bit_offset: 1 + bit_size: 1 + - name: LFCLKFAIL + description: LFXT-EXLF Monitor Fail. + bit_offset: 2 + bit_size: 1 + - name: FLASHDED + description: Flash Double Error Detect. + bit_offset: 3 + bit_size: 1 +fieldset/NMIIIDX: + description: NMI interrupt index. + fields: + - name: STAT + description: The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register. + bit_offset: 0 + bit_size: 3 + enum: NMIIIDX_STAT +fieldset/PMODECFG: + description: Power mode configuration. + fields: + - name: DSLEEP + description: DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU. + bit_offset: 0 + bit_size: 2 + enum: DSLEEP +fieldset/RESETCMD: + description: Execute an application-triggered reset command. + fields: + - name: GO + description: Execute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY. + bit_offset: 0 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: RESETCMD_KEY +fieldset/RESETLEVEL: + description: Reset level for application-triggered reset command. + fields: + - name: LEVEL + description: LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset. + bit_offset: 0 + bit_size: 3 + enum: RESETLEVEL_LEVEL +fieldset/RSTCAUSE: + description: Reset cause. + fields: + - name: ID + description: ID is a read-to-clear field which indicates the lowest level reset cause since the last read. + bit_offset: 0 + bit_size: 5 + enum: ID +fieldset/SECSTATUS: + description: Security Configuration status. + fields: + - name: INITDONE + description: '1: CSC has been completed.' + bit_offset: 0 + bit_size: 1 + - name: CSCEXISTS + description: '1: CSC Exists in the system.' + bit_offset: 2 + bit_size: 1 + - name: FLRXPROT + description: '1: Flash Read Execute Protection Active.' + bit_offset: 4 + bit_size: 1 + - name: FLIPPROT + description: '1: Flash IP Protection Active.' + bit_offset: 6 + bit_size: 1 + - name: SRAMBOUNDARYLOCK + description: '1: SRAM Boundary MMR Locked.' + bit_offset: 8 + bit_size: 1 + - name: FLBANKSWPPOLICY + description: '1: Upper and Lower Banks allowed to be swapped.' + bit_offset: 10 + bit_size: 1 + - name: FLBANKSWP + description: '1: Upper and Lower Banks have been swapped.' + bit_offset: 12 + bit_size: 1 +fieldset/SHDNIOREL: + description: SHUTDOWN IO release control. + fields: + - name: RELEASE + description: Set RELEASE to release the IO after a SHUTDOWN mode exit. + bit_offset: 0 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: SHDNIOREL_KEY +fieldset/SHUTDNSTORE: + description: Shutdown storage memory (byte 0). + fields: + - name: DATA + description: Shutdown storage byte 0. + bit_offset: 0 + bit_size: 8 + - name: PARITY + bit_offset: 8 + bit_size: 1 + - name: PARITYERR + bit_offset: 9 + bit_size: 1 +fieldset/SRAMBOUNDARY: + description: SRAM Write Boundary. + fields: + - name: ADDR + description: 'SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size.' + bit_offset: 5 + bit_size: 15 +fieldset/SWDCFG: + description: Disable the SWD function on the SWD pins. + fields: + - name: DISABLE + description: Set DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO. + bit_offset: 0 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: SWDCFG_KEY +fieldset/SYSOSCCFG: + description: SYSOSC configuration. + fields: + - name: FREQ + description: Target operating frequency for the system oscillator (SYSOSC). + bit_offset: 0 + bit_size: 2 + enum: SYSOSCCFG_FREQ + - name: USE4MHZSTOP + description: USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption. + bit_offset: 8 + bit_size: 1 + - name: DISABLESTOP + description: DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption. + bit_offset: 9 + bit_size: 1 + - name: DISABLE + description: DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK. + bit_offset: 10 + bit_size: 1 + - name: BLOCKASYNCALL + description: BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode. + bit_offset: 16 + bit_size: 1 + - name: FASTCPUEVENT + description: FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency. + bit_offset: 17 + bit_size: 1 +fieldset/SYSOSCFCLCTL: + description: SYSOSC frequency correction loop (FCL) ROSC enable. + fields: + - name: SETUSEFCL + description: Set SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST. + bit_offset: 0 + bit_size: 1 + - name: SETUSEEXRES + description: Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST. + bit_offset: 1 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: SYSOSCFCLCTL_KEY +fieldset/SYSOSCTRIMUSER: + description: SYSOSC user-specified trim. + fields: + - name: FREQ + description: FREQ specifies the target user-trimmed frequency for SYSOSC. + bit_offset: 0 + bit_size: 2 + enum: SYSOSCTRIMUSER_FREQ + - name: CAP + description: CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency. + bit_offset: 4 + bit_size: 3 + - name: RESCOARSE + description: RESCOARSE specifies the resister coarse trim. This value changes with the target frequency. + bit_offset: 8 + bit_size: 6 + - name: RESFINE + description: RESFINE specifies the resister fine trim. This value changes with the target frequency. + bit_offset: 16 + bit_size: 4 + - name: RDIV + description: RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency. + bit_offset: 20 + bit_size: 9 +fieldset/SYSSTATUS: + description: System status information. + fields: + - name: FLASHDED + description: FLASHDED indicates if a flash ECC double bit error was detected (DED). + bit_offset: 0 + bit_size: 1 + - name: FLASHSEC + description: FLASHSEC indicates if a flash ECC single bit error was detected and corrected (SEC). + bit_offset: 1 + bit_size: 1 + - name: BORCURTHRESHOLD + description: BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration. + bit_offset: 2 + bit_size: 2 + enum: BORCURTHRESHOLD + - name: BORLVL + description: BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware. + bit_offset: 4 + bit_size: 1 + - name: ANACPUMPGOOD + description: ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready. + bit_offset: 5 + bit_size: 1 + - name: PMUIREFGOOD + description: PMUIREFGOOD is set by hardware when the PMU current reference is ready. + bit_offset: 6 + bit_size: 1 + - name: EXTRSTPINDIS + description: EXTRSTPINDIS indicates when user has disabled the use of external reset pin. + bit_offset: 12 + bit_size: 1 + - name: SWDCFGDIS + description: SWDCFGDIS indicates when user has disabled the use of SWD Port. + bit_offset: 13 + bit_size: 1 + - name: SHDNIOLOCK + description: SHDNIOLOCK indicates when IO is locked due to SHUTDOWN. + bit_offset: 14 + bit_size: 1 + - name: REBOOTATTEMPTS + description: REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts. + bit_offset: 30 + bit_size: 2 +fieldset/SYSSTATUSCLR: + description: Clear sticky bits of SYSSTATUS. + fields: + - name: ALLECC + description: Set ALLECC to clear all ECC related SYSSTATUS indicators. + bit_offset: 0 + bit_size: 1 + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: SYSSTATUSCLR_KEY +fieldset/SYSTEMCFG: + description: System configuration. + fields: + - name: WWDTLP0RSTDIS + description: WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI. + bit_offset: 0 + bit_size: 1 + - name: FLASHECCRSTDIS + description: FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI. + bit_offset: 2 + bit_size: 1 +fieldset/WRITELOCK: + description: SYSCTL register write lockout. + fields: + - name: ACTIVE + description: ACTIVE controls whether critical SYSCTL registers are write protected or not. + bit_offset: 0 + bit_size: 1 +enum/ANACPUMPCFG: + bit_size: 2 + variants: + - name: ONDEMAND + description: VBOOST is enabled on request from a COMP, GPAMP, or OPA. + value: 0 + - name: ONACTIVE + description: VBOOST is enabled when the device is in RUN or SLEEP mode, or when a COMP/GPAMP/OPA is enabled. + value: 1 + - name: ONALWAYS + description: VBOOST is always enabled. + value: 2 +enum/BORCLRCMD_KEY: + bit_size: 8 + variants: + - name: KEY + value: 199 +enum/BORCURTHRESHOLD: + bit_size: 2 + variants: + - name: BORMIN + description: Default minimum threshold; a BOR0- violation triggers a BOR. + value: 0 + - name: BORLEVEL1 + description: A BOR1- violation generates a BORLVL interrupt. + value: 1 + - name: BORLEVEL2 + description: A BOR2- violation generates a BORLVL interrupt. + value: 2 + - name: BORLEVEL3 + description: A BOR3- violation generates a BORLVL interrupt. + value: 3 +enum/DSLEEP: + bit_size: 2 + variants: + - name: STOP + description: STOP mode is entered. + value: 0 + - name: STANDBY + description: STANDBY mode is entered. + value: 1 + - name: SHUTDOWN + description: SHUTDOWN mode is entered. + value: 2 +enum/EXCLKDIVVAL: + bit_size: 3 + variants: + - name: DIV2 + description: CLK_OUT source is divided by 2. + value: 0 + - name: DIV4 + description: CLK_OUT source is divided by 4. + value: 1 + - name: DIV6 + description: CLK_OUT source is divided by 6. + value: 2 + - name: DIV8 + description: CLK_OUT source is divided by 8. + value: 3 + - name: DIV10 + description: CLK_OUT source is divided by 10. + value: 4 + - name: DIV12 + description: CLK_OUT source is divided by 12. + value: 5 + - name: DIV14 + description: CLK_OUT source is divided by 14. + value: 6 + - name: DIV16 + description: CLK_OUT source is divided by 16. + value: 7 +enum/EXCLKSRC: + bit_size: 3 + variants: + - name: SYSOSC + description: CLK_OUT is SYSOSC. + value: 0 + - name: ULPCLK + description: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled). + value: 1 + - name: LFCLK + description: CLK_OUT is LFCLK. + value: 2 + - name: MFPCLK + description: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled). + value: 3 + - name: HFCLK + description: CLK_OUT is HFCLK. + value: 4 +enum/EXLFCTL_KEY: + bit_size: 8 + variants: + - name: KEY + value: 165 +enum/EXRSTPIN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 30 +enum/FCCCMD_KEY: + bit_size: 8 + variants: + - name: KEY + value: 14 +enum/FCCLVLTRIG: + bit_size: 1 + variants: + - name: RISE2RISE + description: Rising edge to rising edge triggered. + value: 0 + - name: LEVEL + description: Level triggered. + value: 1 +enum/FCCSELCLK: + bit_size: 4 + variants: + - name: MCLK + description: FCC clock is MCLK. + value: 0 + - name: SYSOSC + description: FCC clock is SYSOSC. + value: 1 + - name: HFCLK + description: FCC clock is HFCLK. + value: 2 + - name: EXTCLK + description: FCC clock is the CLK_OUT selection. + value: 3 + - name: FCCIN + description: FCC clock is the FCCIN external input. + value: 7 +enum/FCCTRIGSRC: + bit_size: 1 + variants: + - name: EXTPIN + description: FCC trigger is the external pin. + value: 0 + - name: LFCLK + description: FCC trigger is the LFCLK. + value: 1 +enum/FLASHWAIT: + bit_size: 4 + variants: + - name: WAIT0 + description: No flash wait states are applied. + value: 0 + - name: WAIT1 + description: One flash wait state is applied. + value: 1 + - name: WAIT2 + description: 2 flash wait states are applied. + value: 2 +enum/HFCLK4MFPCLKDIV: + bit_size: 4 + variants: + - name: DIV1 + description: HFCLK is not divided before being used for MFPCLK. + value: 0 + - name: DIV2 + description: HFCLK is divided by 2 before being used for MFPCLK. + value: 1 + - name: DIV3 + description: HFCLK is divided by 3 before being used for MFPCLK. + value: 2 + - name: DIV4 + description: HFCLK is divided by 4 before being used for MFPCLK. + value: 3 + - name: DIV5 + description: HFCLK is divided by 5 before being used for MFPCLK. + value: 4 + - name: DIV6 + description: HFCLK is divided by 6 before being used for MFPCLK. + value: 5 + - name: DIV7 + description: HFCLK is divided by 7 before being used for MFPCLK. + value: 6 + - name: DIV8 + description: HFCLK is divided by 8 before being used for MFPCLK. + value: 7 + - name: DIV9 + description: HFCLK is divided by 9 before being used for MFPCLK. + value: 8 + - name: DIV10 + description: HFCLK is divided by 10 before being used for MFPCLK. + value: 9 + - name: DIV11 + description: HFCLK is divided by 11 before being used for MFPCLK. + value: 10 + - name: DIV12 + description: HFCLK is divided by 12 before being used for MFPCLK. + value: 11 + - name: DIV13 + description: HFCLK is divided by 13 before being used for MFPCLK. + value: 12 + - name: DIV14 + description: HFCLK is divided by 14 before being used for MFPCLK. + value: 13 + - name: DIV15 + description: HFCLK is divided by 15 before being used for MFPCLK. + value: 14 + - name: DIV16 + description: HFCLK is divided by 16 before being used for MFPCLK. + value: 15 +enum/HSCLKMUX: + bit_size: 1 + variants: + - name: SYSOSC + description: MCLK is not sourced from HSCLK. + value: 0 + - name: HSCLK + description: MCLK is sourced from HSCLK. + value: 1 +enum/ID: + bit_size: 5 + variants: + - name: NORST + description: No reset since last read. + value: 0 + - name: PORHWFAIL + description: POR- violation, SHUTDNSTOREx or PMU trim parity fault. + value: 1 + - name: POREXNRST + description: NRST triggered POR (>1s hold). + value: 2 + - name: PORSW + description: Software triggered POR. + value: 3 + - name: BORSUPPLY + description: BOR0- violation. + value: 4 + - name: BORWAKESHUTDN + description: SHUTDOWN mode exit. + value: 5 + - name: BOOTNONPMUPARITY + description: Non-PMU trim parity fault. + value: 8 + - name: BOOTCLKFAIL + description: Fatal clock failure. + value: 9 + - name: BOOTEXNRST + description: NRST triggered BOOTRST (<1s hold). + value: 12 + - name: BOOTSW + description: Software triggered BOOTRST. + value: 13 + - name: BOOTWWDT0 + description: WWDT0 violation. + value: 14 + - name: SYSBSLEXIT + description: BSL exit. + value: 16 + - name: SYSBSLENTRY + description: BSL entry. + value: 17 + - name: SYSWWDT1 + description: WWDT1 violation. + value: 19 + - name: SYSFLASHECC + description: Flash uncorrectable ECC error. + value: 20 + - name: SYSCPULOCK + description: CPULOCK violation. + value: 21 + - name: SYSDBG + description: Debug triggered SYSRST. + value: 26 + - name: SYSSW + description: Software triggered SYSRST. + value: 27 + - name: CPUDBG + description: Debug triggered CPURST. + value: 28 + - name: CPUSW + description: Software triggered CPURST. + value: 29 +enum/IIDX_STAT: + bit_size: 3 + variants: + - name: NO_INTR + description: No interrupt pending. + value: 0 + - name: LFOSCGOOD + description: LFOSCGOOD interrupt pending. + value: 1 + - name: ANACLKERR + value: 2 + - name: FLASHSEC + value: 3 + - name: LFXTGOOD + value: 4 +enum/LFCLKMUX: + bit_size: 2 + variants: + - name: LFOSC + description: LFCLK is sourced from the internal LFOSC. + value: 0 + - name: LFXT + description: LFCLK is sourced from the LFXT (crystal). + value: 1 + - name: EXLF + description: LFCLK is sourced from LFCLK_IN (external digital clock input). + value: 2 +enum/LFXTCTL_KEY: + bit_size: 8 + variants: + - name: KEY + value: 165 +enum/MFPCLKSRC: + bit_size: 1 + variants: + - name: SYSOSC + description: MFPCLK is sourced from SYSOSC. + value: 0 + - name: HFCLK + description: MFPCLK is sourced from HFCLK. + value: 1 +enum/NMIIIDX_STAT: + bit_size: 3 + variants: + - name: NO_INTR + description: No NMI pending. + value: 0 + - name: BORLVL + description: BOR Threshold NMI pending. + value: 1 + - name: WWDT0 + value: 2 + - name: LFCLKFAIL + value: 3 + - name: FLASHDED + value: 4 +enum/RESETCMD_KEY: + bit_size: 8 + variants: + - name: KEY + value: 228 +enum/RESETLEVEL_LEVEL: + bit_size: 3 + variants: + - name: CPU + description: Issue a SYSRST (CPU plus peripherals only). + value: 0 + - name: BOOT + description: Issue a BOOTRST (CPU, peripherals, and boot configuration routine). + value: 1 + - name: BOOTLOADERENTRY + description: Issue a SYSRST and enter the boot strap loader (BSL). + value: 2 + - name: POR + description: Issue a power-on reset (POR). + value: 3 + - name: BOOTLOADEREXIT + description: Issue a SYSRST and exit the boot strap loader (BSL). + value: 4 +enum/SHDNIOREL_KEY: + bit_size: 8 + variants: + - name: KEY + value: 145 +enum/SWDCFG_KEY: + bit_size: 8 + variants: + - name: KEY + value: 98 +enum/SYSOSCCFG_FREQ: + bit_size: 2 + variants: + - name: SYSOSCBASE + description: Base frequency (32MHz). + value: 0 + - name: SYSOSC4M + description: Low frequency (4MHz). + value: 1 + - name: SYSOSCUSER + description: User-trimmed frequency (16 or 24 MHz). + value: 2 +enum/SYSOSCFCLCTL_KEY: + bit_size: 8 + variants: + - name: KEY + value: 42 +enum/SYSOSCFREQ: + bit_size: 2 + variants: + - name: SYSOSC32M + description: SYSOSC is at base frequency (32MHz). + value: 0 + - name: SYSOSC4M + description: SYSOSC is at low frequency (4MHz). + value: 1 + - name: SYSOSCUSER + description: SYSOSC is at the user-trimmed frequency (16 or 24MHz). + value: 2 +enum/SYSOSCTRIMUSER_FREQ: + bit_size: 2 + variants: + - name: SYSOSC16M + description: 16MHz user frequency. + value: 1 + - name: SYSOSC24M + description: 24MHz user frequency. + value: 2 +enum/SYSSTATUSCLR_KEY: + bit_size: 8 + variants: + - name: KEY + value: 206 +enum/XT1DRIVE: + bit_size: 2 + variants: + - name: LOWESTDRV + description: Lowest drive and current. + value: 0 + - name: LOWERDRV + description: Lower drive and current. + value: 1 + - name: HIGHERDRV + description: Higher drive and current. + value: 2 + - name: HIGHESTDRV + description: Highest drive and current. + value: 3 diff --git a/data/registers/vref_v1.yaml b/data/registers/vref_v1.yaml new file mode 100644 index 0000000..7d54eef --- /dev/null +++ b/data/registers/vref_v1.yaml @@ -0,0 +1,155 @@ +block/GPRCM: + items: + - name: PWREN + description: Power enable. + byte_offset: 0 + fieldset: PWREN + - name: RSTCTL + description: Reset Control. + byte_offset: 4 + access: Write + fieldset: RSTCTL + - name: STAT + description: Status Register. + byte_offset: 20 + access: Read + fieldset: STAT +block/VREF: + description: PERIPHERALREGION. + items: + - name: GPRCM + array: + len: 1 + stride: 24 + byte_offset: 2048 + block: GPRCM + - name: CLKDIV + description: Clock Divider. + byte_offset: 4096 + fieldset: CLKDIV + - name: CLKSEL + description: Clock Selection. + byte_offset: 4104 + fieldset: CLKSEL + - name: CTL0 + description: Control 0. + byte_offset: 4352 + fieldset: CTL0 + - name: CTL1 + description: Control 1. + byte_offset: 4356 + fieldset: CTL1 + - name: CTL2 + description: Control 2. + byte_offset: 4360 + fieldset: CTL2 +fieldset/CLKDIV: + description: Clock Divider. + fields: + - name: RATIO + description: Selects divide ratio of module clock to be used in sample and hold logic. + bit_offset: 0 + bit_size: 3 +fieldset/CLKSEL: + description: Clock Selection. + fields: + - name: LFCLK_SEL + description: Selects LFCLK as clock source if enabled. + bit_offset: 1 + bit_size: 1 + - name: MFCLK_SEL + description: Selects MFCLK as clock source if enabled. + bit_offset: 2 + bit_size: 1 + - name: BUSCLK_SEL + description: Selects BUSCLK as clock source if enabled. + bit_offset: 3 + bit_size: 1 +fieldset/CTL0: + description: Control 0. + fields: + - name: ENABLE + description: This bit enables the VREF module. + bit_offset: 0 + bit_size: 1 + - name: BUFCONFIG + description: These bits configure output buffer. + bit_offset: 7 + bit_size: 1 + enum: BUFCONFIG + - name: SHMODE + description: This bit enable sample and hold mode. + bit_offset: 8 + bit_size: 1 +fieldset/CTL1: + description: Control 1. + fields: + - name: READY + description: These bits defines status of VREF. + bit_offset: 0 + bit_size: 1 +fieldset/CTL2: + description: Control 2. + fields: + - name: SHCYCLE + description: Sample and Hold cycle count Total cycles of module clock for sample and hold phase when VREF is working in sample and hold mode in STANDBY to save power. This field should be greater than HCYCLE field. The difference between this field and HCYCLE gives the number of cycles of sample phase. Please refer VREF section of datasheet for recommended values of sample and hold times. + bit_offset: 0 + bit_size: 16 + - name: HCYCLE + description: Hold cycle count Total cycles of module clock for hold phase when VREF is working in sample and hold mode in STANDBY to save power. Please refer VREF section of datasheet for recommended values of sample and hold times. + bit_offset: 16 + bit_size: 16 +fieldset/PWREN: + description: Power enable. + fields: + - name: ENABLE + description: Enable the power. + bit_offset: 0 + bit_size: 1 + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY +fieldset/RSTCTL: + description: Reset Control. + fields: + - name: RESETASSERT + description: Assert reset to the peripheral. + bit_offset: 0 + bit_size: 1 + - name: RESETSTKYCLR + description: Clear the RESETSTKY bit in the STAT register. + bit_offset: 1 + bit_size: 1 + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY +fieldset/STAT: + description: Status Register. + fields: + - name: RESETSTKY + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. + bit_offset: 16 + bit_size: 1 +enum/BUFCONFIG: + bit_size: 1 + variants: + - name: OUTPUT2P5V + description: Configure Output Buffer to 2.5v. + value: 0 + - name: OUTPUT1P4V + description: Configure Output Buffer to 1.4v. + value: 1 +enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 +enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 diff --git a/data/registers/wuc_v1.yaml b/data/registers/wuc_v1.yaml new file mode 100644 index 0000000..aed4ae6 --- /dev/null +++ b/data/registers/wuc_v1.yaml @@ -0,0 +1,17 @@ +block/WUC: + description: PERIPHERALREGION. + items: + - name: FSUB + description: Subscriber Port 0. + array: + len: 2 + stride: 4 + byte_offset: 1024 + fieldset: FPORT +fieldset/FPORT: + description: Subscriber Port 0. + fields: + - name: CHANID + description: 0 = disconnected. 1-15 = connected to channelID = CHANID. + bit_offset: 0 + bit_size: 4 diff --git a/mspm0-data-gen/src/perimap.rs b/mspm0-data-gen/src/perimap.rs index 1d90539..e18be13 100644 --- a/mspm0-data-gen/src/perimap.rs +++ b/mspm0-data-gen/src/perimap.rs @@ -13,7 +13,19 @@ pub static PERIMAP: RegexMap<&str> = RegexMap::new(&[ (".*:adc", "v1"), (".*:wwdt", "v1"), (".*:trng", "v1"), + (".*:spi", "v1"), + (".*:rtc", "v1"), + (".*:crc", "v1"), + (".*:vref", "v1"), + (".*:dac", "v1"), + (".*:comp", "v1"), + (".*:opa", "v1"), + (".*:aes", "v1"), + (".*:flashctl", "v1"), (".*:canfd", "v1"), + (".*:eventlp", "v1"), + (".*:wuc", "v1"), + (".*:debugss", "v1"), ("mspm0c110x:sysctl", "c110x"), ("mspm0c1105_c1106:sysctl", "c110x"), ("msps003fx:sysctl", "c110x"), @@ -23,6 +35,7 @@ pub static PERIMAP: RegexMap<&str> = RegexMap::new(&[ ("mspm0g5..x:sysctl", "g350x_g310x_g150x_g110x"), ("mspm0h321x:sysctl", "h321x"), ("mspm0l..0x:sysctl", "l110x_l130x_l134x"), + ("mspm0l111x:sysctl", "l111x"), ("mspm0l134x:sysctl", "l110x_l130x_l134x"), ("mspm0l.22x:sysctl", "l122x_l222x"), // FIXME: When reference manual is updated for L112/L211x, update these if needed (split out). diff --git a/transforms/AES.yaml b/transforms/AES.yaml new file mode 100644 index 0000000..21b85af --- /dev/null +++ b/transforms/AES.yaml @@ -0,0 +1,253 @@ +# Transform for AES registers based on AES on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # However DeleteUselessEnums does not delete MIS and IMASK (due to CLR being 0 and SET being 1) + - !DeleteEnumsWithVariants + variants: + 0: CLR + 1: SET + + - !DeleteEnumsWithVariants + variants: + 0: CLEARED + 1: SET + + # FREE is useless + - !DeleteEnumsWithVariants + variants: + 0: STOP + 1: RUN + + # RESETASSERT is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: ASSERT + + # RESETSTKY is useless + - !DeleteEnumsWithVariants + variants: + 0: NORES + 1: RESET + + # RESETSTKYCLR is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: CLR + + # INTEVAL is useless + - !DeleteEnumsWithVariants + variants: + 0: DISABLE + 1: EVAL + + # Remove AES_ prefixes + - !RenameRegisters + block: .* + from: AES_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: AES_(.+) + to: $1 + + - !Rename + type: All + from: AES_(.+) + to: $1 + + ## Interrupts - AES has INT_EVENT0-3 + ## INT_EVENT0 -> CPU_INT + - !MergeBlocks + from: INT_EVENT0 + main: INT_EVENT0 + to: CPU_INT + + - !RenameRegisters + block: .* + from: INT_EVENT0(.*) + to: CPU_INT$1 + + - !RenameFields + fieldset: .* + from: INT_EVENT0(.+) + to: CPU_INT$1 + + - !Rename + type: All + from: INT_EVENT0(.+) + to: CPU_INT$1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: CPU_INT_(IMASK|ISET|MIS|RIS|ICLR) + to: CPU_INT + check: NoCheck + + - !RenameRegisters + block: .* + from: CPU_INT_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: CPU_INT_(.+) + to: $1 + + ## INT_EVENT1 -> DMA_TRIG0 + - !MergeBlocks + from: INT_EVENT1 + main: INT_EVENT1 + to: DMA_TRIG0 + + - !RenameRegisters + block: .* + from: INT_EVENT1(.*) + to: DMA_TRIG0$1 + + - !RenameFields + fieldset: .* + from: INT_EVENT1(.+) + to: DMA_TRIG0$1 + + - !Rename + type: All + from: INT_EVENT1(.+) + to: DMA_TRIG0$1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: DMA_TRIG0_(IMASK|ISET|MIS|RIS|ICLR) + to: DMA_TRIG0 + check: NoCheck + + - !RenameRegisters + block: .* + from: DMA_TRIG0_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: DMA_TRIG0_(.+) + to: $1 + + ## INT_EVENT2 -> DMA_TRIG1 + - !MergeBlocks + from: INT_EVENT2 + main: INT_EVENT2 + to: DMA_TRIG1 + + - !RenameRegisters + block: .* + from: INT_EVENT2(.*) + to: DMA_TRIG1$1 + + - !RenameFields + fieldset: .* + from: INT_EVENT2(.+) + to: DMA_TRIG1$1 + + - !Rename + type: All + from: INT_EVENT2(.+) + to: DMA_TRIG1$1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: DMA_TRIG1_(IMASK|ISET|MIS|RIS|ICLR) + to: DMA_TRIG1 + check: NoCheck + + - !RenameRegisters + block: .* + from: DMA_TRIG1_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: DMA_TRIG1_(.+) + to: $1 + + ## INT_EVENT3 -> DMA_TRIG2 + - !MergeBlocks + from: INT_EVENT3 + main: INT_EVENT3 + to: DMA_TRIG2 + + - !RenameRegisters + block: .* + from: INT_EVENT3(.*) + to: DMA_TRIG2$1 + + - !RenameFields + fieldset: .* + from: INT_EVENT3(.+) + to: DMA_TRIG2$1 + + - !Rename + type: All + from: INT_EVENT3(.+) + to: DMA_TRIG2$1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: DMA_TRIG2_(IMASK|ISET|MIS|RIS|ICLR) + to: DMA_TRIG2 + check: NoCheck + + - !RenameRegisters + block: .* + from: DMA_TRIG2_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: DMA_TRIG2_(.+) + to: $1 + + ## Add missing keys + - !AddFields + fieldset: RSTCTL + fields: + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY + + - !AddFields + fieldset: PWREN + fields: + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY + + - !Add + ir: + enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 + enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 + + ## EVT_MODE + - !MergeEnums + from: (INT|EVT)(\d+)_CFG + to: EVT_CFG + + ## Cleanup + - !Sort diff --git a/transforms/CANFD.yaml b/transforms/CANFD.yaml index c434574..4712073 100644 --- a/transforms/CANFD.yaml +++ b/transforms/CANFD.yaml @@ -1,7 +1,11 @@ -# Transforms for CANFD registers from G351x +# Transform for CANFD registers based on CANFD0 on G350x transforms: - !DeleteUselessEnums + - !DeleteFieldsets + from: .* + useless: true + - !DeleteEnumsWithVariants variants: 0: CLR @@ -9,33 +13,36 @@ transforms: - !DeleteEnumsWithVariants variants: - 0: RESET + 0: CLEARED 1: SET - # RESETASSERT is useless - !DeleteEnumsWithVariants variants: 0: NOP 1: ASSERT - # RESETSTKY is useless - !DeleteEnumsWithVariants variants: 0: NORES 1: RESET - # RESETSTKYCLR is useless - !DeleteEnumsWithVariants variants: 0: NOP 1: CLR - - !Rename - type: Block + - !DeleteEnumsWithVariants + variants: + 0: DISABLE + 1: EVAL + + # Merge CANFD0 -> CANFD + - !MergeBlocks from: CANFD0 + main: CANFD0 to: CANFD - # Remove CANFD0 prefixes + # Remove CANFD0_ prefixes - !RenameRegisters block: .* from: CANFD0_(.+) @@ -47,40 +54,13 @@ transforms: to: $1 - !Rename - type: Fieldset - from: CANFD0_(.+) - to: $1 - - - !Rename - type: Block + type: All from: CANFD0_(.+) to: $1 - # Rename blocks - - - !Rename - type: Block - from: MCANSS_REGS - to: SUBSYS - - - !Rename - type: Block - from: MCAN_ECC_REGS - to: ECC - - - !Rename - type: Block - from: MSP - to: MSP - - - !Rename - type: Block - from: (CPU_INT|INT_EVENT0) - to: CPU_INT - - # Remove MCAN prefixes + # MCAN block - remove MCAN_ prefix from registers - !RenameRegisters - block: .* + block: MCAN from: MCAN_(.+) to: $1 @@ -90,134 +70,93 @@ transforms: to: $1 - !Rename - type: Fieldset + type: All from: MCAN_(.+) to: $1 - # Remove MCANSS prefixes + # TI_WRAPPER block - remove TI_WRAPPER_ prefix - !RenameRegisters - block: .* - from: MCANSS_(.+) - to: SUBSYS_$1 + block: TI_WRAPPER + from: TI_WRAPPER_(.+) + to: $1 - !RenameFields fieldset: .* - from: MCANSS_(.+) - to: SUBSYS_$1 + from: TI_WRAPPER_(.+) + to: $1 - !Rename - type: Fieldset - from: MCANSS_(.+) - to: SUBSYS_$1 + type: All + from: TI_WRAPPER_(.+) + to: $1 + + ## Interrupts + - !MergeBlocks + from: INT_EVENT0 + main: INT_EVENT0 + to: CPU_INT - # Change MCANERR prefixes to ERR - !RenameRegisters block: .* - from: MCANERR_(.+) - to: ERR_$1 + from: INT_EVENT0(.*) + to: CPU_INT$1 - !RenameFields fieldset: .* - from: MCANERR_(.+) - to: ERR_$1 + from: INT_EVENT0(.+) + to: CPU_INT$1 - !Rename - type: Fieldset - from: MCANERR_(.+) - to: ERR_$1 + type: All + from: INT_EVENT0(.+) + to: CPU_INT$1 - # NDAT1 and NDAT2 have the same layout - - !MergeFieldsets - from: (NDAT1|NDAT2) - to: NDAT - check: Layout - - - !MakeFieldArray - fieldsets: NDAT - from: ND\d+ - to: ND - - - !MakeFieldArray - fieldsets: TXBAR - from: AR\d+ - to: AR - - - !MakeFieldArray - fieldsets: TXBCF - from: CF\d+ - to: CF - - - !MakeFieldArray - fieldsets: TXCBF - from: AR\d+ - to: AR - - - !MakeFieldArray - fieldsets: TXBCIE - from: CFIE\d+ - to: CFIE - - - !MakeFieldArray - fieldsets: TXBCR - from: CR\d+ - to: CR - - - !MakeFieldArray - fieldsets: TXBRP - from: TRP\d+ - to: TRP - - - !MakeFieldArray - fieldsets: TXBTIE - from: TIE\d+ - to: TIE - - - !MakeFieldArray - fieldsets: TXBTO - from: TO\d+ - to: TO - - # CPU_INT interrupt fields are all the same layout. - !MergeFieldsets - from: (IMASK|ISET|MIS|RIS|ICLR) + from: CPU_INT_(IMASK|ISET|MIS|RIS|ICLR) to: CPU_INT + check: NoCheck - !RenameRegisters - block: MSP - from: INT_EVENT0 - to: CPU_INT + block: .* + from: CPU_INT_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: CPU_INT_(.+) + to: $1 ## Add missing keys - !AddFields - fieldset: PWREN + fieldset: RSTCTL fields: - name: KEY - description: KEY to allow Power State Change 26h = KEY to allow write access to this register + description: Unlock key B1h = KEY to allow write access to this register bit_offset: 24 bit_size: 8 - enum: PWREN_KEY + enum: RESET_KEY - !AddFields - fieldset: RSTCTL + fieldset: PWREN fields: - name: KEY - description: Unlock key B1h = KEY to allow write access to this register + description: KEY to allow Power State Change 26h = KEY to allow write access to this register bit_offset: 24 bit_size: 8 - enum: RESET_KEY + enum: PWREN_KEY - !Add ir: - enum/PWREN_KEY: + enum/RESET_KEY: bit_size: 8 variants: - name: KEY - value: 38 - enum/RESET_KEY: + value: 177 + enum/PWREN_KEY: bit_size: 8 variants: - name: KEY - value: 177 + value: 38 - # Cleanup + ## Cleanup - !Sort diff --git a/transforms/COMP.yaml b/transforms/COMP.yaml new file mode 100644 index 0000000..49e9f3f --- /dev/null +++ b/transforms/COMP.yaml @@ -0,0 +1,146 @@ +# Transform for COMP registers based on COMP0 on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # However DeleteUselessEnums does not delete MIS and IMASK (due to CLR being 0 and SET being 1) + - !DeleteEnumsWithVariants + variants: + 0: CLR + 1: SET + + - !DeleteEnumsWithVariants + variants: + 0: CLEARED + 1: SET + + # RESETASSERT is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: ASSERT + + # RESETSTKY is useless + - !DeleteEnumsWithVariants + variants: + 0: NORES + 1: RESET + + # RESETSTKYCLR is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: CLR + + # INTEVAL is useless + - !DeleteEnumsWithVariants + variants: + 0: DISABLE + 1: EVAL + + # Merge COMP0 -> COMP + - !MergeBlocks + from: COMP0 + main: COMP0 + to: COMP + + # Remove COMP0_ prefixes + - !RenameRegisters + block: .* + from: COMP0_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: COMP0_(.+) + to: $1 + + - !Rename + type: All + from: COMP0_(.+) + to: $1 + + ## Interrupts - COMP has INT_EVENT[0..1] + - !MergeBlocks + from: INT_EVENT + main: INT_EVENT + to: INT_EVENT + + - !RenameRegisters + block: .* + from: INT_EVENT_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: INT_EVENT_(.+) + to: $1 + + - !Rename + type: All + from: INT_EVENT_(.+) + to: $1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: (IMASK|ISET|MIS|RIS|ICLR) + to: INT + check: NoCheck + + ## Publisher/Subscriber ports + # CHANID is an int + - !DeleteEnums + from: .*CHANID + bit_size: 4 + + - !MergeFieldsets + from: (FPUB|FSUB)_\d+ + to: FPORT + + - !MakeRegisterArray + blocks: .* + from: FSUB_(\d+) + to: FSUB + + ## Add missing keys + - !AddFields + fieldset: RSTCTL + fields: + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY + + - !AddFields + fieldset: PWREN + fields: + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY + + - !Add + ir: + enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 + enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 + + ## EVT_MODE + - !MergeEnums + from: (INT|EVT)(\d+)_CFG + to: EVT_CFG + + ## Cleanup + - !Sort diff --git a/transforms/CRC.yaml b/transforms/CRC.yaml new file mode 100644 index 0000000..5382ae3 --- /dev/null +++ b/transforms/CRC.yaml @@ -0,0 +1,76 @@ +# Transform for CRC registers based on CRC on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # RESETASSERT is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: ASSERT + + # RESETSTKY is useless + - !DeleteEnumsWithVariants + variants: + 0: NORES + 1: RESET + + # RESETSTKYCLR is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: CLR + + # Remove CRC_ prefixes + - !RenameRegisters + block: .* + from: CRC_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: CRC_(.+) + to: $1 + + - !Rename + type: All + from: CRC_(.+) + to: $1 + + ## Add missing keys + - !AddFields + fieldset: RSTCTL + fields: + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY + + - !AddFields + fieldset: PWREN + fields: + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY + + - !Add + ir: + enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 + enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 + + ## Cleanup + - !Sort diff --git a/transforms/DAC.yaml b/transforms/DAC.yaml new file mode 100644 index 0000000..80b5190 --- /dev/null +++ b/transforms/DAC.yaml @@ -0,0 +1,147 @@ +# Transform for DAC registers based on DAC0 on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # However DeleteUselessEnums does not delete MIS and IMASK (due to CLR being 0 and SET being 1) + - !DeleteEnumsWithVariants + variants: + 0: CLR + 1: SET + + - !DeleteEnumsWithVariants + variants: + 0: CLEARED + 1: SET + + # RESETASSERT is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: ASSERT + + # RESETSTKY is useless + - !DeleteEnumsWithVariants + variants: + 0: NORES + 1: RESET + + # RESETSTKYCLR is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: CLR + + # INTEVAL is useless + - !DeleteEnumsWithVariants + variants: + 0: DISABLE + 1: EVAL + + # Merge DAC0 -> DAC + - !MergeBlocks + from: DAC0 + main: DAC0 + to: DAC + + # Remove DAC0_ prefixes + - !RenameRegisters + block: .* + from: DAC0_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: DAC0_(.+) + to: $1 + + - !Rename + type: All + from: DAC0_(.+) + to: $1 + + ## Interrupts - DAC has INT_EVENT[0..1] + # Merge INT_EVENT blocks + - !MergeBlocks + from: INT_EVENT + main: INT_EVENT + to: INT_EVENT + + - !RenameRegisters + block: .* + from: INT_EVENT_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: INT_EVENT_(.+) + to: $1 + + - !Rename + type: All + from: INT_EVENT_(.+) + to: $1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: (IMASK|ISET|MIS|RIS|ICLR) + to: INT + check: NoCheck + + ## Publisher/Subscriber ports + # CHANID is an int + - !DeleteEnums + from: .*CHANID + bit_size: 4 + + - !MergeFieldsets + from: (FPUB|FSUB)_\d+ + to: FPORT + + - !MakeRegisterArray + blocks: .* + from: FSUB_(\d+) + to: FSUB + + ## Add missing keys + - !AddFields + fieldset: RSTCTL + fields: + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY + + - !AddFields + fieldset: PWREN + fields: + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY + + - !Add + ir: + enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 + enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 + + ## EVT_MODE + - !MergeEnums + from: (INT|EVT)(\d+)_CFG + to: EVT_CFG + + ## Cleanup + - !Sort diff --git a/transforms/DEBUGSS.yaml b/transforms/DEBUGSS.yaml new file mode 100644 index 0000000..920ef44 --- /dev/null +++ b/transforms/DEBUGSS.yaml @@ -0,0 +1,54 @@ +# Transform for DEBUGSS registers based on DEBUGSS on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # However DeleteUselessEnums does not delete MIS and IMASK (due to CLR being 0 and SET being 1) + - !DeleteEnumsWithVariants + variants: + 0: CLR + 1: SET + + - !DeleteEnumsWithVariants + variants: + 0: CLEARED + 1: SET + + - !DeleteEnumsWithVariants + variants: + 0: NO_EFFECT + 1: SET + + # INTEVAL is useless + - !DeleteEnumsWithVariants + variants: + 0: DISABLE + 1: EVAL + + # Remove DEBUGSS_ prefixes + - !RenameRegisters + block: .* + from: DEBUGSS_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: DEBUGSS_(.+) + to: $1 + + - !Rename + type: All + from: DEBUGSS_(.+) + to: $1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: (IMASK|ISET|MIS|RIS|ICLR) + to: INT + check: NoCheck + + ## Cleanup + - !Sort diff --git a/transforms/EVENTLP.yaml b/transforms/EVENTLP.yaml new file mode 100644 index 0000000..099ad6c --- /dev/null +++ b/transforms/EVENTLP.yaml @@ -0,0 +1,55 @@ +# Transform for EVENTLP registers based on EVENTLP on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # However DeleteUselessEnums does not delete MIS and IMASK (due to CLR being 0 and SET being 1) + - !DeleteEnumsWithVariants + variants: + 0: CLR + 1: SET + + - !DeleteEnumsWithVariants + variants: + 0: CLEARED + 1: SET + + # INTEVAL is useless + - !DeleteEnumsWithVariants + variants: + 0: DISABLE + 1: EVAL + + # DIAGPAR ASSERTDIAG is useless + - !DeleteEnumsWithVariants + variants: + 0: NO_EFFECT + 1: START + + # DIAGPAR ASSERTDIAG CLR is useless + - !DeleteEnumsWithVariants + variants: + 0: NO_EFFECT + 1: CLR + + # Remove EVENTLP_ prefixes + - !RenameRegisters + block: .* + from: EVENTLP_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: EVENTLP_(.+) + to: $1 + + - !Rename + type: All + from: EVENTLP_(.+) + to: $1 + + ## Cleanup + - !Sort diff --git a/transforms/FLASHCTL.yaml b/transforms/FLASHCTL.yaml new file mode 100644 index 0000000..5531ab4 --- /dev/null +++ b/transforms/FLASHCTL.yaml @@ -0,0 +1,58 @@ +# Transform for FLASHCTL registers based on FLASHCTL on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # However DeleteUselessEnums does not delete MIS and IMASK (due to CLR being 0 and SET being 1) + - !DeleteEnumsWithVariants + variants: + 0: CLR + 1: SET + + - !DeleteEnumsWithVariants + variants: + 0: CLEARED + 1: SET + + # INTEVAL is useless + - !DeleteEnumsWithVariants + variants: + 0: DISABLE + 1: EVAL + + # Remove FLASHCTL_ prefixes + - !RenameRegisters + block: .* + from: FLASHCTL_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: FLASHCTL_(.+) + to: $1 + + - !Rename + type: All + from: FLASHCTL_(.+) + to: $1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: (IMASK|ISET|MIS|RIS|ICLR) + to: INT + check: NoCheck + + ## EVT_MODE + - !MergeEnums + from: (INT|EVT)(\d+)_CFG + to: EVT_CFG + + ## Delete broken BANKNOTINRD enum - values don't fit bit size + - !DeleteEnums + from: BANKNOTINRD + + ## Cleanup + - !Sort diff --git a/transforms/OPA.yaml b/transforms/OPA.yaml new file mode 100644 index 0000000..a1768bb --- /dev/null +++ b/transforms/OPA.yaml @@ -0,0 +1,82 @@ +# Transform for OPA registers based on OPA0 on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # RESETASSERT is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: ASSERT + + # RESETSTKY is useless + - !DeleteEnumsWithVariants + variants: + 0: NORES + 1: RESET + + # RESETSTKYCLR is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: CLR + + # Merge OPA0 -> OPA + - !MergeBlocks + from: OPA0 + main: OPA0 + to: OPA + + # Remove OPA0_ prefixes + - !RenameRegisters + block: .* + from: OPA0_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: OPA0_(.+) + to: $1 + + - !Rename + type: All + from: OPA0_(.+) + to: $1 + + ## Add missing keys + - !AddFields + fieldset: RSTCTL + fields: + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY + + - !AddFields + fieldset: PWREN + fields: + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY + + - !Add + ir: + enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 + enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 + + ## Cleanup + - !Sort diff --git a/transforms/RTC.yaml b/transforms/RTC.yaml new file mode 100644 index 0000000..d58cac3 --- /dev/null +++ b/transforms/RTC.yaml @@ -0,0 +1,194 @@ +# Transform for RTC registers based on RTC on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # However DeleteUselessEnums does not delete MIS and IMASK (due to CLR being 0 and SET being 1) + - !DeleteEnumsWithVariants + variants: + 0: CLR + 1: SET + + - !DeleteEnumsWithVariants + variants: + 0: CLEARED + 1: SET + + # FREE is useless + - !DeleteEnumsWithVariants + variants: + 0: STOP + 1: RUN + + # RESETASSERT is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: ASSERT + + # RESETSTKY is useless + - !DeleteEnumsWithVariants + variants: + 0: NORES + 1: RESET + + # RESETSTKYCLR is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: CLR + + # INTEVAL is useless + - !DeleteEnumsWithVariants + variants: + 0: DISABLE + 1: EVAL + + # Remove RTC_ prefixes + - !RenameRegisters + block: .* + from: RTC_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: RTC_(.+) + to: $1 + + - !Rename + type: All + from: RTC_(.+) + to: $1 + + ## Interrupts + ## INT_EVENT0 -> CPU_INT + - !MergeBlocks + from: INT_EVENT0 + main: INT_EVENT0 + to: CPU_INT + + - !RenameRegisters + block: .* + from: INT_EVENT0(.*) + to: CPU_INT$1 + + - !RenameFields + fieldset: .* + from: INT_EVENT0(.+) + to: CPU_INT$1 + + - !Rename + type: All + from: INT_EVENT0(.+) + to: CPU_INT$1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: CPU_INT_(IMASK|ISET|MIS|RIS|ICLR) + to: CPU_INT + check: NoCheck + + - !RenameRegisters + block: .* + from: CPU_INT_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: CPU_INT_(.+) + to: $1 + + ## INT_EVENT1 -> EVT_OUT (RTC uses event output, not DMA) + - !MergeBlocks + from: INT_EVENT1 + main: INT_EVENT1 + to: EVT_OUT + + - !RenameRegisters + block: .* + from: INT_EVENT1(.*) + to: EVT_OUT$1 + + - !RenameFields + fieldset: .* + from: INT_EVENT1(.+) + to: EVT_OUT$1 + + - !Rename + type: All + from: INT_EVENT1(.+) + to: EVT_OUT$1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: EVT_OUT_(IMASK|ISET|MIS|RIS|ICLR) + to: EVT_OUT + check: NoCheck + + - !RenameRegisters + block: .* + from: EVT_OUT_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: EVT_OUT_(.+) + to: $1 + + ## Publisher/Subscriber ports + # CHANID is an int + - !DeleteEnums + from: CHANID + bit_size: 4 + + ## Add missing keys + - !AddFields + fieldset: RSTCTL + fields: + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY + + - !AddFields + fieldset: PWREN + fields: + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY + + - !Add + ir: + enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 + enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 + + ## EVT_MODE + - !MergeEnums + from: (INT|EVT)(\d+)_CFG + to: EVT_CFG + + - !RenameFields + fieldset: EVT_MODE + from: INT0_CFG + to: CPU + - !RenameFields + fieldset: EVT_MODE + from: EVT1_CFG + to: EVT_OUT + + ## Cleanup + - !Sort diff --git a/transforms/SPI.yaml b/transforms/SPI.yaml new file mode 100644 index 0000000..78ccf99 --- /dev/null +++ b/transforms/SPI.yaml @@ -0,0 +1,263 @@ +# Transform for SPI registers based on SPI0 on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # However DeleteUselessEnums does not delete MIS and IMASK (due to CLR being 0 and SET being 1) + - !DeleteEnumsWithVariants + variants: + 0: CLR + 1: SET + + - !DeleteEnumsWithVariants + variants: + 0: CLEARED + 1: SET + + # FREE is useless + - !DeleteEnumsWithVariants + variants: + 0: STOP + 1: RUN + + # RESETASSERT is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: ASSERT + + # RESETSTKY is useless + - !DeleteEnumsWithVariants + variants: + 0: NORES + 1: RESET + + # RESETSTKYCLR is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: CLR + + # INTEVAL is useless + - !DeleteEnumsWithVariants + variants: + 0: DISABLE + 1: EVAL + + # Merge SPI0 -> SPI + - !MergeBlocks + from: SPI0 + main: SPI0 + to: SPI + + # Remove prefixes + - !RenameRegisters + block: .* + from: SPI0_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: SPI0_(.+) + to: $1 + + - !Rename + type: All + from: SPI0_(.+) + to: $1 + + ## Interrupts + ## INT_EVENT0 -> CPU_INT + - !MergeBlocks + from: INT_EVENT0 + main: INT_EVENT0 + to: CPU_INT + + - !RenameRegisters + block: .* + from: INT_EVENT0(.*) + to: CPU_INT$1 + + - !RenameFields + fieldset: .* + from: INT_EVENT0(.+) + to: CPU_INT$1 + + - !Rename + type: All + from: INT_EVENT0(.+) + to: CPU_INT$1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: CPU_INT_(IMASK|ISET|MIS|RIS|ICLR) + to: CPU_INT + check: NoCheck + + # Remove redundant prefixes in the CPU_INT block + - !RenameRegisters + block: .* + from: CPU_INT_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: CPU_INT_(.+) + to: $1 + + ## INT_EVENT1 -> DMA_TRIG_RX + - !MergeBlocks + from: INT_EVENT1 + main: INT_EVENT1 + to: DMA_TRIG_RX + + - !RenameRegisters + block: .* + from: INT_EVENT1(.*) + to: DMA_TRIG_RX$1 + + - !RenameFields + fieldset: .* + from: INT_EVENT1(.+) + to: DMA_TRIG_RX$1 + + - !Rename + type: All + from: INT_EVENT1(.+) + to: DMA_TRIG_RX$1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: DMA_TRIG_RX_(IMASK|ISET|MIS|RIS|ICLR) + to: DMA_TRIG_RX + check: NoCheck + + # Remove redundant prefixes in the DMA_TRIG_RX block + - !RenameRegisters + block: .* + from: DMA_TRIG_RX_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: DMA_TRIG_RX_(.+) + to: $1 + + ## INT_EVENT2 -> DMA_TRIG_TX + - !MergeBlocks + from: INT_EVENT2 + main: INT_EVENT2 + to: DMA_TRIG_TX + + - !RenameRegisters + block: .* + from: INT_EVENT2(.*) + to: DMA_TRIG_TX$1 + + - !RenameFields + fieldset: .* + from: INT_EVENT2(.+) + to: DMA_TRIG_TX$1 + + - !Rename + type: All + from: INT_EVENT2(.+) + to: DMA_TRIG_TX$1 + + # These interrupt fields are all the same layout. + - !MergeFieldsets + from: DMA_TRIG_TX_(IMASK|ISET|MIS|RIS|ICLR) + to: DMA_TRIG_TX + check: NoCheck + + # Remove redundant prefixes in the DMA_TRIG_TX block + - !RenameRegisters + block: .* + from: DMA_TRIG_TX_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: DMA_TRIG_TX_(.+) + to: $1 + + ## Add missing keys + - !AddFields + fieldset: RSTCTL + fields: + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY + + - !AddFields + fieldset: PWREN + fields: + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY + + - !AddFields + fieldset: CLKCFG + fields: + - name: KEY + description: KEY to Allow State Change A9h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: CLKCFG_KEY + + - !Add + ir: + enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 + enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 + enum/CLKCFG_KEY: + bit_size: 8 + variants: + - name: KEY + value: 0xA9 + + ## EVT_MODE + # Merge INTx_CFG and EVTx_CFG enums + - !MergeEnums + from: (INT|EVT)(\d+)_CFG + to: EVT_CFG + + # Rename fields to match interrupt names + - !RenameFields + fieldset: EVT_MODE + from: INT0_CFG + to: CPU + - !RenameFields + fieldset: EVT_MODE + from: INT1_CFG + to: DMA_TRIG_RX + - !RenameFields + fieldset: EVT_MODE + from: EVT2_CFG + to: DMA_TRIG_TX + + ## CLKDIV enums are same + - !MergeEnums + from: CLKDIV(.*) + to: CLKDIV + + - !MergeFieldsets + from: CLKDIV(.*) + to: CLKDIV + + ## Cleanup + - !Sort diff --git a/transforms/SYSCTL_L111x.yaml b/transforms/SYSCTL_L111x.yaml new file mode 100644 index 0000000..46a6ce9 --- /dev/null +++ b/transforms/SYSCTL_L111x.yaml @@ -0,0 +1,259 @@ +# Transform using SYSCTL from L111x +# L111x has LFXT support (HSCLKEN, LFCLKCFG, LFXTCTL, EXLFCTL) and flash protection registers +# that are not present in L110x/L130x/L134x +transforms: + - !DeleteFieldsets + from: .* + useless: true + + - !DeleteUselessEnums + + # Remove SYSCTL prefixes + - !RenameRegisters + block: .* + from: SYSCTL_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: SYSCTL_(.+) + to: $1 + + - !Rename + type: All + from: SYSCTL_(.+) + to: $1 + + # IMASK, RIS, MIS, ISET, ICLR are the same type + - !MergeFieldsets + from: (IMASK|RIS|MIS|ISET|ICLR) + to: INT + + # FIXME: Rename IIDX_STAT to INT_STAT in all chips + # Note: L111x has correct interrupt structure in SVD: + # bit 0: LFOSCGOOD, bit 1: ANACLKERR, bit 2: FLASHSEC, bit 3: LFXTGOOD + + # NMIRIS, NMIISET and NMIICLR are the same type + - !MergeFieldsets + from: NMI(RIS|ISET|ICLR) + to: NMI + + # Remove SYSOSCTURBO variants, not defined on L-series + - !DeleteEnumVariants + enum: (SYSOSCCFG_FREQ|SYSOSCFREQ) + from: SYSOSCTURBO + + # FIXME: Rename NMIIIDX to be consistent across chips + + # Note: L111x has correct RSTCAUSE.ID values in SVD: + # BOOTWWDT0 = 14, SYSWWDT1 = 19 (no modifications needed) + + # RESETCMD: Add KEY + - !Add + ir: + enum/RESETCMD_KEY: + bit_size: 8 + variants: + - name: KEY + value: 228 + + - !AddFields + fieldset: RESETCMD + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: RESETCMD_KEY + + # BORTHRESHOLD_LEVEL is useless + - !DeleteEnums + from: BORTHRESHOLD_LEVEL + + # BORCLRCMD: Add key + - !Add + ir: + enum/BORCLRCMD_KEY: + bit_size: 8 + variants: + - name: KEY + value: 199 + + - !AddFields + fieldset: BORCLRCMD + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: BORCLRCMD_KEY + + # SYSOSCFCLCTL: Add key + - !Add + ir: + enum/SYSOSCFCLCTL_KEY: + bit_size: 8 + variants: + - name: KEY + value: 42 + + - !AddFields + fieldset: SYSOSCFCLCTL + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: SYSOSCFCLCTL_KEY + + # SHDNIOREL: Add key + - !Add + ir: + enum/SHDNIOREL_KEY: + bit_size: 8 + variants: + - name: KEY + value: 145 + + - !AddFields + fieldset: SHDNIOREL + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: SHDNIOREL_KEY + + # EXRSTPIN: Add key + - !Add + ir: + enum/EXRSTPIN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 30 + + - !AddFields + fieldset: EXRSTPIN + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: EXRSTPIN_KEY + + # SYSSTATUSCLR: Add key + - !Add + ir: + enum/SYSSTATUSCLR_KEY: + bit_size: 8 + variants: + - name: KEY + value: 206 + + - !AddFields + fieldset: SYSSTATUSCLR + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: SYSSTATUSCLR_KEY + + # SWDCFG: Add key + - !Add + ir: + enum/SWDCFG_KEY: + bit_size: 8 + variants: + - name: KEY + value: 98 + + - !AddFields + fieldset: SWDCFG + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: SWDCFG_KEY + + # FCCCMD: Add key + - !Add + ir: + enum/FCCCMD_KEY: + bit_size: 8 + variants: + - name: KEY + value: 14 + + - !AddFields + fieldset: FCCCMD + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: FCCCMD_KEY + + # L111x specific: LFXTCTL: Add key + - !Add + ir: + enum/LFXTCTL_KEY: + bit_size: 8 + variants: + - name: KEY + value: 165 + + - !AddFields + fieldset: LFXTCTL + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: LFXTCTL_KEY + + # L111x specific: EXLFCTL: Add key + - !Add + ir: + enum/EXLFCTL_KEY: + bit_size: 8 + variants: + - name: KEY + value: 165 + + - !AddFields + fieldset: EXLFCTL + fields: + - name: KEY + bit_offset: 24 + bit_size: 8 + enum: EXLFCTL_KEY + + # SHUTDNSTORE: Flatten + - !MergeFieldsets + from: SHUTDNSTORE(\d+) + to: SHUTDNSTORE + + - !MakeRegisterArray + blocks: SYSCTL + from: SHUTDNSTORE(\d+) + to: SHUTDNSTORE + + # SHUTDNSTORE: SVDs do not contain PARITY and PARITYERR fields + - !AddFields + fieldset: SHUTDNSTORE + fields: + - name: PARITY + bit_offset: 8 + bit_size: 1 + - name: PARITYERR + bit_offset: 9 + bit_size: 1 + + # MGMT registers are TI internal and don't exist in the datasheet. + # Do not include these. + - !DeleteEnumsUsedIn + fieldsets: MGMT_(.*) + + - !DeleteFieldsets + from: MGMT_(.*) + + - !DeleteRegisters + block: SYSCTL + from: MGMT_(.*) + + ## Cleanup + - !Sort diff --git a/transforms/VREF.yaml b/transforms/VREF.yaml new file mode 100644 index 0000000..b832b5f --- /dev/null +++ b/transforms/VREF.yaml @@ -0,0 +1,76 @@ +# Transform for VREF registers based on VREF on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # RESETASSERT is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: ASSERT + + # RESETSTKY is useless + - !DeleteEnumsWithVariants + variants: + 0: NORES + 1: RESET + + # RESETSTKYCLR is useless + - !DeleteEnumsWithVariants + variants: + 0: NOP + 1: CLR + + # Remove VREF_ prefixes + - !RenameRegisters + block: .* + from: VREF_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: VREF_(.+) + to: $1 + + - !Rename + type: All + from: VREF_(.+) + to: $1 + + ## Add missing keys + - !AddFields + fieldset: RSTCTL + fields: + - name: KEY + description: Unlock key B1h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: RESET_KEY + + - !AddFields + fieldset: PWREN + fields: + - name: KEY + description: KEY to allow Power State Change 26h = KEY to allow write access to this register + bit_offset: 24 + bit_size: 8 + enum: PWREN_KEY + + - !Add + ir: + enum/RESET_KEY: + bit_size: 8 + variants: + - name: KEY + value: 177 + enum/PWREN_KEY: + bit_size: 8 + variants: + - name: KEY + value: 38 + + ## Cleanup + - !Sort diff --git a/transforms/WUC.yaml b/transforms/WUC.yaml new file mode 100644 index 0000000..01e120f --- /dev/null +++ b/transforms/WUC.yaml @@ -0,0 +1,41 @@ +# Transform for WUC (Wake Up Controller) registers based on WUC on G350x +transforms: + - !DeleteUselessEnums + + - !DeleteFieldsets + from: .* + useless: true + + # Remove WUC_ prefixes + - !RenameRegisters + block: .* + from: WUC_(.+) + to: $1 + + - !RenameFields + fieldset: .* + from: WUC_(.+) + to: $1 + + - !Rename + type: All + from: WUC_(.+) + to: $1 + + ## Publisher/Subscriber ports + # CHANID is an int + - !DeleteEnums + from: .*CHANID + bit_size: 4 + + - !MergeFieldsets + from: FSUB_\d+ + to: FPORT + + - !MakeRegisterArray + blocks: .* + from: FSUB_(\d+) + to: FSUB + + ## Cleanup + - !Sort