-
Notifications
You must be signed in to change notification settings - Fork 3
/
envelope_generator.vhd
410 lines (390 loc) · 13.5 KB
/
envelope_generator.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:06:08 08/04/2014
-- Design Name:
-- Module Name: envelope_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity envelope_generator is port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
update: in std_logic;
update_ack: out std_logic;
keyOn: in std_logic;
attackRate: in unsigned(5 downto 0);
decayRate: in unsigned(5 downto 0);
sustainRate: in unsigned(5 downto 0);
sustainLevel: in unsigned(6 downto 0);
releaseRate: in unsigned(5 downto 0);
keyscale: in unsigned(1 downto 0);
blockNumber: unsigned(4 downto 0);
nxt: in std_logic;
eglevel: out unsigned(9 downto 0);
valid: out std_logic
); end envelope_generator;
architecture Behavioral of envelope_generator is
type ratetable_type is array(0 to 63) of signed(31 downto 0);
constant ratetable: ratetable_type := (
0 => to_signed(0,32), 1 => to_signed(0,32), 2 => to_signed(0,32), 3 => to_signed(0,32),
4 => to_signed(75552,32), 5 => to_signed(75552,32), 6 => to_signed(113328,32), 7 => to_signed(113328,32),
8 => to_signed(151104,32), 9 => to_signed(188880,32), 10 => to_signed(226656,32), 11 => to_signed(264432,32),
12 => to_signed(302208,32), 13 => to_signed(377760,32), 14 => to_signed(453312,32), 15 => to_signed(528864,32),
16 => to_signed(604416,32), 17 => to_signed(755520,32), 18 => to_signed(906624,32), 19 => to_signed(1057728,32),
20 => to_signed(1208832,32), 21 => to_signed(1511040,32), 22 => to_signed(1813248,32), 23 => to_signed(2115456,32),
24 => to_signed(2417664,32), 25 => to_signed(3022080,32), 26 => to_signed(3626496,32), 27 => to_signed(4230912,32),
28 => to_signed(4835328,32), 29 => to_signed(6044160,32), 30 => to_signed(7252992,32), 31 => to_signed(8461824,32),
32 => to_signed(9670656,32), 33 => to_signed(12088320,32), 34 => to_signed(14505984,32), 35 => to_signed(16923648,32),
36 => to_signed(19341312,32), 37 => to_signed(24176640,32), 38 => to_signed(29011968,32), 39 => to_signed(33847296,32),
40 => to_signed(38682624,32), 41 => to_signed(48353280,32), 42 => to_signed(58023936,32), 43 => to_signed(67694592,32),
44 => to_signed(77365248,32), 45 => to_signed(96706560,32), 46 => to_signed(116047872,32), 47 => to_signed(135389184,32),
48 => to_signed(77365248,32), 49 => to_signed(96706560,32), 50 => to_signed(116047872,32), 51 => to_signed(135389184,32),
52 => to_signed(77365248,32), 53 => to_signed(96706560,32), 54 => to_signed(116047872,32), 55 => to_signed(135389184,32),
56 => to_signed(77365248,32), 57 => to_signed(96706560,32), 58 => to_signed(116047872,32), 59 => to_signed(135389184,32),
60 => to_signed(154730496,32), 61 => to_signed(154730496,32), 62 => to_signed(154730496,32), 63 => to_signed(154730496,32)
);
-- increment by 3<<27
constant egstep_increment: signed(31 downto 0) := to_signed(402653184, 32);
type eg_state_type is (state_idle, state_prepare_rate, state_setegrate, state_shiftphase, state_prepare_ack,
state_envelope_check, state_envelope_checklevel_attack, state_envelope_checklevel_other,
state_envelope_done);
type adsr_state_type is (adsr_attack, adsr_decay, adsr_sustain, adsr_release, adsr_off);
type reg_type is record
state: eg_state_type;
adsr_state: adsr_state_type;
keyOff_req: std_logic;
keyOn_req: std_logic;
egstep: signed(31 downto 0);
update_req: std_logic;
update_ack: std_logic;
key: std_logic;
ksr: unsigned(4 downto 0);
egstepd: signed(31 downto 0);
egtransa: unsigned(3 downto 0);
egtransd: unsigned(3 downto 0);
egrate: unsigned(5 downto 0); -- intermediate for SetEGRate
setegrate_callback: eg_state_type; -- where to go after SetEGRate
shiftphase: adsr_state_type; -- desired "next phase" for ShiftPhase
shiftphase_callback: eg_state_type; -- where to go after ShiftPhase
eglevel: unsigned(9 downto 0);
eglvnext: unsigned(9 downto 0);
nxt_req: std_logic; -- latched high when nxt is strobed
valid: std_logic;
end record;
constant reg_reset: reg_type := (
state => state_idle,
adsr_state => adsr_off,
keyOff_req => '0',
keyOn_req => '0',
egstep => to_signed(0, 32),
update_req => '0',
update_ack => '0',
key => '0',
ksr => "00000",
egstepd => to_signed(0, 32),
egtransa => "0000",
egtransd => "0000",
egrate => "000000",
setegrate_callback => state_idle,
shiftphase => adsr_off,
shiftphase_callback => state_idle,
eglevel => "0011111111",
eglvnext => to_unsigned(0, 10),
nxt_req => '0',
valid => '0'
);
signal reg: reg_type := reg_reset;
signal ci_next: reg_type;
begin
COMB: process(reg, rst, update, nxt, keyOn,
attackRate, decayRate, sustainRate, sustainLevel, releaseRate, keyscale, blockNumber)
variable ci: reg_type;
variable egtransa: unsigned(5 downto 0);
variable egtransa_sized: unsigned(3 downto 0);
variable egtransd: unsigned(3 downto 0);
variable eglevel_attack_decrement: unsigned(9 downto 0);
begin
ci := reg;
-- self-clearing
ci.update_ack := '0';
ci.valid := '0';
-- always check these "asynchronously", i.e. while other processing is happening
if(reg.key = '1' and keyOn = '0') then
ci.key := '0';
ci.keyOff_req := '1';
end if;
if(reg.key = '0' and keyOn = '1') then
ci.key := '1';
ci.keyOn_req := '1';
end if;
if(reg.update_req = '0' and update = '1') then
ci.update_req := '1';
end if;
if(reg.nxt_req = '0' and nxt = '1') then
ci.nxt_req := '1';
end if;
-- egtransa = Limit(15 - r>>2, 4, 1)
egtransa := 15 - shift_right(reg.egrate, 2);
if(egtransa > 4) then
egtransa_sized := to_unsigned(4, 4);
elsif(egtransa < 1) then
egtransa_sized := to_unsigned(1, 4);
else
egtransa_sized := unsigned("0" & egtransa(2 downto 0));
end if;
-- egtransd = 16 >> egtransa
case egtransa_sized is
when "0001" =>
egtransd := "1000";
when "0010" =>
egtransd := "0100";
when "0011" =>
egtransd := "0010";
when "0100" =>
egtransd := "0001";
when others => -- shouldn't happen
egtransd := "0000";
end case;
eglevel_attack_decrement := (1 + shift_right(reg.eglevel, to_integer(reg.egtransa)));
if(rst = '1') then
ci := reg_reset;
else
case reg.state is
when state_idle =>
-- check for key-on/key-off first; key-off has priority
if(reg.keyOff_req = '1') then
ci.keyOff_req := '0';
-- Key Off
ci.shiftphase := adsr_release;
ci.state := state_shiftphase;
ci.shiftphase_callback := state_idle;
elsif(reg.keyOn_req = '1') then
ci.keyOn_req := '0';
-- Key On
if(reg.adsr_state = adsr_off or reg.adsr_state = adsr_release) then
ci.shiftphase := adsr_attack;
ci.state := state_shiftphase;
ci.shiftphase_callback := state_idle;
else
ci.state := state_envelope_check;
end if;
elsif(reg.update_req = '1') then
ci.update_req := '0';
-- calculate ksr (key-scale rate)
-- ksr = bn >> (3 - ks)
ci.ksr := shift_right(blockNumber, to_integer(keyscale));
ci.state := state_prepare_rate;
elsif(reg.nxt_req = '1') then
ci.nxt_req := '0';
-- decrement egstep
ci.egstep := reg.egstep - reg.egstepd;
ci.state := state_envelope_check;
end if;
when state_setegrate => -- "function call"
ci.egstepd := ratetable(to_integer(reg.egrate));
ci.egtransa := egtransa_sized;
ci.egtransd := egtransd;
ci.state := reg.setegrate_callback;
when state_shiftphase => -- "function call"
case reg.shiftphase is
when adsr_attack =>
if(attackRate + reg.ksr < to_unsigned(62, 7)) then
if(attackRate = "000000") then
ci.egrate := to_unsigned(0, 6);
else
ci.egrate := attackRate + reg.ksr;
end if;
ci.setegrate_callback := reg.shiftphase_callback;
ci.state := state_setegrate;
ci.adsr_state := adsr_attack;
else
ci.shiftphase := adsr_decay;
end if;
when adsr_decay =>
if(sustainLevel = "0000000") then
ci.shiftphase := adsr_sustain;
else
ci.eglevel := to_unsigned(0, 10);
ci.eglvnext := unsigned(sustainLevel & "000"); -- sl * 8
if(decayRate = "000000") then
ci.egrate := to_unsigned(0, 6);
elsif(decayRate + reg.ksr < to_unsigned(63, 7)) then
ci.egrate := decayRate + reg.ksr;
else
ci.egrate := to_unsigned(63, 6);
end if;
ci.setegrate_callback := reg.shiftphase_callback;
ci.state := state_setegrate;
ci.adsr_state := adsr_decay;
end if;
when adsr_sustain =>
ci.eglevel := unsigned(sustainLevel & "000"); -- sl * 8
ci.eglvnext := "0100000000";
if(sustainRate = "000000") then
ci.egrate := to_unsigned(0, 6);
elsif(sustainRate + reg.ksr < to_unsigned(63, 7)) then
ci.egrate := sustainRate + reg.ksr;
else
ci.egrate := to_unsigned(63, 6);
end if;
ci.setegrate_callback := reg.shiftphase_callback;
ci.state := state_setegrate;
ci.adsr_state := adsr_sustain;
when adsr_release =>
if(reg.adsr_state = adsr_attack or reg.eglevel < 256) then
ci.eglvnext := "0100000000";
if(releaseRate + reg.ksr < to_unsigned(63, 7)) then
ci.egrate := releaseRate + reg.ksr;
else
ci.egrate := to_unsigned(63, 6);
end if;
ci.setegrate_callback := reg.shiftphase_callback;
ci.state := state_setegrate;
ci.adsr_state := adsr_release;
else
ci.shiftphase := adsr_off;
end if;
when others =>
-- off
ci.eglevel := "0011111111";
ci.eglvnext := "0100000000";
-- SetEGRate(0)
ci.egrate := to_unsigned(0, 6);
ci.setegrate_callback := reg.shiftphase_callback;
ci.state := state_setegrate;
ci.adsr_state := adsr_off;
end case;
when state_envelope_check =>
if(reg.egstep > 0) then
-- stop here, do not change envelope
ci.valid := '1';
ci.state := state_idle;
else
ci.egstep := reg.egstep + egstep_increment;
if(reg.adsr_state = adsr_attack) then
-- decrement eglevel by (1 + eglevel >> egtransa) but do not let it become negative
if(eglevel_attack_decrement > reg.eglevel) then
ci.eglevel := to_unsigned(0, 10);
else
ci.eglevel := reg.eglevel - eglevel_attack_decrement;
end if;
ci.state := state_envelope_checklevel_attack;
else
-- increment eglevel by egtransd
ci.eglevel := reg.eglevel + reg.egtransd;
ci.state := state_envelope_checklevel_other;
end if;
end if;
when state_envelope_checklevel_attack =>
if(reg.eglevel <= 0) then
-- ShiftPhase to decay
ci.state := state_shiftphase;
ci.shiftphase := adsr_decay;
ci.shiftphase_callback := state_envelope_done;
else
-- done
ci.valid := '1';
ci.state := state_idle;
end if;
when state_envelope_checklevel_other =>
if(reg.eglevel >= reg.eglvnext) then
-- ShiftPhase to next phase
case reg.adsr_state is
when adsr_attack => ci.shiftphase := adsr_decay;
when adsr_decay => ci.shiftphase := adsr_sustain;
when adsr_sustain => ci.shiftphase := adsr_release;
when adsr_release => ci.shiftphase := adsr_off;
when others => -- should never happen...
ci.shiftphase := adsr_off;
end case;
ci.state := state_shiftphase;
ci.shiftphase_callback := state_envelope_done;
else
-- done
ci.valid := '1';
ci.state := state_idle;
end if;
when state_envelope_done =>
ci.valid := '1';
ci.state := state_idle;
when state_prepare_rate =>
case reg.adsr_state is
-- load egrate and "call" SetEGRate()
when adsr_attack =>
if(attackRate = "000000") then
ci.egrate := "000000";
elsif(attackRate + reg.ksr > to_unsigned(63, 7)) then
ci.egrate := "111111";
else
ci.egrate := attackRate + reg.ksr;
end if;
ci.setegrate_callback := state_prepare_ack;
ci.state := state_setegrate;
when adsr_decay =>
if(decayRate = "000000") then
ci.egrate := "000000";
elsif(decayRate + reg.ksr > to_unsigned(63, 7)) then
ci.egrate := "111111";
else
ci.egrate := decayRate + reg.ksr;
end if;
ci.setegrate_callback := state_prepare_ack;
ci.state := state_setegrate;
when adsr_sustain =>
if(sustainRate = "000000") then
ci.egrate := "000000";
elsif(sustainRate + reg.ksr > to_unsigned(63, 7)) then
ci.egrate := "111111";
else
ci.egrate := sustainRate + reg.ksr;
end if;
ci.setegrate_callback := state_prepare_ack;
ci.state := state_setegrate;
when adsr_release =>
if(releaseRate + reg.ksr > to_unsigned(63, 7)) then
ci.egrate := "111111";
else
ci.egrate := releaseRate + reg.ksr;
end if;
ci.setegrate_callback := state_prepare_ack;
ci.state := state_setegrate;
when others =>
ci.state := state_prepare_ack;
end case;
when state_prepare_ack =>
ci.update_ack := '1';
ci.state := state_idle;
when others => null;
end case;
end if;
ci_next <= ci;
end process COMB;
SEQ: process(clk, ci_next)
begin
if(rising_edge(clk)) then
reg <= ci_next;
end if;
end process SEQ;
-- outputs
update_ack <= reg.update_ack;
eglevel <= reg.eglevel;
valid <= reg.valid;
end Behavioral;