simplified.mem

# Example Memory File for Drachma

name: Simplified Memory Configuration

/#
  this is where you would put defining parameters
  to describe traits of a memory configuration. a
  memory configuration denotes the hierarchy of
  memory devices that are accessible by the ICAP.
  if the ICAP needs to locate a bitstream it will
  attempt to do so first in the lowest memory
  level; if cache is present, this will always
  be L1 first.

  all paramters are of the following format:
    <param name>: <param value>

  the following are acceptable definitions.
  descriptions with a double astrisk** are always required.
  descriptions with an asterisk* are required under certain circumstance
    
    name: "name of the memory configuration"**

    main name: "main memory name"
    main size: "main memory size (in kB)"**
    main read latency: "main memory read cost (in clock cycles)"**
    main search latency: "main memory search cost (in clock cycles)"**

    l1 name: "lowest cache level name"
    l1 size: "lowest cache level size (in kB)"*
      level's supported up to l9
      > required if declaring a cache level
    l1 read latency: "lowest cache level read cost (in clock cycles)"*
      > required if declaring a cache level
    l1 search latency: "lowest cache level search cost (in clock cycles)"*
      > required if declaring a cache level
#/

main name: QSPI Serial NOR Flash Memory (Spansion S25FL256S)
/#
  actually, SPI/BPI (Byte Peripheral Interface) Flash memory
  see UG909, p.116
  "SPI and BPI flash can be used to store partial bitstreams, ..."

  how to store in DRR? https://forums.xilinx.com/t5/FPGA-Configuration/How-to-store-the-bitstreams-into-the-DDR/td-p/810218

  e.g. Spansion S25FL256S for the ZedBoard
#/
main size: 256000

# TODO: Get rid of these.
main read latency: 8
main search latency: 32

# TODO: Switch to this:
# main read speed: 104.00