README.md

Verilog AST (VAST)

VAST is a Rust library for building and manipulating Verilog ASTs. The goal is to support features from two different versions of the standard 2005 and 2017, v05 and v17 respectively. The subset directory contains types that are common between the two.

Using VAST

Add vast to your Cargo.toml like this:

[dependencies]
vast = "0.3.0"

Creating a module in Verilog-2005

use vast::v05::ast::Module;

fn main() {
    let mut module = Module::new("foo");
    module.add_input("a", 32);
    let res = module.to_string();
    let exp = r#"module foo (
    input wire [31:0] a
);
endmodule
"#;
    assert_eq!(res, exp);
}

Creating a module in SystemVerilog-2017

use vast::v17::ast::Module;

fn main() {
    let mut module = Module::new("foo");
    module.add_input("a", 32);
    let res = module.to_string();
    let exp = r#"module foo (
    input logic [31:0] a
);
endmodule
"#;
    assert_eq!(res, exp);
}