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As you know I am trying to port multicomp6809 to the Altera DE1. I wanted to see if the MMU and my sRAM wiring logic was working properly after my changes and found the code in camelforth/mmu_test.txt. Unfortunately when I run this everything works until:
789A FDFF ! \ write to RAM block 6
After this CamelForth seems to blow up, not recognizing any words after this. So I can't tell if the MMU or sRAM wiring correct or not because I can't do any further debugging after this.
If I do different tests which don't do any manipulation to the ROM area then it seems the MMU is working and addressing ram correctly:
HEX
MMUMAP
: W8 40 8 DO 24 FFDE ! I FFDF C! I 8000 C! LOOP ;
: R8 40 8 DO 24 FFDE ! I FFDF C! 8000 C@ . LOOP ;
: RA 40 8 DO 25 FFDE ! I FFDF C! A000 C@ . LOOP ;
Running those I see 0x08 through 0x3F and no repeats, so I'm assuming the MMU and RAM Mapping logic are working? Any additional hints?
The text was updated successfully, but these errors were encountered:
The particular test sequence you refer to as failing is part of the test for the "Fixed RAM Top" (FRT) functionality. Refer to the .vhd header for a detailed description, but this basically cuts a 256 byte hole at the very top of memory and maps it permanently to the top of block 7.
It seems strange that it would fail for the block6 write but be OK for the block7 write. Please will you confirm if your wiring fixup solved this problem?
thanks,
Neal.
As you know I am trying to port multicomp6809 to the Altera DE1. I wanted to see if the MMU and my sRAM wiring logic was working properly after my changes and found the code in camelforth/mmu_test.txt. Unfortunately when I run this everything works until:
After this CamelForth seems to blow up, not recognizing any words after this. So I can't tell if the MMU or sRAM wiring correct or not because I can't do any further debugging after this.
If I do different tests which don't do any manipulation to the ROM area then it seems the MMU is working and addressing ram correctly:
Running those I see 0x08 through 0x3F and no repeats, so I'm assuming the MMU and RAM Mapping logic are working? Any additional hints?
The text was updated successfully, but these errors were encountered: