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Diff for: ‎ALU.v

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`include "Adder.v"
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`include "Mux.v"
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`include "Gates.v"
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module ALU(in1, in2, Binvert, Cin, Operation, Result, Carry);
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input [31:0] in1, in2;
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input [1:0] Operation;
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input Binvert, Cin;
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output [31:0] Result;
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output Carry;
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wire [31:0] not_in2, mux_out, and_out, or_out, sum;
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wire newc;
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mux2to1 m1(newc, Operation[1], Cin, 1'b1);
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bit32Not n1(not_in2, in2);
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bit32_2to1mux b0(mux_out, Binvert, in2, not_in2);
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thirtytwoBitFullAdder fa(sum, Carry, in1, mux_out, newc);
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bit32And a1(and_out, in1, mux_out);
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bit32Or o1(or_out, in1, mux_out);
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bit32_3to1mux b1(Result, Operation, and_out, or_out, sum);
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endmodule

Diff for: ‎ALUController.v

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module ALUControlUnit (Operation, FuncField, ALUOp);
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input [5:0] FuncField;
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input [1:0] ALUOp;
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output [2:0] Operation;
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wire and_out, or_out;
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and a1(and_out, ALUOp[1], FuncField[1]);
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or o1(Operation[2], ALUOp[0], and_out);
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or o2(or_out, FuncField[0], FuncField[3]);
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and a2(Operation[0], ALUOp[1], or_out);
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nand(Operation[1], ALUOp[1], FuncField[2]);
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endmodule

Diff for: ‎Adder.v

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module halfAdder(sum,carry,in1,in2);
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input in1, in2;
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output sum, carry;
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xor x1(sum, in1, in2);
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and a1(carry, in1, in2);
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endmodule
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/*module testbench1;
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reg i1, i2;
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wire s, c;
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halfAdder ha1(s, c, i1, i2);
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initial
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begin
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$monitor($time, " input1 = %b, input2 = %b, Sum = %b, Carry = %b", i1, i2, s, c);
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#2 i1 = 1'b 0; i2 = 1'b 0;
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#2 i1 = 1'b 0; i2 = 1'b 1;
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#2 i1 = 1'b 1; i2 = 1'b 0;
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#2 i1 = 1'b 1; i2 = 1'b 1;
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end
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endmodule */
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module oneBitFullAdder(sum, carry, in1, in2, cin);
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input in1, in2, cin;
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output sum, carry;
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wire s1, c1, c2;
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halfAdder ha1(s1, c1, in1, in2);
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halfAdder ha2(sum, c2, s1, cin);
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or o1(carry, c1, c2);
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endmodule
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/*module testbench2;
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reg in1, in2, cin;
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wire sum, carry;
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oneBitFullAdder fa1(sum, carry, in1, in2, cin);
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initial
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begin
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$monitor($time, " input1 = %b, input2 = %b, carryIn = %b, sum = %b, carry = %b", in1, in2, cin, sum, carry);
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#2 in1 = 1'b 0; in2 = 1'b 0; cin = 1'b 0;
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#2 in1 = 1'b 0; in2 = 1'b 1; cin = 1'b 0;
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#2 in1 = 1'b 1; in2 = 1'b 0; cin = 1'b 0;
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#2 in1 = 1'b 1; in2 = 1'b 1; cin = 1'b 0;
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#2 in1 = 1'b 0; in2 = 1'b 0; cin = 1'b 1;
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#2 in1 = 1'b 0; in2 = 1'b 1; cin = 1'b 1;
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#2 in1 = 1'b 1; in2 = 1'b 0; cin = 1'b 1;
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#2 in1 = 1'b 1; in2 = 1'b 1; cin = 1'b 1;
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end
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endmodule */
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module fourBitFullAdder(sum, carry, in1, in2, cin);
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input [3:0] in1, in2;
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input cin;
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output [3:0] sum;
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output carry;
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wire c0, c1, c2;
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oneBitFullAdder obfa1(sum[0], c0, in1[0], in2[0], cin);
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oneBitFullAdder obfa2(sum[1], c1, in1[1], in2[1], c0);
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oneBitFullAdder obfa3(sum[2], c2, in1[2], in2[2], c1);
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oneBitFullAdder obfa4(sum[3], carry, in1[3], in2[3], c2);
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endmodule
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/*module testbench3;
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reg [3:0] in1, in2;
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reg cin;
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wire [3:0] sum;
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wire carry;
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fourBitFullAdder fbfa1(sum, carry, in1, in2, cin);
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initial
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begin
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$monitor($time, " input1 = %b, input2 = %b, carryIn = %b, sum = %b, carry = %b", in1, in2, cin, sum, carry);
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#2 in1 = 4'b 0000; in2 = 4'b 0000; cin = 1'b 0;
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#2 in1 = 4'b 0010; in2 = 4'b 0100; cin = 1'b 1;
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#2 in1 = 4'b 0000; in2 = 4'b 1111; cin = 1'b 0;
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#2 in1 = 4'b 1111; in2 = 4'b 0001; cin = 1'b 1;
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end
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endmodule */
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module eightBitFullAdder(sum, carry, in1, in2, cin);
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input [7:0] in1, in2;
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input cin;
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output [7:0] sum;
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output carry;
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wire caux;
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fourBitFullAdder fbfa1(sum[3:0], caux, in1[3:0], in2[3:0], cin);
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fourBitFullAdder fbfa2(sum[7:4], carry, in1[7:4], in2[7:4], caux);
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endmodule
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/*module testbench4;
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reg [7:0] in1, in2;
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reg cin;
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wire [7:0] sum;
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wire carry;
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eightBitFullAdder ebfa1(sum, carry, in1, in2, cin);
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initial
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begin
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$monitor($time, " input1 = %b, input2 = %b, carryIn = %b, sum = %b, carry = %b", in1, in2, cin, sum, carry);
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#2 in1 = 8'b 00000000; in2 = 8'b 00000000; cin = 1'b 0;
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#2 in1 = 8'b 10101010; in2 = 8'b 01010101; cin = 1'b 1;
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#2 in1 = 8'b 11111111; in2 = 8'b 00000000; cin = 1'b 1;
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#2 in1 = 8'b 11111111; in2 = 8'b 11111111; cin = 1'b 1;
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end
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endmodule */
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module thirtytwoBitFullAdder(sum, carry, in1, in2, cin);
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input [31:0] in1, in2;
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input cin;
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output [31:0] sum;
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output carry;
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wire caux1, caux2, caux3;
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eightBitFullAdder ebfa1(sum[7:0], caux1, in1[7:0], in2[7:0], cin);
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eightBitFullAdder ebfa2(sum[15:8], caux2, in1[15:8], in2[15:8], caux1);
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eightBitFullAdder ebfa3(sum[23:16], caux3, in1[23:16], in2[23:16], caux2);
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eightBitFullAdder ebfa4(sum[31:24], carry, in1[31:24], in2[31:24], caux3);
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endmodule

Diff for: ‎Gates.v

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module bit32And (out, in1, in2);
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input [31:0] in1, in2;
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output [31:0] out;
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assign {out} = in1 & in2;
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endmodule
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module bit32Or (out, in1, in2);
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input [31:0] in1, in2;
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output [31:0] out;
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assign {out} = in1 | in2;
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endmodule

Diff for: ‎MainController.v

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module MainControlUnit (RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUOp, Op);
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input [5:0] Op;
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output RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch;
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output [1:0] ALUOp;
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wire Rformat, lw, sw, beq;
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assign Rformat = (~Op[0]) & (~Op[1]) & (~Op[2]) & (~Op[3]) & (~Op[4]) & (~Op[5]);
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assign lw = (Op[0]) & (Op[1]) & (~Op[2]) & (~Op[3]) & (~Op[4]) & (Op[5]);
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assign sw = (Op[0]) & (Op[1]) & (~Op[2]) & (Op[3]) & (~Op[4]) & (Op[5]);
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assign beq = (~Op[0]) & (~Op[1]) & (Op[2]) & (~Op[3]) & (~Op[4]) & (~Op[5]);
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assign RegDst = Rformat;
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assign ALUSrc = lw | sw;
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assign MemtoReg = lw;
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assign RegWrite = Rformat | lw;
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assign MemRead = lw;
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assign MemWrite = sw;
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assign Branch = beq;
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assign ALUOp[0] = Rformat;
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assign ALUOp[1] = beq;
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endmodule

Diff for: ‎Mux.v

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module mux2to1(out, select, in1, in2);
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input in1, in2, select;
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output out;
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wire not_select, w1, w2;
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not (not_select, select);
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and (w1, select, in2);
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and (w2, not_select, in1);
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or(out, w1, w2);
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endmodule
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module mux3to1(out, select, in1, in2, in3);
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input in1, in2, in3;
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input [1:0] select;
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output out;
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wire w;
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mux2to1 m1(w, select[0], in1, in2); //in1 - 00; in2 - 01; in3 - 1x
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mux2to1 m2(out, select[1], w, in3);
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endmodule
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module bit32_3to1mux (out, select, in1, in2, in3);
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input [31:0] in1, in2, in3;
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input [1:0] select;
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output [31:0] out;
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genvar j;
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generate
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for(j = 0; j <32; j = j + 1) begin: mux_loop
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mux3to1 m1(out[j], select, in1[j], in2[j], in3[j]);
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end
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endgenerate
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endmodule

Diff for: ‎Reg32.v

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module dff_async_clear(q, d, clk, reset);
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input d, reset, clk;
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output q;
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reg q;
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always @ (negedge reset or posedge clk)
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begin
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if (!reset) q <= 1'b0;
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else q <= d;
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end
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endmodule
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module reg_32bit(q, d, clk, reset);
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input [31:0] d;
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input reset, clk;
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output [31:0] q;
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genvar j;
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generate for (j = 0; j < 32; j = j + 1) begin: reg_loop
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dff_async_clear d(q[j], d[j], clk, reset);
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end
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endgenerate
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endmodule

Diff for: ‎RegFile.v

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module RegFile(clk, reset, ReadReg1, ReadReg2, WriteData, WriteReg, RegWrite, ReadData1, ReadData2);
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input clk, reset, RegWrite;
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input [31:0] WriteData;
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input [1:0] WriteReg, ReadReg1, ReadReg2;
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output [31:0] ReadData1, ReadData2;
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wire [3:0] decw;
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wire [3:0] andout;
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wire [31:0] q0, q1, q2, q3;
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genvar j;
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bit1_2to4decoder dec(decw, WriteReg[0], WriteReg[1]);
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generate
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for (j = 0; j < 4; j = j + 1) begin: reg_loop
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bit1_3to1and a1(andout[j], clk, RegWrite, decw[j]);
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end
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endgenerate
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reg_32bit reg1(q0, WriteData, andout[0], reset);
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reg_32bit reg2(q1, WriteData, andout[1], reset);
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reg_32bit reg3(q2, WriteData, andout[2], reset);
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reg_32bit reg4(q3, WriteData, andout[3], reset);
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bit32_4to1mux mux1(ReadData1, ReadReg1, q0, q1, q2, q3);
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bit32_4to1mux mux2(ReadData2, ReadReg2, q0, q1, q2, q3);
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endmodule

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