|
| 1 | +<?xml version="1.0" encoding="UTF-8"?> |
| 2 | +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> |
| 3 | + <spirit:vendor>ustcpetergu.com</spirit:vendor> |
| 4 | + <spirit:library>user</spirit:library> |
| 5 | + <spirit:name>alu</spirit:name> |
| 6 | + <spirit:version>1.0</spirit:version> |
| 7 | + <spirit:model> |
| 8 | + <spirit:views> |
| 9 | + <spirit:view> |
| 10 | + <spirit:name>xilinx_anylanguagesynthesis</spirit:name> |
| 11 | + <spirit:displayName>Synthesis</spirit:displayName> |
| 12 | + <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier> |
| 13 | + <spirit:language>Verilog</spirit:language> |
| 14 | + <spirit:modelName>alu</spirit:modelName> |
| 15 | + <spirit:fileSetRef> |
| 16 | + <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName> |
| 17 | + </spirit:fileSetRef> |
| 18 | + <spirit:parameters> |
| 19 | + <spirit:parameter> |
| 20 | + <spirit:name>viewChecksum</spirit:name> |
| 21 | + <spirit:value>7bf5aeae</spirit:value> |
| 22 | + </spirit:parameter> |
| 23 | + </spirit:parameters> |
| 24 | + </spirit:view> |
| 25 | + <spirit:view> |
| 26 | + <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name> |
| 27 | + <spirit:displayName>Simulation</spirit:displayName> |
| 28 | + <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier> |
| 29 | + <spirit:language>Verilog</spirit:language> |
| 30 | + <spirit:modelName>alu</spirit:modelName> |
| 31 | + <spirit:fileSetRef> |
| 32 | + <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName> |
| 33 | + </spirit:fileSetRef> |
| 34 | + <spirit:parameters> |
| 35 | + <spirit:parameter> |
| 36 | + <spirit:name>viewChecksum</spirit:name> |
| 37 | + <spirit:value>7bf5aeae</spirit:value> |
| 38 | + </spirit:parameter> |
| 39 | + </spirit:parameters> |
| 40 | + </spirit:view> |
| 41 | + <spirit:view> |
| 42 | + <spirit:name>xilinx_testbench</spirit:name> |
| 43 | + <spirit:displayName>Test Bench</spirit:displayName> |
| 44 | + <spirit:envIdentifier>:vivado.xilinx.com:simulation.testbench</spirit:envIdentifier> |
| 45 | + <spirit:modelName>sort_simu</spirit:modelName> |
| 46 | + <spirit:fileSetRef> |
| 47 | + <spirit:localName>xilinx_testbench_view_fileset</spirit:localName> |
| 48 | + </spirit:fileSetRef> |
| 49 | + <spirit:parameters> |
| 50 | + <spirit:parameter> |
| 51 | + <spirit:name>viewChecksum</spirit:name> |
| 52 | + <spirit:value>079ef021</spirit:value> |
| 53 | + </spirit:parameter> |
| 54 | + </spirit:parameters> |
| 55 | + </spirit:view> |
| 56 | + <spirit:view> |
| 57 | + <spirit:name>xilinx_xpgui</spirit:name> |
| 58 | + <spirit:displayName>UI Layout</spirit:displayName> |
| 59 | + <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier> |
| 60 | + <spirit:fileSetRef> |
| 61 | + <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName> |
| 62 | + </spirit:fileSetRef> |
| 63 | + <spirit:parameters> |
| 64 | + <spirit:parameter> |
| 65 | + <spirit:name>viewChecksum</spirit:name> |
| 66 | + <spirit:value>b030f5a2</spirit:value> |
| 67 | + </spirit:parameter> |
| 68 | + </spirit:parameters> |
| 69 | + </spirit:view> |
| 70 | + </spirit:views> |
| 71 | + <spirit:ports> |
| 72 | + <spirit:port> |
| 73 | + <spirit:name>m</spirit:name> |
| 74 | + <spirit:wire> |
| 75 | + <spirit:direction>in</spirit:direction> |
| 76 | + <spirit:vector> |
| 77 | + <spirit:left spirit:format="long">2</spirit:left> |
| 78 | + <spirit:right spirit:format="long">0</spirit:right> |
| 79 | + </spirit:vector> |
| 80 | + <spirit:wireTypeDefs> |
| 81 | + <spirit:wireTypeDef> |
| 82 | + <spirit:typeName>std_logic_vector</spirit:typeName> |
| 83 | + <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef> |
| 84 | + <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef> |
| 85 | + </spirit:wireTypeDef> |
| 86 | + </spirit:wireTypeDefs> |
| 87 | + </spirit:wire> |
| 88 | + </spirit:port> |
| 89 | + <spirit:port> |
| 90 | + <spirit:name>a</spirit:name> |
| 91 | + <spirit:wire> |
| 92 | + <spirit:direction>in</spirit:direction> |
| 93 | + <spirit:vector> |
| 94 | + <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.WIDTH')) - 1)">31</spirit:left> |
| 95 | + <spirit:right spirit:format="long">0</spirit:right> |
| 96 | + </spirit:vector> |
| 97 | + <spirit:wireTypeDefs> |
| 98 | + <spirit:wireTypeDef> |
| 99 | + <spirit:typeName>std_logic_vector</spirit:typeName> |
| 100 | + <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef> |
| 101 | + <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef> |
| 102 | + </spirit:wireTypeDef> |
| 103 | + </spirit:wireTypeDefs> |
| 104 | + </spirit:wire> |
| 105 | + </spirit:port> |
| 106 | + <spirit:port> |
| 107 | + <spirit:name>b</spirit:name> |
| 108 | + <spirit:wire> |
| 109 | + <spirit:direction>in</spirit:direction> |
| 110 | + <spirit:vector> |
| 111 | + <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.WIDTH')) - 1)">31</spirit:left> |
| 112 | + <spirit:right spirit:format="long">0</spirit:right> |
| 113 | + </spirit:vector> |
| 114 | + <spirit:wireTypeDefs> |
| 115 | + <spirit:wireTypeDef> |
| 116 | + <spirit:typeName>std_logic_vector</spirit:typeName> |
| 117 | + <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef> |
| 118 | + <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef> |
| 119 | + </spirit:wireTypeDef> |
| 120 | + </spirit:wireTypeDefs> |
| 121 | + </spirit:wire> |
| 122 | + </spirit:port> |
| 123 | + <spirit:port> |
| 124 | + <spirit:name>y</spirit:name> |
| 125 | + <spirit:wire> |
| 126 | + <spirit:direction>out</spirit:direction> |
| 127 | + <spirit:vector> |
| 128 | + <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.WIDTH')) - 1)">31</spirit:left> |
| 129 | + <spirit:right spirit:format="long">0</spirit:right> |
| 130 | + </spirit:vector> |
| 131 | + <spirit:wireTypeDefs> |
| 132 | + <spirit:wireTypeDef> |
| 133 | + <spirit:typeName>std_logic_vector</spirit:typeName> |
| 134 | + <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef> |
| 135 | + <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef> |
| 136 | + </spirit:wireTypeDef> |
| 137 | + </spirit:wireTypeDefs> |
| 138 | + </spirit:wire> |
| 139 | + </spirit:port> |
| 140 | + <spirit:port> |
| 141 | + <spirit:name>zf</spirit:name> |
| 142 | + <spirit:wire> |
| 143 | + <spirit:direction>out</spirit:direction> |
| 144 | + <spirit:wireTypeDefs> |
| 145 | + <spirit:wireTypeDef> |
| 146 | + <spirit:typeName>std_logic</spirit:typeName> |
| 147 | + <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef> |
| 148 | + <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef> |
| 149 | + </spirit:wireTypeDef> |
| 150 | + </spirit:wireTypeDefs> |
| 151 | + </spirit:wire> |
| 152 | + </spirit:port> |
| 153 | + <spirit:port> |
| 154 | + <spirit:name>cf</spirit:name> |
| 155 | + <spirit:wire> |
| 156 | + <spirit:direction>out</spirit:direction> |
| 157 | + <spirit:wireTypeDefs> |
| 158 | + <spirit:wireTypeDef> |
| 159 | + <spirit:typeName>std_logic</spirit:typeName> |
| 160 | + <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef> |
| 161 | + <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef> |
| 162 | + </spirit:wireTypeDef> |
| 163 | + </spirit:wireTypeDefs> |
| 164 | + </spirit:wire> |
| 165 | + </spirit:port> |
| 166 | + <spirit:port> |
| 167 | + <spirit:name>of</spirit:name> |
| 168 | + <spirit:wire> |
| 169 | + <spirit:direction>out</spirit:direction> |
| 170 | + <spirit:wireTypeDefs> |
| 171 | + <spirit:wireTypeDef> |
| 172 | + <spirit:typeName>std_logic</spirit:typeName> |
| 173 | + <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef> |
| 174 | + <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef> |
| 175 | + </spirit:wireTypeDef> |
| 176 | + </spirit:wireTypeDefs> |
| 177 | + </spirit:wire> |
| 178 | + </spirit:port> |
| 179 | + </spirit:ports> |
| 180 | + <spirit:modelParameters> |
| 181 | + <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer"> |
| 182 | + <spirit:name>WIDTH</spirit:name> |
| 183 | + <spirit:displayName>Width</spirit:displayName> |
| 184 | + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WIDTH">32</spirit:value> |
| 185 | + </spirit:modelParameter> |
| 186 | + </spirit:modelParameters> |
| 187 | + </spirit:model> |
| 188 | + <spirit:fileSets> |
| 189 | + <spirit:fileSet> |
| 190 | + <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name> |
| 191 | + <spirit:file> |
| 192 | + <spirit:name>src/alu.v</spirit:name> |
| 193 | + <spirit:fileType>verilogSource</spirit:fileType> |
| 194 | + <spirit:userFileType>CHECKSUM_7bf5aeae</spirit:userFileType> |
| 195 | + <spirit:userFileType>IMPORTED_FILE</spirit:userFileType> |
| 196 | + </spirit:file> |
| 197 | + </spirit:fileSet> |
| 198 | + <spirit:fileSet> |
| 199 | + <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name> |
| 200 | + <spirit:file> |
| 201 | + <spirit:name>src/alu.v</spirit:name> |
| 202 | + <spirit:fileType>verilogSource</spirit:fileType> |
| 203 | + <spirit:userFileType>IMPORTED_FILE</spirit:userFileType> |
| 204 | + </spirit:file> |
| 205 | + </spirit:fileSet> |
| 206 | + <spirit:fileSet> |
| 207 | + <spirit:name>xilinx_testbench_view_fileset</spirit:name> |
| 208 | + <spirit:file> |
| 209 | + <spirit:name>src/sort_simu.v</spirit:name> |
| 210 | + <spirit:fileType>verilogSource</spirit:fileType> |
| 211 | + <spirit:userFileType>IMPORTED_FILE</spirit:userFileType> |
| 212 | + <spirit:userFileType>USED_IN_implementation</spirit:userFileType> |
| 213 | + <spirit:userFileType>USED_IN_simulation</spirit:userFileType> |
| 214 | + <spirit:userFileType>USED_IN_synthesis</spirit:userFileType> |
| 215 | + </spirit:file> |
| 216 | + </spirit:fileSet> |
| 217 | + <spirit:fileSet> |
| 218 | + <spirit:name>xilinx_xpgui_view_fileset</spirit:name> |
| 219 | + <spirit:file> |
| 220 | + <spirit:name>xgui/alu_v1_0.tcl</spirit:name> |
| 221 | + <spirit:fileType>tclSource</spirit:fileType> |
| 222 | + <spirit:userFileType>CHECKSUM_b030f5a2</spirit:userFileType> |
| 223 | + <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType> |
| 224 | + </spirit:file> |
| 225 | + </spirit:fileSet> |
| 226 | + </spirit:fileSets> |
| 227 | + <spirit:description>alu_v1_0</spirit:description> |
| 228 | + <spirit:parameters> |
| 229 | + <spirit:parameter> |
| 230 | + <spirit:name>WIDTH</spirit:name> |
| 231 | + <spirit:displayName>Width</spirit:displayName> |
| 232 | + <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WIDTH">32</spirit:value> |
| 233 | + </spirit:parameter> |
| 234 | + <spirit:parameter> |
| 235 | + <spirit:name>Component_Name</spirit:name> |
| 236 | + <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">alu_v1_0</spirit:value> |
| 237 | + </spirit:parameter> |
| 238 | + </spirit:parameters> |
| 239 | + <spirit:vendorExtensions> |
| 240 | + <xilinx:coreExtensions> |
| 241 | + <xilinx:supportedFamilies> |
| 242 | + <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family> |
| 243 | + <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family> |
| 244 | + <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family> |
| 245 | + <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family> |
| 246 | + <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family> |
| 247 | + </xilinx:supportedFamilies> |
| 248 | + <xilinx:taxonomies> |
| 249 | + <xilinx:taxonomy>/UserIP</xilinx:taxonomy> |
| 250 | + </xilinx:taxonomies> |
| 251 | + <xilinx:displayName>alu_v1_0</xilinx:displayName> |
| 252 | + <xilinx:definitionSource>package_project</xilinx:definitionSource> |
| 253 | + <xilinx:coreRevision>1</xilinx:coreRevision> |
| 254 | + <xilinx:upgrades> |
| 255 | + <xilinx:canUpgradeFrom>user.org:user:alu:1.0</xilinx:canUpgradeFrom> |
| 256 | + </xilinx:upgrades> |
| 257 | + <xilinx:coreCreationDateTime>2020-05-06T13:03:33Z</xilinx:coreCreationDateTime> |
| 258 | + <xilinx:tags> |
| 259 | + <xilinx:tag xilinx:name="ui.data.coregen.dd@35733fc2_ARCHIVE_LOCATION">/home/petergu/MyHome/COD/ip</xilinx:tag> |
| 260 | + <xilinx:tag xilinx:name="ui.data.coregen.dd@699b901e_ARCHIVE_LOCATION">/home/petergu/MyHome/COD/ip</xilinx:tag> |
| 261 | + <xilinx:tag xilinx:name="ui.data.coregen.dd@d1e0736_ARCHIVE_LOCATION">/home/petergu/MyHome/COD/ip</xilinx:tag> |
| 262 | + <xilinx:tag xilinx:name="ui.data.coregen.dd@701722a9_ARCHIVE_LOCATION">/home/petergu/MyHome/COD/ip</xilinx:tag> |
| 263 | + <xilinx:tag xilinx:name="ui.data.coregen.dd@7b42f9b0_ARCHIVE_LOCATION">/home/petergu/MyHome/COD/ip</xilinx:tag> |
| 264 | + <xilinx:tag xilinx:name="ui.data.coregen.dd@1788dc30_ARCHIVE_LOCATION">/home/petergu/MyHome/COD/ip</xilinx:tag> |
| 265 | + <xilinx:tag xilinx:name="ui.data.coregen.dd@281ccfa0_ARCHIVE_LOCATION">/home/petergu/MyHome/COD/ip</xilinx:tag> |
| 266 | + </xilinx:tags> |
| 267 | + </xilinx:coreExtensions> |
| 268 | + <xilinx:packagingInfo> |
| 269 | + <xilinx:xilinxVersion>2019.1</xilinx:xilinxVersion> |
| 270 | + <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bf9b2c8e"/> |
| 271 | + <xilinx:checksum xilinx:scope="ports" xilinx:value="c400300f"/> |
| 272 | + <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="6d1236b8"/> |
| 273 | + <xilinx:checksum xilinx:scope="parameters" xilinx:value="f46a4aa8"/> |
| 274 | + </xilinx:packagingInfo> |
| 275 | + </spirit:vendorExtensions> |
| 276 | +</spirit:component> |
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