{"payload":{"header_redesign_enabled":false,"results":[{"id":"548625064","archived":false,"color":"#adb2cb","followers":0,"has_funding_file":false,"hl_name":"nhasbun/lse_fiuba_clp","hl_trunc_description":"Trabajo Práctico Final - Circuitos Lógicos Programables - CESE - FIUBA","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":548625064,"name":"lse_fiuba_clp","owner_id":9024967,"owner_login":"nhasbun","updated_at":"2022-10-15T13:42:26.015Z","has_issues":true}},"sponsorable":false,"topics":["fpga","vhdl","rtl","cyclone","verilog","hdmi","vga","quartus","vga-controller","adv7513"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":49,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Anhasbun%252Flse_fiuba_clp%2B%2Blanguage%253AVHDL","metadata":null,"csrf_tokens":{"/nhasbun/lse_fiuba_clp/star":{"post":"xBSHVDZBe3YFF1hYBJyR8kvTFO8Twv47f1mUhwDGYCNZ0vQY2jX3Q9KNWH6jtkMfaCgCz_0oiBLSbQ7evYblfw"},"/nhasbun/lse_fiuba_clp/unstar":{"post":"ROhFANIxpAEnVtC708l-4M2t8Sw0jOcPPeToORIHlOngOa5Fum1hVAm_RHUgyL91MA4CWK1s13JwIIybjU1eFg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"q0tr1GDNFZad-cym8PPp1f56taCXX2CO2y7THJUOq2Vfeqolz9S4EkYbeIFMMqPCqq1uu_zOXulU71TOULYxWg"}}},"title":"Repository search results"}