From c16d2aec2d02807a27870b92df477e38dcb7ef2a Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Sat, 2 Nov 2024 21:55:39 +0000 Subject: [PATCH] PSL assertions should not be postponed --- src/rt/model.c | 2 +- test/regress/psl13.vhd | 2 +- test/regress/psl2.vhd | 3 +-- test/regress/psl3.vhd | 2 +- test/regress/psl5.vhd | 2 +- test/regress/psl6.vhd | 2 +- 6 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/rt/model.c b/src/rt/model.c index d373c8a46..ddab056ff 100644 --- a/src/rt/model.c +++ b/src/rt/model.c @@ -535,7 +535,7 @@ static void scope_for_block(rt_model_t *m, tree_t block, rt_scope_t *parent) p->wakeable.kind = W_PROPERTY; p->wakeable.pending = false; - p->wakeable.postponed = true; + p->wakeable.postponed = false; p->wakeable.delayed = false; APUSH(s->properties, p); diff --git a/test/regress/psl13.vhd b/test/regress/psl13.vhd index cd0a03121..db8eba940 100644 --- a/test/regress/psl13.vhd +++ b/test/regress/psl13.vhd @@ -20,7 +20,7 @@ begin cgen: c <= seq_c(clk); dgen: d <= seq_d(clk); - -- psl default clock is clk'event; + -- psl default clock is clk'delayed(0 ns)'event; -- Should fail at: 3 ns and 7 ns -- psl asrt_1 : assert always {a;b} |=> {c;d}; diff --git a/test/regress/psl2.vhd b/test/regress/psl2.vhd index 8cd2592dc..c7a53f5ea 100644 --- a/test/regress/psl2.vhd +++ b/test/regress/psl2.vhd @@ -18,8 +18,7 @@ architecture psl of psl2 is signal clk : natural; -- All is sensitive to rising edge of clk - -- psl default clock is clk'event; - + -- psl default clock is clk'delayed(0 ns)'event; begin clkgen: clk <= clk + 1 after 1 ns when clk < 5; diff --git a/test/regress/psl3.vhd b/test/regress/psl3.vhd index aefa03e29..c616107f8 100644 --- a/test/regress/psl3.vhd +++ b/test/regress/psl3.vhd @@ -22,7 +22,7 @@ architecture psl of psl3 is signal clk : natural; -- All is sensitive to rising edge of clk - default clock is clk'event; + default clock is clk'delayed(0 ns)'event; begin diff --git a/test/regress/psl5.vhd b/test/regress/psl5.vhd index 91aea8888..db73656cd 100644 --- a/test/regress/psl5.vhd +++ b/test/regress/psl5.vhd @@ -26,7 +26,7 @@ architecture psl of psl5 is signal clk : natural; -- All is sensitive to rising edge of clk - -- psl default clock is clk'event; + -- psl default clock is clk'delayed(0 ns)'event; begin diff --git a/test/regress/psl6.vhd b/test/regress/psl6.vhd index 67f2ccc62..380c770ef 100644 --- a/test/regress/psl6.vhd +++ b/test/regress/psl6.vhd @@ -28,7 +28,7 @@ architecture psl of psl6 is signal clk : natural; -- All is sensitive to rising edge of clk - -- psl default clock is clk'event; + -- psl default clock is clk'delayed(0 ns)'event; begin