dac intf and sample rate #356
rookiebeotch
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Could you explain what is going on here in dac_intf.v
`assign dac_data_internal_after_sel = (ant_flag_in_rf_domain?{dac_data_internal,32'd0}:{32'd0,dac_data_internal});
assign dac_data = (simple_cdd_flag_in_rf_domain?{dac_data_internal_delay2, dac_data_internal}:dac_data_internal_after_sel);
// generate 1 baseband (20Msps) sample delay in dac clk (40MHz) domain
always @( posedge dac_clk )
begin
if ( dac_rst == 1 ) begin
dac_data_internal_delay1 <= 0;
dac_data_internal_delay2 <= 0;
end else begin
dac_data_internal_delay1 <= dac_data_internal;
dac_data_internal_delay2 <= dac_data_internal_delay1;
end
end`
In a normal 20 MHz channel mode with 1 RF Port what is the value of simple_cdd_flag_in_rf_domain and ant_flag_in_rf_domain supposed to be?
Is the dac_data supposed to be ICH0,QCH0,ICH1,QCH1 for 64 bit total?
Not understanding using the delay data with new data.
I have a 20Msps setup and my output looks a little odd.
i appreciate any insight.
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