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Early
Our image is used directly or you build your own image?
I used our image
What is your own modification?
Clock tree
Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision
Ubuntu16,vivado 2018.3, the latest branch of openwifi
Board/hardware type
E310V2
WiFi channel number
01
Steps to reproduce the issue, and the related error message, screenshot, etc
Hi, Dr Jiao,
I wanna know why does the clock of openwifi-ip come from 9361? actually, I can not use 9361's clock for openwifi becasue the reason of reset for dma, I use FCLK from PS side(100MHz) for openwifi IP. It's work. But when I change the BW from 20MHz to 5MHz, And the FCLK change to 25MHz(It's same frequency with the openwifi-ip's clk if i use the clk from 9361). The TX side is working, but in RX side, I can not receive any packet from another E310V2.
I change the BW by change the FIR file and the six parameters. Any things need to modify?
Thanks for your help.
Cordialement.
The text was updated successfully, but these errors were encountered:
Early
I used our image
Clock tree
Ubuntu16,vivado 2018.3, the latest branch of openwifi
E310V2
01
Hi, Dr Jiao,
I wanna know why does the clock of openwifi-ip come from 9361? actually, I can not use 9361's clock for openwifi becasue the reason of reset for dma, I use FCLK from PS side(100MHz) for openwifi IP. It's work. But when I change the BW from 20MHz to 5MHz, And the FCLK change to 25MHz(It's same frequency with the openwifi-ip's clk if i use the clk from 9361). The TX side is working, but in RX side, I can not receive any packet from another E310V2.
I change the BW by change the FIR file and the six parameters. Any things need to modify?
Thanks for your help.
Cordialement.
The text was updated successfully, but these errors were encountered: