Perf_counters_instrctions program hanging at finished dumping memory

[Spoorthi102003]

I am tying to run the perf_counters_instructions program in the directory $CORE_V_VERIF/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instrcutions.c

I am facing the an error where it is hanging at finishes dumping memory and it is also giving a warning
%Warning: ips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.hex:0: $readmem file not found

Background: trying to run the program on cv32e40x using the verilator 5.008 version.

/home/chips/Storage/riscv/riscv_toolchain//bin/riscv32-unknown-elf-gcc

-O3 -g -static -mabi=ilp32 -march=rv32imc_zba_zbb_zbc_zbs_zicsr_zifencei -Wall -pedantic -lm

-I ../../tests/asm
-I /home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/bsp
-o /home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.elf
-nostartfiles
/home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.c
-T /home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/bsp/link.ld
-L simulation_results/perf_counters_instructions/0/test_program/bsp
-lcv-verif
/home/chips/Storage/riscv/riscv_toolchain/lib/gcc/riscv32-unknown-elf/13.2.0/../../../../riscv32-unknown-elf/bin/ld: warning: /home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.elf has a LOAD segment with RWX permissions

---

• Generating hexfile, readelf and objdump files

---

/home/chips/Storage/riscv/riscv_toolchain//bin/riscv32-unknown-elf-objcopy -O verilog
/home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.elf
/home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.hex
/home/chips/Storage/riscv/riscv_toolchain//bin/riscv32-unknown-elf-readelf -a /home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.elf > /home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.readelf
/home/chips/Storage/riscv/riscv_toolchain//bin/riscv32-unknown-elf-objdump
-d
-M no-aliases
-M numeric
-S
/home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.elf > /home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.objdump
/home/chips/Storage/riscv/riscv_toolchain//bin/riscv32-unknown-elf-objdump
-d
-S
-M no-aliases
-M numeric
-l
/home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.elf | /home/chips/Storage/Tuppu/profiler/core-v-verif/bin/objdump2itb - > /home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.itb

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• Running with Verilator: logfile in cobj_dir/logs/perf_counters_instructions.log

---

mkdir -p cobj_dir/logs
./testbench_verilator
"+firmware=/home/chips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.hex"
| tee cobj_dir/logs/perf_counters_instructions.log
scopesDump:
SCOPE 0x7f6c1b165e00: TOP.tb_top_verilator
SCOPE 0x7f6c1b165e38: TOP.tb_top_verilator.cv32e40x_tb_wrapper_i.ram_i
SCOPE 0x7f6c1b165e70: TOP.tb_top_verilator.cv32e40x_tb_wrapper_i.ram_i.dp_ram_i
DPI-EXPORT 0x5603ca6408b4: read_byte
DPI-EXPORT 0x5603ca6408c1: write_byte

%Warning: ips/Storage/Tuppu/profiler/core-v-verif/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.hex:0: $readmem file not found
[tb_top_verilator] finished dumping memory

make veri-test TEST=perf_counters_instructions
Would appreciate any help provided. Thanks in advance.

[MikeOpenHWGroup]

Hi @Spoorthi102003, thanks for our interest in the CV32E40X. Unfortunately, Verilator has never been able to compile the CV32E40X RTL because it contains SystemVerilog interfaces. So we have not put a lot of effort into the the Verilator testbench (we call it the "core" testbench for historical reasons.

It is entirely possible that Veriator v5+ is now able to compile the RTL model, and if that is the case, I'd be willing to work with you to get this running.

From your logfiles it seems as if a Verilator model was successfully compiled - frankly I'm suspicous. Can you send me:

1. Your exact command-lines, starting with git clone .... and ending with 'make veri-test.
2. The logfiles generated (as file attachment).