diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index fd1bb481dae..4b4647ddb6b 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -243,13 +243,15 @@ cvxif-regression:
     DASHBOARD_SORT_INDEX: 5
     DASHBOARD_JOB_CATEGORY: "Basic"
     COLLECT_SIMU_LOGS: 1
+    SPIKE_TANDEM: 1
   parallel:
     matrix:
       - DV_SIMULATORS:
         - "veri-testharness,spike"
-        - "vcs-testharness,spike"
+        - "vcs-testharness"
   script:
     - bash verif/regress/cvxif_verif_regression.sh
+    - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
     - !reference [.simu_after_script]
 
 asic-synthesis:
@@ -327,7 +329,8 @@ riscv_arch_test:
     DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
     DASHBOARD_SORT_INDEX: 0
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness"
+    DV_SIMULATORS: "vcs-testharness"
+    SPIKE_TANDEM: 1
   script: source verif/regress/dv-riscv-arch-test.sh
   after_script: *simu_after_script
 
@@ -339,7 +342,8 @@ compliance:
     DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
     DASHBOARD_SORT_INDEX: 2
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness"
+    DV_SIMULATORS: "vcs-testharness"
+    SPIKE_TANDEM: 1
   script: source verif/regress/dv-riscv-compliance.sh
   after_script: *simu_after_script
 
@@ -351,7 +355,7 @@ riscv-tests-v:
     DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (virtual)"
     DASHBOARD_SORT_INDEX: 3
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness"
+    DV_SIMULATORS: "veri-testharness,spike"
     DV_TARGET: cv64a6_imafdc_sv39
     DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
   script: source verif/regress/dv-riscv-tests.sh
@@ -365,7 +369,8 @@ riscv-tests-p:
     DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (physical)"
     DASHBOARD_SORT_INDEX: 4
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness"
+    DV_SIMULATORS: "vcs-testharness"
+    SPIKE_TANDEM: 1
     DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-p.yaml"
   script: source verif/regress/dv-riscv-tests.sh
   after_script: *simu_after_script
@@ -388,7 +393,7 @@ mmu_sv32_tests:
     DASHBOARD_JOB_DESCRIPTION: "MMU SV32 regression suite"
     DASHBOARD_SORT_INDEX: 0
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness"
+    DV_SIMULATORS: "veri-testharness,spike"
     DV_TARGET: cv32a6_imac_sv32
   script: source verif/regress/dv-riscv-mmu-sv32-test.sh
   after_script: *simu_after_script
@@ -399,6 +404,8 @@ generated_tests:
   variables:
     DASHBOARD_SORT_INDEX: 11
     DASHBOARD_JOB_CATEGORY: "Code Coverage"
+    SPIKE_TANDEM: 1
+    DV_SIMULATORS: "vcs-uvm"
   parallel:
     matrix:
       - list_num: 1
@@ -432,6 +439,8 @@ generated_tests:
   variables:
     DASHBOARD_SORT_INDEX: 12
     DASHBOARD_JOB_CATEGORY: "Code Coverage"
+    SPIKE_TANDEM: 1
+    DV_SIMULATORS: "vcs-uvm"
   parallel:
     matrix:
       - list_num: 1
@@ -450,6 +459,8 @@ directed_isacov-tests:
   variables:
     DASHBOARD_SORT_INDEX: 13
     DASHBOARD_JOB_CATEGORY: "Functional Coverage"
+    SPIKE_TANDEM: 1
+    DV_SIMULATORS: "vcs-uvm"
   parallel:
     matrix:
       - list_num: 0
@@ -470,11 +481,12 @@ csr_embedded_tests:
     DASHBOARD_SORT_INDEX: 15
     DASHBOARD_JOB_CATEGORY: "CSR tests"
     DV_SIMULATORS: "vcs-uvm"
+    SPIKE_TANDEM: 1
   script:
     - mkdir -p artifacts/coverage
     - source verif/regress/dv-csr-embedded-tests.sh
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
-    - python3 .gitlab-ci/scripts/report_pass.py
+    - python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim
 
 .backend_test:
   stage: backend tests
diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml
index 1d9ac0d44da..821ccb50033 100644
--- a/.gitlab-ci/expected_synth.yml
+++ b/.gitlab-ci/expected_synth.yml
@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 171460
+  gates: 170380
diff --git a/Makefile b/Makefile
index a49494ae4bf..8010e80e8fc 100644
--- a/Makefile
+++ b/Makefile
@@ -274,10 +274,15 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
 compile_flag     += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 +permissive -svinputport=compat +define+$(defines) -suppress 8386 -suppress vlog-2577
 vopt_flag += -suppress 2085 -suppress 7063 -suppress 2698 -suppress 13262
 
+ifdef config-file
+  spike-yaml-plusarg = +config_file=$(spike_yaml)
+endif
+
 uvm-flags        += +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
 questa-flags     += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) \
 			+tohost_addr=$(shell ${RISCV}/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
-			+core_name=$(target) +define+QUESTA -suppress 3356 -suppress 3579
+			+core_name=$(target) +define+QUESTA -suppress 3356 -suppress 3579 +report_file=$(report_file) \
+			$(spike-yaml-plusarg)
 compile_flag_vhd += -64 -nologo -quiet -2008
 
 # Iterate over all include directories and write them with +incdir+ prefixed
diff --git a/README.md b/README.md
index 06da367765b..02787e3169d 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
-![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)
+![Build Status](https://riscv-ci.pages.thales-invia.fr/dashboard/)
 
 
 [CVA6 dashboard](util/toolchain-builder/README.md#Prerequisites)
diff --git a/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml b/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml
index 289f7762dd5..09b20e40996 100644
--- a/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml
+++ b/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml
@@ -13,14 +13,15 @@ spike_param_tree:
   core_configs:
     -
       isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
+      extensions: cv32a60x,cvxif
       boot_addr: 2147483648
-      marchid: 3
-      misa_we: false
-      misa_we_enable: true
+      marchid_override_mask: 0xFFFFFFFF
+      marchid_override_value: 0x3
+      misa_write_mask: 0x0
       pmpaddr0: 0
       pmpcfg0: 0
-      pmpregions: 64
-      usable_pmpregions: 8
+      pmpregions_max: 64
+      pmpregions_writable: 8
       priv: M
       status_fs_field_we: false
       status_fs_field_we_enable: false
@@ -29,4 +30,17 @@ spike_param_tree:
       mstatus_write_mask: 136
       mstatus_override_mask: 6144
       mtval_write_mask: 0
+      tinfo_accessible: 0
+      mscontext_accessible: 0
+      mcontext_accessible: 0
+      tdata1_accessible: 0
+      tdata2_accessible: 0
+      tdata3_accessible: 0
+      tselect_accessible: 0
+      mhartid: 0
+      mvendorid_override_mask : 0xFFFFFFFF
+      mvendorid_override_value: 1538
+      csr_counters_injection: true
       unified_traps: true
+      mcycleh_implemented: false
+      mhpmevent31_implemented: false
diff --git a/core/cva6.sv b/core/cva6.sv
index 82ca7b7f26f..419f72d8925 100644
--- a/core/cva6.sv
+++ b/core/cva6.sv
@@ -1062,7 +1062,7 @@ module cva6
       .*
   );
 
-  assign commit_ack = commit_ack_commit_id & ~commit_drop_id_commit;
+  assign commit_ack = commit_macro_ack & ~commit_drop_id_commit;
 
   // ---------
   // CSR
@@ -1078,7 +1078,7 @@ module cva6
       .flush_o                 (flush_csr_ctrl),
       .halt_csr_o              (halt_csr_ctrl),
       .commit_instr_i          (commit_instr_id_commit),
-      .commit_ack_i            (commit_macro_ack),
+      .commit_ack_i            (commit_ack),
       .boot_addr_i             (boot_addr_i[CVA6Cfg.VLEN-1:0]),
       .hart_id_i               (hart_id_i[CVA6Cfg.XLEN-1:0]),
       .ex_i                    (ex_commit),
@@ -1715,7 +1715,7 @@ module cva6
 
       .lsu_ctrl_i  (rvfi_lsu_ctrl),
       .wbdata_i    (wbdata_ex_id),
-      .commit_ack_i(commit_macro_ack),
+      .commit_ack_i(commit_ack),
       .mem_paddr_i (rvfi_mem_paddr),
       .debug_mode_i(debug_mode),
       .wdata_i     (wdata_commit_id),
diff --git a/verif/core-v-verif b/verif/core-v-verif
index 628ba12664c..3cf0c815230 160000
--- a/verif/core-v-verif
+++ b/verif/core-v-verif
@@ -1 +1 @@
-Subproject commit 628ba12664c19f3657661c07d3dab8d949dd21c2
+Subproject commit 3cf0c81523093d1895c6c50c4a941141df28bc3e
diff --git a/verif/regress/install-spike.sh b/verif/regress/install-spike.sh
index af28fe2cc9d..e240f64bdbb 100755
--- a/verif/regress/install-spike.sh
+++ b/verif/regress/install-spike.sh
@@ -52,11 +52,11 @@ if ! [ -f "$SPIKE_INSTALL_DIR/bin/spike" ]; then
   fi
   # Build both shared and static versions of the yaml-cpp library in sequence
   # prior to building Spike.
-  make yaml-cpp-static
-  make yaml-cpp
+  make -j${NUM_JOBS} yaml-cpp-static
+  make -j${NUM_JOBS} yaml-cpp
   make -j${NUM_JOBS}
   echo "Installing Spike in '$SPIKE_INSTALL_DIR'..."
-  make install
+  make -j${NUM_JOBS} install
   cd $CALLER_DIR
 else
   echo "Spike already installed in '$SPIKE_INSTALL_DIR'."
diff --git a/verif/sim/Makefile b/verif/sim/Makefile
index 89f1f7e3c89..976b7811c93 100644
--- a/verif/sim/Makefile
+++ b/verif/sim/Makefile
@@ -67,6 +67,9 @@ spike_params_final = $(spike_params)
 ifneq ($(wildcard $(spike_yaml)),)
   spike_params_final := $(spike_params_final) --param-file $(spike_yaml)
   spike-yaml-plusarg = +config_file=$(spike_yaml)
+  spike-yaml-makearg = config_file=$(spike_yaml)
+else
+  spike_params_final := $(spike_params_final) --extension=cvxif
 endif
 
 ##############################################
@@ -131,10 +134,6 @@ else
 	cov-run-opt  =
 endif
 
-ifdef cvxif
-	spike_extension = --extension=cvxif
-endif
-
 ###############################################################################
 # Spike specific commands, variables
 ###############################################################################
@@ -434,6 +433,7 @@ xrun-testharness:
 questa-testharness:
 	mkdir -p $(path_var)/tmp
 	make -C $(path_var) sim target=$(target) defines=$(subst +define+,,$(isscomp_opts)+core_name=$(target)) batch-mode=1 elf_file=$(elf) \
+	    report_file=$(log).yaml $(spike-yaml-makearg)
 	# TODO: Add support for waveform collection.
 	$(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log)
 	grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm
diff --git a/verif/tb/core/uvma_cva6pkg_utils.sv b/verif/tb/core/uvma_cva6pkg_utils.sv
index ac2b4d044aa..c64c30fd820 100644
--- a/verif/tb/core/uvma_cva6pkg_utils.sv
+++ b/verif/tb/core/uvma_cva6pkg_utils.sv
@@ -38,7 +38,7 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
     cfg.ext_zicsr_supported = 1;
     cfg.ext_zicntr_supported = 0;
 
-    cfg.ext_cv32a60x_supported = 1;
+    cfg.ext_cv32a60x_supported = 0;
 
     // FIXME TODO: Temporary solution. We need explicit info on memory map.
     // FORNOW The solution below relies on specific region ordering.
@@ -78,7 +78,7 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
 
     void'(spike_set_param_bool(base, "hide_csrs_based_on_priv", 1));
     void'(spike_set_param_uint64_t(base, "mtvec_vectored_alignment", 64 * 4));
-    void'(spike_set_param_str(base, "extensions", "cv32a60x"));
+    void'(spike_set_param_str(base, "extensions", "cvxif"));
 
     // All enabled except XS and TW bits
     void'(spike_set_param_uint64_t(base, "mstatus_write_mask", 'hFFDE_7FFF));