[CV32A6*X] Disable Zifencei across the verification infrastructure. (#2822)

This MR implements the non-RTL part of CVA6 project changes needed for #2734:
* changes to scripts
* changes to configuration files
* turn off Zifencei support in RTL configuration.

Author: zchamski

.gitlab-ci/scripts/report_benchmark.py

@@ -19,10 +19,10 @@
 # Keep it up-to-date with compiler version and core performance improvements
 # Will fail if the number of cycles is different from this one
 valid_cycles = {
-    "dhrystone_dual": 21226,
-    "dhrystone_single": 23624,
-    "coremark_dual": 1194262,
-    "coremark_single": 1291549,
+    "dhrystone_dual": 21176,
+    "dhrystone_single": 23524,
+    "coremark_dual": 1194268,
+    "coremark_single": 1291566,
     "dhrystone_cv32a65x": 35952,
     "dhrystone_cv32a60x": 38856,
 }

config/gen_from_riscv_config/cv32a60x/spike/spike.yaml

@@ -8,16 +8,18 @@ spike_param_tree:
   generic_core_config: false
   max_steps: 200000
   max_steps_enabled: false
-  isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
+  isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif
   priv: M
   core_configs:
     -
-      isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
-      extensions: cv32a60x,cvxif
+      isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif
+      extensions: cv32a60x
       boot_addr: 2147483648
       marchid_override_mask: 0xFFFFFFFF
       marchid_override_value: 0x3
       misa_write_mask: 0x0
+      misa_override_mask: 0x00800000
+      misa_override_value: 0x00000000
       pmp_granularity: 8
       pmpaddr0: 0
       pmpcfg0: 0
@@ -37,14 +39,16 @@ spike_param_tree:
       mip_override_mask: 0xfffff77f
       mip_override_value: 0x00000000
       mtval_write_mask: 0
-      mtvec_write_mask: 0xFFFFFFFE
       tinfo_accessible: 0
       mscontext_accessible: 0
       mcontext_accessible: 0
       tdata1_accessible: 0
       tdata2_accessible: 0
       tdata3_accessible: 0
       tselect_accessible: 0
+      mtvec_write_mask:     0xFFFFFFFC
+      mtvec_override_mask:  0x00000003
+      mtvec_override_value: 0x00000000
       mhartid: 0
       mvendorid_override_mask : 0xFFFFFFFF
       mvendorid_override_value: 1538
@@ -53,3 +57,4 @@ spike_param_tree:
       unified_traps: true
       mcycleh_implemented: false
       mhpmevent31_implemented: false
+      cvxif_x_num_rs: 2

config/gen_from_riscv_config/cv32a65x/spike/spike.yaml

@@ -8,21 +8,23 @@ spike_param_tree:
   generic_core_config: false
   max_steps: 200000
   max_steps_enabled: false
-  isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
+  isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif
   priv: M
   core_configs:
     -
-      isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
-      extensions: cv32a60x,cvxif
+      isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif
+      extensions: cv32a60x
       boot_addr: 2147483648
       marchid_override_mask: 0xFFFFFFFF
       marchid_override_value: 0x3
       misa_write_mask: 0x0
+      misa_override_mask: 0x00800000
+      misa_override_value: 0x00000000
       pmp_granularity: 8
       pmpaddr0: 0
       pmpcfg0: 0
       pmpregions_max: 64
-      pmpregions_writable: 8
+      pmpregions_writable: 0
       priv: M
       status_fs_field_we: false
       status_fs_field_we_enable: false
@@ -44,15 +46,9 @@ spike_param_tree:
       tdata2_accessible: 0
       tdata3_accessible: 0
       tselect_accessible: 0
-      pmpaddr0_write_mask: 0xFFFFFFFE
-      pmpaddr1_write_mask: 0xFFFFFFFE
-      pmpaddr2_write_mask: 0xFFFFFFFE
-      pmpaddr3_write_mask: 0xFFFFFFFE
-      pmpaddr4_write_mask: 0xFFFFFFFE
-      pmpaddr5_write_mask: 0xFFFFFFFE
-      pmpaddr6_write_mask: 0xFFFFFFFE
-      pmpaddr7_write_mask: 0xFFFFFFFE
-      mtvec_write_mask: 0xFFFFFFFE
+      mtvec_write_mask:     0xFFFFFFFC
+      mtvec_override_mask:  0x00000003
+      mtvec_override_value: 0x00000000
       mhartid: 0
       mvendorid_override_mask : 0xFFFFFFFF
       mvendorid_override_value: 1538
@@ -61,3 +57,4 @@ spike_param_tree:
       unified_traps: true
       mcycleh_implemented: false
       mhpmevent31_implemented: false
+      cvxif_x_num_rs: 2

config/riscv-config/cv32a60x/generated/custom_gen.yaml

@@ -0,0 +1,67 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Zbigniew CHAMSKI - Thales
+
+hart_ids: [0]
+hart0:
+    icache:
+        reset-val: 0x1
+        rv64:
+            accessible: false
+        rv32:
+            accessible: true
+            icache:
+                implemented: true
+                type:
+                    rw: true
+                description: bit for cache-enable of instruction cache
+                msb: 0
+                lsb: 0
+                shadow:
+                shadow_type:
+            fields:
+              - icache
+              -
+                  -
+                      - 1
+                      - 31
+        description: the register controls the operation of the i-cache unit.
+        address: 0x7c0
+        priv_mode: M
+    dcache:
+        reset-val: 0x1
+        rv64:
+            accessible: false
+        rv32:
+            accessible: true
+            dcache:
+                implemented: true
+                type:
+                    rw: true
+                description: bit for cache-enable of data cache
+                shadow:
+                shadow_type:
+                msb: 0
+                lsb: 0
+            fields:
+              - dcache
+              -
+                  -
+                      - 1
+                      - 31
+        description: the register controls the operation of the d-cache unit.
+        address: 0x7c1
+        priv_mode: M
+