From cb5c623e5083656fd6bead45c6a7128e891f121a Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 15 Jan 2025 21:17:37 +1100 Subject: [PATCH] mmu: Fix pmpcfg, pmpaddr width (#2707) PR #2692 changed the bus width for `pmpcfg` and `pmpaddr` in most modules. Do the same in `cva6_mmu` and `cva6_ptw` to fix port width mismatches. --- core/cva6_mmu/cva6_mmu.sv | 4 ++-- core/cva6_mmu/cva6_ptw.sv | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/core/cva6_mmu/cva6_mmu.sv b/core/cva6_mmu/cva6_mmu.sv index 8c1791bbf0..5382279938 100644 --- a/core/cva6_mmu/cva6_mmu.sv +++ b/core/cva6_mmu/cva6_mmu.sv @@ -100,8 +100,8 @@ module cva6_mmu // PMP - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i ); // memory management, pte for cva6 diff --git a/core/cva6_mmu/cva6_ptw.sv b/core/cva6_mmu/cva6_ptw.sv index 0700891db0..a5fef76fcc 100644 --- a/core/cva6_mmu/cva6_ptw.sv +++ b/core/cva6_mmu/cva6_ptw.sv @@ -83,8 +83,8 @@ module cva6_ptw output logic shared_tlb_miss_o, // PMP - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, output logic [CVA6Cfg.PLEN-1:0] bad_paddr_o, output logic [CVA6Cfg.GPLEN-1:0] bad_gpaddr_o );