@@ -216,10 +216,10 @@ module cve2_id_stage #(
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// Register file interface
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- rf_wd_sel_e rf_wdata_sel;
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- logic rf_we_dec, rf_we_raw;
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- logic rf_ren_a, rf_ren_b;
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- logic rf_ren_a_dec, rf_ren_b_dec;
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+ logic [XInterface : 0 ] rf_wdata_sel;
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+ logic rf_we_dec, rf_we_raw;
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+ logic rf_ren_a, rf_ren_b;
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+ logic rf_ren_a_dec, rf_ren_b_dec;
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// Read enables should only be asserted for valid and legal instructions
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assign rf_ren_a = instr_valid_i & ~ instr_fetch_err_i & ~ illegal_insn_o & rf_ren_a_dec;
@@ -418,19 +418,12 @@ module cve2_id_stage #(
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// Register file write data mux
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always_comb begin : rf_wdata_id_mux
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- if (XInterface)
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- unique case (rf_wdata_sel)
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- RF_WD_EX : rf_wdata_id_o = result_ex_i;
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- RF_WD_CSR : rf_wdata_id_o = csr_rdata_i;
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- RF_WD_COPROC : rf_wdata_id_o = x_result_i.data;
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- default : rf_wdata_id_o = result_ex_i;
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- endcase
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- else
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- unique case (rf_wdata_sel)
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- RF_WD_EX : rf_wdata_id_o = result_ex_i;
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- RF_WD_CSR : rf_wdata_id_o = csr_rdata_i;
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- default : rf_wdata_id_o = result_ex_i;
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- endcase
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+ unique case (rf_wdata_sel)
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+ RF_WD_EX : rf_wdata_id_o = result_ex_i;
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+ RF_WD_CSR : rf_wdata_id_o = csr_rdata_i;
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+ RF_WD_COPROC : rf_wdata_id_o = XInterface? x_result_i.data : result_ex_i;
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+ default : rf_wdata_id_o = result_ex_i;
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+ endcase
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end
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// ///////////
@@ -826,7 +819,7 @@ module cve2_id_stage #(
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// Stall ID/EX stage for reason that relates to instruction in ID/EX, update assertion below if
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// modifying this.
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assign stall_id = stall_mem | stall_multdiv | stall_jump | stall_branch |
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- stall_alu | stall_coproc;
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+ stall_alu | (XInterface & stall_coproc) ;
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// Generally illegal instructions have no reason to stall, however they must still stall waiting
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// for outstanding memory requests so exceptions related to them take priority over the illegal
@@ -902,10 +895,17 @@ module cve2_id_stage #(
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OP_A_FWD ,
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OP_A_CURRPC ,
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OP_A_IMM } )
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- `ASSERT (IbexRegfileWdataSelValid, instr_valid_i | - > rf_wdata_sel inside {
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- RF_WD_EX ,
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- RF_WD_CSR ,
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- RF_WD_COPROC } )
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+ if (XInterface) begin : gen_asserts_xif
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+ `ASSERT (IbexRegfileWdataSelValid, instr_valid_i | - > rf_wdata_sel inside {
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+ RF_WD_EX ,
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+ RF_WD_CSR ,
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+ RF_WD_COPROC } )
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+ end
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+ else begin : no_gen_asserts_xif
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+ `ASSERT (IbexRegfileWdataSelValid, instr_valid_i | - > rf_wdata_sel inside {
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+ RF_WD_EX ,
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+ RF_WD_CSR } )
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+ end
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`ASSERT_KNOWN (IbexWbStateKnown, id_fsm_q)
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// Branch decision must be valid when jumping.
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