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davideschiavoneFrancescoDeMalde-syntharacairo-caplan
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add X-IF 1.0 (#284)
* Core-V eXtension Interface (CV-X-IF) integration (#277) * minor fixes (#283) * minor fix again * Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line (#289) * Fix remaining sec inconsistency regarding the X-IF addition (#291) * Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line * [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present * [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present * Clean Verilator warning about X-IF addition while keeping the RTL SEC-safe (#292) * Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line * [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present * [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present * [rtl][xif][verilator] Clean warnings about enum-logic[] width mismatch on Verilator, while keeping the design logically equivalent. This is due to the cve2_decoder's rf_wdata_sel_o signal, which has its width dependent of the X-IF. * fix xif --------- Co-authored-by: FrancescoDeMalde-synthara <[email protected]> Co-authored-by: Cairo Caplan <[email protected]>
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‎rtl/cve2_core.sv‎

Lines changed: 42 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,8 @@ module cve2_core import cve2_pkg::*; #(
2222
parameter rv32m_e RV32M = RV32MFast,
2323
parameter rv32b_e RV32B = RV32BNone,
2424
parameter bit DbgTriggerEn = 1'b0,
25-
parameter int unsigned DbgHwBreakNum = 1
25+
parameter int unsigned DbgHwBreakNum = 1,
26+
parameter bit XInterface = 1'b0
2627
) (
2728
// Clock and Reset
2829
input logic clk_i,
@@ -52,6 +53,25 @@ module cve2_core import cve2_pkg::*; #(
5253
input logic [31:0] data_rdata_i,
5354
input logic data_err_i,
5455

56+
// Core-V Extension Interface (CV-X-IF)
57+
// Issue Interface
58+
output logic x_issue_valid_o,
59+
input logic x_issue_ready_i,
60+
output x_issue_req_t x_issue_req_o,
61+
input x_issue_resp_t x_issue_resp_i,
62+
63+
// Register Interface
64+
output x_register_t x_register_o,
65+
66+
// Commit Interface
67+
output logic x_commit_valid_o,
68+
output x_commit_t x_commit_o,
69+
70+
// Result Interface
71+
input logic x_result_valid_i,
72+
output logic x_result_ready_o,
73+
input x_result_t x_result_i,
74+
5575
// Interrupt inputs
5676
input logic irq_software_i,
5777
input logic irq_timer_i,
@@ -355,7 +375,8 @@ module cve2_core import cve2_pkg::*; #(
355375
cve2_id_stage #(
356376
.RV32E (RV32E),
357377
.RV32M (RV32M),
358-
.RV32B (RV32B)
378+
.RV32B (RV32B),
379+
.XInterface (XInterface)
359380
) id_stage_i (
360381
.clk_i (clk_i),
361382
.rst_ni(rst_ni),
@@ -439,6 +460,25 @@ module cve2_core import cve2_pkg::*; #(
439460
.lsu_load_err_i (lsu_load_err),
440461
.lsu_store_err_i(lsu_store_err),
441462

463+
// Core-V Extension Interface (CV-X-IF)
464+
// Issue Interface
465+
.x_issue_valid_o(x_issue_valid_o),
466+
.x_issue_ready_i(x_issue_ready_i),
467+
.x_issue_req_o(x_issue_req_o),
468+
.x_issue_resp_i(x_issue_resp_i),
469+
470+
// Register Interface
471+
.x_register_o(x_register_o),
472+
473+
// Commit Interface
474+
.x_commit_valid_o(x_commit_valid_o),
475+
.x_commit_o(x_commit_o),
476+
477+
// Result Interface
478+
.x_result_valid_i(x_result_valid_i),
479+
.x_result_ready_o(x_result_ready_o),
480+
.x_result_i(x_result_i),
481+
442482
// Interrupt Signals
443483
.csr_mstatus_mie_i(csr_mstatus_mie),
444484
.irq_pending_i (irq_pending_o),

‎rtl/cve2_decoder.sv‎

Lines changed: 43 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,8 @@
1616
module cve2_decoder #(
1717
parameter bit RV32E = 0,
1818
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
19-
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
19+
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,
20+
parameter bit XInterface = 1'b0
2021
) (
2122
input logic clk_i,
2223
input logic rst_ni,
@@ -50,46 +51,50 @@ module cve2_decoder #(
5051
output logic [31:0] zimm_rs1_type_o,
5152

5253
// register file
53-
output cve2_pkg::rf_wd_sel_e rf_wdata_sel_o, // RF write data selection
54-
output logic rf_we_o, // write enable for regfile
55-
output logic [4:0] rf_raddr_a_o,
56-
output logic [4:0] rf_raddr_b_o,
57-
output logic [4:0] rf_waddr_o,
58-
output logic rf_ren_a_o, // Instruction reads from RF addr A
59-
output logic rf_ren_b_o, // Instruction reads from RF addr B
54+
output logic [XInterface:0] rf_wdata_sel_o, // RF write data selection
55+
output logic rf_we_o, // write enable for regfile
56+
output logic [4:0] rf_raddr_a_o,
57+
output logic [4:0] rf_raddr_b_o,
58+
output logic [4:0] rf_waddr_o,
59+
output logic rf_ren_a_o, // Instruction reads from RF addr A
60+
output logic rf_ren_b_o, // Instruction reads from RF addr B
6061

6162
// ALU
62-
output cve2_pkg::alu_op_e alu_operator_o, // ALU operation selection
63-
output cve2_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC,
64-
// immediate or zero
65-
output cve2_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or
66-
// immediate
67-
output logic alu_multicycle_o, // ternary bitmanip instruction
63+
output cve2_pkg::alu_op_e alu_operator_o, // ALU operation selection
64+
output cve2_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC,
65+
// immediate or zero
66+
output cve2_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or
67+
// immediate
68+
output logic alu_multicycle_o, // ternary bitmanip instruction
6869

6970
// MULT & DIV
70-
output logic mult_en_o, // perform integer multiplication
71-
output logic div_en_o, // perform integer division or remainder
72-
output logic mult_sel_o, // as above but static, for data muxes
73-
output logic div_sel_o, // as above but static, for data muxes
71+
output logic mult_en_o, // perform integer multiplication
72+
output logic div_en_o, // perform integer division or remainder
73+
output logic mult_sel_o, // as above but static, for data muxes
74+
output logic div_sel_o, // as above but static, for data muxes
7475

75-
output cve2_pkg::md_op_e multdiv_operator_o,
76-
output logic [1:0] multdiv_signed_mode_o,
76+
output cve2_pkg::md_op_e multdiv_operator_o,
77+
output logic [1:0] multdiv_signed_mode_o,
7778

7879
// CSRs
79-
output logic csr_access_o, // access to CSR
80-
output cve2_pkg::csr_op_e csr_op_o, // operation to perform on CSR
80+
output logic csr_access_o, // access to CSR
81+
output cve2_pkg::csr_op_e csr_op_o, // operation to perform on CSR
8182

8283
// LSU
83-
output logic data_req_o, // start transaction to data memory
84-
output logic data_we_o, // write enable
85-
output logic [1:0] data_type_o, // size of transaction: byte, half
86-
// word or word
87-
output logic data_sign_extension_o, // sign extension for data read from
84+
output logic data_req_o, // start transaction to data memory
85+
output logic data_we_o, // write enable
86+
output logic [1:0] data_type_o, // size of transaction: byte, half
87+
// word or word
88+
output logic data_sign_extension_o, // sign extension for data read from
8889
// memory
8990

91+
// Core-V eXtension interface (CV-X-IF)
92+
input cve2_pkg::readregflags_t x_issue_resp_register_read_i,
93+
input cve2_pkg::writeregflags_t x_issue_resp_writeback_i,
94+
9095
// jump/branches
91-
output logic jump_in_dec_o, // jump is being calculated in ALU
92-
output logic branch_in_dec_o
96+
output logic jump_in_dec_o, // jump is being calculated in ALU
97+
output logic branch_in_dec_o
9398
);
9499

95100
import cve2_pkg::*;
@@ -205,7 +210,7 @@ module cve2_decoder #(
205210
multdiv_operator_o = MD_OP_MULL;
206211
multdiv_signed_mode_o = 2'b00;
207212

208-
rf_wdata_sel_o = RF_WD_EX;
213+
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_EX});
209214
rf_we = 1'b0;
210215
rf_ren_a_o = 1'b0;
211216
rf_ren_b_o = 1'b0;
@@ -612,7 +617,7 @@ module cve2_decoder #(
612617
end else begin
613618
// instruction to read/modify CSR
614619
csr_access_o = 1'b1;
615-
rf_wdata_sel_o = RF_WD_CSR;
620+
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_CSR});
616621
rf_we = 1'b1;
617622

618623
if (~instr[14]) begin
@@ -653,6 +658,13 @@ module cve2_decoder #(
653658
jump_set_o = 1'b0;
654659
branch_in_dec_o = 1'b0;
655660
csr_access_o = 1'b0;
661+
// CV-X-IF
662+
if(XInterface) begin
663+
rf_ren_a_o = x_issue_resp_register_read_i[0];
664+
rf_ren_b_o = x_issue_resp_register_read_i[1];
665+
rf_we = x_issue_resp_writeback_i;
666+
rf_wdata_sel_o = $bits(rf_wdata_sel_o)'({RF_WD_COPROC});
667+
end
656668
end
657669
end
658670

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