diff --git a/Makefile b/Makefile index ff42a6ff74..cc89127dd0 100644 --- a/Makefile +++ b/Makefile @@ -11,103 +11,110 @@ help: @echo "or how to set-up the different environments." # Use a parallel run (make -j N) for a faster build -build-all: build-riscv-compliance build-simple-system build-arty-100 \ - build-csr-test +# build-all: build-riscv-compliance build-simple-system build-arty-100 \ +# build-csr-test +build-all: build-riscv-compliance # RISC-V compliance .PHONY: build-riscv-compliance build-riscv-compliance: fusesoc --cores-root=. run --target=sim --setup --build \ - lowrisc:cve2:cve2_riscv_compliance \ + openhwgroup:cve2:cve2_riscv_compliance \ $(FUSESOC_CONFIG_OPTS) -# Simple system -# Use the following targets: -# - "build-simple-system" -# - "run-simple-system" -.PHONY: build-simple-system -build-simple-system: - fusesoc --cores-root=. run --target=sim --setup --build \ - lowrisc:cve2:cve2_simple_system \ - $(FUSESOC_CONFIG_OPTS) +# # Simple system +# # Use the following targets: +# # - "build-simple-system" +# # - "run-simple-system" +# .PHONY: build-simple-system +# build-simple-system: +# fusesoc --cores-root=. run --target=sim --setup --build \ +# openhwgroup:cve2:cve2_simple_system \ +# $(FUSESOC_CONFIG_OPTS) -simple-system-program = examples/sw/simple_system/hello_test/hello_test.vmem -sw-simple-hello: $(simple-system-program) +# simple-system-program = examples/sw/simple_system/hello_test/hello_test.vmem +# sw-simple-hello: $(simple-system-program) -.PHONY: $(simple-system-program) -$(simple-system-program): - cd examples/sw/simple_system/hello_test && $(MAKE) +# .PHONY: $(simple-system-program) +# $(simple-system-program): +# cd examples/sw/simple_system/hello_test && $(MAKE) -Vcve2_simple_system = \ - build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system -$(Vcve2_simple_system): - @echo "$@ not found" - @echo "Run \"make build-simple-system\" to create the dependency" - @false +# Vcve2_simple_system = \ +# build/openhwgroup_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system +# $(Vcve2_simple_system): +# @echo "$@ not found" +# @echo "Run \"make build-simple-system\" to create the dependency" +# @false -run-simple-system: sw-simple-hello | $(Vcve2_simple_system) - build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system \ - --raminit=$(simple-system-program) +# run-simple-system: sw-simple-hello | $(Vcve2_simple_system) +# build/openhwgroup_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system \ +# --raminit=$(simple-system-program) compile_verilator: fusesoc --cores-root . run --no-export --target=lint --tool=verilator --setup --build openhwgroup:cve2:cve2_top:0.1 2>&1 | tee buildsim.log -# Arty A7 FPGA example -# Use the following targets (depending on your hardware): -# - "build-arty-35" -# - "build-arty-100" -# - "program-arty" -arty-sw-program = examples/sw/led/led.vmem -sw-led: $(arty-sw-program) +# # Arty A7 FPGA example +# # Use the following targets (depending on your hardware): +# # - "build-arty-35" +# # - "build-arty-100" +# # - "program-arty" +# arty-sw-program = examples/sw/led/led.vmem +# sw-led: $(arty-sw-program) -.PHONY: $(arty-sw-program) -$(arty-sw-program): - cd examples/sw/led && $(MAKE) +# .PHONY: $(arty-sw-program) +# $(arty-sw-program): +# cd examples/sw/led && $(MAKE) -.PHONY: build-arty-35 -build-arty-35: sw-led - fusesoc --cores-root=. run --target=synth --setup --build \ - lowrisc:cve2:top_artya7 --part xc7a35ticsg324-1L +# .PHONY: build-arty-35 +# build-arty-35: sw-led +# fusesoc --cores-root=. run --target=synth --setup --build \ +# openhwgroup:cve2:top_artya7 --part xc7a35ticsg324-1L -.PHONY: build-arty-100 -build-arty-100: sw-led - fusesoc --cores-root=. run --target=synth --setup --build \ - lowrisc:cve2:top_artya7 --part xc7a100tcsg324-1 +# .PHONY: build-arty-100 +# build-arty-100: sw-led +# fusesoc --cores-root=. run --target=synth --setup --build \ +# openhwgroup:cve2:top_artya7 --part xc7a100tcsg324-1 -.PHONY: program-arty -program-arty: - fusesoc --cores-root=. run --target=synth --run \ - lowrisc:cve2:top_artya7 +# .PHONY: program-arty +# program-arty: +# fusesoc --cores-root=. run --target=synth --run \ +# openhwgroup:cve2:top_artya7 # Lint check -.PHONY: lint-core-tracing -lint-core-tracing: - fusesoc --cores-root . run --target=lint lowrisc:cve2:cve2_core_tracing \ +.PHONY: lint-top-tracing +lint-top-tracing: + fusesoc --cores-root . run --target=lint openhwgroup:cve2:cve2_top_tracing \ + $(FUSESOC_CONFIG_OPTS) + +# Lint check +.PHONY: lint-top +lint-top: + fusesoc --cores-root . run --target=lint openhwgroup:cve2:cve2_top \ $(FUSESOC_CONFIG_OPTS) -# CS Registers testbench -# Use the following targets: -# - "build-csr-test" -# - "run-csr-test" -.PHONY: build-csr-test -build-csr-test: - fusesoc --cores-root=. run --target=sim --setup --build \ - --tool=verilator lowrisc:cve2:tb_cs_registers -Vtb_cs_registers = \ - build/lowrisc_cve2_tb_cs_registers_0/sim-verilator/Vtb_cs_registers -$(Vtb_cs_registers): - @echo "$@ not found" - @echo "Run \"make build-csr-test\" to create the dependency" - @false - -.PHONY: run-csr-test -run-csr-test: | $(Vtb_cs_registers) - fusesoc --cores-root=. run --target=sim --run \ - --tool=verilator lowrisc:cve2:tb_cs_registers +# # CS Registers testbench +# # Use the following targets:c +# # - "build-csr-test" +# # - "run-csr-test" +# .PHONY: build-csr-test +# build-csr-test: +# fusesoc --cores-root=. run --target=sim --setup --build \ +# --tool=verilator openhwgroup:cve2:tb_cs_registers +# Vtb_cs_registers = \ +# build/openhwgroup_cve2_tb_cs_registers_0/sim-verilator/Vtb_cs_registers +# $(Vtb_cs_registers): +# @echo "$@ not found" +# @echo "Run \"make build-csr-test\" to create the dependency" +# @false + +# .PHONY: run-csr-test +# run-csr-test: | $(Vtb_cs_registers) +# fusesoc --cores-root=. run --target=sim --run \ +# --tool=verilator openhwgroup:cve2:tb_cs_registers # Echo the parameters passed to fusesoc for the chosen CVE2_CONFIG .PHONY: test-cfg @@ -117,3 +124,12 @@ test-cfg: .PHONY: python-lint python-lint: $(MAKE) -C util lint + +# Sequential Equivalence Checking +.PHONY: sec +sec: + ./scripts/sec/sec.sh -t yosys + +.PHONY: clean +clean: + -rm -rf ./build ./formal/riscv-formal/build \ No newline at end of file diff --git a/README.md b/README.md index 3f2725019b..e23270ea00 100644 --- a/README.md +++ b/README.md @@ -1,9 +1,9 @@ -# OpenHW Group CORE-V CVE2 RISC-V IP +# OpenHW Foundation CORE-V CVE2 RISC-V IP -CVE2 is a class of 2-stage pipeline OpenHW Group cores. Currently, the only core in this class is the CV32E20. +CVE2 is a class of 2-stage pipeline OpenHW Foundation cores. Currently, the only core in this class is the CV32E20. CV32E20 is a fork of the [Ibex](https://github.com/lowRISC/ibex) core. -Differently to Ibex, cv32e2 will target low cost as originally intended in the [Zero-riscy](https://doi.org/10.1109/PATMOS.2017.8106976) project. -The core will be made compatible with the OpenHW Group OBI protocol, it will use the same sleep unit of CV32E4 family, and it will achieve TRL5 with the industrial-level verification [core-v-verif](https://github.com/openhwgroup/core-v-verif). +Differently to Ibex, CV32E20 will target low cost as originally intended in the [Zero-riscy](https://doi.org/10.1109/PATMOS.2017.8106976) project. +The core will be made compatible with the OpenHW Foundation OBI protocol, it will use the same sleep unit of CV32E4 family, and it will achieve TRL5 with the industrial-level verification [core-v-verif](https://github.com/openhwgroup/core-v-verif). # CV32E20 RISC-V Core @@ -21,7 +21,7 @@ pipeline. CV32E20 was initially developed as part of the [PULP platform](https://www.pulp-platform.org) under the name ["Zero-riscy"](https://doi.org/10.1109/PATMOS.2017.8106976), and has been contributed to [lowRISC](https://www.lowrisc.org) who maintains it and develops it further. -It was further adopted by the OpenHW Group to work towards an improved industrialization +It was further adopted by the OpenHW Foundation to work towards an improved industrialization use through extensive verification, with the aid of the [Core-V Verification](https://github.com/openhwgroup/cv32e20-dv) environment. ## Verification @@ -29,7 +29,7 @@ The verification environment for the CVE2 is _not_ in this Repository. There is useful for experimentation only and should not be used to validate any changes to the RTL prior to pushing to the master branch of this repo. -The verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the +The verification environment for this core as well as other cores in the OpenHW Foundation CORE-V family is at the [core-v-verif](https://github.com/openhwgroup/core-v-verif) repository on GitHub. The Makefiles supported in the **core-v-verif** project automatically clone the appropriate version of the **cve2** RTL sources. @@ -39,7 +39,7 @@ The Makefiles supported in the **core-v-verif** project automatically clone the A changelog is generated automatically in the documentation from the individual pull requests. In order to enable automatic changelog generation within the documentation, the committer is required to label each pull request that touches any file in 'rtl' (or any of its subdirectories) with *Component:RTL* and label each pull request that touches any file in -'docs' (or any of its subdirectories) with *Component:Doc*. Pull requests taht are not labeled or labeled with *ignore-for-release* are +'docs' (or any of its subdirectories) with *Component:Doc*. Pull requests that are not labeled or labeled with *ignore-for-release* are ignored for the changelog generation. Only the person who actually performs the merge can add these labels (you need committer rights). The changelog flow only works if at most @@ -100,8 +100,7 @@ please: * Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit! * Do not mix updates within the 'rtl' directory with updates within the 'docs' directory into the same pull request. -* Write meaningful commit messages. For more information, please check out the [the Ibex contribution - guide](https://github.com/lowrisc/ibex/blob/master/CONTRIBUTING.md). +* Write meaningful commit messages. For more information, please check out the [CVE2 contribution guide](CONTRIBUTING.md). * If asked to modify your changes, do fix up your commits and rebase your branch to maintain a clean history. * If the PR gets accepted and merged into the **dev** branch, an action is triggered automatically to check whether the changes are logically equivalent to the frozen RTL on a given set of parameters. If the changes are logically equivalent, the **dev** branch is automatically merged into the **master** branch. Otherwise, we need to investigate manually. If a bug is found, thus the changes are not logically equivalent, we follow the procedure documented [here](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/core_versions.html). diff --git a/cv32e20_manifest.flist b/cv32e20_manifest.flist index 4a0142d800..4e5a3dcde9 100644 --- a/cv32e20_manifest.flist +++ b/cv32e20_manifest.flist @@ -1,5 +1,6 @@ /////////////////////////////////////////////////////////////////////////////// // +// Copyright (c) 2025 Eclipse Foundation // Copyright 2022 OpenHW Group // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); @@ -60,4 +61,4 @@ ${DESIGN_RTL_DIR}/cve2_top.sv ${DESIGN_RTL_DIR}/cve2_top_tracing.sv ${DESIGN_RTL_DIR}/cve2_tracer.sv -${DESIGN_RTL_DIR}/../bhv/cve2_sim_clock_gate.sv +${DESIGN_RTL_DIR}/cve2_clock_gate.sv diff --git a/cve2_configs.yaml b/cve2_configs.yaml index 1dba358d05..3b21d1a07f 100644 --- a/cve2_configs.yaml +++ b/cve2_configs.yaml @@ -1,94 +1,20 @@ +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -# Ibex configurations files, holds the parameter sets that are tested under CI. +# CVE2 configurations files, holds the parameter sets that are tested under CI. # Each configuration must specify the same set of parameters # Two-stage pipeline without additional branch target ALU and 3 cycle multiplier # (4 cycles for mulh), resulting in 2 stall cycles for mul (3 for mulh) small: + MHPMCounterNum : 10 + MHPMCounterWidth : 40 RV32E : 0 RV32M : "cve2_pkg::RV32MFast" - RV32B : "cve2_pkg::RV32BNone" - RegFile : "cve2_pkg::RegFileFF" - WritebackStage : 0 - PMPEnable : 0 - PMPGranularity : 0 - PMPNumRegions : 4 - -# Configuration to match that used in the OpenTitan project -opentitan: - RV32E : 0 - RV32M : "cve2_pkg::RV32MSingleCycle" - RV32B : "cve2_pkg::RV32BOTEarlGrey" - RegFile : "cve2_pkg::RegFileFF" - WritebackStage : 1 - PMPEnable : 1 - PMPGranularity : 0 - PMPNumRegions : 16 - -# =============================== -# * EXPERIMENTAL CONFIGURATIONS * -# =============================== - -# Three-stage pipeline with additional branch traget ALU and 1 cycle multiplier -# (2 cycles for mulh) so mul does not stall (mulh stall 1 cycles). This is the -# maximum performance configuration. -experimental-maxperf: - RV32E : 0 - RV32M : "cve2_pkg::RV32MSingleCycle" - RV32B : "cve2_pkg::RV32BNone" - RegFile : "cve2_pkg::RegFileFF" - WritebackStage : 1 - PMPEnable : 0 - PMPGranularity : 0 - PMPNumRegions : 4 - -# experimental-maxperf config above plus PMP enabled with 16 regions. -experimental-maxperf-pmp: - RV32E : 0 - RV32M : "cve2_pkg::RV32MSingleCycle" - RV32B : "cve2_pkg::RV32BNone" - RegFile : "cve2_pkg::RegFileFF" - WritebackStage : 1 - PMPEnable : 1 - PMPGranularity : 0 - PMPNumRegions : 16 - -# experimental-maxperf-pmp config above with balanced bitmanip extension -experimental-maxperf-pmp-bmbalanced: - RV32E : 0 - RV32M : "cve2_pkg::RV32MSingleCycle" - RV32B : "cve2_pkg::RV32BBalanced" - RegFile : "cve2_pkg::RegFileFF" - WritebackStage : 1 - PMPEnable : 1 - PMPGranularity : 0 - PMPNumRegions : 16 - -# experimental-maxperf-pmp config above with full bitmanip extension -experimental-maxperf-pmp-bmfull: - RV32E : 0 - RV32M : "cve2_pkg::RV32MSingleCycle" - RV32B : "cve2_pkg::RV32BFull" - RegFile : "cve2_pkg::RegFileFF" - WritebackStage : 1 - PMPEnable : 1 - PMPGranularity : 0 - PMPNumRegions : 16 - -# experimental-maxperf with branch predictor switched on. This exists to allow -# easy use of Ibex with the branch predictor in particular for CI runs. The -# branch predictor will be enabled in all the 'maxperf' configs after further -# development. -experimental-branch-predictor: - RV32E : 0 - RV32M : "cve2_pkg::RV32MSingleCycle" - RV32B : "cve2_pkg::RV32BNone" - RegFile : "cve2_pkg::RegFileFF" - WritebackStage : 1 - PMPEnable : 0 - PMPGranularity : 0 - PMPNumRegions : 4 + # RV32B : "cve2_pkg::RV32BNone" + # PMPEnable : 0 + # PMPGranularity : 0 + # PMPNumRegions : 4 diff --git a/cve2_core.core b/cve2_core.core index 6d621a4370..3661763672 100644 --- a/cve2_core.core +++ b/cve2_core.core @@ -1,9 +1,10 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "openhwgroup:cve2:cve2_core:0.1" -description: "Ibex CPU Core Components" +description: "CVE2 CPU Core Components" filesets: files_rtl: diff --git a/cve2_icache.core b/cve2_icache.core index ad2c2617ad..d4d1ba668a 100644 --- a/cve2_icache.core +++ b/cve2_icache.core @@ -1,15 +1,16 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:cve2:cve2_icache:0.1" -description: "Ibex instruction cache" +name: "openhwgroup:cve2:cve2_icache:0.1" +description: "CVE2 instruction cache" filesets: files_rtl: depend: - lowrisc:prim:secded - lowrisc:prim:assert - - lowrisc:cve2:cve2_pkg + - openhwgroup:cve2:cve2_pkg files: - rtl/cve2_icache.sv file_type: systemVerilogSource @@ -19,4 +20,4 @@ targets: filesets: - files_rtl toplevel: cve2_icache - default_tool: vcs + default_tool: vcs \ No newline at end of file diff --git a/cve2_multdiv.core b/cve2_multdiv.core index 700e6c9e2c..e397f1936f 100644 --- a/cve2_multdiv.core +++ b/cve2_multdiv.core @@ -1,15 +1,16 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:cve2:cve2_multdiv:0.1" +name: "openhwgroup:cve2:cve2_multdiv:0.1" description: "Multiplier and divider" filesets: files_rtl: depend: - lowrisc:prim:assert - - lowrisc:cve2:cve2_pkg + - openhwgroup:cve2:cve2_pkg files: - rtl/cve2_multdiv_fast.sv - rtl/cve2_multdiv_slow.sv diff --git a/cve2_top.core b/cve2_top.core index cb4e23b4cb..405a580f61 100644 --- a/cve2_top.core +++ b/cve2_top.core @@ -1,9 +1,10 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "openhwgroup:cve2:cve2_top:0.1" -description: "Ibex, a small RV32 CPU core" +description: "A single-issue 2-stage pipeline embedded class of RISC-V CPUs" filesets: files_rtl: @@ -33,7 +34,7 @@ filesets: files_clk_gate: files: - - bhv/cve2_sim_clock_gate.sv + - rtl/cve2_clock_gate.sv file_type: systemVerilogSource parameters: @@ -51,6 +52,16 @@ parameters: default: false paramtype: vlogdefine + MHPMCounterNum: + datatype: int + default: 10 + paramtype: vlogparam + + MHPMCounterWidth: + datatype: int + default: 40 + paramtype: vlogparam + RV32E: datatype: int default: 0 @@ -62,11 +73,11 @@ parameters: paramtype: vlogdefine description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values." - RV32B: - datatype: str - default: cve2_pkg::RV32BNone - paramtype: vlogdefine - description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values." +# RV32B: +# datatype: str +# default: cve2_pkg::RV32BNone +# paramtype: vlogdefine +# description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values." targets: default: &default_target @@ -84,6 +95,10 @@ targets: parameters: - SYNTHESIS=true - RVFI=true + - MHPMCounterNum + - MHPMCounterWidth + - RV32E + - RV32M filesets_append: - files_clk_gate default_tool: verilator @@ -91,10 +106,13 @@ targets: verilator: mode: lint-only verilator_options: - - "-Wall" + # - "-Wall" # RAM primitives wider than 64bit (required for ECC) fail to build in # Verilator without increasing the unroll count (see Verilator#1266) - "--unroll-count 72" + - "-Wno-COMBDLY" + - "-Wno-WIDTHEXPAND" + - "-Wno-WIDTHTRUNC" format: filesets: @@ -102,6 +120,10 @@ targets: parameters: - SYNTHESIS=true - RVFI=true + - MHPMCounterNum + - MHPMCounterWidth + - RV32E + - RV32M default_tool: veribleformat toplevel: cve2_top tools: diff --git a/cve2_top_tracing.core b/cve2_top_tracing.core index 65d2b5b77c..01c3d58f13 100644 --- a/cve2_top_tracing.core +++ b/cve2_top_tracing.core @@ -1,18 +1,24 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:cve2:cve2_top_tracing:0.1" -description: "Ibex, a small RV32 CPU core with tracing enabled" +name: "openhwgroup:cve2:cve2_top_tracing:0.1" +description: "CVE2, a small RV32 CPU core with tracing enabled" filesets: files_rtl: depend: - - lowrisc:cve2:cve2_top - - lowrisc:cve2:cve2_tracer + - openhwgroup:cve2:cve2_top + - openhwgroup:cve2:cve2_tracer files: - rtl/cve2_top_tracing.sv file_type: systemVerilogSource + files_clk_gate: + files: + - rtl/cve2_clock_gate.sv + file_type: systemVerilogSource + parameters: # The tracer uses the RISC-V Formal Interface (RVFI) to collect trace signals. RVFI: @@ -35,70 +41,21 @@ parameters: paramtype: vlogdefine description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values." - RV32B: - datatype: str - default: cve2_pkg::RV32BNone - paramtype: vlogdefine - description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values." - - RegFile: - datatype: str - default: cve2_pkg::RegFileFF - paramtype: vlogdefine - description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values." - - ICache: - datatype: int - default: 0 - paramtype: vlogparam - description: "Enable instruction cache" - - ICacheECC: - datatype: int - default: 0 - paramtype: vlogparam - description: "Enable ECC protection in instruction cache" - - WritebackStage: + MHPMCounterNum: datatype: int - default: 0 - paramtype: vlogparam - description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]" - - SecureCVE2: - datatype: int - default: 0 - paramtype: vlogparam - description: "Enables security hardening features (EXPERIMENTAL) [0/1]" - - ICacheScramble: - datatype: int - default: 0 - paramtype: vlogparam - description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]" - - PMPEnable: - datatype: int - default: 0 - paramtype: vlogparam - description: "Enable PMP" - - PMPGranularity: - datatype: int - default: 0 + default: 10 paramtype: vlogparam - description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc" - PMPNumRegions: + MHPMCounterWidth: datatype: int - default: 4 + default: 40 paramtype: vlogparam - description: "Number of PMP regions" targets: default: &default_target filesets: - files_rtl + - target_sim ? (files_clk_gate) parameters: - RVFI=true toplevel: cve2_top_tracing @@ -110,25 +67,22 @@ targets: - SYNTHESIS=true - RV32E - RV32M - - RV32B - - RegFile - - ICache - - ICacheECC - - WritebackStage - - SecureCVE2 - - ICacheScramble - - PMPEnable - - PMPGranularity - - PMPNumRegions + - MHPMCounterNum + - MHPMCounterWidth + filesets_append: + - files_clk_gate default_tool: verilator tools: verilator: mode: lint-only verilator_options: - - "-Wall" + # - "-Wall" # RAM primitives wider than 64bit (required for ECC) fail to build in # Verilator without increasing the unroll count (see Verilator#1266) - "--unroll-count 72" + - "-Wno-COMBDLY" + - "-Wno-WIDTHEXPAND" + - "-Wno-WIDTHTRUNC" format: filesets: - files_rtl diff --git a/cve2_tracer.core b/cve2_tracer.core index 0e43a80624..219d69c43a 100644 --- a/cve2_tracer.core +++ b/cve2_tracer.core @@ -1,14 +1,15 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:cve2:cve2_tracer:0.1" -description: "Tracer for use with Ibex using the RVFI interface" +name: "openhwgroup:cve2:cve2_tracer:0.1" +description: "Tracer for use with CVE2 using the RVFI interface" filesets: files_rtl: depend: - lowrisc:prim:assert - - lowrisc:cve2:cve2_pkg + - openhwgroup:cve2:cve2_pkg files: - rtl/cve2_tracer_pkg.sv - rtl/cve2_tracer.sv diff --git a/doc/01_specification/index.rst b/doc/01_specification/index.rst index eaaa026b99..6d882ac159 100644 --- a/doc/01_specification/index.rst +++ b/doc/01_specification/index.rst @@ -58,7 +58,7 @@ The specification is complemented by a :ref:`user's guide`. A `List of Abbreviations`_ is available at the end of this document. -This development is co-sponsored by NXP and Intrinsix ( acquired by Cadence Design Systems in 2023...), and by the EU-funded `TRISTAN project `_. +This development is co-sponsored by NXP, Intrinsix (acquired by Cadence Design Systems in 2023) and by the EU-funded `TRISTAN project `_. Scope ===== @@ -101,6 +101,8 @@ As displayed in the above figure, the IP comprises: - Support for basic set of Configuration & Status Registers (:term:`CSRs`) + - Optional support for the Core-V eXtension Interface (:term:`CV-X-IF`) [X-IF]_ + At the :term:`coreplex` design level, the following functions are added to the processor core: @@ -131,25 +133,40 @@ The following topics are beyond the scope of this specification: - Other features included in the testbench (main memory, firmware, interconnect…), the coverage of which are not measured -Golden configurations ---------------------- +Configurations +-------------- + +The CVE2 member of CORE-V family or RISC-V cores, under its currently +unique named cv32e20, can be set into one of the many configurations +listed below, varying on the destination hardware target and the presence +of the :term:`CV-X-IF` support. + + ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ +| **Configuration** | **Target** | **RV32{E,I} ISA** | Golden | CV-X-IF | **TRL** | ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ +| cv32e20_emc_fpga | :term:`FPGA` | RV32EMC | Yes | No | | ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ +| cv32e20_imc_fpga | FPGA | RV32IMC | Yes | No | | ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ +| cv32e20_emc_asic | :term:`ASIC` | RV32EMC | Yes | No | | ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ +| cv32e20_imc_asic | ASIC | RV32IMC | Yes | No | | ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ +| cv32e20x_emc_fpga | FPGA | RV32EMC | No | Yes | | ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ +| cv32e20x_imc_fpga | FPGA | RV32IMC | No | Yes | | ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ +| cv32e20x_emc_asic | ASIC | RV32EMC | No | Yes | | ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ +| cv32e20x_imc_asic | ASIC | RV32IMC | No | Yes | | ++-----------------------------+-----------------+-------------------+-----------+-----------+---------+ It is not possible to verify all 2\ :sup:`n` combinations of design -parameters. Below is the list of golden configurations that will undergo -verification in the project and their main parameters. The full list of -parameters for each golden configuration are detailed in the user guide. - -+----------------------------+-----------------+----------------------+-------+ -| **Configuration** | **Target** | **RV32{E,I} ISA** |**TRL**| -+----------------------------+-----------------+----------------------+-------+ -| cv32e2_emc_fpga | :term:`FPGA` | RV32EMC | | -+----------------------------+-----------------+----------------------+-------+ -| cv32e2_imc_fpga | FPGA | RV32IMC | | -+----------------------------+-----------------+----------------------+-------+ -| cv32e2_emc_asic | :term:`ASIC` | RV32EMC | | -+----------------------------+-----------------+----------------------+-------+ -| cv32e2_imc_asic | ASIC | RV32IMC | | -+----------------------------+-----------------+----------------------+-------+ +parameters. The list of configurations and their main parameters that will +undergo thorough verification is set by the "Golden" column of the table. +The full list of parameters for each golden configuration are detailed in +the user guide. References ========== @@ -180,6 +197,9 @@ identify the versions of RISC-V extensions from these specifications. .. [OPENHW-OBI] OpenHW Open Bus Interface (OBI) protocol, version 1.4, https://github.com/openhwgroup/obi/blob/main/OBI-v1.4.pdf +.. [X-IF] OpenHW Group Specification: Core-V eXtension interface (CV-X-IF), version v1.0.0, + https://github.com/openhwgroup/core-v-xif/releases/tag/v1.0.0 + .. [AMBA-AHB] “AMBA® AHB Protocol Specification”, ARM IHI 0033C (ID090921), https://developer.arm.com/documentation/ihi0033/latest @@ -676,13 +696,13 @@ Coprocessor interface +--------+-------------------------------------------------------------+ | XIF-10 | For *subsequent* core implementations, CV32E20 shall | -| | support the coprocessor interface compliant with [CV-X-IF] | +| | support the coprocessor interface compliant with [X-IF] | | | to extend the supported instructions. The goal is a set of | | | compatible interfaces between the CORE-V cores, for | | | example, CV32E40{P,S,X}, CV32E20, … | | | | | | The initial version of CV32E20 shall not support the | -| | CV-X-IF coprocessor interface. | +| | :term:`CV-X-IF` coprocessor interface. | +--------+-------------------------------------------------------------+ PPA targets @@ -716,6 +736,7 @@ integrated in the continuous integration flow. | | CV32E20\_?\_fpga configuration on Kintex 7 FPGA technology. | | | | | | Metric details to be supplied later. | +.. TODO PPA-30 Clock frequency requirement on a FPGA implementation +--------+-------------------------------------------------------------+ | PPA-50 | CV32E20 should operate at more than ? MHz in the | | | CV32E20\_? configuration on 16-nm FFT technology in the | @@ -723,6 +744,7 @@ integrated in the continuous integration flow. | | voltage. | | | | | | Metric details to be supplied later. | +.. TODO PPA-50 Clock frequency requirement on an (16nm FinFET) ASIC implementation +--------+-------------------------------------------------------------+ Physical design rules @@ -793,7 +815,7 @@ List of abbreviations Control and Status Register CV-X-IF - Core-V Coprocessor (X) Interface + Core-V eXtension Interface DTM Debug Transport Module diff --git a/doc/Makefile b/doc/Makefile index 2b8ed89d96..fff3fce36e 100644 --- a/doc/Makefile +++ b/doc/Makefile @@ -4,7 +4,7 @@ # You can set these variables from the command line. SPHINXOPTS = SPHINXBUILD = sphinx-build -SPHINXPROJ = ibex +SPHINXPROJ = cve2 SOURCEDIR = . BUILDDIR = _build diff --git a/doc/make.bat b/doc/make.bat index 8a1058b722..dcb6e409f0 100644 --- a/doc/make.bat +++ b/doc/make.bat @@ -9,7 +9,7 @@ if "%SPHINXBUILD%" == "" ( ) set SOURCEDIR=. set BUILDDIR=_build -set SPHINXPROJ=ibex +set SPHINXPROJ=cve2 if "%1" == "" goto help diff --git a/dv/riscv_compliance/README.md b/dv/riscv_compliance/README.md index 5a4ad69e0f..067e939f1c 100644 --- a/dv/riscv_compliance/README.md +++ b/dv/riscv_compliance/README.md @@ -1,16 +1,30 @@ -Ibex simulation for RISC-V Compliance Testing +CVE2 simulation for RISC-V Compliance Testing ============================================= -This directory contains a compiled simulation of Ibex to be used as target +--- +**NOTE** + +**This document is NOT up-to-date**. + +The RISC-V Compliance check, originally referred in this document made for +lowRISC's Ibex core, [was made obsolete](https://github.com/riscv-non-isa/riscv-arch-test/tree/old-framework-2.x) +as of 1st May 2022 in favour of the [RISC-V Architectural Test Framework (RISCOF)](https://github.com/riscv-software-src/riscof). + +At the time of writing, we are working to adapt the instructions of this +document to work with the RISCOF project - see issue [#221](https://github.com/openhwgroup/cve2/issues/221) of the repository. + +--- + + +This directory contains a compiled simulation of CVE2 to be used as target in the [RISC-V Compliance Test](https://github.com/riscv/riscv-compliance). -In addition to Ibex itself, it contains a 64 kB RAM and a memory-mapped helper +In addition to CVE2 itself, it contains a 64 kB RAM and a memory-mapped helper module to interact with the software, e.g. to dump out the test signature and to end the simulation. -The simulation is designed for Verilator, but can be adapted to other simulators -if needed. +The simulation is designed for Verilator, but can be adapted to other simulators if needed. -How to run RISC-V Compliance on Ibex +How to run RISC-V Compliance on CVE2 ------------------------------------ 0. Check your prerequisites @@ -33,21 +47,23 @@ How to run RISC-V Compliance on Ibex https://www.veripool.org/projects/verilator/wiki/Installing for installation instructions. -1. Build a simulation of Ibex +1. Build a simulation of CVE2 ```sh - cd $IBEX_REPO_BASE - fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_riscv_compliance --RV32E=0 --RV32M=cve2_pkg::RV32MNone + cd $CVE2_REPO_BASE + fusesoc --cores-root=. run --target=sim --setup --build openhwgroup:cve2:cve2_riscv_compliance --RV32E=0 --RV32M=cve2_pkg::RV32MNone ``` You can use the two compile-time options `--RV32M` and `--RV32E` to enable/disable the M and E ISA extensions, respectively. - You can now find the compiled simulation at `build/lowrisc_cve2_cve2_riscv_compliance_0.1/sim-verilator/Vcve2_riscv_compliance`. + You can now find the compiled simulation at `build/openhwgroup_cve2_cve2_riscv_compliance_0.1/sim-verilator/Vcve2_riscv_compliance`. 2. Get the RISC-V Compliance test suite - The upstream RISC-V compliance test suite supports Ibex out of the box. + The upstream RISC-V compliance test suite supports Ibex out of the box, + but still need to be adapted to the CVE2. + ``` git clone https://github.com/riscv/riscv-compliance.git @@ -58,13 +74,13 @@ How to run RISC-V Compliance on Ibex ```sh cd $RISCV_COMPLIANCE_REPO_BASE # adjust to match your compiler name - export RISCV_PREFIX=riscv32-unknown-elf- + export RISCV_PREFIX=riscv32-unknown-elf- # or riscv32-corev-elf- # give the absolute path to the simulation binary compiled in step 1 - export TARGET_SIM=/path/to/your/Vcve2_riscv_compliance + # e.g. export TARGET_SIM=/path/to/your/Vcve2_riscv_compliance + export TARGET_SIM=../../build/openhwgroup_cve2_cve2_riscv_compliance_0.1/sim-verilator/Vcve2_riscv_compliance export RISCV_DEVICE=rv32imc - export RISCV_TARGET=ibex - + export RISCV_TARGET=cve2 # ibex # Note: rv32imc does not include the I and M extension tests make RISCV_ISA=rv32i && make RISCV_ISA=rv32im && make RISCV_ISA=rv32imc && \ make RISCV_ISA=rv32Zicsr && make RISCV_ISA=rv32Zifencei @@ -76,7 +92,7 @@ Compliance test suite system This directory contains a system designed especially to run the compliance test suite. The system consists of -- an Ibex core, +- a CVE2 core, - a bus, - a single-port memory for data and instructions, - a bus-attached test utility. diff --git a/dv/riscv_compliance/cve2_riscv_compliance.core b/dv/riscv_compliance/cve2_riscv_compliance.core index bcc129babb..a34b44539b 100644 --- a/dv/riscv_compliance/cve2_riscv_compliance.core +++ b/dv/riscv_compliance/cve2_riscv_compliance.core @@ -1,14 +1,15 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:cve2:cve2_riscv_compliance:0.1" -description: "Ibex simulation for RISC-V compliance testing (using Verilator)" +name: "openhwgroup:cve2:cve2_riscv_compliance:0.1" +description: "CVE2 simulation for RISC-V compliance testing (using Verilator)" filesets: files_sim: depend: - - lowrisc:cve2:cve2_top_tracing - - lowrisc:cve2:sim_shared + - openhwgroup:cve2:cve2_top_tracing + - openhwgroup:cve2:sim_shared files: - rtl/cve2_riscv_compliance.sv - rtl/riscv_testutil.sv @@ -35,59 +36,69 @@ parameters: paramtype: vlogdefine description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values." - RV32B: - datatype: str - default: cve2_pkg::RV32BNone - paramtype: vlogdefine - description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values." +# RV32B: +# datatype: str +# default: cve2_pkg::RV32BNone +# paramtype: vlogdefine +# description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values." - RegFile: - datatype: str - default: cve2_pkg::RegFileFF - paramtype: vlogdefine - description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values." +# RegFile: +# datatype: str +# default: cve2_pkg::RegFileFF +# paramtype: vlogdefine +# description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values." - ICache: + MHPMCounterNum: datatype: int - default: 0 + default: 10 paramtype: vlogparam - description: "Enable instruction cache" - ICacheECC: + MHPMCounterWidth: datatype: int - default: 0 + default: 40 paramtype: vlogparam - description: "Enable ECC protection in instruction cache" - PMPEnable: - datatype: int - default: 0 - paramtype: vlogparam - description: "Enable PMP" +# ICache: +# datatype: int +# default: 0 +# paramtype: vlogparam +# description: "Enable instruction cache" - PMPGranularity: - datatype: int - default: 0 - paramtype: vlogparam - description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc" +# ICacheECC: +# datatype: int +# default: 0 +# paramtype: vlogparam +# description: "Enable ECC protection in instruction cache" - PMPNumRegions: - datatype: int - default: 4 - paramtype: vlogparam - description: "Number of PMP regions" +# PMPEnable: +# datatype: int +# default: 0 +# paramtype: vlogparam +# description: "Enable PMP" - SecureIbex: - datatype: int - paramtype: vlogparam - default: 0 - description: "Enables security hardening features (EXPERIMENTAL) [0/1]" +# PMPGranularity: +# datatype: int +# default: 0 +# paramtype: vlogparam +# description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc" - ICacheScramble: - datatype: int - paramtype: vlogparam - default: 0 - description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]" +# PMPNumRegions: +# datatype: int +# default: 4 +# paramtype: vlogparam +# description: "Number of PMP regions" + +# SecureCVE2: +# datatype: int +# paramtype: vlogparam +# default: 0 +# description: "Enables security hardening features (EXPERIMENTAL) [0/1]" + +# ICacheScramble: +# datatype: int +# paramtype: vlogparam +# default: 0 +# description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]" targets: sim: @@ -98,15 +109,17 @@ targets: parameters: - RV32E - RV32M - - RV32B - - RegFile - - ICache - - ICacheECC - - PMPEnable - - PMPGranularity - - PMPNumRegions - - SecureIbex - - ICacheScramble +# - RV32B +# - RegFile + - MHPMCounterNum + - MHPMCounterWidth +# - ICache +# - ICacheECC +# - PMPEnable +# - PMPGranularity +# - PMPNumRegions +# - SecureCVE2 +# - ICacheScramble toplevel: cve2_riscv_compliance tools: verilator: @@ -119,6 +132,9 @@ targets: - '--trace-structs' - '--trace-params' - '--trace-max-array 1024' - - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=cve2_riscv_compliance -g"' + - '-CFLAGS "-std=c++14 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=cve2_riscv_compliance -g"' - '-LDFLAGS "-pthread -lutil -lelf"' - - "-Wall" + # - "-Wall" + - "-Wno-COMBDLY" + - "-Wno-WIDTHEXPAND" + - "-Wno-WIDTHTRUNC" diff --git a/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv b/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv index 2ff1f7f344..196304897b 100644 --- a/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv +++ b/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv @@ -1,5 +1,5 @@ // Copyright lowRISC contributors. -// Copyright 2025 OpenHW Group. +// Copyright (c) 2025 Eclipse Foundation // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -16,17 +16,10 @@ module cve2_riscv_compliance ( input IO_RST_N ); - parameter bit PMPEnable = 1'b0; - parameter int unsigned PMPGranularity = 0; - parameter int unsigned PMPNumRegions = 4; - parameter bit RV32E = 1'b0; - parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast; - parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone; - parameter cve2_pkg::regfile_e RegFile = cve2_pkg::RegFileFF; - parameter bit ICache = 1'b0; - parameter bit ICacheECC = 1'b0; - parameter bit SecureIbex = 1'b0; - parameter bit ICacheScramble = 1'b0; + parameter int unsigned MHPMCounterNum = 10; + parameter int unsigned MHPMCounterWidth = 40; + parameter bit RV32E = 1'b0; + parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast; logic clk_sys, rst_sys_n; @@ -112,23 +105,16 @@ module cve2_riscv_compliance ( ); cve2_top_tracing #( - .PMPEnable (PMPEnable ), - .PMPGranularity (PMPGranularity ), - .PMPNumRegions (PMPNumRegions ), + .MHPMCounterNum (MHPMCounterNum ), + .MHPMCounterWidth(MHPMCounterWidth), .RV32E (RV32E ), - .RV32M (RV32M ), - .RV32B (RV32B ), - .RegFile (RegFile ), - .ICache (ICache ), - .ICacheECC (ICacheECC ), - .SecureIbex (SecureIbex ), - .ICacheScramble (ICacheScramble ) + .RV32M (RV32M ) ) u_top ( .clk_i (clk_sys ), .rst_ni (rst_sys_n ), .test_en_i ('b0 ), - .scan_rst_ni (1'b1 ), + // .scan_rst_ni (1'b1 ), .ram_cfg_i ('b0 ), .hart_id_i (32'b0 ), @@ -140,7 +126,7 @@ module cve2_riscv_compliance ( .instr_rvalid_i (host_rvalid[CoreI] ), .instr_addr_o (host_addr[CoreI] ), .instr_rdata_i (host_rdata[CoreI] ), - .instr_rdata_intg_i ('0 ), + // .instr_rdata_intg_i ('0 ), .instr_err_i (host_err[CoreI] ), .data_req_o (host_req[CoreD] ), @@ -150,33 +136,47 @@ module cve2_riscv_compliance ( .data_be_o (host_be[CoreD] ), .data_addr_o (host_addr[CoreD] ), .data_wdata_o (host_wdata[CoreD] ), - .data_wdata_intg_o ( ), + // .data_wdata_intg_o ( ), .data_rdata_i (host_rdata[CoreD] ), - .data_rdata_intg_i ('0 ), + // .data_rdata_intg_i ('0 ), .data_err_i (host_err[CoreD] ), + .x_issue_valid_o ( ), + .x_issue_ready_i ('0 ), + .x_issue_req_o ( ), + .x_issue_resp_i ('0 ), + + .x_register_o ( ), + + .x_commit_valid_o ( ), + .x_commit_o ( ), + + .x_result_valid_i ('0 ), + .x_result_ready_o ( ), + .x_result_i ('0 ), + .irq_software_i (1'b0 ), .irq_timer_i (1'b0 ), .irq_external_i (1'b0 ), .irq_fast_i (15'b0 ), .irq_nm_i (1'b0 ), - .scramble_key_valid_i ('0 ), - .scramble_key_i ('0 ), - .scramble_nonce_i ('0 ), - .scramble_req_o ( ), + // .scramble_key_valid_i ('0 ), + // .scramble_key_i ('0 ), + // .scramble_nonce_i ('0 ), + // .scramble_req_o ( ), .debug_req_i ('b0 ), .debug_halted_o ( ), .dm_halt_addr_i (32'h00000000 ), .dm_exception_addr_i (32'h00000000 ), .crash_dump_o ( ), - .double_fault_seen_o ( ), + // .double_fault_seen_o ( ), - .fetch_enable_i (cve2_pkg::FetchEnableOn), - .alert_minor_o ( ), - .alert_major_internal_o ( ), - .alert_major_bus_o ( ), + .fetch_enable_i (1'b1 ), + // .alert_minor_o ( ), + // .alert_major_internal_o ( ), + // .alert_major_bus_o ( ), .core_sleep_o ( ) ); diff --git a/formal/.gitignore b/formal/.gitignore index 4a1cec9c32..2fee4c5df2 100644 --- a/formal/.gitignore +++ b/formal/.gitignore @@ -1,2 +1,2 @@ build/ -ibex.v +cve2.v diff --git a/formal/data_ind_timing/Makefile b/formal/data_ind_timing/Makefile index 701617bdb2..e7ae61e4c7 100644 --- a/formal/data_ind_timing/Makefile +++ b/formal/data_ind_timing/Makefile @@ -1,10 +1,11 @@ +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # A simple wrapper around fusesoc to make it a bit easier to run the formal flow -core-name := lowrisc:fpv:cve2_data_ind_timing +core-name := openhwgroup:fpv:cve2_data_ind_timing vlnv := $(subst :,_,$(core-name)) build-root := $(abspath ../../build/$(vlnv)) diff --git a/formal/data_ind_timing/cve2_data_ind_timing.core b/formal/data_ind_timing/cve2_data_ind_timing.core index 93210241f6..555b05879a 100644 --- a/formal/data_ind_timing/cve2_data_ind_timing.core +++ b/formal/data_ind_timing/cve2_data_ind_timing.core @@ -1,16 +1,17 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:fpv:cve2_data_ind_timing:0.1" +name: "openhwgroup:fpv:cve2_data_ind_timing:0.1" description: "Formal test for data independent timing" filesets: testbench: depend: - - lowrisc:cve2:cve2_pkg - - lowrisc:cve2:cve2_multdiv + - openhwgroup:cve2:cve2_pkg + - openhwgroup:cve2:cve2_multdiv - lowrisc:util:sv2v files: - run.sby.j2 : {file_type: sbyConfigTemplate} diff --git a/formal/icache/Makefile b/formal/icache/Makefile index ee2638e465..92d9991372 100644 --- a/formal/icache/Makefile +++ b/formal/icache/Makefile @@ -7,7 +7,7 @@ # Whether to use ECC (0 for disabled; 1 for enabled) ECC := 0 -core-name := lowrisc:fpv:cve2_icache_fpv +core-name := openhwgroup:fpv:cve2_icache_fpv vlnv := $(subst :,_,$(core-name)) build-root := $(abspath ../../build/$(vlnv)) diff --git a/formal/icache/cve2_icache_fpv.core b/formal/icache/cve2_icache_fpv.core index 1afb51538e..ef05c1d4ca 100644 --- a/formal/icache/cve2_icache_fpv.core +++ b/formal/icache/cve2_icache_fpv.core @@ -1,15 +1,16 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:fpv:cve2_icache_fpv:0.1" -description: "Formal properties for Ibex ICache" +name: "openhwgroup:fpv:cve2_icache_fpv:0.1" +description: "Formal properties for CVE2 ICache" filesets: all: depend: - - lowrisc:cve2:cve2_icache + - openhwgroup:cve2:cve2_icache - lowrisc:prim:assert - lowrisc:util:sv2v files: diff --git a/formal/riscv-formal/Makefile b/formal/riscv-formal/Makefile index b577feb8ba..c336b0c616 100644 --- a/formal/riscv-formal/Makefile +++ b/formal/riscv-formal/Makefile @@ -1,12 +1,13 @@ +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -# Provide a convenient way to create a Verilog source of Ibex. +# Provide a convenient way to create a Verilog source of CVE2. # This is used by riscv-formal. See README.md for more details. # Name of the output file -IBEX_OUT := ibex.v +CVE2_OUT := cve2.v # Build folder name OUTDIR := build @@ -24,8 +25,9 @@ INC_DIRS := \ $(LOWRISC_IP)/ip/prim/rtl \ $(LOWRISC_IP)/dv/sv/dv_utils -# SystemVerilog sources of Ibex +# SystemVerilog sources of CVE2 SRCS_SV ?= \ + $(SRC_DIR)/cve2_clock_gate.sv \ $(SRC_DIR)/cve2_alu.sv \ $(SRC_DIR)/cve2_compressed_decoder.sv \ $(SRC_DIR)/cve2_controller.sv \ @@ -51,11 +53,9 @@ PKGS ?= \ $(SRC_DIR)/cve2_pkg.sv \ $(LOWRISC_IP)/ip/prim/rtl/prim_ram_1p_pkg.sv -PRIM_CLOCK ?= $(SYN_DIR)/rtl/prim_clock_gating.v - GEN_V := $(patsubst %.sv,%.v,$(patsubst $(SRC_DIR)%,$(OUTDIR)%,$(SRCS_SV))) -all: $(IBEX_OUT) +all: $(CVE2_OUT) verilog: $(GEN_V) @@ -67,14 +67,14 @@ $(GEN_V): $(OUTDIR)%.v: $(SRC_DIR)%.sv $(PKGS) | $(OUTDIR) sv2v --define=RISCV_FORMAL $(addprefix -I,$(INC_DIRS)) $(PKGS) \ $< > $@ -# Combine multiple Verilog sources into one Ibex Verilog file +# Combine multiple Verilog sources into one CVE2 Verilog file # Disable "M" extension -$(IBEX_OUT): $(GEN_V) $(PRIM_CLOCK) - yosys -p "read_verilog $(PRIM_CLOCK) $(GEN_V)" \ - -p "chparam -set RV32M 0 cve2_top" \ - -p "synth -top cve2_top" \ - -p "write_verilog $(IBEX_OUT)" +$(CVE2_OUT): $(GEN_V) + yosys -p "read_verilog $(GEN_V)" \ + -p "chparam -set RV32M 0 cve2_top" \ + -p "synth -top cve2_top" \ + -p "write_verilog $(CVE2_OUT)" .PHONY: clean clean: - -rm -rf $(IBEX_OUT) $(OUTDIR) + -rm -rf $(CVE2_OUT) $(OUTDIR) diff --git a/formal/riscv-formal/README.md b/formal/riscv-formal/README.md index b1007b5b14..cd52474202 100644 --- a/formal/riscv-formal/README.md +++ b/formal/riscv-formal/README.md @@ -4,8 +4,8 @@ The Verilog source created here is used by [riscv-formal](https://github.com/SymbioticEDA/riscv-formal). -Riscv-formal uses Yosys, but the SystemVerilog front-end of Yosys does not support all the language features used by Ibex. -The `Makefile` provided here uses sv2v and Yosys to create a single Verilog source of Ibex. +Riscv-formal uses Yosys, but the SystemVerilog front-end of Yosys does not support all the language features used by CVE2. +The `Makefile` provided here uses sv2v and Yosys to create a single Verilog source of CVE2. This flow has some similarities to [syn](../syn/README.md), but uses only a simplified subset. @@ -24,13 +24,13 @@ The "M" extension is currently disabled. ## Usage -It should not be necessary to create the Verilog source manually as it is used by the riscv-formal Ibex build system. +It should not be necessary to create the Verilog source manually as it is used by the riscv-formal CVE2 build system. -Run the following command from the top level directory of Ibex to create the Verilog source. +Run the following command from the top level directory of CVE2 to create the Verilog source. ```console make -C formal/riscv-formal ``` This will create a directory *formal/riscv-formal/build* which contains an equivalent Verilog file for each SystemVerilog source. -The single output file *formal/riscv-formal/ibex.v* contains the complete Ibex source, which can then be imported by riscv-formal. +The single output file *formal/riscv-formal/cve2.v* contains the complete CVE2 source, which can then be imported by riscv-formal. diff --git a/lint/verilator_waiver.vlt b/lint/verilator_waiver.vlt index bac40c20f7..e690729235 100644 --- a/lint/verilator_waiver.vlt +++ b/lint/verilator_waiver.vlt @@ -70,7 +70,6 @@ lint_off -file "*/lowrisc_prim_*/rtl/*.sv" lint_off -rule UNUSED -file "*/rtl/cve2_top_tracing.sv" -match "*RndCnstLfsrSeed*" lint_off -rule UNUSED -file "*/rtl/cve2_top_tracing.sv" -match "*RndCnstLfsrPerm*" -lint_off -rule DECLFILENAME -file "*/bhv/cve2_sim_clock_gate.sv" -match "Filename 'cve2_sim_clock_gate' does not match MODULE name: 'cve2_clock_gate'" lint_off -rule UNOPTFLAT -file "*/rtl/cve2_core.sv" -match "Signal unoptimizable: Feedback to clock or circular logic: 'cve2_top.u_cve2_core.irqs'" lint_off -rule UNUSED -file "*/rtl/cve2_wb.sv" -match "Signal is not used: 'clk_i'*" lint_off -rule UNUSED -file "*/rtl/cve2_wb.sv" -match "Signal is not used: 'rst_ni'*" diff --git a/python-requirements.txt b/python-requirements.txt index 6fa63fbd8e..235a059b5d 100644 --- a/python-requirements.txt +++ b/python-requirements.txt @@ -12,7 +12,7 @@ pyyaml mako junit-xml -# Needed by dvsim.py (not actually used in Ibex) +# Needed by dvsim.py (not actually used in CVE2) hjson mistletoe>=0.7.2 # Premailer 3.9.0 broke the API by introducing an allow_loading_external_files @@ -22,4 +22,7 @@ mistletoe>=0.7.2 premailer < 3.9.0 # Recurse to get any requirements from riscv-dv --r vendor/google_riscv-dv/requirements.txt +# -r vendor/google_riscv-dv/requirements.txt + +# Used by python-lint +mypy diff --git a/rtl/cve2_alu.sv b/rtl/cve2_alu.sv index 2471c621e0..e233e85894 100644 --- a/rtl/cve2_alu.sv +++ b/rtl/cve2_alu.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. diff --git a/rtl/cve2_branch_predict.sv b/rtl/cve2_branch_predict.sv index e49c700743..2bc8bfc682 100644 --- a/rtl/cve2_branch_predict.sv +++ b/rtl/cve2_branch_predict.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/bhv/cve2_sim_clock_gate.sv b/rtl/cve2_clock_gate.sv similarity index 80% rename from bhv/cve2_sim_clock_gate.sv rename to rtl/cve2_clock_gate.sv index 7974cf926d..311db388d6 100644 --- a/bhv/cve2_sim_clock_gate.sv +++ b/rtl/cve2_clock_gate.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright 2017 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in @@ -8,7 +9,7 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -// !!! cve2_sim_clock_gate file is meant for simulation only !!! +// !!! cve2_clock_gate file is meant for simulation only !!! // !!! It must not be used for ASIC synthesis !!! // !!! It must not be used for FPGA synthesis !!! @@ -19,6 +20,11 @@ module cve2_clock_gate ( output logic clk_o ); + // `ifdef SYNTHESIS + // `error "cve2_clock_gate module is meant for simulation only. " \ + // "It should not be used for ASIC or FPGA synthesis" + // `endif + logic clk_en; always_latch begin diff --git a/rtl/cve2_compressed_decoder.sv b/rtl/cve2_compressed_decoder.sv index 1b5b17fff4..0ce2a4a7ec 100644 --- a/rtl/cve2_compressed_decoder.sv +++ b/rtl/cve2_compressed_decoder.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -283,21 +284,21 @@ module cve2_compressed_decoder ( //////////////// // The valid_i signal used to gate below assertions must be known. - `ASSERT_KNOWN(IbexInstrValidKnown, valid_i) + `ASSERT_KNOWN(CVE2InstrValidKnown, valid_i) // Selectors must be known/valid. - `ASSERT(IbexInstrLSBsKnown, valid_i |-> + `ASSERT(CVE2InstrLSBsKnown, valid_i |-> !$isunknown(instr_i[1:0])) - `ASSERT(IbexC0Known1, (valid_i && (instr_i[1:0] == 2'b00)) |-> + `ASSERT(CVE2C0Known1, (valid_i && (instr_i[1:0] == 2'b00)) |-> !$isunknown(instr_i[15:13])) - `ASSERT(IbexC1Known1, (valid_i && (instr_i[1:0] == 2'b01)) |-> + `ASSERT(CVE2C1Known1, (valid_i && (instr_i[1:0] == 2'b01)) |-> !$isunknown(instr_i[15:13])) - `ASSERT(IbexC1Known2, (valid_i && (instr_i[1:0] == 2'b01) && (instr_i[15:13] == 3'b100)) |-> + `ASSERT(CVE2C1Known2, (valid_i && (instr_i[1:0] == 2'b01) && (instr_i[15:13] == 3'b100)) |-> !$isunknown(instr_i[11:10])) - `ASSERT(IbexC1Known3, (valid_i && + `ASSERT(CVE2C1Known3, (valid_i && (instr_i[1:0] == 2'b01) && (instr_i[15:13] == 3'b100) && (instr_i[11:10] == 2'b11)) |-> !$isunknown({instr_i[12], instr_i[6:5]})) - `ASSERT(IbexC2Known1, (valid_i && (instr_i[1:0] == 2'b10)) |-> + `ASSERT(CVE2C2Known1, (valid_i && (instr_i[1:0] == 2'b10)) |-> !$isunknown(instr_i[15:13])) endmodule diff --git a/rtl/cve2_controller.sv b/rtl/cve2_controller.sv index fba4352f32..d14e9d2060 100644 --- a/rtl/cve2_controller.sv +++ b/rtl/cve2_controller.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -246,7 +247,7 @@ module cve2_controller #( end end - `ASSERT_IF(IbexExceptionPrioOnehot, + `ASSERT_IF(CVE2ExceptionPrioOnehot, $onehot({instr_fetch_err_prio, illegal_insn_prio, ecall_insn_prio, @@ -767,7 +768,7 @@ module cve2_controller #( //////////////// // Selectors must be known/valid. - `ASSERT(IbexCtrlStateValid, ctrl_fsm_cs inside { + `ASSERT(CVE2CtrlStateValid, ctrl_fsm_cs inside { RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH, IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID}) @@ -819,16 +820,16 @@ module cve2_controller #( // Once an exception request has been accepted it must be handled before controller goes back to // DECODE - `ASSERT(IbexNoDoubleExceptionReq, exception_req_accepted |-> ctrl_fsm_cs != DECODE) + `ASSERT(CVE2NoDoubleExceptionReq, exception_req_accepted |-> ctrl_fsm_cs != DECODE) // Only signal ready, allowing a new instruction into ID, if there is no exception request // pending or it is done this cycle. - `ASSERT(IbexDontSkipExceptionReq, + `ASSERT(CVE2DontSkipExceptionReq, id_in_ready_o |-> !exception_req_pending || exception_req_done) // Once a PC set has been performed for an exception request there must not be any other // excepting those to move into debug mode. - `ASSERT(IbexNoDoubleSpecialReqPCSet, + `ASSERT(CVE2NoDoubleSpecialReqPCSet, seen_exception_pc_set && !((ctrl_fsm_cs inside {DBG_TAKEN_IF, DBG_TAKEN_ID}) && (pc_mux_o == PC_EXC) && (exc_pc_mux_o == EXC_PC_DBD)) @@ -836,12 +837,12 @@ module cve2_controller #( // When an exception request is done there must have been an appropriate PC set (either this // cycle or a previous one). - `ASSERT(IbexSetExceptionPCOnSpecialReqIfExpected, + `ASSERT(CVE2SetExceptionPCOnSpecialReqIfExpected, exception_req_pending && expect_exception_pc_set && exception_req_done |-> seen_exception_pc_set || exception_pc_set) // If there's a pending exception req that doesn't need a PC set we must not see one - `ASSERT(IbexNoPCSetOnSpecialReqIfNotExpected, + `ASSERT(CVE2NoPCSetOnSpecialReqIfNotExpected, exception_req_pending && !expect_exception_pc_set |-> ~pc_set_o) `endif diff --git a/rtl/cve2_core.sv b/rtl/cve2_core.sv index c62eb44806..419fd2688f 100644 --- a/rtl/cve2_core.sv +++ b/rtl/cve2_core.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -800,13 +801,13 @@ module cve2_core import cve2_pkg::*; #( ); // These assertions are in top-level as instr_valid_id required as the enable term - `ASSERT(IbexCsrOpValid, instr_valid_id |-> csr_op inside { + `ASSERT(CVE2CsrOpValid, instr_valid_id |-> csr_op inside { CSR_OP_READ, CSR_OP_WRITE, CSR_OP_SET, CSR_OP_CLEAR }) - `ASSERT_KNOWN_IF(IbexCsrWdataIntKnown, cs_registers_i.csr_wdata_int, csr_op_en) + `ASSERT_KNOWN_IF(CVE2CsrWdataIntKnown, cs_registers_i.csr_wdata_int, csr_op_en) if (PMPEnable) begin : g_pmp logic [33:0] pmp_req_addr [PMP_NUM_CHAN]; @@ -928,6 +929,34 @@ module cve2_core import cve2_pkg::*; #( logic [3:0] rvfi_dbg; logic rvfi_dbg_mode; + struct { + logic rvfi_valid; + logic [63:0] rvfi_order; + logic [31:0] rvfi_insn; + logic rvfi_trap; + logic rvfi_halt; + logic [3:0] rvfi_dbg; + logic rvfi_dbg_mode; + logic [15:0] rvfi_intr; + logic [1:0] rvfi_mode; + logic [1:0] rvfi_ixl; + logic [4:0] rvfi_rs1_addr; + logic [31:0] rvfi_rs1_rdata; + logic [4:0] rvfi_rs2_addr; + logic [31:0] rvfi_rs2_rdata; + logic [4:0] rvfi_rs3_addr; + logic [31:0] rvfi_rs3_rdata; + logic [4:0] rvfi_rd1_addr; + logic [31:0] rvfi_rd1_wdata; + logic [31:0] rvfi_pc_rdata; + logic [31:0] rvfi_pc_wdata; + logic [31:0] rvfi_mem_addr; + logic [3:0] rvfi_mem_rmask; + logic [3:0] rvfi_mem_wmask; + logic [31:0] rvfi_mem_rdata; + logic [4:0] rvfi_mem_wdata; + } rvfi_instr_if; + logic new_debug_req; logic new_nmi; logic new_irq; diff --git a/rtl/cve2_counter.sv b/rtl/cve2_counter.sv index 417614b16b..7a39bdb48d 100644 --- a/rtl/cve2_counter.sv +++ b/rtl/cve2_counter.sv @@ -1,3 +1,8 @@ +// Copyright (c) 2025 Eclipse Foundation +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + module cve2_counter #( parameter int CounterWidth = 32, // When set `counter_val_upd_o` provides an incremented version of the counter value, otherwise diff --git a/rtl/cve2_cs_registers.sv b/rtl/cve2_cs_registers.sv index 92ffa824e3..be94f68ed0 100644 --- a/rtl/cve2_cs_registers.sv +++ b/rtl/cve2_cs_registers.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -286,10 +287,10 @@ import cve2_pkg::*; csr_rdata_int[CSR_MSTATUS_TW_BIT] = mstatus_q.tw; end - // mstatush: All zeros for Ibex (fixed little endian and all other bits reserved) + // mstatush: All zeros for CVE2 (fixed little endian and all other bits reserved) CSR_MSTATUSH: csr_rdata_int = '0; - // menvcfg: machine environment configuration, all zeros for Ibex (none of the relevant + // menvcfg: machine environment configuration, all zeros for CVE2 (none of the relevant // features are implemented) CSR_MENVCFG, CSR_MENVCFGH: csr_rdata_int = '0; @@ -1447,6 +1448,27 @@ import cve2_pkg::*; `ifdef RVFI logic [63:0] mstatus_extended_read, mie_extended_read, mip_extended_read, mcause_extended_read; + struct { + logic clk; + logic reset_n; + } clknrst_if; + + assign clknrst_if.clk = clk_i; + assign clknrst_if.reset_n = rst_ni; + + struct { + logic [63:0] rvfi_named_csr_rmask; + logic [63:0] rvfi_named_csr_wmask; + logic [63:0] rvfi_named_csr_rdata; + logic [63:0] rvfi_named_csr_wdata; + + // Generic READ/WRITE values + logic [63:0] rvfi_csr_addr; + logic [63:0] rvfi_csr_rmask; + logic [63:0] rvfi_csr_wmask; + logic [63:0] rvfi_csr_rdata; + logic [63:0] rvfi_csr_wdata; + } rvfi_csr_if; // Extended Reads assign mstatus_extended_read[CSR_MSTATUS_MIE_BIT] = mstatus_q.mie; @@ -1464,7 +1486,7 @@ import cve2_pkg::*; assign mip_extended_read[CSR_MEIX_BIT] = mip.irq_external; assign mip_extended_read[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mip.irq_fast; - assign mcause_extended_read = {mcause_q[6], 25'b0, mcause_q[5:0]}; + assign mcause_extended_read = {32'b0, mcause_q[6], 25'b0, mcause_q[5:0]}; // Extended Writes logic [63:0] mstatus_extended_write, mie_extended_write, mcause_extended_write; @@ -1480,7 +1502,7 @@ import cve2_pkg::*; assign mstatus_extended_write[CSR_MSTATUS_MPRV_BIT] = mstatus_d.mprv; assign mstatus_extended_write[CSR_MSTATUS_TW_BIT] = mstatus_d.tw; - assign mcause_extended_write = {mcause_d[6], 25'b0, mcause_d[5:0]}; + assign mcause_extended_write = {32'b0, mcause_d[6], 25'b0, mcause_d[5:0]}; wire [63:0] rvfi_csr_bypass; diff --git a/rtl/cve2_csr.sv b/rtl/cve2_csr.sv index b464bccedb..e36e666698 100644 --- a/rtl/cve2_csr.sv +++ b/rtl/cve2_csr.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -52,6 +53,6 @@ module cve2_csr #( assign rd_error_o = 1'b0; end - `ASSERT_KNOWN(IbexCSREnValid, wr_en_i) + `ASSERT_KNOWN(CVE2CSREnValid, wr_en_i) endmodule diff --git a/rtl/cve2_decoder.sv b/rtl/cve2_decoder.sv index 3d4ed8c716..7d524f5740 100644 --- a/rtl/cve2_decoder.sv +++ b/rtl/cve2_decoder.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -1183,6 +1184,6 @@ module cve2_decoder #( //////////////// // Selectors must be known/valid. - `ASSERT(IbexRegImmAluOpKnown, (opcode == OPCODE_OP_IMM) |-> + `ASSERT(CVE2RegImmAluOpKnown, (opcode == OPCODE_OP_IMM) |-> !$isunknown(instr[14:12])) endmodule // controller diff --git a/rtl/cve2_ex_block.sv b/rtl/cve2_ex_block.sv index 98713a3d85..f84d990fe1 100644 --- a/rtl/cve2_ex_block.sv +++ b/rtl/cve2_ex_block.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. diff --git a/rtl/cve2_fetch_fifo.sv b/rtl/cve2_fetch_fifo.sv index 60933a0302..8acb18e091 100644 --- a/rtl/cve2_fetch_fifo.sv +++ b/rtl/cve2_fetch_fifo.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -241,11 +242,11 @@ module cve2_fetch_fifo #( //////////////// // Must not push and pop simultaneously when FIFO full. - `ASSERT(IbexFetchFifoPushPopFull, + `ASSERT(CVE2FetchFifoPushPopFull, (in_valid_i && pop_fifo) |-> (!valid_q[DEPTH-1] || clear_i)) // Must not push to FIFO when full. - `ASSERT(IbexFetchFifoPushFull, + `ASSERT(CVE2FetchFifoPushFull, (in_valid_i) |-> (!valid_q[DEPTH-1] || clear_i)) endmodule diff --git a/rtl/cve2_id_stage.sv b/rtl/cve2_id_stage.sv index 6f4d727f31..83efe6b564 100644 --- a/rtl/cve2_id_stage.sv +++ b/rtl/cve2_id_stage.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -381,7 +382,7 @@ module cve2_id_stage #( default: imm_b = 32'h4; endcase end - `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside { + `ASSERT(CVE2ImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside { IMM_B_I, IMM_B_S, IMM_B_B, @@ -889,8 +890,8 @@ module cve2_id_stage #( //////////////// // Selectors must be known/valid. - `ASSERT_KNOWN_IF(IbexAluOpMuxSelKnown, alu_op_a_mux_sel, instr_valid_i) - `ASSERT(IbexAluAOpMuxSelValid, instr_valid_i |-> alu_op_a_mux_sel inside { + `ASSERT_KNOWN_IF(CVE2AluOpMuxSelKnown, alu_op_a_mux_sel, instr_valid_i) + `ASSERT(CVE2AluAOpMuxSelValid, instr_valid_i |-> alu_op_a_mux_sel inside { OP_A_REG_A, OP_A_FWD, OP_A_CURRPC, @@ -909,15 +910,15 @@ module cve2_id_stage #( `ASSERT_KNOWN(IbexWbStateKnown, id_fsm_q) // Branch decision must be valid when jumping. - `ASSERT_KNOWN_IF(IbexBranchDecisionValid, branch_decision_i, + `ASSERT_KNOWN_IF(CVE2BranchDecisionValid, branch_decision_i, instr_valid_i && !(illegal_csr_insn_i || instr_fetch_err_i)) // Instruction delivered to ID stage can not contain X. - `ASSERT_KNOWN_IF(IbexIdInstrKnown, instr_rdata_i, + `ASSERT_KNOWN_IF(CVE2IdInstrKnown, instr_rdata_i, instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i)) // Instruction delivered to ID stage can not contain X. - `ASSERT_KNOWN_IF(IbexIdInstrALUKnown, instr_rdata_alu_i, + `ASSERT_KNOWN_IF(CVE2IdInstrALUKnown, instr_rdata_alu_i, instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i)) // Multicycle enable signals must be unique. @@ -927,10 +928,10 @@ module cve2_id_stage #( // Duplicated instruction flops must match // === as DV environment can produce instructions with Xs in, so must use precise match that // includes Xs - `ASSERT(IbexDuplicateInstrMatch, instr_valid_i |-> instr_rdata_i === instr_rdata_alu_i) + `ASSERT(CVE2DuplicateInstrMatch, instr_valid_i |-> instr_rdata_i === instr_rdata_alu_i) `ifdef CHECK_MISALIGNED - `ASSERT(IbexMisalignedMemoryAccess, !lsu_addr_incr_req_i) + `ASSERT(CVE2MisalignedMemoryAccess, !lsu_addr_incr_req_i) `endif endmodule diff --git a/rtl/cve2_if_stage.sv b/rtl/cve2_if_stage.sv index 4e09103728..f71f3bd799 100644 --- a/rtl/cve2_if_stage.sv +++ b/rtl/cve2_if_stage.sv @@ -1,6 +1,6 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. -// Copyright 2025 OpenHW Group. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -177,6 +177,23 @@ module cve2_if_stage import cve2_pkg::*; ( .busy_o ( prefetch_busy ) ); + `ifndef SYNTHESIS + // (As instroduced on the Ibex core project) + // Needed by the RISC-V compliance checking simulation model for linking + // against C++ testbench code, that expects the simutil_get_scramble_key + // or simutil_get_scramble_nonce functions. + // As a slightly ugly hack, let's define the DPI functions here (the + // real versions are defined in prim_util_get_scramble_params.svh) + export "DPI-C" function simutil_get_scramble_key; + export "DPI-C" function simutil_get_scramble_nonce; + function automatic int simutil_get_scramble_key(output bit [127:0] val); + return 0; + endfunction + function automatic int simutil_get_scramble_nonce(output bit [319:0] nonce); + return 0; + endfunction + `endif + assign unused_fetch_addr_n0 = fetch_addr_n[0]; assign branch_req = pc_set_i; @@ -266,15 +283,15 @@ module cve2_if_stage import cve2_pkg::*; ( //////////////// // Selectors must be known/valid. - `ASSERT_KNOWN(IbexExcPcMuxKnown, exc_pc_mux_i) + `ASSERT_KNOWN(CVE2ExcPcMuxKnown, exc_pc_mux_i) // Boot address must be aligned to 256 bytes. - `ASSERT(IbexBootAddrUnaligned, boot_addr_i[7:0] == 8'h00) + `ASSERT(CVE2BootAddrUnaligned, boot_addr_i[7:0] == 8'h00) // Address must not contain X when request is sent. - `ASSERT(IbexInstrAddrUnknown, instr_req_o |-> !$isunknown(instr_addr_o)) + `ASSERT(CVE2InstrAddrUnknown, instr_req_o |-> !$isunknown(instr_addr_o)) // Address must be word aligned when request is sent. - `ASSERT(IbexInstrAddrUnaligned, instr_req_o |-> (instr_addr_o[1:0] == 2'b00)) + `ASSERT(CVE2InstrAddrUnaligned, instr_req_o |-> (instr_addr_o[1:0] == 2'b00)) endmodule diff --git a/rtl/cve2_load_store_unit.sv b/rtl/cve2_load_store_unit.sv index 3575fadf9b..cee7bb9af5 100644 --- a/rtl/cve2_load_store_unit.sv +++ b/rtl/cve2_load_store_unit.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -505,18 +506,18 @@ module cve2_load_store_unit //////////////// // Selectors must be known/valid. - `ASSERT(IbexDataTypeKnown, (lsu_req_i | busy_o) |-> !$isunknown(lsu_type_i)) - `ASSERT(IbexDataOffsetKnown, (lsu_req_i | busy_o) |-> !$isunknown(data_offset)) - `ASSERT_KNOWN(IbexRDataOffsetQKnown, rdata_offset_q) - `ASSERT_KNOWN(IbexDataTypeQKnown, data_type_q) - `ASSERT(IbexLsuStateValid, ls_fsm_cs inside { + `ASSERT(CVE2DataTypeKnown, (lsu_req_i | busy_o) |-> !$isunknown(lsu_type_i)) + `ASSERT(CVE2DataOffsetKnown, (lsu_req_i | busy_o) |-> !$isunknown(data_offset)) + `ASSERT_KNOWN(CVE2RDataOffsetQKnown, rdata_offset_q) + `ASSERT_KNOWN(CVE2DataTypeQKnown, data_type_q) + `ASSERT(CVE2LsuStateValid, ls_fsm_cs inside { IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT, WAIT_RVALID_MIS_GNTS_DONE}) // Address must not contain X when request is sent. - `ASSERT(IbexDataAddrUnknown, data_req_o |-> !$isunknown(data_addr_o)) + `ASSERT(CVE2DataAddrUnknown, data_req_o |-> !$isunknown(data_addr_o)) // Address must be word aligned when request is sent. - `ASSERT(IbexDataAddrUnaligned, data_req_o |-> (data_addr_o[1:0] == 2'b00)) + `ASSERT(CVE2DataAddrUnaligned, data_req_o |-> (data_addr_o[1:0] == 2'b00)) endmodule diff --git a/rtl/cve2_multdiv_fast.sv b/rtl/cve2_multdiv_fast.sv index d1d400a312..1f23e8c6a2 100644 --- a/rtl/cve2_multdiv_fast.sv +++ b/rtl/cve2_multdiv_fast.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -249,7 +250,7 @@ module cve2_multdiv_fast #( assign unused_mult1_res_uns = mult1_res_uns[33:32]; // States must be knwon/valid. - `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q) + `ASSERT_KNOWN(CVE2MultStateKnown, mult_state_q) // The fast multiplier uses one 17 bit multiplier to compute MUL instructions in 3 cycles // and MULH instructions in 4 cycles. @@ -367,7 +368,7 @@ module cve2_multdiv_fast #( end // States must be knwon/valid. - `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q) + `ASSERT_KNOWN(CVE2MultStateKnown, mult_state_q) end // gen_mult_fast @@ -518,7 +519,7 @@ module cve2_multdiv_fast #( assign valid_o = mult_valid | div_valid; // States must be knwon/valid. - `ASSERT(IbexMultDivStateValid, md_state_q inside { + `ASSERT(CVE2MultDivStateValid, md_state_q inside { MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH}) `ifdef FORMAL diff --git a/rtl/cve2_multdiv_slow.sv b/rtl/cve2_multdiv_slow.sv index 70732cc6d3..f8ddfd0339 100644 --- a/rtl/cve2_multdiv_slow.sv +++ b/rtl/cve2_multdiv_slow.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -364,7 +365,7 @@ module cve2_multdiv_slow //////////////// // State must be valid. - `ASSERT(IbexMultDivStateValid, md_state_q inside { + `ASSERT(CVE2MultDivStateValid, md_state_q inside { MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH }, clk_i, !rst_ni) diff --git a/rtl/cve2_pkg.sv b/rtl/cve2_pkg.sv index 37c08c0312..c37d799c32 100644 --- a/rtl/cve2_pkg.sv +++ b/rtl/cve2_pkg.sv @@ -1,10 +1,11 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 /** - * Package with constants used by Ibex + * Package with constants used by CVE2 */ package cve2_pkg; @@ -31,6 +32,12 @@ package cve2_pkg; // Parameter Enums // ///////////////////// + // typedef enum integer { + // RegFileFF = 0, + // RegFileFPGA = 1, + // RegFileLatch = 2 + // } regfile_e; + typedef enum integer { RV32MNone = 0, RV32MSlow = 1, diff --git a/rtl/cve2_pmp.sv b/rtl/cve2_pmp.sv index b531eefdf1..1ffba60e26 100644 --- a/rtl/cve2_pmp.sv +++ b/rtl/cve2_pmp.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/rtl/cve2_pmp_reset_default.svh b/rtl/cve2_pmp_reset_default.svh index cda701b358..9d9e5d91b4 100644 --- a/rtl/cve2_pmp_reset_default.svh +++ b/rtl/cve2_pmp_reset_default.svh @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -6,7 +7,7 @@ // (PMPNumRegions) is less than 16 the reset values for the higher numbered // regions are ignored. // -// See the Ibex Reference Guide (Custom Reset Values under Physical Memory +// See the CVE2 Reference Guide (Custom Reset Values under Physical Memory // Protection) for more information. localparam pmp_cfg_t pmp_cfg_rst[16] = '{ diff --git a/rtl/cve2_prefetch_buffer.sv b/rtl/cve2_prefetch_buffer.sv index 51b1195ce1..c32e49a4e0 100644 --- a/rtl/cve2_prefetch_buffer.sv +++ b/rtl/cve2_prefetch_buffer.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. diff --git a/rtl/cve2_register_file_ff.sv b/rtl/cve2_register_file_ff.sv index 148ba225eb..de45f8f50c 100644 --- a/rtl/cve2_register_file_ff.sv +++ b/rtl/cve2_register_file_ff.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. diff --git a/rtl/cve2_top.sv b/rtl/cve2_top.sv index 5f240695c8..cb799c170b 100644 --- a/rtl/cve2_top.sv +++ b/rtl/cve2_top.sv @@ -1,6 +1,7 @@ +// Copyright (c) 2025 Eclipse Foundation +// Copyright 2023 OpenHW Group. // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. -// Copyright 2025 OpenHW Group. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -286,30 +287,30 @@ module cve2_top import cve2_pkg::*; #( // X checks for top-level outputs - `ASSERT_KNOWN(IbexInstrReqX, instr_req_o) - `ASSERT_KNOWN_IF(IbexInstrReqPayloadX, instr_addr_o, instr_req_o) + `ASSERT_KNOWN(CVE2InstrReqX, instr_req_o) + `ASSERT_KNOWN_IF(CVE2InstrReqPayloadX, instr_addr_o, instr_req_o) - `ASSERT_KNOWN(IbexDataReqX, data_req_o) - `ASSERT_KNOWN_IF(IbexDataReqPayloadX, + `ASSERT_KNOWN(CVE2DataReqX, data_req_o) + `ASSERT_KNOWN_IF(CVE2DataReqPayloadX, {data_we_o, data_be_o, data_addr_o, data_wdata_o}, data_req_o) - `ASSERT_KNOWN(IbexCoreSleepX, core_sleep_o) + `ASSERT_KNOWN(CVE2CoreSleepX, core_sleep_o) // X check for top-level inputs - `ASSERT_KNOWN(IbexTestEnX, test_en_i) - `ASSERT_KNOWN(IbexRamCfgX, ram_cfg_i) - `ASSERT_KNOWN(IbexHartIdX, hart_id_i) - `ASSERT_KNOWN(IbexBootAddrX, boot_addr_i) - - `ASSERT_KNOWN(IbexInstrGntX, instr_gnt_i) - `ASSERT_KNOWN(IbexInstrRValidX, instr_rvalid_i) - `ASSERT_KNOWN_IF(IbexInstrRPayloadX, + `ASSERT_KNOWN(CVE2TestEnX, test_en_i) + `ASSERT_KNOWN(CVE2RamCfgX, ram_cfg_i) + `ASSERT_KNOWN(CVE2HartIdX, hart_id_i) + `ASSERT_KNOWN(CVE2BootAddrX, boot_addr_i) + + `ASSERT_KNOWN(CVE2InstrGntX, instr_gnt_i) + `ASSERT_KNOWN(CVE2InstrRValidX, instr_rvalid_i) + `ASSERT_KNOWN_IF(CVE2InstrRPayloadX, {instr_rdata_i, instr_err_i}, instr_rvalid_i) - `ASSERT_KNOWN(IbexDataGntX, data_gnt_i) - `ASSERT_KNOWN(IbexDataRValidX, data_rvalid_i) + `ASSERT_KNOWN(CVE2DataGntX, data_gnt_i) + `ASSERT_KNOWN(CVE2DataRValidX, data_rvalid_i) - `ASSERT_KNOWN(IbexIrqX, {irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i}) + `ASSERT_KNOWN(CVE2IrqX, {irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i}) - `ASSERT_KNOWN(IbexDebugReqX, debug_req_i) + `ASSERT_KNOWN(CVE2DebugReqX, debug_req_i) endmodule diff --git a/rtl/cve2_top_tracing.sv b/rtl/cve2_top_tracing.sv index f0015c9884..1f92346ae4 100644 --- a/rtl/cve2_top_tracing.sv +++ b/rtl/cve2_top_tracing.sv @@ -1,5 +1,5 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. -// Copyright 2025 OpenHW Group. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/rtl/cve2_tracer.sv b/rtl/cve2_tracer.sv index 707419e449..43f12788b8 100644 --- a/rtl/cve2_tracer.sv +++ b/rtl/cve2_tracer.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -759,9 +760,11 @@ module cve2_tracer ( end always_comb begin + /* verilator lint_off MULTIDRIVEN */ decoded_str = ""; data_accessed = 5'h0; insn_is_compressed = 0; + /* verilator lint_on MULTIDRIVEN */ // Check for compressed instructions if (rvfi_insn[1:0] != 2'b11) begin diff --git a/rtl/cve2_tracer_pkg.sv b/rtl/cve2_tracer_pkg.sv index 700dd37b38..2c9fc30cdd 100644 --- a/rtl/cve2_tracer_pkg.sv +++ b/rtl/cve2_tracer_pkg.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md. // Licensed under the Apache License, Version 2.0, see LICENSE for details. diff --git a/rtl/cve2_wb.sv b/rtl/cve2_wb.sv index dee73f74ef..abd9f28619 100644 --- a/rtl/cve2_wb.sv +++ b/rtl/cve2_wb.sv @@ -1,3 +1,4 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/scripts/sec/sec.sh b/scripts/sec/sec.sh index 7126df4fb5..26c6846928 100755 --- a/scripts/sec/sec.sh +++ b/scripts/sec/sec.sh @@ -1,6 +1,7 @@ #!/bin/bash -# Copyright 2023-2025 OpenHW Foundation +# Copyright (c) 2025 Eclipse Foundation +# Copyright 2023 OpenHW Group # # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -14,6 +15,13 @@ # See the License for the specific language governing permissions and # limitations under the License. +CVE2_REPO_BASE="$(readlink -f -- "$( dirname -- "$( readlink -f -- "$0"; )"; )/../../")" +SEC_BUILD_DIR="$CVE2_REPO_BASE/build/sec/" + +if [ ! -d $SEC_BUILD_DIR ]; then + mkdir -p $SEC_BUILD_DIR +fi + usage() { # Function: Print a help message. echo "Usage: $0 [ -t {cadence,mentor,synopsys,yosys} ]" 1>&2 } @@ -40,8 +48,8 @@ do esac done -if [ ! -d ./reports/ ]; then - mkdir -p ./reports/ +if [ ! -d "$SEC_BUILD_DIR/reports/" ]; then + mkdir -p "$SEC_BUILD_DIR/reports/" fi if [[ "${target_tool}" != "cadence" && "${target_tool}" != "synopsys" @@ -49,30 +57,28 @@ if [[ "${target_tool}" != "cadence" && "${target_tool}" != "synopsys" exit_abnormal fi +GOLDEN_DIR=$(readlink -f $SEC_BUILD_DIR/ref_design/) if [[ -z "${GOLDEN_RTL}" ]]; then echo "The env variable GOLDEN_RTL is empty." - if [ ! -d "./ref_design" ]; then + if [ ! -d "$SEC_BUILD_DIR/ref_design" ]; then echo "Cloning Golden Design...." - git clone https://github.com/openhwgroup/cve2.git ref_design + git clone https://github.com/openhwgroup/cve2.git $GOLDEN_DIR fi - export GOLDEN_RTL=$(pwd)/ref_design/rtl + export GOLDEN_RTL=$GOLDEN_DIR/rtl else echo "SEC: Using ${GOLDEN_RTL} as reference design" fi -REVISED_DIR=$( readlink -f $(pwd)/../../) - -GOLDEN_DIR=$(readlink -f ./ref_design/) - +REVISED_DIR=$CVE2_REPO_BASE var_golden_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "wrapper") print $0 }' ${GOLDEN_DIR}/cv32e20_manifest.flist | sed 's|${DESIGN_RTL_DIR}|./ref_design/rtl/|') var_revised_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "wrapper") print $0 }' ${REVISED_DIR}/cv32e20_manifest.flist | sed 's|${DESIGN_RTL_DIR}|../../rtl/|') -echo $var_golden_rtl > golden.src -echo $var_revised_rtl > revised.src +echo $var_golden_rtl > "$SEC_BUILD_DIR/golden.src" +echo $var_revised_rtl > "$SEC_BUILD_DIR/revised.src" -report_dir=$(readlink -f $(dirname "${BASH_SOURCE[0]}"))/reports/$(date +%Y-%m-%d/%H-%M)/ +report_dir="$SEC_BUILD_DIR/reports/$(date +%Y-%m-%d/%H-%M)/" if [[ -d ${report_dir} ]]; then rm -rf ${report_dir} @@ -84,47 +90,50 @@ if [[ "${target_tool}" == "cadence" ]]; then jg -sec -proj ${report_dir} -batch -tcl ${tcl_script} -define report_dir ${report_dir} &> ${report_dir}/output.cadence.log if [ ! -f ${report_dir}/summary.cadence.log ]; then - echo "Something went wrong during the process" + echo "Something went wrong during the process" 1>&2 exit 1 fi grep -Eq "Overall SEC status[ ]+- Complete" ${report_dir}/summary.cadence.log RESULT=$? elif [[ "${target_tool}" == "synopsys" ]]; then - echo "Synopsys tool is not implemented yet" + echo "Synopsys tool is not implemented yet" 1>&2 exit 1 elif [[ "${target_tool}" == "mentor" ]]; then - echo "Mentor tool is not implemented yet" + echo "Mentor tool is not implemented yet" 1>&2 exit 1 elif [[ "${target_tool}" == "yosys" ]]; then echo "Using Yosys EQY" + mkdir -p "$SEC_BUILD_DIR/yosys" if ! [ -x "$(command -v eqy)" ]; then - echo "Yosys EQY (eqy) could not be found" + echo "Yosys EQY (eqy) could not be found" 1>&2 exit 1 fi - eqy -f yosys/sec.eqy -j $(($(nproc)/2)) -d ${report_dir} &> /dev/null + (cd $SEC_BUILD_DIR && \ + eqy -f $CVE2_REPO_BASE/scripts/sec/yosys/sec.eqy -j $(($(nproc)/2)) -d ${report_dir} &> /dev/null + ) mv ${report_dir}/logfile.txt ${report_dir}/output.yosys.log - rm yosys/golden_io.txt + rm "$SEC_BUILD_DIR/yosys/golden_io.txt" if [ -f "${report_dir}/PASS" ]; then RESULT=0 elif [ -f "${report_dir}/FAIL" ]; then RESULT=1 - echo "Check ${report_dir}/output.yosys.log" + echo "Check ${report_dir}/output.yosys.log" 1>&2 else - echo "Failed to run Yosys EQY" + echo "Failed to run Yosys EQY" 1>&2 exit 1 fi fi if [[ $RESULT == 0 ]]; then - echo "SEC: The DESIGN IS SEQUENTIAL EQUIVALENT" + echo "SEC: The DESIGN IS SEQUENTIALLY EQUIVALENT" exit 0 else - echo "SEC: The DESIGN IS NOT SEQUENTIAL EQUIVALENT" + echo "SEC: The DESIGN IS NOT SEQUENTIALLY EQUIVALENT" 1>&2 exit 1 fi diff --git a/scripts/verilator/verilate.sh b/scripts/verilator/verilate.sh index 0ae2a98a82..df0a71cb66 100755 --- a/scripts/verilator/verilate.sh +++ b/scripts/verilator/verilate.sh @@ -1,16 +1,17 @@ #!/bin/bash -VLT_CONFIG="./lint/verilator_waiver.vlt" +CVE2_REPO_BASE="$(readlink -f -- "$( dirname -- "$( readlink -f -- "$0"; )"; )/../../")" +VLT_CONFIG="$CVE2_REPO_BASE/lint/verilator_waiver.vlt" -SV_DEPS="./vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv rtl/cve2_pkg.sv ./bhv/cve2_sim_clock_gate.sv" -SV_TOP="./rtl/cve2_top.sv" +SV_DEPS="$CVE2_REPO_BASE/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv $CVE2_REPO_BASE/rtl/cve2_pkg.sv $CVE2_REPO_BASE/rtl/cve2_clock_gate.sv" +SV_TOP="$CVE2_REPO_BASE/rtl/cve2_top.sv" verilator --lint-only \ -Wall \ - -I./rtl \ - -I./vendor/lowrisc_ip/ip/prim/rtl \ - -I./vendor/lowrisc_ip/dv/sv/dv_utils \ + -I$CVE2_REPO_BASE/rtl \ + -I$CVE2_REPO_BASE/vendor/lowrisc_ip/ip/prim/rtl \ + -I$CVE2_REPO_BASE/vendor/lowrisc_ip/dv/sv/dv_utils \ ${VLT_CONFIG} \ ${SV_DEPS} \ ${SV_TOP} diff --git a/shared/fpga_xilinx.core b/shared/fpga_xilinx.core index 044822f29c..df20c60936 100644 --- a/shared/fpga_xilinx.core +++ b/shared/fpga_xilinx.core @@ -1,8 +1,9 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:cve2:fpga_xilinx_shared" +name: "openhwgroup:cve2:fpga_xilinx_shared" description: "Collection of useful RTL for Xilinx based examples" filesets: files_sv: diff --git a/shared/rtl/bus.sv b/shared/rtl/bus.sv index 2fcf09c241..b3de651a54 100644 --- a/shared/rtl/bus.sv +++ b/shared/rtl/bus.sv @@ -1,9 +1,10 @@ +// Copyright (c) 2025 Eclipse Foundation // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 /** - * Simplistic Ibex bus implementation + * Simplistic CVE2 bus implementation * * This module is designed for demo and simulation purposes, do not use it in * a real-world system. diff --git a/shared/sim_shared.core b/shared/sim_shared.core index 3d61b87cc4..61e917bc6a 100644 --- a/shared/sim_shared.core +++ b/shared/sim_shared.core @@ -1,8 +1,9 @@ CAPI=2: +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:cve2:sim_shared" +name: "openhwgroup:cve2:sim_shared" description: "Collection of useful RTL for building simulations" filesets: files_sim_sv: diff --git a/syn/README.md b/syn/README.md index 64e82715af..57c8fad51e 100644 --- a/syn/README.md +++ b/syn/README.md @@ -2,7 +2,7 @@ tape-out quality netlists and area/timing numbers it generates are not representative of what would be achievable with a tape-out quality flow** -# Yosys/OpenSTA Ibex Synthesis Flow +# Yosys/OpenSTA CVE2 Synthesis Flow This is a synthesis-only implementation flow using Yosys for Synthesis and OpenSTA to produce timing reports. Its outputs are: @@ -11,15 +11,15 @@ OpenSTA to produce timing reports. Its outputs are: been mapped to a standard-cell library yet * A post synthesis netlist - Gate-level verilog after optimisation mapped to a standard-cell library -* An STA netlist - Logically equivilent to the netlist above but with changes to +* An STA netlist - Logically equivalent to the netlist above but with changes to allow processing by OpenSTA * Area/Cell Usage report - Total area consumed by utilised cells and counts of each cell instance used -* Timing reports - Overal timing report and reports broken down into various +* Timing reports - Overall timing report and reports broken down into various path groups (register to register paths and per IO reports) -Yosys doesn't yet support the full subset of SystemVerilog used by Ibex so the -sv2v tool is used to first convert the Ibex RTL into the SystemVerilog subset +Yosys doesn't yet support the full subset of SystemVerilog used by CVE2 so the +sv2v tool is used to first convert the CVE2 RTL into the SystemVerilog subset Yosys can process. # Synthesis flow requirements @@ -71,7 +71,7 @@ flow. All outputs are placed under the `syn/syn_out` directory with the prefix - syn.log - Log of the Yosys run - sta.log - Log of the OpenSTA run - `generated` - - *.v - Ibex RTL after sv2v processing + - *.v - CVE2 RTL after sv2v processing - cve2_top.pre_map.v - Pre-mapping synthesis netlists - cve2_top_netlist.v - Post-synthesis netlist - cve2_top_netlist.sta.v - Post-synthesis netlist usable by OpenSTA @@ -89,7 +89,7 @@ flow. These are used to generate a single .sdc file * `cve2_top_lr_synth_core.tcl` - This specifies the constraints on all inputs and outputs as a fraction of a clock cycle, the names of the clock and reset inputs and the desired clock period in ps -* `ibex.[library-name].sdc` - Header to include in generated .sdc file. Settings +* `cve2.[library-name].sdc` - Header to include in generated .sdc file. Settings can be library dependent so the `LR_SYNTH_CELL_LIBRARY_NAME` environment varible is used to supply the `[library-name]` part of the name diff --git a/syn/cve2_top_lr_synth_conf.tcl b/syn/cve2_top_lr_synth_conf.tcl index f3f8622d6c..44b16b4b5b 100644 --- a/syn/cve2_top_lr_synth_conf.tcl +++ b/syn/cve2_top_lr_synth_conf.tcl @@ -1,3 +1,4 @@ +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -51,7 +52,7 @@ set lr_synth_clk_input clk_i set lr_synth_rst_input rst_ni # clock period in ps, this gives a 250 MHz clock. using the nangate45 library -# Ibex can happily meet this on all paths with the lr_synth_abc_clk_uprate +# CVE2 can happily meet this on all paths with the lr_synth_abc_clk_uprate # setting below. With a lower uprate timing may not be met. set lr_synth_clk_period 4000.0 diff --git a/syn/lec_sv2v.sh b/syn/lec_sv2v.sh index 0c3ce66e50..df6af545a9 100755 --- a/syn/lec_sv2v.sh +++ b/syn/lec_sv2v.sh @@ -23,7 +23,7 @@ #------------------------------------------------------------------------- rm -Rf build lec_out fusesoc --cores-root .. run --tool=icarus --target=lint \ - --setup "lowrisc:cve2:cve2_top" > /dev/null 2>&1 + --setup "openhwgroup:cve2:cve2_top" > /dev/null 2>&1 # copy all files to lec_out mkdir lec_out @@ -52,9 +52,9 @@ done # remove *pkg.v files (they are empty files and not needed) rm -f *_pkg.v prim_assert.v prim_util_memload.v -# overwrite the prim_clock_gating modules with the module from ../rtl -cp ../rtl/prim_clock_gating.v . -cp ../rtl/prim_clock_gating.v prim_clock_gating.sv +# # overwrite the prim_clock_gating modules with the module from ../rtl +# cp ../rtl/prim_clock_gating.v . +# cp ../rtl/prim_clock_gating.v prim_clock_gating.sv #------------------------------------------------------------------------- # run LEC (generated Verilog vs. original SystemVerilog) diff --git a/syn/rtl/cve2_clock_gating.v b/syn/rtl/cve2_clock_gating.v deleted file mode 100644 index 903500188a..0000000000 --- a/syn/rtl/cve2_clock_gating.v +++ /dev/null @@ -1,23 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Example clock gating module for yosys synthesis - -module cve2_clock_gate ( - input clk_i, - input en_i, - input scan_cg_en_i, - output clk_o -); - - reg en_latch; - - always @* begin - if (!clk_i) begin - en_latch = en_i | test_en_i; - end - end - assign clk_o = en_latch & clk_i; - -endmodule diff --git a/syn/rtl/prim_clock_gating.v b/syn/rtl/prim_clock_gating.v deleted file mode 100644 index 14d197459a..0000000000 --- a/syn/rtl/prim_clock_gating.v +++ /dev/null @@ -1,23 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Example clock gating module for yosys synthesis - -module prim_clock_gating ( - input clk_i, - input en_i, - input test_en_i, - output clk_o -); - - reg en_latch; - - always @* begin - if (!clk_i) begin - en_latch = en_i | test_en_i; - end - end - assign clk_o = en_latch & clk_i; - -endmodule diff --git a/syn/syn_setup.example.sh b/syn/syn_setup.example.sh index f3b6f4e9ec..a1ec60e2bd 100644 --- a/syn/syn_setup.example.sh +++ b/syn/syn_setup.example.sh @@ -1,5 +1,6 @@ #!/bin/bash +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -7,7 +8,7 @@ if [ $# -eq 1 ]; then export LR_SYNTH_OUT_DIR=$1 elif [ $# -eq 0 ]; then - export LR_SYNTH_OUT_DIR_PREFIX="syn_out/ibex" + export LR_SYNTH_OUT_DIR_PREFIX="syn_out/cve2" export LR_SYNTH_OUT_DIR=$(date +"${LR_SYNTH_OUT_DIR_PREFIX}_%d_%m_%Y_%H_%M_%S") else echo "Usage $0 [synth_out_dir]" diff --git a/syn/syn_setup.sh b/syn/syn_setup.sh old mode 100644 new mode 100755 index c7c5cd8e61..398080e741 --- a/syn/syn_setup.sh +++ b/syn/syn_setup.sh @@ -1,5 +1,6 @@ #!/bin/bash +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 diff --git a/syn/syn_yosys.sh b/syn/syn_yosys.sh index 34eef10bd9..4136886609 100755 --- a/syn/syn_yosys.sh +++ b/syn/syn_yosys.sh @@ -1,10 +1,11 @@ #!/bin/bash +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -# This script drives the experimental Ibex synthesis flow. More details can be +# This script drives the experimental CVE2 synthesis flow. More details can be # found in README.md set -e diff --git a/syn/tcl/lr_synth_flow_var_setup.tcl b/syn/tcl/lr_synth_flow_var_setup.tcl index 8ec7a5b720..fb22be8771 100644 --- a/syn/tcl/lr_synth_flow_var_setup.tcl +++ b/syn/tcl/lr_synth_flow_var_setup.tcl @@ -1,3 +1,4 @@ +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -13,11 +14,11 @@ set_flow_var config_file "${lr_synth_top_module}_lr_synth_conf.tcl" "Synth confi set_flow_var rpt_out "./${lr_synth_out_dir}/reports" "Report output directory" set_flow_bool_var flatten 1 "flatten" set_flow_bool_var timing_run 0 "timing run" -set_flow_bool_var cve2_branch_target_alu 0 "Enable branch target ALU in Ibex" -set_flow_bool_var cve2_writeback_stage 0 "Enable writeback stage in Ibex" -set_flow_var cve2_bitmanip 0 "Bitmanip extenion setting for Ibex (see cve2_pkg::rv32b_e for permitted values. Enum names are not supported in Yosys.)" -set_flow_var cve2_multiplier 2 "Multiplier extension setting for Ibex (see cve2_pkg::rv32m_e for permitted values. Enum names are not supported in Yosys.)" -set_flow_var cve2_regfile 2 "Register file implementation selection for Ibex (see cve2_pkg::regfile_e for permitted values. Enum names are not supported in Yosys.)" +set_flow_bool_var cve2_branch_target_alu 0 "Enable branch target ALU in CVE2" +set_flow_bool_var cve2_writeback_stage 0 "Enable writeback stage in CVE2" +set_flow_var cve2_bitmanip 0 "Bitmanip extenion setting for CVE2 (see cve2_pkg::rv32b_e for permitted values. Enum names are not supported in Yosys.)" +set_flow_var cve2_multiplier 2 "Multiplier extension setting for CVE2 (see cve2_pkg::rv32m_e for permitted values. Enum names are not supported in Yosys.)" +set_flow_var cve2_regfile 2 "Register file implementation selection for CVE2 (see cve2_pkg::regfile_e for permitted values. Enum names are not supported in Yosys.)" source $lr_synth_config_file diff --git a/syn/tcl/yosys_run_synth.tcl b/syn/tcl/yosys_run_synth.tcl index ff83276fd3..26c57cfc04 100644 --- a/syn/tcl/yosys_run_synth.tcl +++ b/syn/tcl/yosys_run_synth.tcl @@ -1,3 +1,4 @@ +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -14,11 +15,11 @@ if { $lr_synth_timing_run } { write_sdc_out $lr_synth_sdc_file_in $lr_synth_sdc_file_out } -yosys "read_verilog -defer -sv ./rtl/cve2_clock_gating.v $lr_synth_out_dir/generated/*.v" +yosys "read_verilog -defer -sv ../rtl/cve2_clock_gate.v $lr_synth_out_dir/generated/*.v" -if { $lr_synth_cve2_writeback_stage } { - yosys "chparam -set WritebackStage 1 $lr_synth_top_module" -} +# if { $lr_synth_cve2_writeback_stage } { +# yosys "chparam -set WritebackStage 1 $lr_synth_top_module" +# } yosys "chparam -set RV32M $lr_synth_cve2_multiplier $lr_synth_top_module" diff --git a/util/cve2_config.py b/util/cve2_config.py index 4c7a818c7e..00a226e34e 100755 --- a/util/cve2_config.py +++ b/util/cve2_config.py @@ -1,5 +1,6 @@ #!/usr/bin/env python3 +# Copyright (c) 2025 Eclipse Foundation # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -219,11 +220,11 @@ def parse_config(config_name, config_filename): Arguments: - config_name: Name of the chosen Ibex core config + config_name: Name of the chosen CVE2 core config config_filename: Name of the configuration filename to be parsed - Returns: the chosen Ibex config as a YAML object. + Returns: the chosen CVE2 config as a YAML object. Raises a ConfigException if there are any error while parsing the YAML. @@ -275,7 +276,7 @@ def main(): ] argparser = argparse.ArgumentParser(description=( - 'Outputs Ibex configuration parameters for a named config in a number ' + 'Outputs CVE2 configuration parameters for a named config in a number ' 'of formats. If not specified on the command line the config will be ' 'read from {0}. This default can be overridden by setting the ' 'CVE2_CONFIG_FILE environment variable. Some output types support ' @@ -283,7 +284,7 @@ def main(): 'followed by --help').format(get_config_file_location())) argparser.add_argument('config_name', - help=('The name of the Ibex ' + help=('The name of the CVE2 ' 'configuration to output')) argparser.add_argument('--config_filename', diff --git a/vendor/lowrisc_ip.vendor.hjson b/vendor/lowrisc_ip.vendor.hjson index d450750546..9ae2cea2d6 100644 --- a/vendor/lowrisc_ip.vendor.hjson +++ b/vendor/lowrisc_ip.vendor.hjson @@ -14,22 +14,22 @@ {from: "hw/dv/sv/common_ifs", to: "dv/sv/common_ifs"}, {from: "hw/dv/sv/csr_utils", to: "dv/sv/csr_utils"}, {from: "hw/dv/sv/dv_base_reg", to: "dv/sv/dv_base_reg"}, - {from: "hw/dv/sv/mem_model", to: "dv/sv/mem_model"}, - {from: "hw/dv/sv/mem_bkdr_util", to: "dv/sv/mem_bkdr_util"}, + // {from: "hw/dv/sv/mem_model", to: "dv/sv/mem_model"}, + // {from: "hw/dv/sv/mem_bkdr_util", to: "dv/sv/mem_bkdr_util"}, {from: "hw/dv/sv/str_utils", to: "dv/sv/str_utils"}, // We apply a patch to fix the bus_params_pkg core file name when // vendoring in dv_lib and dv_utils. This allows us to have an - // Ibex-specific core file for these defines. + // CVE2-specific core file for these defines. { from: "hw/dv/sv/dv_lib", to: "dv/sv/dv_lib", - patch_dir: "dv_lib", + // patch_dir: "dv_lib", }, { from: "hw/dv/sv/dv_utils", to: "dv/sv/dv_utils", - patch_dir: "dv_utils", + // patch_dir: "dv_utils", }, // We have to apply a patch to the vendored files from hw/dv/tools // because they contain OpenTitan specific paths. diff --git a/vendor/patches/lowrisc_ip/dv_lib/0001-use-ibex-bus-params.patch b/vendor/patches/lowrisc_ip/dv_lib/0001-use-ibex-bus-params.patch deleted file mode 100644 index 5a44e6a773..0000000000 --- a/vendor/patches/lowrisc_ip/dv_lib/0001-use-ibex-bus-params.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/dv_lib/dv_lib.core b/dv_lib/dv_lib.core -index e6e3f9e8..ad1b98ff 100644 ---- a/dv_lib.core -+++ b/dv_lib.core -@@ -11,6 +11,6 @@ filesets: - - lowrisc:dv:dv_utils - - lowrisc:dv:csr_utils - - lowrisc:dv:dv_base_reg -- - lowrisc:opentitan:bus_params_pkg -+ - lowrisc:cve2:bus_params_pkg - files: - - dv_lib_pkg.sv diff --git a/vendor/patches/lowrisc_ip/dv_utils/0001-use-ibex-bus-params.patch b/vendor/patches/lowrisc_ip/dv_utils/0001-use-ibex-bus-params.patch deleted file mode 100644 index a0ca6ba810..0000000000 --- a/vendor/patches/lowrisc_ip/dv_utils/0001-use-ibex-bus-params.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff --git a/dv_utils/dv_utils.core b/dv_utils/dv_utils.core -index 0dba0235..801e84f6 100644 ---- a/dv_utils.core -+++ b/dv_utils.core -@@ -11,7 +11,7 @@ filesets: - - lowrisc:dv:dv_macros - - lowrisc:dv:dv_fcov_macros - - lowrisc:dv:common_ifs - - lowrisc:prim:assert:0.1 -- - lowrisc:opentitan:bus_params_pkg -+ - lowrisc:cve2:bus_params_pkg - - lowrisc:dv:str_utils - - lowrisc:dv:dv_test_status - files: