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The EBU receives flush signals (necessary to solve a logic bug). These are now on the critical path, but not in the version of the critical path reported in Chapter 6.
For example, buscachefsm has Flush affecting HTRANS. See the code and timing report below. In the timing report, a branch misprediction raises FlushD, which affects HTRANS. busfsm is similar.
Rose Thompson feels the right fix is to issue the transaction anyway in the Execute stage, but to send a signal in the memory stage for the controller to cancel the transaction via the AHB protocol. If this isn't feasible, it might be possible to kill HWSTRB in the memory stage so that transaction has no effect.
After the fix, rerun Linux boot in lock step, and regenerate Chapter 6 synthesis results.
Resolved in a feature branch ahbopt. Improved Arty A7 clock speed from 20 Mhz to 25 MHz. However, we are saving this for after tag 1.0 as this change won't match the book.
The EBU receives flush signals (necessary to solve a logic bug). These are now on the critical path, but not in the version of the critical path reported in Chapter 6.
For example, buscachefsm has Flush affecting HTRANS. See the code and timing report below. In the timing report, a branch misprediction raises FlushD, which affects HTRANS. busfsm is similar.
Rose Thompson feels the right fix is to issue the transaction anyway in the Execute stage, but to send a signal in the memory stage for the controller to cancel the transaction via the AHB protocol. If this isn't feasible, it might be possible to kill HWSTRB in the memory stage so that transaction has no effect.
After the fix, rerun Linux boot in lock step, and regenerate Chapter 6 synthesis results.
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