or1k: cmpxchg_mask: mask set register

The code that emits this instruction will have loaded the value
that should be set in the lower x-bits of the 'set' register and
then left shift the value in the register into the right position.
It is however not guaranteed that the upper bits of the register
is zero, so this will use the mask register (which also have the
the same x-bits set to 1 right shifted into the right position)
to mask in only the relevant bits.

ChangeLog/
	* config/or1k/or1k.md (cmpxchg_mask): Mask set register.

gcc/ChangeLog.or1k

@@ -1,3 +1,7 @@
+2015-01-17  Stefan Kristiansson  <[email protected]>
+
+	* config/or1k/or1k.md (cmpxchg_mask): Mask set register.
+
 2014-08-13  Stefan Kristiansson  <[email protected]>
 
 	* config/or1k/or1k.h (ASM_PREFERRED_EH_DATA_FORMAT): Define.

gcc/config/or1k/or1k.md

@@ -1489,7 +1489,8 @@
   ""
   "
    l.lwa   \t%6,%2    # cmpxchg: load
-   l.and   \t%1,%6,%5 # cmpxchg: mask
+   l.and   \t%1,%6,%5 # cmpxchg: mask old
+   l.and   \t%4,%4,%5 # cmpxchg: mask set
    l.sfeq  \t%1,%3    # cmpxchg: cmp
    l.bnf   \t1f       # cmpxchg: not expected
     l.ori  \t%0,r0,0  # cmpxchg: result = 0