From f519696100a9fca410e35a3333d5bf8e0e9958a2 Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Wed, 5 Mar 2014 16:22:35 +0700
Subject: [PATCH 01/12] Minor change

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index cefa9312..089a305a 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
 orpsoc-cores
 ============
 
-Core description files for ORPSoCv3
+Core description files for ORPSoCv3.

From 29d667e2ad227646479f2ef2a31f8888668522c9 Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Wed, 5 Mar 2014 17:51:59 +0700
Subject: [PATCH 02/12] system: add Altera DE2 board support (alpha, need more
 testing, originally written by Tran Cong Nam

---
 systems/de2/backend/rtl/verilog/pll.v         |  377 ++++
 systems/de2/data/de2.sdc                      |    8 +
 systems/de2/data/options.tcl                  |   17 +
 systems/de2/data/pinmap.tcl                   |  208 ++
 systems/de2/data/wb_intercon.conf             |   43 +
 systems/de2/de2.core                          |   44 +
 systems/de2/de2.system                        |   15 +
 systems/de2/rtl/verilog/clkgen.v              |  128 ++
 .../de2/rtl/verilog/include/or1200_defines.v  | 1824 +++++++++++++++++
 .../de2/rtl/verilog/include/orpsoc-defines.v  |   39 +
 systems/de2/rtl/verilog/include/timescale.v   |    1 +
 .../de2/rtl/verilog/include/uart_defines.v    |  250 +++
 systems/de2/rtl/verilog/orpsoc_top.v          |  705 +++++++
 systems/de2/rtl/verilog/rom.v                 |  127 ++
 systems/de2/rtl/verilog/wb_intercon.v         |  360 ++++
 systems/de2/rtl/verilog/wb_intercon.vh        |  197 ++
 systems/de2/scripts/build_summary             |   21 +
 17 files changed, 4364 insertions(+)
 create mode 100755 systems/de2/backend/rtl/verilog/pll.v
 create mode 100755 systems/de2/data/de2.sdc
 create mode 100755 systems/de2/data/options.tcl
 create mode 100755 systems/de2/data/pinmap.tcl
 create mode 100755 systems/de2/data/wb_intercon.conf
 create mode 100755 systems/de2/de2.core
 create mode 100755 systems/de2/de2.system
 create mode 100755 systems/de2/rtl/verilog/clkgen.v
 create mode 100755 systems/de2/rtl/verilog/include/or1200_defines.v
 create mode 100755 systems/de2/rtl/verilog/include/orpsoc-defines.v
 create mode 100755 systems/de2/rtl/verilog/include/timescale.v
 create mode 100755 systems/de2/rtl/verilog/include/uart_defines.v
 create mode 100755 systems/de2/rtl/verilog/orpsoc_top.v
 create mode 100755 systems/de2/rtl/verilog/rom.v
 create mode 100755 systems/de2/rtl/verilog/wb_intercon.v
 create mode 100755 systems/de2/rtl/verilog/wb_intercon.vh
 create mode 100755 systems/de2/scripts/build_summary

diff --git a/systems/de2/backend/rtl/verilog/pll.v b/systems/de2/backend/rtl/verilog/pll.v
new file mode 100755
index 00000000..c3f34d76
--- /dev/null
+++ b/systems/de2/backend/rtl/verilog/pll.v
@@ -0,0 +1,377 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.0 Build 157 04/27/2011 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	areset,
+	inclk0,
+	c0,
+	c1,
+	c2,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  c2;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [5:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire7 = 1'h0;
+	wire [2:2] sub_wire4 = sub_wire0[2:2];
+	wire [0:0] sub_wire3 = sub_wire0[0:0];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  c0 = sub_wire3;
+	wire  c2 = sub_wire4;
+	wire  sub_wire5 = inclk0;
+	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire6),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 2,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 1,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 1,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk2_divide_by = 5,
+		altpll_component.clk2_duty_cycle = 50,
+		altpll_component.clk2_multiply_by = 1,
+		altpll_component.clk2_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.gate_lock_signal = "NO",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.invalid_lock_multiplier = 5,
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_USED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "5"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "10.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/systems/de2/data/de2.sdc b/systems/de2/data/de2.sdc
new file mode 100755
index 00000000..aad4ab21
--- /dev/null
+++ b/systems/de2/data/de2.sdc
@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "sys_clk_pad_i" -period 20.000ns [get_ports {sys_clk_pad_i}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
diff --git a/systems/de2/data/options.tcl b/systems/de2/data/options.tcl
new file mode 100755
index 00000000..2b66c97e
--- /dev/null
+++ b/systems/de2/data/options.tcl
@@ -0,0 +1,17 @@
+# See Cyclone II FPGA Family Errata, needed for ddual-port dual-clock mode M4K
+# (http://www.altera.com/support/kdb/solutions/fb27180.html)
+
+set_parameter -name CYCLONEII_SAFE_WRITE  "VERIFIED_SAFE"
+
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS_INPUT_TRI_STATED"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+
+# Make it pass STA
+
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
diff --git a/systems/de2/data/pinmap.tcl b/systems/de2/data/pinmap.tcl
new file mode 100755
index 00000000..440485a2
--- /dev/null
+++ b/systems/de2/data/pinmap.tcl
@@ -0,0 +1,208 @@
+# Clock / Reset
+
+set_location_assignment PIN_G26 -to rst_n_pad_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pad_i
+set_location_assignment PIN_N2 -to sys_clk_pad_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i
+
+# SD card
+#set_location_assignment PIN_V20 -to sd_clk_pad_o
+  
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_clk_pad_o
+#set_location_assignment PIN_Y20 -to sd_cmd_pad_o
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_cmd_pad_o
+#set_location_assignment PIN_W20 -to sd_dat_pad_i
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_dat_pad_i
+#set_location_assignment PIN_U20 -to sd_dat3_pad_o
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_dat3_pad_o
+
+# UART
+set_location_assignment PIN_C25 -to uart0_srx_pad_i
+   
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i
+set_location_assignment PIN_B25 -to uart0_stx_pad_o
+  
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o
+
+# SDRAM
+set_location_assignment PIN_T6 -to sdram_a_pad_o[0]
+      
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[0]
+set_location_assignment PIN_V4 -to sdram_a_pad_o[1]
+       
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[1]
+set_location_assignment PIN_V3 -to sdram_a_pad_o[2]
+       
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[2]
+set_location_assignment PIN_W2 -to sdram_a_pad_o[3]
+      
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[3]
+set_location_assignment PIN_W1 -to sdram_a_pad_o[4]
+     	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[4]
+set_location_assignment PIN_U6 -to sdram_a_pad_o[5]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[5]
+set_location_assignment PIN_U7 -to sdram_a_pad_o[6]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[6]
+set_location_assignment PIN_U5 -to sdram_a_pad_o[7]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[7]
+set_location_assignment PIN_W4 -to sdram_a_pad_o[8]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[8]
+set_location_assignment PIN_W3 -to sdram_a_pad_o[9]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[9]
+set_location_assignment PIN_Y1 -to sdram_a_pad_o[10]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[10]
+set_location_assignment PIN_V5 -to sdram_a_pad_o[11]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[11]
+
+set_location_assignment PIN_V6 -to sdram_dq_pad_io[0]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[0]
+set_location_assignment PIN_AA2 -to sdram_dq_pad_io[1]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[1]
+set_location_assignment PIN_AA1 -to sdram_dq_pad_io[2]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[2]
+set_location_assignment PIN_Y3 -to sdram_dq_pad_io[3]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[3]
+set_location_assignment PIN_Y4 -to sdram_dq_pad_io[4]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[4]
+set_location_assignment PIN_R8 -to sdram_dq_pad_io[5]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[5]
+set_location_assignment PIN_T8 -to sdram_dq_pad_io[6]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[6]
+set_location_assignment PIN_V7 -to sdram_dq_pad_io[7]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[7]
+set_location_assignment PIN_W6 -to sdram_dq_pad_io[8]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[8]
+set_location_assignment PIN_AB2 -to sdram_dq_pad_io[9]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[9]
+set_location_assignment PIN_AB1 -to sdram_dq_pad_io[10]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[10]
+set_location_assignment PIN_AA4 -to sdram_dq_pad_io[11]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[11]
+set_location_assignment PIN_AA3 -to sdram_dq_pad_io[12]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[12]
+set_location_assignment PIN_AC2 -to sdram_dq_pad_io[13]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[13]
+set_location_assignment PIN_AC1 -to sdram_dq_pad_io[14]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[14]
+set_location_assignment PIN_AA5 -to sdram_dq_pad_io[15]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[15]
+
+set_location_assignment PIN_AD2 -to sdram_dqm_pad_o[0]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[0]
+set_location_assignment PIN_Y5 -to sdram_dqm_pad_o[1]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[1]
+
+set_location_assignment PIN_AE2 -to sdram_ba_pad_o[0]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[0]
+set_location_assignment PIN_AE3 -to sdram_ba_pad_o[1]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[1]
+
+set_location_assignment PIN_AB3 -to sdram_cas_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cas_pad_o
+
+set_location_assignment PIN_AA6 -to sdram_cke_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cke_pad_o
+
+set_location_assignment PIN_AC3 -to sdram_cs_n_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cs_n_pad_o
+
+set_location_assignment PIN_AB4 -to sdram_ras_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ras_pad_o
+
+set_location_assignment PIN_AD3 -to sdram_we_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_we_pad_o
+
+set_location_assignment PIN_AA7 -to sdram_clk_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_clk_pad_o
+
+# RED LED
+set_location_assignment PIN_AE23 -to led_r_pad_o[0]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[0]
+set_location_assignment PIN_AF23 -to led_r_pad_o[1]
+			
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[1]
+set_location_assignment PIN_AB21 -to led_r_pad_o[2]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[2]
+set_location_assignment PIN_AC22 -to led_r_pad_o[3]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[3]
+set_location_assignment PIN_AD22 -to led_r_pad_o[4]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[4]
+set_location_assignment PIN_AD23 -to led_r_pad_o[5]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[5]
+set_location_assignment PIN_AD21 -to led_r_pad_o[6]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[6]
+set_location_assignment PIN_AC21 -to led_r_pad_o[7]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[7]
+set_location_assignment PIN_AA14 -to led_r_pad_o[8]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[8]
+set_location_assignment PIN_Y13 -to led_r_pad_o[9]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[9]
+
+# GREEN LED
+set_location_assignment PIN_AE22 -to gpio0_io[0]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[0]
+set_location_assignment PIN_AF22 -to gpio0_io[1]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[1]
+set_location_assignment PIN_W19 -to gpio0_io[2]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[2]
+set_location_assignment PIN_V18 -to gpio0_io[3]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[3]
+set_location_assignment PIN_U18 -to gpio0_io[4]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[4]
+set_location_assignment PIN_U17 -to gpio0_io[5]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[5]
+set_location_assignment PIN_AA20 -to gpio0_io[6]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[6]
+set_location_assignment PIN_Y18 -to gpio0_io[7]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[7]
diff --git a/systems/de2/data/wb_intercon.conf b/systems/de2/data/wb_intercon.conf
new file mode 100755
index 00000000..0fe144fc
--- /dev/null
+++ b/systems/de2/data/wb_intercon.conf
@@ -0,0 +1,43 @@
+; or1k instruction bus master
+[master or1k_i]
+slaves =
+ sdram_ibus
+ rom0
+
+; or1k data bus master
+[master or1k_d]
+slaves =
+ sdram_dbus
+ uart0
+ gpio0
+
+; debug master
+[master dbg]
+slaves =
+ sdram_dbus
+ uart0
+ gpio0
+
+[slave uart0]
+datawidth=8
+offset=0x90000000
+size=32
+
+[slave gpio0]
+datawidth=8
+offset=0x91000000
+size=2
+
+[slave rom0]
+offset=0xf0000100
+size=64
+
+; SDRAM
+; Have several ports with buffering features,
+; so we split each port into a seperate slave
+[slave sdram_dbus]
+offset=0
+size=0x2000000 ; 32MB
+[slave sdram_ibus]
+offset=0
+size=0x2000000 ; 32MB
diff --git a/systems/de2/de2.core b/systems/de2/de2.core
new file mode 100755
index 00000000..918bf988
--- /dev/null
+++ b/systems/de2/de2.core
@@ -0,0 +1,44 @@
+CAPI=1
+[main]
+depend =
+ jtag_tap
+ wb_intercon
+ adv_debug_sys
+ or1200
+ uart16550
+ or1k-elf-loader
+ vlog_tb_utils
+ jtag_vpi
+ wiredelay
+ wb_sdram_ctrl
+ mor1kx
+ mt48lc16m16a2
+ gpio
+ altera_virtual_jtag
+
+simulators =
+ icarus
+ modelsim
+
+[verilog]
+src_files = 
+ rtl/verilog/clkgen.v
+ rtl/verilog/orpsoc_top.v
+ backend/rtl/verilog/pll.v
+ rtl/verilog/rom.v
+ rtl/verilog/wb_intercon.v
+
+
+include_files =
+ rtl/verilog/include/or1200_defines.v
+ rtl/verilog/include/orpsoc-defines.v
+ rtl/verilog/include/timescale.v
+ rtl/verilog/include/uart_defines.v
+ rtl/verilog/wb_intercon.vh
+
+[icarus]
+iverilog_options = -DICARUS_SIM -DSIM
+
+[modelsim]
+vlog_options = +define+SIM +define+MODELSIM_SIM
+vsim_options = -L altera_mf_ver -L altera_mf
diff --git a/systems/de2/de2.system b/systems/de2/de2.system
new file mode 100755
index 00000000..7d48909b
--- /dev/null
+++ b/systems/de2/de2.system
@@ -0,0 +1,15 @@
+SAPI=1
+[main]
+name = de2
+description = "Altera de2 board OpenRISC system"
+
+backend = quartus
+
+[quartus]
+family = "Cyclone II"
+device = EP2C35F672C6
+sdc_files = data/de2.sdc
+tcl_files = data/pinmap.tcl
+            data/options.tcl
+
+
diff --git a/systems/de2/rtl/verilog/clkgen.v b/systems/de2/rtl/verilog/clkgen.v
new file mode 100755
index 00000000..08dd6278
--- /dev/null
+++ b/systems/de2/rtl/verilog/clkgen.v
@@ -0,0 +1,128 @@
+//////////////////////////////////////////////////////////////////////
+//
+// clkgen
+//
+// Handles clock and reset generation for rest of design
+//
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+`include "orpsoc-defines.v"
+
+module clkgen
+(
+	// Main clocks in, depending on board
+	input	sys_clk_pad_i,
+	// Asynchronous, active low reset in
+	input	rst_n_pad_i,
+	// Input reset - through a buffer, asynchronous
+	output	async_rst_o,
+
+	// Wishbone clock and reset out
+	output	wb_clk_o,
+	output	wb_rst_o,
+
+	// JTAG clock
+`ifdef SIM
+	input	tck_pad_i,
+	output	dbg_tck_o,
+`endif
+
+	// Main memory clocks
+	output	sdram_clk_o,
+	output	sdram_rst_o
+);
+
+// First, deal with the asychronous reset
+wire	async_rst;
+wire	async_rst_n;
+
+assign	async_rst_n  = rst_n_pad_i;
+assign	async_rst  = ~async_rst_n;
+
+// Everyone likes active-high reset signals...
+assign	async_rst_o = ~async_rst_n;
+
+`ifdef SIM
+assign	dbg_tck_o = tck_pad_i;
+`endif
+
+//
+// Declare synchronous reset wires here
+//
+
+// An active-low synchronous reset signal (usually a PLL lock signal)
+wire	sync_rst_n;
+
+wire	pll_lock;
+
+`ifndef SIM
+pll pll0 (
+	.areset	(async_rst),
+	.inclk0	(sys_clk_pad_i),
+	.c0	(sdram_clk_o),
+	.c1	(wb_clk_o),
+	.locked	(pll_lock)
+);
+`else
+assign sdram_clk_o = sys_clk_pad_i;
+assign wb_clk_o = sys_clk_pad_i;
+assign pll_lock = 1'b1;
+`endif
+
+assign sync_rst_n = pll_lock;
+
+//
+// Reset generation
+//
+//
+
+// Reset generation for wishbone
+reg [15:0]	wb_rst_shr;
+
+always @(posedge wb_clk_o or posedge async_rst)
+	if (async_rst)
+		wb_rst_shr <= 16'hffff;
+	else
+		wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
+
+assign wb_rst_o = wb_rst_shr[15];
+
+// Reset generation for SDRAM controller
+reg [15:0]	sdram_rst_shr;
+
+always @(posedge sdram_clk_o or posedge async_rst)
+	if (async_rst)
+		sdram_rst_shr <= 16'hffff;
+	else
+		sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};
+
+assign sdram_rst_o = sdram_rst_shr[15];
+
+endmodule // clkgen
diff --git a/systems/de2/rtl/verilog/include/or1200_defines.v b/systems/de2/rtl/verilog/include/or1200_defines.v
new file mode 100755
index 00000000..840f66f6
--- /dev/null
+++ b/systems/de2/rtl/verilog/include/or1200_defines.v
@@ -0,0 +1,1824 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  OR1200's definitions                                        ////
+////                                                              ////
+////  This file is part of the OpenRISC 1200 project              ////
+////  http://opencores.org/project,or1k                           ////
+////                                                              ////
+////  Description                                                 ////
+////  Defines for the OR1200 core                                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////   - add parameters that are missing                          ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Damjan Lampret, lampret@opencores.org                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Log: or1200_defines.v,v $
+// Revision 2.0  2010/06/30 11:00:00  ORSoC
+// Minor update: 
+// Defines added, bugs fixed. 
+
+//
+// Dump VCD
+//
+//`define OR1200_VCD_DUMP
+
+//
+// Generate debug messages during simulation
+//
+//`define OR1200_VERBOSE
+
+//  `define OR1200_ASIC
+////////////////////////////////////////////////////////
+//
+// Typical configuration for an ASIC
+//
+`ifdef OR1200_ASIC
+
+//
+// Target ASIC memories
+//
+//`define OR1200_ARTISAN_SSP
+//`define OR1200_ARTISAN_SDP
+//`define OR1200_ARTISAN_STP
+`define OR1200_VIRTUALSILICON_SSP
+//`define OR1200_VIRTUALSILICON_STP_T1
+//`define OR1200_VIRTUALSILICON_STP_T2
+
+//
+// Do not implement Data cache
+//
+//`define OR1200_NO_DC
+
+//
+// Do not implement Insn cache
+//
+//`define OR1200_NO_IC
+
+//
+// Do not implement Data MMU
+//
+//`define OR1200_NO_DMMU
+
+//
+// Do not implement Insn MMU
+//
+//`define OR1200_NO_IMMU
+
+//
+// Select between ASIC optimized and generic multiplier
+//
+//`define OR1200_ASIC_MULTP2_32X32
+`define OR1200_GENERIC_MULTP2_32X32
+
+//
+// Size/type of insn/data cache if implemented
+//
+// `define OR1200_IC_1W_512B
+// `define OR1200_IC_1W_4KB
+`define OR1200_IC_1W_8KB
+// `define OR1200_DC_1W_4KB
+`define OR1200_DC_1W_8KB
+
+`else
+
+
+/////////////////////////////////////////////////////////
+//
+// Typical configuration for an FPGA
+//
+
+//
+// Target FPGA memories
+//
+`define OR1200_ALTERA_LPM
+//`define OR1200_XILINX_RAMB16
+//`define OR1200_XILINX_RAMB4
+//`define OR1200_XILINX_RAM32X1D
+//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
+// Generic models should infer RAM blocks at synthesis time (not only effects 
+// single port ram.)
+//`define OR1200_GENERIC
+
+//
+// Do not implement Data cache
+//
+//`define OR1200_NO_DC
+
+//
+// Do not implement Insn cache
+//
+//`define OR1200_NO_IC
+
+//
+// Do not implement Data MMU
+//
+//`define OR1200_NO_DMMU
+
+//
+// Do not implement Insn MMU
+//
+//`define OR1200_NO_IMMU
+
+//
+// Select between ASIC and generic multiplier
+//
+// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
+//
+//`define OR1200_ASIC_MULTP2_32X32
+`define OR1200_GENERIC_MULTP2_32X32
+
+//
+// Size/type of insn/data cache if implemented
+// (consider available FPGA memory resources)
+//
+//`define OR1200_IC_1W_512B
+`define OR1200_IC_1W_4KB
+//`define OR1200_IC_1W_8KB
+//`define OR1200_IC_1W_16KB
+//`define OR1200_IC_1W_32KB
+`define OR1200_DC_1W_4KB
+//`define OR1200_DC_1W_8KB
+//`define OR1200_DC_1W_16KB
+//`define OR1200_DC_1W_32KB
+
+`endif
+
+
+//////////////////////////////////////////////////////////
+//
+// Do not change below unless you know what you are doing
+//
+
+//
+// Reset active low
+//
+//`define OR1200_RST_ACT_LOW
+
+//
+// Enable RAM BIST
+//
+// At the moment this only works for Virtual Silicon
+// single port RAMs. For other RAMs it has not effect.
+// Special wrapper for VS RAMs needs to be provided
+// with scan flops to facilitate bist scan.
+//
+//`define OR1200_BIST
+
+//
+// Register OR1200 WISHBONE outputs
+// (must be defined/enabled)
+//
+`define OR1200_REGISTERED_OUTPUTS
+
+//
+// Register OR1200 WISHBONE inputs
+//
+// (must be undefined/disabled)
+//
+//`define OR1200_REGISTERED_INPUTS
+
+//
+// Disable bursts if they are not supported by the
+// memory subsystem (only affect cache line fill)
+//
+//`define OR1200_NO_BURSTS
+//
+
+//
+// WISHBONE retry counter range
+//
+// 2^value range for retry counter. Retry counter
+// is activated whenever *wb_rty_i is asserted and
+// until retry counter expires, corresponding
+// WISHBONE interface is deactivated.
+//
+// To disable retry counters and *wb_rty_i all together,
+// undefine this macro.
+//
+//`define OR1200_WB_RETRY 7
+
+//
+// WISHBONE Consecutive Address Burst
+//
+// This was used prior to WISHBONE B3 specification
+// to identify bursts. It is no longer needed but
+// remains enabled for compatibility with old designs.
+//
+// To remove *wb_cab_o ports undefine this macro.
+//
+//`define OR1200_WB_CAB
+
+//
+// WISHBONE B3 compatible interface
+//
+// This follows the WISHBONE B3 specification.
+// It is not enabled by default because most
+// designs still don't use WB b3.
+//
+// To enable *wb_cti_o/*wb_bte_o ports,
+// define this macro.
+//
+`define OR1200_WB_B3
+
+//
+// LOG all WISHBONE accesses
+//
+`define OR1200_LOG_WB_ACCESS
+
+//
+// Enable additional synthesis directives if using
+// _Synopsys_ synthesis tool
+//
+//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
+
+//
+// Enables default statement in some case blocks
+// and disables Synopsys synthesis directive full_case
+//
+// By default it is enabled. When disabled it
+// can increase clock frequency.
+//
+`define OR1200_CASE_DEFAULT
+
+//
+// Operand width / register file address width
+//
+// (DO NOT CHANGE)
+//
+`define OR1200_OPERAND_WIDTH		32
+`define OR1200_REGFILE_ADDR_WIDTH	5
+
+//
+// l.add/l.addi/l.and and optional l.addc/l.addic
+// also set (compare) flag when result of their
+// operation equals zero
+//
+// At the time of writing this, default or32
+// C/C++ compiler doesn't generate code that
+// would benefit from this optimization.
+//
+// By default this optimization is disabled to
+// save area.
+//
+//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
+
+//
+// Implement l.addc/l.addic instructions
+//
+// By default implementation of l.addc/l.addic
+// instructions is enabled in case you need them.
+// If you don't use them, then disable implementation
+// to save area.
+//
+//`define OR1200_IMPL_ADDC
+
+//
+// Implement l.sub instruction
+//
+// By default implementation of l.sub instructions
+// is enabled to be compliant with the simulator.
+// If you don't use carry bit, then disable
+// implementation to save area.
+//
+`define OR1200_IMPL_SUB
+
+//
+// Implement carry bit SR[CY]
+//
+//
+// By default implementation of SR[CY] is enabled
+// to be compliant with the simulator. However SR[CY]
+// is explicitly only used by l.addc/l.addic/l.sub
+// instructions and if these three insns are not
+// implemented there is not much point having SR[CY].
+//
+//`define OR1200_IMPL_CY
+
+//
+// Implement carry bit SR[OV]
+//
+// Compiler doesn't use this, but other code may like
+// to.
+//
+//`define OR1200_IMPL_OV
+
+//
+// Implement carry bit SR[OVE]
+//
+// Overflow interrupt indicator. When enabled, SR[OV] flag
+// does not remain asserted after exception.
+//
+//`define OR1200_IMPL_OVE
+
+
+//
+// Implement rotate in the ALU
+//
+// At the time of writing this, or32
+// C/C++ compiler doesn't generate rotate
+// instructions. However or32 assembler
+// can assemble code that uses rotate insn.
+// This means that rotate instructions
+// must be used manually inserted.
+//
+// By default implementation of rotate
+// is disabled to save area and increase
+// clock frequency.
+//
+//`define OR1200_IMPL_ALU_ROTATE
+
+//
+// Type of ALU compare to implement
+//
+// Try either one to find what yields
+// higher clock frequencyin your case.
+//
+//`define OR1200_IMPL_ALU_COMP1
+`define OR1200_IMPL_ALU_COMP2
+//`define OR1200_IMPL_ALU_COMP3
+
+//
+// Implement Find First/Last '1'
+//
+`define OR1200_IMPL_ALU_FFL1
+
+//
+// Implement l.cust5 ALU instruction
+//
+//`define OR1200_IMPL_ALU_CUST5
+
+//
+// Implement l.extXs and l.extXz instructions
+//
+//`define OR1200_IMPL_ALU_EXT
+
+//
+// Implement multiplier
+//
+// By default multiplier is implemented
+//
+`define OR1200_MULT_IMPLEMENTED
+
+//
+// Implement multiply-and-accumulate
+//
+// By default MAC is implemented. To
+// implement MAC, multiplier (non-serial) needs to be
+// implemented.
+//
+//`define OR1200_MAC_IMPLEMENTED
+
+//
+// Implement optional l.div/l.divu instructions
+//
+// By default divide instructions are not implemented
+// to save area.
+//
+//
+`define OR1200_DIV_IMPLEMENTED
+
+//
+// Serial multiplier.
+//
+`define OR1200_MULT_SERIAL
+
+//
+// Serial divider.
+// Uncomment to use a serial divider, otherwise will
+// be a generic parallel implementation.
+//
+`define OR1200_DIV_SERIAL
+
+//
+// Implement HW Single Precision FPU
+//
+//`define OR1200_FPU_IMPLEMENTED
+
+//
+// Clock ratio RISC clock versus WB clock
+//
+// If you plan to run WB:RISC clock fixed to 1:1, disable
+// both defines
+//
+// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
+// and use clmode to set ratio
+//
+// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
+// clmode to set ratio
+//
+//`define OR1200_CLKDIV_2_SUPPORTED
+//`define OR1200_CLKDIV_4_SUPPORTED
+
+//
+// Type of register file RAM
+//
+// Memory macro w/ two ports (see or1200_tpram_32x32.v)
+//`define OR1200_RFRAM_TWOPORT
+//
+// Memory macro dual port (see or1200_dpram.v)
+`define OR1200_RFRAM_DUALPORT
+
+//
+// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
+//`define OR1200_RFRAM_GENERIC
+//  Generic register file supports - 16 registers 
+`ifdef OR1200_RFRAM_GENERIC
+//    `define OR1200_RFRAM_16REG
+`endif
+
+//
+// Type of mem2reg aligner to implement.
+//
+// Once OR1200_IMPL_MEM2REG2 yielded faster
+// circuit, however with today tools it will
+// most probably give you slower circuit.
+//
+`define OR1200_IMPL_MEM2REG1
+//`define OR1200_IMPL_MEM2REG2
+
+//
+// Reset value and event
+//
+`ifdef OR1200_RST_ACT_LOW
+  `define OR1200_RST_VALUE      (1'b0)
+  `define OR1200_RST_EVENT      negedge
+`else
+  `define OR1200_RST_VALUE      (1'b1)
+  `define OR1200_RST_EVENT      posedge
+`endif
+
+//
+// ALUOPs
+//
+`define OR1200_ALUOP_WIDTH	5
+`define OR1200_ALUOP_NOP	5'b0_0100
+/* LS-nibble encodings correspond to bits [3:0] of instruction */
+`define OR1200_ALUOP_ADD	5'b0_0000 // 0
+`define OR1200_ALUOP_ADDC	5'b0_0001 // 1
+`define OR1200_ALUOP_SUB	5'b0_0010 // 2
+`define OR1200_ALUOP_AND	5'b0_0011 // 3
+`define OR1200_ALUOP_OR		5'b0_0100 // 4
+`define OR1200_ALUOP_XOR	5'b0_0101 // 5
+`define OR1200_ALUOP_MUL	5'b0_0110 // 6
+`define OR1200_ALUOP_RESERVED	5'b0_0111 // 7
+`define OR1200_ALUOP_SHROT	5'b0_1000 // 8
+`define OR1200_ALUOP_DIV	5'b0_1001 // 9
+`define OR1200_ALUOP_DIVU	5'b0_1010 // a
+`define OR1200_ALUOP_MULU	5'b0_1011 // b
+`define OR1200_ALUOP_EXTHB	5'b0_1100 // c
+`define OR1200_ALUOP_EXTW	5'b0_1101 // d
+`define OR1200_ALUOP_CMOV	5'b0_1110 // e
+`define OR1200_ALUOP_FFL1	5'b0_1111 // f
+
+/* Values sent to ALU from decode unit - not defined by ISA */
+`define OR1200_ALUOP_COMP       5'b1_0000 // Comparison
+`define OR1200_ALUOP_MOVHI      5'b1_0001 // Move-high
+`define OR1200_ALUOP_CUST5	5'b1_0010 // l.cust5
+
+// ALU instructions second opcode field
+`define OR1200_ALUOP2_POS	9:6
+`define OR1200_ALUOP2_WIDTH	4
+
+//
+// MACOPs
+//
+`define OR1200_MACOP_WIDTH	3
+`define OR1200_MACOP_NOP	3'b000
+`define OR1200_MACOP_MAC	3'b001
+`define OR1200_MACOP_MSB	3'b010
+
+//
+// Shift/rotate ops
+//
+`define OR1200_SHROTOP_WIDTH	4
+`define OR1200_SHROTOP_NOP	4'd0
+`define OR1200_SHROTOP_SLL	4'd0
+`define OR1200_SHROTOP_SRL	4'd1
+`define OR1200_SHROTOP_SRA	4'd2
+`define OR1200_SHROTOP_ROR	4'd3
+
+//
+// Zero/Sign Extend ops
+//
+`define OR1200_EXTHBOP_WIDTH      4
+`define OR1200_EXTHBOP_BS         4'h1
+`define OR1200_EXTHBOP_HS         4'h0
+`define OR1200_EXTHBOP_BZ         4'h3
+`define OR1200_EXTHBOP_HZ         4'h2
+`define OR1200_EXTWOP_WIDTH       4
+`define OR1200_EXTWOP_WS          4'h0
+`define OR1200_EXTWOP_WZ          4'h1
+
+// Execution cycles per instruction
+`define OR1200_MULTICYCLE_WIDTH	3
+`define OR1200_ONE_CYCLE		3'd0
+`define OR1200_TWO_CYCLES		3'd1
+
+// Execution control which will "wait on" a module to finish
+`define OR1200_WAIT_ON_WIDTH 2
+`define OR1200_WAIT_ON_NOTHING    `OR1200_WAIT_ON_WIDTH'd0
+`define OR1200_WAIT_ON_MULTMAC    `OR1200_WAIT_ON_WIDTH'd1
+`define OR1200_WAIT_ON_FPU        `OR1200_WAIT_ON_WIDTH'd2
+`define OR1200_WAIT_ON_MTSPR      `OR1200_WAIT_ON_WIDTH'd3
+
+
+// Operand MUX selects
+`define OR1200_SEL_WIDTH		2
+`define OR1200_SEL_RF			2'd0
+`define OR1200_SEL_IMM			2'd1
+`define OR1200_SEL_EX_FORW		2'd2
+`define OR1200_SEL_WB_FORW		2'd3
+
+//
+// BRANCHOPs
+//
+`define OR1200_BRANCHOP_WIDTH		3
+`define OR1200_BRANCHOP_NOP		3'd0
+`define OR1200_BRANCHOP_J		3'd1
+`define OR1200_BRANCHOP_JR		3'd2
+`define OR1200_BRANCHOP_BAL		3'd3
+`define OR1200_BRANCHOP_BF		3'd4
+`define OR1200_BRANCHOP_BNF		3'd5
+`define OR1200_BRANCHOP_RFE		3'd6
+
+//
+// LSUOPs
+//
+// Bit 0: sign extend
+// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
+// Bit 3: 0 load, 1 store
+`define OR1200_LSUOP_WIDTH		4
+`define OR1200_LSUOP_NOP		4'b0000
+`define OR1200_LSUOP_LBZ		4'b0010
+`define OR1200_LSUOP_LBS		4'b0011
+`define OR1200_LSUOP_LHZ		4'b0100
+`define OR1200_LSUOP_LHS		4'b0101
+`define OR1200_LSUOP_LWZ		4'b0110
+`define OR1200_LSUOP_LWS		4'b0111
+`define OR1200_LSUOP_LD			4'b0001
+`define OR1200_LSUOP_SD			4'b1000
+`define OR1200_LSUOP_SB			4'b1010
+`define OR1200_LSUOP_SH			4'b1100
+`define OR1200_LSUOP_SW			4'b1110
+
+// Number of bits of load/store EA precalculated in ID stage
+// for balancing ID and EX stages.
+//
+// Valid range: 2,3,...,30,31
+`define OR1200_LSUEA_PRECALC		2
+
+// FETCHOPs
+`define OR1200_FETCHOP_WIDTH		1
+`define OR1200_FETCHOP_NOP		1'b0
+`define OR1200_FETCHOP_LW		1'b1
+
+//
+// Register File Write-Back OPs
+//
+// Bit 0: register file write enable
+// Bits 3-1: write-back mux selects
+//
+`define OR1200_RFWBOP_WIDTH		4
+`define OR1200_RFWBOP_NOP		4'b0000
+`define OR1200_RFWBOP_ALU		3'b000
+`define OR1200_RFWBOP_LSU		3'b001
+`define OR1200_RFWBOP_SPRS		3'b010
+`define OR1200_RFWBOP_LR		3'b011
+`define OR1200_RFWBOP_FPU		3'b100
+
+// Compare instructions
+`define OR1200_COP_SFEQ       3'b000
+`define OR1200_COP_SFNE       3'b001
+`define OR1200_COP_SFGT       3'b010
+`define OR1200_COP_SFGE       3'b011
+`define OR1200_COP_SFLT       3'b100
+`define OR1200_COP_SFLE       3'b101
+`define OR1200_COP_X          3'b111
+`define OR1200_SIGNED_COMPARE 'd3
+`define OR1200_COMPOP_WIDTH	4
+
+//
+// FP OPs
+//
+// MSbit indicates FPU operation valid
+//
+`define OR1200_FPUOP_WIDTH	8
+// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
+`define OR1200_FPUOP_CYCLES 3'd4
+// FP instruction is double precision if bit 4 is set. We're a 32-bit 
+// implementation thus do not support double precision FP 
+`define OR1200_FPUOP_DOUBLE_BIT 4
+`define OR1200_FPUOP_ADD  8'b0000_0000
+`define OR1200_FPUOP_SUB  8'b0000_0001
+`define OR1200_FPUOP_MUL  8'b0000_0010
+`define OR1200_FPUOP_DIV  8'b0000_0011
+`define OR1200_FPUOP_ITOF 8'b0000_0100
+`define OR1200_FPUOP_FTOI 8'b0000_0101
+`define OR1200_FPUOP_REM  8'b0000_0110
+`define OR1200_FPUOP_RESERVED  8'b0000_0111
+// FP Compare instructions
+`define OR1200_FPCOP_SFEQ 8'b0000_1000
+`define OR1200_FPCOP_SFNE 8'b0000_1001
+`define OR1200_FPCOP_SFGT 8'b0000_1010
+`define OR1200_FPCOP_SFGE 8'b0000_1011
+`define OR1200_FPCOP_SFLT 8'b0000_1100
+`define OR1200_FPCOP_SFLE 8'b0000_1101
+
+//
+// TAGs for instruction bus
+//
+`define OR1200_ITAG_IDLE	4'h0	// idle bus
+`define	OR1200_ITAG_NI		4'h1	// normal insn
+`define OR1200_ITAG_BE		4'hb	// Bus error exception
+`define OR1200_ITAG_PE		4'hc	// Page fault exception
+`define OR1200_ITAG_TE		4'hd	// TLB miss exception
+
+//
+// TAGs for data bus
+//
+`define OR1200_DTAG_IDLE	4'h0	// idle bus
+`define	OR1200_DTAG_ND		4'h1	// normal data
+`define OR1200_DTAG_AE		4'ha	// Alignment exception
+`define OR1200_DTAG_BE		4'hb	// Bus error exception
+`define OR1200_DTAG_PE		4'hc	// Page fault exception
+`define OR1200_DTAG_TE		4'hd	// TLB miss exception
+
+
+//////////////////////////////////////////////
+//
+// ORBIS32 ISA specifics
+//
+
+// SHROT_OP position in machine word
+`define OR1200_SHROTOP_POS		7:6
+
+//
+// Instruction opcode groups (basic)
+//
+`define OR1200_OR32_J                 6'b000000
+`define OR1200_OR32_JAL               6'b000001
+`define OR1200_OR32_BNF               6'b000011
+`define OR1200_OR32_BF                6'b000100
+`define OR1200_OR32_NOP               6'b000101
+`define OR1200_OR32_MOVHI             6'b000110
+`define OR1200_OR32_MACRC             6'b000110
+`define OR1200_OR32_XSYNC             6'b001000
+`define OR1200_OR32_RFE               6'b001001
+/* */
+`define OR1200_OR32_JR                6'b010001
+`define OR1200_OR32_JALR              6'b010010
+`define OR1200_OR32_MACI              6'b010011
+/* */
+`define OR1200_OR32_LWZ               6'b100001
+`define OR1200_OR32_LWS               6'b100010
+`define OR1200_OR32_LBZ               6'b100011
+`define OR1200_OR32_LBS               6'b100100
+`define OR1200_OR32_LHZ               6'b100101
+`define OR1200_OR32_LHS               6'b100110
+`define OR1200_OR32_ADDI              6'b100111
+`define OR1200_OR32_ADDIC             6'b101000
+`define OR1200_OR32_ANDI              6'b101001
+`define OR1200_OR32_ORI               6'b101010
+`define OR1200_OR32_XORI              6'b101011
+`define OR1200_OR32_MULI              6'b101100
+`define OR1200_OR32_MFSPR             6'b101101
+`define OR1200_OR32_SH_ROTI 	      6'b101110
+`define OR1200_OR32_SFXXI             6'b101111
+/* */
+`define OR1200_OR32_MTSPR             6'b110000
+`define OR1200_OR32_MACMSB            6'b110001
+`define OR1200_OR32_FLOAT             6'b110010
+/* */
+`define OR1200_OR32_SW                6'b110101
+`define OR1200_OR32_SB                6'b110110
+`define OR1200_OR32_SH                6'b110111
+`define OR1200_OR32_ALU               6'b111000
+`define OR1200_OR32_SFXX              6'b111001
+`define OR1200_OR32_CUST5             6'b111100
+
+/////////////////////////////////////////////////////
+//
+// Exceptions
+//
+
+//
+// Exception vectors per OR1K architecture:
+// 0xPPPPP100 - reset
+// 0xPPPPP200 - bus error
+// ... etc
+// where P represents exception prefix.
+//
+// Exception vectors can be customized as per
+// the following formula:
+// 0xPPPPPNVV - exception N
+//
+// P represents exception prefix
+// N represents exception N
+// VV represents length of the individual vector space,
+//   usually it is 8 bits wide and starts with all bits zero
+//
+
+//
+// PPPPP and VV parts
+//
+// Sum of these two defines needs to be 28
+//
+`define OR1200_EXCEPT_EPH0_P    20'h00000
+`define OR1200_EXCEPT_EPH1_P    20'hF0000
+`define OR1200_EXCEPT_V		    8'h00
+
+//
+// N part width
+//
+`define OR1200_EXCEPT_WIDTH 4
+
+//
+// Definition of exception vectors
+//
+// To avoid implementation of a certain exception,
+// simply comment out corresponding line
+//
+`define OR1200_EXCEPT_UNUSED		`OR1200_EXCEPT_WIDTH'hf
+`define OR1200_EXCEPT_TRAP		`OR1200_EXCEPT_WIDTH'he
+`define OR1200_EXCEPT_FLOAT		`OR1200_EXCEPT_WIDTH'hd
+`define OR1200_EXCEPT_SYSCALL		`OR1200_EXCEPT_WIDTH'hc
+`define OR1200_EXCEPT_RANGE		`OR1200_EXCEPT_WIDTH'hb
+`define OR1200_EXCEPT_ITLBMISS		`OR1200_EXCEPT_WIDTH'ha
+`define OR1200_EXCEPT_DTLBMISS		`OR1200_EXCEPT_WIDTH'h9
+`define OR1200_EXCEPT_INT		`OR1200_EXCEPT_WIDTH'h8
+`define OR1200_EXCEPT_ILLEGAL		`OR1200_EXCEPT_WIDTH'h7
+`define OR1200_EXCEPT_ALIGN		`OR1200_EXCEPT_WIDTH'h6
+`define OR1200_EXCEPT_TICK		`OR1200_EXCEPT_WIDTH'h5
+`define OR1200_EXCEPT_IPF		`OR1200_EXCEPT_WIDTH'h4
+`define OR1200_EXCEPT_DPF		`OR1200_EXCEPT_WIDTH'h3
+`define OR1200_EXCEPT_BUSERR		`OR1200_EXCEPT_WIDTH'h2
+`define OR1200_EXCEPT_RESET		`OR1200_EXCEPT_WIDTH'h1
+`define OR1200_EXCEPT_NONE		`OR1200_EXCEPT_WIDTH'h0
+
+
+/////////////////////////////////////////////////////
+//
+// SPR groups
+//
+
+// Bits that define the group
+`define OR1200_SPR_GROUP_BITS	15:11
+
+// Width of the group bits
+`define OR1200_SPR_GROUP_WIDTH 	5
+
+// Bits that define offset inside the group
+`define OR1200_SPR_OFS_BITS 10:0
+
+// List of groups
+`define OR1200_SPR_GROUP_SYS	5'd00
+`define OR1200_SPR_GROUP_DMMU	5'd01
+`define OR1200_SPR_GROUP_IMMU	5'd02
+`define OR1200_SPR_GROUP_DC	5'd03
+`define OR1200_SPR_GROUP_IC	5'd04
+`define OR1200_SPR_GROUP_MAC	5'd05
+`define OR1200_SPR_GROUP_DU	5'd06
+`define OR1200_SPR_GROUP_PM	5'd08
+`define OR1200_SPR_GROUP_PIC	5'd09
+`define OR1200_SPR_GROUP_TT	5'd10
+`define OR1200_SPR_GROUP_FPU    5'd11
+
+/////////////////////////////////////////////////////
+//
+// System group
+//
+
+//
+// System registers
+//
+`define OR1200_SPR_CFGR		7'd0
+`define OR1200_SPR_RF		6'd32	// 1024 >> 5
+`define OR1200_SPR_NPC		11'd16
+`define OR1200_SPR_SR		11'd17
+`define OR1200_SPR_PPC		11'd18
+`define OR1200_SPR_FPCSR        11'd20
+`define OR1200_SPR_EPCR		11'd32
+`define OR1200_SPR_EEAR		11'd48
+`define OR1200_SPR_ESR		11'd64
+
+//
+// SR bits
+//
+`define OR1200_SR_WIDTH 17
+`define OR1200_SR_SM   0
+`define OR1200_SR_TEE  1
+`define OR1200_SR_IEE  2
+`define OR1200_SR_DCE  3
+`define OR1200_SR_ICE  4
+`define OR1200_SR_DME  5
+`define OR1200_SR_IME  6
+`define OR1200_SR_LEE  7
+`define OR1200_SR_CE   8
+`define OR1200_SR_F    9
+`define OR1200_SR_CY   10	// Optional
+`define OR1200_SR_OV   11	// Optional
+`define OR1200_SR_OVE  12	// Optional
+`define OR1200_SR_DSX  13	// Unused
+`define OR1200_SR_EPH  14
+`define OR1200_SR_FO   15
+`define OR1200_SR_TED  16
+`define OR1200_SR_CID  31:28	// Unimplemented
+
+//
+// Bits that define offset inside the group
+//
+`define OR1200_SPROFS_BITS 10:0
+
+//
+// Default Exception Prefix
+//
+// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
+// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
+//
+`define OR1200_SR_EPH_DEF	1'b0
+
+
+//
+// FPCSR bits
+//
+`define OR1200_FPCSR_WIDTH 12
+`define OR1200_FPCSR_FPEE  0
+`define OR1200_FPCSR_RM    2:1
+`define OR1200_FPCSR_OVF   3
+`define OR1200_FPCSR_UNF   4
+`define OR1200_FPCSR_SNF   5
+`define OR1200_FPCSR_QNF   6
+`define OR1200_FPCSR_ZF    7
+`define OR1200_FPCSR_IXF   8
+`define OR1200_FPCSR_IVF   9
+`define OR1200_FPCSR_INF   10
+`define OR1200_FPCSR_DZF   11
+`define OR1200_FPCSR_RES   31:12
+
+/////////////////////////////////////////////////////
+//
+// Power Management (PM)
+//
+
+// Define it if you want PM implemented
+//`define OR1200_PM_IMPLEMENTED
+
+// Bit positions inside PMR (don't change)
+`define OR1200_PM_PMR_SDF 3:0
+`define OR1200_PM_PMR_DME 4
+`define OR1200_PM_PMR_SME 5
+`define OR1200_PM_PMR_DCGE 6
+`define OR1200_PM_PMR_UNUSED 31:7
+
+// PMR offset inside PM group of registers
+`define OR1200_PM_OFS_PMR 11'b0
+
+// PM group
+`define OR1200_SPRGRP_PM 5'd8
+
+// Define if PMR can be read/written at any address inside PM group
+`define OR1200_PM_PARTIAL_DECODING
+
+// Define if reading PMR is allowed
+`define OR1200_PM_READREGS
+
+// Define if unused PMR bits should be zero
+`define OR1200_PM_UNUSED_ZERO
+
+
+/////////////////////////////////////////////////////
+//
+// Debug Unit (DU)
+//
+
+// Define it if you want DU implemented
+`define OR1200_DU_IMPLEMENTED
+
+//
+// Define if you want HW Breakpoints
+// (if HW breakpoints are not implemented
+// only default software trapping is
+// possible with l.trap insn - this is
+// however already enough for use
+// with or32 gdb)
+//
+//`define OR1200_DU_HWBKPTS
+
+// Number of DVR/DCR pairs if HW breakpoints enabled
+//	Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
+//	DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
+`define OR1200_DU_DVRDCR_PAIRS 8
+
+// Define if you want trace buffer
+//	(for now only available for Xilinx Virtex FPGAs)
+//`define OR1200_DU_TB_IMPLEMENTED
+
+
+//
+// Address offsets of DU registers inside DU group
+//
+// To not implement a register, doq not define its address
+//
+`ifdef OR1200_DU_HWBKPTS
+`define OR1200_DU_DVR0		11'd0
+`define OR1200_DU_DVR1		11'd1
+`define OR1200_DU_DVR2		11'd2
+`define OR1200_DU_DVR3		11'd3
+`define OR1200_DU_DVR4		11'd4
+`define OR1200_DU_DVR5		11'd5
+`define OR1200_DU_DVR6		11'd6
+`define OR1200_DU_DVR7		11'd7
+`define OR1200_DU_DCR0		11'd8
+`define OR1200_DU_DCR1		11'd9
+`define OR1200_DU_DCR2		11'd10
+`define OR1200_DU_DCR3		11'd11
+`define OR1200_DU_DCR4		11'd12
+`define OR1200_DU_DCR5		11'd13
+`define OR1200_DU_DCR6		11'd14
+`define OR1200_DU_DCR7		11'd15
+`endif
+`define OR1200_DU_DMR1		11'd16
+`ifdef OR1200_DU_HWBKPTS
+`define OR1200_DU_DMR2		11'd17
+`define OR1200_DU_DWCR0		11'd18
+`define OR1200_DU_DWCR1		11'd19
+`endif
+`define OR1200_DU_DSR		11'd20
+`define OR1200_DU_DRR		11'd21
+`ifdef OR1200_DU_TB_IMPLEMENTED
+`define OR1200_DU_TBADR		11'h0ff
+`define OR1200_DU_TBIA		11'h1??
+`define OR1200_DU_TBIM		11'h2??
+`define OR1200_DU_TBAR		11'h3??
+`define OR1200_DU_TBTS		11'h4??
+`endif
+
+// Position of offset bits inside SPR address
+`define OR1200_DUOFS_BITS	10:0
+
+// DCR bits
+`define OR1200_DU_DCR_DP	0
+`define OR1200_DU_DCR_CC	3:1
+`define OR1200_DU_DCR_SC	4
+`define OR1200_DU_DCR_CT	7:5
+
+// DMR1 bits
+`define OR1200_DU_DMR1_CW0	1:0
+`define OR1200_DU_DMR1_CW1	3:2
+`define OR1200_DU_DMR1_CW2	5:4
+`define OR1200_DU_DMR1_CW3	7:6
+`define OR1200_DU_DMR1_CW4	9:8
+`define OR1200_DU_DMR1_CW5	11:10
+`define OR1200_DU_DMR1_CW6	13:12
+`define OR1200_DU_DMR1_CW7	15:14
+`define OR1200_DU_DMR1_CW8	17:16
+`define OR1200_DU_DMR1_CW9	19:18
+`define OR1200_DU_DMR1_CW10	21:20
+`define OR1200_DU_DMR1_ST	22
+`define OR1200_DU_DMR1_BT	23
+`define OR1200_DU_DMR1_DXFW	24
+`define OR1200_DU_DMR1_ETE	25
+
+// DMR2 bits
+`define OR1200_DU_DMR2_WCE0	0
+`define OR1200_DU_DMR2_WCE1	1
+`define OR1200_DU_DMR2_AWTC	12:2
+`define OR1200_DU_DMR2_WGB	23:13
+
+// DWCR bits
+`define OR1200_DU_DWCR_COUNT	15:0
+`define OR1200_DU_DWCR_MATCH	31:16
+
+// DSR bits
+`define OR1200_DU_DSR_WIDTH	14
+`define OR1200_DU_DSR_RSTE	0
+`define OR1200_DU_DSR_BUSEE	1
+`define OR1200_DU_DSR_DPFE	2
+`define OR1200_DU_DSR_IPFE	3
+`define OR1200_DU_DSR_TTE	4
+`define OR1200_DU_DSR_AE	5
+`define OR1200_DU_DSR_IIE	6
+`define OR1200_DU_DSR_IE	7
+`define OR1200_DU_DSR_DME	8
+`define OR1200_DU_DSR_IME	9
+`define OR1200_DU_DSR_RE	10
+`define OR1200_DU_DSR_SCE	11
+`define OR1200_DU_DSR_FPE	12
+`define OR1200_DU_DSR_TE	13
+
+// DRR bits
+`define OR1200_DU_DRR_RSTE	0
+`define OR1200_DU_DRR_BUSEE	1
+`define OR1200_DU_DRR_DPFE	2
+`define OR1200_DU_DRR_IPFE	3
+`define OR1200_DU_DRR_TTE	4
+`define OR1200_DU_DRR_AE	5
+`define OR1200_DU_DRR_IIE	6
+`define OR1200_DU_DRR_IE	7
+`define OR1200_DU_DRR_DME	8
+`define OR1200_DU_DRR_IME	9
+`define OR1200_DU_DRR_RE	10
+`define OR1200_DU_DRR_SCE	11
+`define OR1200_DU_DRR_FPE	12
+`define OR1200_DU_DRR_TE	13
+
+// Define if reading DU regs is allowed
+`define OR1200_DU_READREGS
+
+// Define if unused DU registers bits should be zero
+`define OR1200_DU_UNUSED_ZERO
+
+// Define if IF/LSU status is not needed by devel i/f
+`define OR1200_DU_STATUS_UNIMPLEMENTED
+
+/////////////////////////////////////////////////////
+//
+// Programmable Interrupt Controller (PIC)
+//
+
+// Define it if you want PIC implemented
+`define OR1200_PIC_IMPLEMENTED
+
+// Define number of interrupt inputs (2-31)
+`define OR1200_PIC_INTS 31
+
+// Address offsets of PIC registers inside PIC group
+`define OR1200_PIC_OFS_PICMR 2'd0
+`define OR1200_PIC_OFS_PICSR 2'd2
+
+// Position of offset bits inside SPR address
+`define OR1200_PICOFS_BITS 1:0
+
+// Define if you want these PIC registers to be implemented
+`define OR1200_PIC_PICMR
+`define OR1200_PIC_PICSR
+
+// Define if reading PIC registers is allowed
+`define OR1200_PIC_READREGS
+
+// Define if unused PIC register bits should be zero
+`define OR1200_PIC_UNUSED_ZERO
+
+
+/////////////////////////////////////////////////////
+//
+// Tick Timer (TT)
+//
+
+// Define it if you want TT implemented
+`define OR1200_TT_IMPLEMENTED
+
+// Address offsets of TT registers inside TT group
+`define OR1200_TT_OFS_TTMR 1'd0
+`define OR1200_TT_OFS_TTCR 1'd1
+
+// Position of offset bits inside SPR group
+`define OR1200_TTOFS_BITS 0
+
+// Define if you want these TT registers to be implemented
+`define OR1200_TT_TTMR
+`define OR1200_TT_TTCR
+
+// TTMR bits
+`define OR1200_TT_TTMR_TP 27:0
+`define OR1200_TT_TTMR_IP 28
+`define OR1200_TT_TTMR_IE 29
+`define OR1200_TT_TTMR_M 31:30
+
+// Define if reading TT registers is allowed
+`define OR1200_TT_READREGS
+
+
+//////////////////////////////////////////////
+//
+// MAC
+//
+`define OR1200_MAC_ADDR		0	// MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
+`define OR1200_MAC_SPR_WE		// Define if MACLO/MACHI are SPR writable
+
+//
+// Shift {MACHI,MACLO} into destination register when executing l.macrc
+//
+// According to architecture manual there is no shift, so default value is 0.
+// However the implementation has deviated in this from the arch manual and had
+// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
+// (if using libmad fixed point library). Shifts are no longer default setup, 
+// but if you need to remain backward compatible, define your shift bits, which
+// were normally
+// dest_GPR = {MACHI,MACLO}[59:28]
+`define OR1200_MAC_SHIFTBY	0	// 0 = According to arch manual, 28 = obsolete backward compatibility
+
+
+//////////////////////////////////////////////
+//
+// Data MMU (DMMU)
+//
+
+//
+// Address that selects between TLB TR and MR
+//
+`define OR1200_DTLB_TM_ADDR	7
+
+//
+// DTLBMR fields
+//
+`define	OR1200_DTLBMR_V_BITS	0
+`define	OR1200_DTLBMR_CID_BITS	4:1
+`define	OR1200_DTLBMR_RES_BITS	11:5
+`define OR1200_DTLBMR_VPN_BITS	31:13
+
+//
+// DTLBTR fields
+//
+`define	OR1200_DTLBTR_CC_BITS	0
+`define	OR1200_DTLBTR_CI_BITS	1
+`define	OR1200_DTLBTR_WBC_BITS	2
+`define	OR1200_DTLBTR_WOM_BITS	3
+`define	OR1200_DTLBTR_A_BITS	4
+`define	OR1200_DTLBTR_D_BITS	5
+`define	OR1200_DTLBTR_URE_BITS	6
+`define	OR1200_DTLBTR_UWE_BITS	7
+`define	OR1200_DTLBTR_SRE_BITS	8
+`define	OR1200_DTLBTR_SWE_BITS	9
+`define	OR1200_DTLBTR_RES_BITS	11:10
+`define OR1200_DTLBTR_PPN_BITS	31:13
+
+//
+// DTLB configuration
+//
+`define	OR1200_DMMU_PS		13					// 13 for 8KB page size
+`define	OR1200_DTLB_INDXW	6					// 6 for 64 entry DTLB	7 for 128 entries
+`define OR1200_DTLB_INDXL	`OR1200_DMMU_PS				// 13			13
+`define OR1200_DTLB_INDXH	`OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1	// 18			19
+`define	OR1200_DTLB_INDX	`OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL	// 18:13		19:13
+`define OR1200_DTLB_TAGW	32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS	// 13			12
+`define OR1200_DTLB_TAGL	`OR1200_DTLB_INDXH+1			// 19			20
+`define	OR1200_DTLB_TAG		31:`OR1200_DTLB_TAGL			// 31:19		31:20
+`define	OR1200_DTLBMRW		`OR1200_DTLB_TAGW+1			// +1 because of V bit
+`define	OR1200_DTLBTRW		32-`OR1200_DMMU_PS+5			// +5 because of protection bits and CI
+
+//
+// Cache inhibit while DMMU is not enabled/implemented
+//
+// cache inhibited 0GB-4GB		1'b1
+// cache inhibited 0GB-2GB		!dcpu_adr_i[31]
+// cache inhibited 0GB-1GB 2GB-3GB	!dcpu_adr_i[30]
+// cache inhibited 1GB-2GB 3GB-4GB	dcpu_adr_i[30]
+// cache inhibited 2GB-4GB (default)	dcpu_adr_i[31]
+// cached 0GB-4GB			1'b0
+//
+`define OR1200_DMMU_CI			dcpu_adr_i[31]
+
+
+//////////////////////////////////////////////
+//
+// Insn MMU (IMMU)
+//
+
+//
+// Address that selects between TLB TR and MR
+//
+`define OR1200_ITLB_TM_ADDR	7
+
+//
+// ITLBMR fields
+//
+`define	OR1200_ITLBMR_V_BITS	0
+`define	OR1200_ITLBMR_CID_BITS	4:1
+`define	OR1200_ITLBMR_RES_BITS	11:5
+`define OR1200_ITLBMR_VPN_BITS	31:13
+
+//
+// ITLBTR fields
+//
+`define	OR1200_ITLBTR_CC_BITS	0
+`define	OR1200_ITLBTR_CI_BITS	1
+`define	OR1200_ITLBTR_WBC_BITS	2
+`define	OR1200_ITLBTR_WOM_BITS	3
+`define	OR1200_ITLBTR_A_BITS	4
+`define	OR1200_ITLBTR_D_BITS	5
+`define	OR1200_ITLBTR_SXE_BITS	6
+`define	OR1200_ITLBTR_UXE_BITS	7
+`define	OR1200_ITLBTR_RES_BITS	11:8
+`define OR1200_ITLBTR_PPN_BITS	31:13
+
+//
+// ITLB configuration
+//
+`define	OR1200_IMMU_PS		13					// 13 for 8KB page size
+`define	OR1200_ITLB_INDXW	6					// 6 for 64 entry ITLB	7 for 128 entries
+`define OR1200_ITLB_INDXL	`OR1200_IMMU_PS				// 13			13
+`define OR1200_ITLB_INDXH	`OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1	// 18			19
+`define	OR1200_ITLB_INDX	`OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL	// 18:13		19:13
+`define OR1200_ITLB_TAGW	32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS	// 13			12
+`define OR1200_ITLB_TAGL	`OR1200_ITLB_INDXH+1			// 19			20
+`define	OR1200_ITLB_TAG		31:`OR1200_ITLB_TAGL			// 31:19		31:20
+`define	OR1200_ITLBMRW		`OR1200_ITLB_TAGW+1			// +1 because of V bit
+`define	OR1200_ITLBTRW		32-`OR1200_IMMU_PS+3			// +3 because of protection bits and CI
+
+//
+// Cache inhibit while IMMU is not enabled/implemented
+// Note: all combinations that use icpu_adr_i cause async loop
+//
+// cache inhibited 0GB-4GB		1'b1
+// cache inhibited 0GB-2GB		!icpu_adr_i[31]
+// cache inhibited 0GB-1GB 2GB-3GB	!icpu_adr_i[30]
+// cache inhibited 1GB-2GB 3GB-4GB	icpu_adr_i[30]
+// cache inhibited 2GB-4GB (default)	icpu_adr_i[31]
+// cached 0GB-4GB			1'b0
+//
+`define OR1200_IMMU_CI			1'b0
+
+
+/////////////////////////////////////////////////
+//
+// Insn cache (IC)
+//
+
+// 4 for 16 byte line, 5 for 32 byte lines.
+`ifdef OR1200_IC_1W_32KB
+ `define OR1200_ICLS		5
+`else
+ `define OR1200_ICLS		4
+`endif
+
+//
+// IC configurations
+//
+`ifdef OR1200_IC_1W_512B
+`define OR1200_ICSIZE                   9                       // 512
+`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 7
+`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 8
+`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 9
+`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS // 5
+`define OR1200_ICTAG_W                  24
+`endif
+`ifdef OR1200_IC_1W_4KB
+`define OR1200_ICSIZE			12			// 4096
+`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 10
+`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 11
+`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 12
+`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 8
+`define	OR1200_ICTAG_W			21
+`endif
+`ifdef OR1200_IC_1W_8KB
+`define OR1200_ICSIZE			13			// 8192
+`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 11
+`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 12
+`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 13
+`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 9
+`define	OR1200_ICTAG_W			20
+`endif
+`ifdef OR1200_IC_1W_16KB
+`define OR1200_ICSIZE			14			// 16384
+`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 12
+`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 13
+`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 14
+`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 10
+`define	OR1200_ICTAG_W			19
+`endif
+`ifdef OR1200_IC_1W_32KB
+`define OR1200_ICSIZE			15			// 32768
+`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 13
+`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 14
+`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 14
+`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 10
+`define	OR1200_ICTAG_W			18
+`endif
+
+
+/////////////////////////////////////////////////
+//
+// Data cache (DC)
+//
+
+// 4 for 16 bytes, 5 for 32 bytes
+`ifdef OR1200_DC_1W_32KB
+ `define OR1200_DCLS		5
+`else
+ `define OR1200_DCLS		4
+`endif
+
+// Define to enable default behavior of cache as write through
+// Turning this off enabled write back statergy
+//
+`define OR1200_DC_WRITETHROUGH
+
+// Define to enable stores from the stack not doing writethrough.
+// EXPERIMENTAL
+//`define OR1200_DC_NOSTACKWRITETHROUGH
+
+// Data cache SPR definitions
+`define OR1200_SPRGRP_DC_ADR_WIDTH 3
+// Data cache group SPR addresses
+`define OR1200_SPRGRP_DC_DCCR		3'd0 // Not implemented
+`define OR1200_SPRGRP_DC_DCBPR		3'd1 // Not implemented
+`define OR1200_SPRGRP_DC_DCBFR		3'd2
+`define OR1200_SPRGRP_DC_DCBIR		3'd3
+`define OR1200_SPRGRP_DC_DCBWR		3'd4 // Not implemented
+`define OR1200_SPRGRP_DC_DCBLR		3'd5 // Not implemented
+
+//
+// DC configurations
+//
+`ifdef OR1200_DC_1W_4KB
+`define OR1200_DCSIZE			12			// 4096
+`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 10
+`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 11
+`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 12
+`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 8
+`define	OR1200_DCTAG_W			21
+`endif
+`ifdef OR1200_DC_1W_8KB
+`define OR1200_DCSIZE			13			// 8192
+`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 11
+`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 12
+`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 13
+`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 9
+`define	OR1200_DCTAG_W			20
+`endif
+`ifdef OR1200_DC_1W_16KB
+`define OR1200_DCSIZE			14			// 16384
+`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 12
+`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 13
+`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 14
+`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 10
+`define	OR1200_DCTAG_W			19
+`endif
+`ifdef OR1200_DC_1W_32KB
+`define OR1200_DCSIZE			15			// 32768
+`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 13
+`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 14
+`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 15
+`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 10
+`define	OR1200_DCTAG_W			18
+`endif
+
+
+/////////////////////////////////////////////////
+//
+// Store buffer (SB)
+//
+
+//
+// Store buffer
+//
+// It will improve performance by "caching" CPU stores
+// using store buffer. This is most important for function
+// prologues because DC can only work in write though mode
+// and all stores would have to complete external WB writes
+// to memory.
+// Store buffer is between DC and data BIU.
+// All stores will be stored into store buffer and immediately
+// completed by the CPU, even though actual external writes
+// will be performed later. As a consequence store buffer masks
+// all data bus errors related to stores (data bus errors
+// related to loads are delivered normally).
+// All pending CPU loads will wait until store buffer is empty to
+// ensure strict memory model. Right now this is necessary because
+// we don't make destinction between cached and cache inhibited
+// address space, so we simply empty store buffer until loads
+// can begin.
+//
+// It makes design a bit bigger, depending what is the number of
+// entries in SB FIFO. Number of entries can be changed further
+// down.
+//
+//`define OR1200_SB_IMPLEMENTED
+
+//
+// Number of store buffer entries
+//
+// Verified number of entries are 4 and 8 entries
+// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
+// always match 2**OR1200_SB_LOG.
+// To disable store buffer, undefine
+// OR1200_SB_IMPLEMENTED.
+//
+`define OR1200_SB_LOG		2	// 2 or 3
+`define OR1200_SB_ENTRIES	4	// 4 or 8
+
+
+/////////////////////////////////////////////////
+//
+// Quick Embedded Memory (QMEM)
+//
+
+//
+// Quick Embedded Memory
+//
+// Instantiation of dedicated insn/data memory (RAM or ROM).
+// Insn fetch has effective throughput 1insn / clock cycle.
+// Data load takes two clock cycles / access, data store
+// takes 1 clock cycle / access (if there is no insn fetch)).
+// Memory instantiation is shared between insn and data,
+// meaning if insn fetch are performed, data load/store
+// performance will be lower.
+//
+// Main reason for QMEM is to put some time critical functions
+// into this memory and to have predictable and fast access
+// to these functions. (soft fpu, context switch, exception
+// handlers, stack, etc)
+//
+// It makes design a bit bigger and slower. QMEM sits behind
+// IMMU/DMMU so all addresses are physical (so the MMUs can be
+// used with QMEM and QMEM is seen by the CPU just like any other
+// memory in the system). IC/DC are sitting behind QMEM so the
+// whole design timing might be worse with QMEM implemented.
+//
+//`define OR1200_QMEM_IMPLEMENTED
+
+//
+// Base address and mask of QMEM
+//
+// Base address defines first address of QMEM. Mask defines
+// QMEM range in address space. Actual size of QMEM is however
+// determined with instantiated RAM/ROM. However bigger
+// mask will reserve more address space for QMEM, but also
+// make design faster, while more tight mask will take
+// less address space but also make design slower. If
+// instantiated RAM/ROM is smaller than space reserved with
+// the mask, instatiated RAM/ROM will also be shadowed
+// at higher addresses in reserved space.
+//
+`define OR1200_QMEM_IADDR	32'h0080_0000
+`define OR1200_QMEM_IMASK	32'hfff0_0000 // Max QMEM size 1MB
+`define OR1200_QMEM_DADDR	32'h0080_0000
+`define OR1200_QMEM_DMASK	32'hfff0_0000 // Max QMEM size 1MB
+
+//
+// QMEM interface byte-select capability
+//
+// To enable qmem_sel* ports, define this macro.
+//
+//`define OR1200_QMEM_BSEL
+
+//
+// QMEM interface acknowledge
+//
+// To enable qmem_ack port, define this macro.
+//
+//`define OR1200_QMEM_ACK
+
+/////////////////////////////////////////////////////
+//
+// VR, UPR and Configuration Registers
+//
+//
+// VR, UPR and configuration registers are optional. If 
+// implemented, operating system can automatically figure
+// out how to use the processor because it knows 
+// what units are available in the processor and how they
+// are configured.
+//
+// This section must be last in or1200_defines.v file so
+// that all units are already configured and thus
+// configuration registers are properly set.
+// 
+
+// Define if you want configuration registers implemented
+`define OR1200_CFGR_IMPLEMENTED
+
+// Define if you want full address decode inside SYS group
+`define OR1200_SYS_FULL_DECODE
+
+// Offsets of VR, UPR and CFGR registers
+`define OR1200_SPRGRP_SYS_VR		4'h0
+`define OR1200_SPRGRP_SYS_UPR		4'h1
+`define OR1200_SPRGRP_SYS_CPUCFGR	4'h2
+`define OR1200_SPRGRP_SYS_DMMUCFGR	4'h3
+`define OR1200_SPRGRP_SYS_IMMUCFGR	4'h4
+`define OR1200_SPRGRP_SYS_DCCFGR	4'h5
+`define OR1200_SPRGRP_SYS_ICCFGR	4'h6
+`define OR1200_SPRGRP_SYS_DCFGR	4'h7
+
+// VR fields
+`define OR1200_VR_REV_BITS		5:0
+`define OR1200_VR_RES1_BITS		15:6
+`define OR1200_VR_CFG_BITS		23:16
+`define OR1200_VR_VER_BITS		31:24
+
+// VR values
+`define OR1200_VR_REV			6'h08
+`define OR1200_VR_RES1			10'h000
+`define OR1200_VR_CFG			8'h00
+`define OR1200_VR_VER			8'h12
+
+// UPR fields
+`define OR1200_UPR_UP_BITS		0
+`define OR1200_UPR_DCP_BITS		1
+`define OR1200_UPR_ICP_BITS		2
+`define OR1200_UPR_DMP_BITS		3
+`define OR1200_UPR_IMP_BITS		4
+`define OR1200_UPR_MP_BITS		5
+`define OR1200_UPR_DUP_BITS		6
+`define OR1200_UPR_PCUP_BITS		7
+`define OR1200_UPR_PMP_BITS		8
+`define OR1200_UPR_PICP_BITS		9
+`define OR1200_UPR_TTP_BITS		10
+`define OR1200_UPR_FPP_BITS		11
+`define OR1200_UPR_RES1_BITS		23:12
+`define OR1200_UPR_CUP_BITS		31:24
+
+// UPR values
+`define OR1200_UPR_UP			1'b1
+`ifdef OR1200_NO_DC
+`define OR1200_UPR_DCP			1'b0
+`else
+`define OR1200_UPR_DCP			1'b1
+`endif
+`ifdef OR1200_NO_IC
+`define OR1200_UPR_ICP			1'b0
+`else
+`define OR1200_UPR_ICP			1'b1
+`endif
+`ifdef OR1200_NO_DMMU
+`define OR1200_UPR_DMP			1'b0
+`else
+`define OR1200_UPR_DMP			1'b1
+`endif
+`ifdef OR1200_NO_IMMU
+`define OR1200_UPR_IMP			1'b0
+`else
+`define OR1200_UPR_IMP			1'b1
+`endif
+`ifdef OR1200_MAC_IMPLEMENTED
+`define OR1200_UPR_MP			1'b1
+`else
+`define OR1200_UPR_MP			1'b0
+`endif
+`ifdef OR1200_DU_IMPLEMENTED
+`define OR1200_UPR_DUP			1'b1
+`else
+`define OR1200_UPR_DUP			1'b0
+`endif
+`define OR1200_UPR_PCUP			1'b0	// Performance counters not present
+`ifdef OR1200_PM_IMPLEMENTED
+`define OR1200_UPR_PMP			1'b1
+`else
+`define OR1200_UPR_PMP			1'b0
+`endif
+`ifdef OR1200_PIC_IMPLEMENTED
+`define OR1200_UPR_PICP			1'b1
+`else
+`define OR1200_UPR_PICP			1'b0
+`endif
+`ifdef OR1200_TT_IMPLEMENTED
+`define OR1200_UPR_TTP			1'b1
+`else
+`define OR1200_UPR_TTP			1'b0
+`endif
+`ifdef OR1200_FPU_IMPLEMENTED
+`define OR1200_UPR_FPP			1'b1
+`else
+`define OR1200_UPR_FPP			1'b0
+`endif
+`define OR1200_UPR_RES1			12'h000
+`define OR1200_UPR_CUP			8'h00
+
+// CPUCFGR fields
+`define OR1200_CPUCFGR_NSGF_BITS	3:0
+`define OR1200_CPUCFGR_HGF_BITS     4
+`define OR1200_CPUCFGR_OB32S_BITS	5
+`define OR1200_CPUCFGR_OB64S_BITS	6
+`define OR1200_CPUCFGR_OF32S_BITS	7
+`define OR1200_CPUCFGR_OF64S_BITS	8
+`define OR1200_CPUCFGR_OV64S_BITS	9
+`define OR1200_CPUCFGR_RES1_BITS	31:10
+
+// CPUCFGR values
+`define OR1200_CPUCFGR_NSGF		    4'h0
+`ifdef OR1200_RFRAM_16REG
+    `define OR1200_CPUCFGR_HGF  		1'b1
+`else
+    `define OR1200_CPUCFGR_HGF  		1'b0
+`endif
+`define OR1200_CPUCFGR_OB32S		1'b1
+`define OR1200_CPUCFGR_OB64S		1'b0
+`ifdef OR1200_FPU_IMPLEMENTED
+ `define OR1200_CPUCFGR_OF32S		1'b1
+`else
+ `define OR1200_CPUCFGR_OF32S		1'b0
+`endif
+
+`define OR1200_CPUCFGR_OF64S		1'b0
+`define OR1200_CPUCFGR_OV64S		1'b0
+`define OR1200_CPUCFGR_RES1		22'h000000
+
+// DMMUCFGR fields
+`define OR1200_DMMUCFGR_NTW_BITS	1:0
+`define OR1200_DMMUCFGR_NTS_BITS	4:2
+`define OR1200_DMMUCFGR_NAE_BITS	7:5
+`define OR1200_DMMUCFGR_CRI_BITS	8
+`define OR1200_DMMUCFGR_PRI_BITS	9
+`define OR1200_DMMUCFGR_TEIRI_BITS	10
+`define OR1200_DMMUCFGR_HTR_BITS	11
+`define OR1200_DMMUCFGR_RES1_BITS	31:12
+
+// DMMUCFGR values
+`ifdef OR1200_NO_DMMU
+`define OR1200_DMMUCFGR_NTW		2'h0	// Irrelevant
+`define OR1200_DMMUCFGR_NTS		3'h0	// Irrelevant
+`define OR1200_DMMUCFGR_NAE		3'h0	// Irrelevant
+`define OR1200_DMMUCFGR_CRI		1'b0	// Irrelevant
+`define OR1200_DMMUCFGR_PRI		1'b0	// Irrelevant
+`define OR1200_DMMUCFGR_TEIRI		1'b0	// Irrelevant
+`define OR1200_DMMUCFGR_HTR		1'b0	// Irrelevant
+`define OR1200_DMMUCFGR_RES1		20'h00000
+`else
+`define OR1200_DMMUCFGR_NTW		2'h0	// 1 TLB way
+`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW	// Num TLB sets
+`define OR1200_DMMUCFGR_NAE		3'h0	// No ATB entries
+`define OR1200_DMMUCFGR_CRI		1'b0	// No control register
+`define OR1200_DMMUCFGR_PRI		1'b0	// No protection reg
+`define OR1200_DMMUCFGR_TEIRI		1'b0	// TLB entry inv reg NOT impl.
+`define OR1200_DMMUCFGR_HTR		1'b0	// No HW TLB reload
+`define OR1200_DMMUCFGR_RES1		20'h00000
+`endif
+
+// IMMUCFGR fields
+`define OR1200_IMMUCFGR_NTW_BITS	1:0
+`define OR1200_IMMUCFGR_NTS_BITS	4:2
+`define OR1200_IMMUCFGR_NAE_BITS	7:5
+`define OR1200_IMMUCFGR_CRI_BITS	8
+`define OR1200_IMMUCFGR_PRI_BITS	9
+`define OR1200_IMMUCFGR_TEIRI_BITS	10
+`define OR1200_IMMUCFGR_HTR_BITS	11
+`define OR1200_IMMUCFGR_RES1_BITS	31:12
+
+// IMMUCFGR values
+`ifdef OR1200_NO_IMMU
+`define OR1200_IMMUCFGR_NTW		2'h0	// Irrelevant
+`define OR1200_IMMUCFGR_NTS		3'h0	// Irrelevant
+`define OR1200_IMMUCFGR_NAE		3'h0	// Irrelevant
+`define OR1200_IMMUCFGR_CRI		1'b0	// Irrelevant
+`define OR1200_IMMUCFGR_PRI		1'b0	// Irrelevant
+`define OR1200_IMMUCFGR_TEIRI		1'b0	// Irrelevant
+`define OR1200_IMMUCFGR_HTR		1'b0	// Irrelevant
+`define OR1200_IMMUCFGR_RES1		20'h00000
+`else
+`define OR1200_IMMUCFGR_NTW		2'h0	// 1 TLB way
+`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW	// Num TLB sets
+`define OR1200_IMMUCFGR_NAE		3'h0	// No ATB entry
+`define OR1200_IMMUCFGR_CRI		1'b0	// No control reg
+`define OR1200_IMMUCFGR_PRI		1'b0	// No protection reg
+`define OR1200_IMMUCFGR_TEIRI		1'b0	// TLB entry inv reg NOT impl
+`define OR1200_IMMUCFGR_HTR		1'b0	// No HW TLB reload
+`define OR1200_IMMUCFGR_RES1		20'h00000
+`endif
+
+// DCCFGR fields
+`define OR1200_DCCFGR_NCW_BITS		2:0
+`define OR1200_DCCFGR_NCS_BITS		6:3
+`define OR1200_DCCFGR_CBS_BITS		7
+`define OR1200_DCCFGR_CWS_BITS		8
+`define OR1200_DCCFGR_CCRI_BITS		9
+`define OR1200_DCCFGR_CBIRI_BITS	10
+`define OR1200_DCCFGR_CBPRI_BITS	11
+`define OR1200_DCCFGR_CBLRI_BITS	12
+`define OR1200_DCCFGR_CBFRI_BITS	13
+`define OR1200_DCCFGR_CBWBRI_BITS	14
+`define OR1200_DCCFGR_RES1_BITS	31:15
+
+// DCCFGR values
+`ifdef OR1200_NO_DC
+`define OR1200_DCCFGR_NCW		3'h0	// Irrelevant
+`define OR1200_DCCFGR_NCS		4'h0	// Irrelevant
+`define OR1200_DCCFGR_CBS		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CWS		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CCRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBIRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBPRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBLRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBFRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBWBRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_RES1		17'h00000
+`else
+`define OR1200_DCCFGR_NCW		3'h0	// 1 cache way
+`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)	// Num cache sets
+`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
+`ifdef OR1200_DC_WRITETHROUGH
+ `define OR1200_DCCFGR_CWS		1'b0	// Write-through strategy
+`else
+ `define OR1200_DCCFGR_CWS		1'b1	// Write-back strategy
+`endif
+`define OR1200_DCCFGR_CCRI		1'b1	// Cache control reg impl.
+`define OR1200_DCCFGR_CBIRI		1'b1	// Cache block inv reg impl.
+`define OR1200_DCCFGR_CBPRI		1'b0	// Cache block prefetch reg not impl.
+`define OR1200_DCCFGR_CBLRI		1'b0	// Cache block lock reg not impl.
+`define OR1200_DCCFGR_CBFRI		1'b1	// Cache block flush reg impl.
+`ifdef OR1200_DC_WRITETHROUGH
+ `define OR1200_DCCFGR_CBWBRI		1'b0	// Cache block WB reg not impl.
+`else
+ `define OR1200_DCCFGR_CBWBRI		1'b1	// Cache block WB reg impl.
+`endif
+`define OR1200_DCCFGR_RES1		17'h00000
+`endif
+
+// ICCFGR fields
+`define OR1200_ICCFGR_NCW_BITS		2:0
+`define OR1200_ICCFGR_NCS_BITS		6:3
+`define OR1200_ICCFGR_CBS_BITS		7
+`define OR1200_ICCFGR_CWS_BITS		8
+`define OR1200_ICCFGR_CCRI_BITS		9
+`define OR1200_ICCFGR_CBIRI_BITS	10
+`define OR1200_ICCFGR_CBPRI_BITS	11
+`define OR1200_ICCFGR_CBLRI_BITS	12
+`define OR1200_ICCFGR_CBFRI_BITS	13
+`define OR1200_ICCFGR_CBWBRI_BITS	14
+`define OR1200_ICCFGR_RES1_BITS	31:15
+
+// ICCFGR values
+`ifdef OR1200_NO_IC
+`define OR1200_ICCFGR_NCW		3'h0	// Irrelevant
+`define OR1200_ICCFGR_NCS 		4'h0	// Irrelevant
+`define OR1200_ICCFGR_CBS 		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CWS		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CCRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBIRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBPRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBLRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBFRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBWBRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_RES1		17'h00000
+`else
+`define OR1200_ICCFGR_NCW		3'h0	// 1 cache way
+`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)	// Num cache sets
+`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1	// 16 byte cache block
+`define OR1200_ICCFGR_CWS		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CCRI		1'b1	// Cache control reg impl.
+`define OR1200_ICCFGR_CBIRI		1'b1	// Cache block inv reg impl.
+`define OR1200_ICCFGR_CBPRI		1'b0	// Cache block prefetch reg not impl.
+`define OR1200_ICCFGR_CBLRI		1'b0	// Cache block lock reg not impl.
+`define OR1200_ICCFGR_CBFRI		1'b1	// Cache block flush reg impl.
+`define OR1200_ICCFGR_CBWBRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_RES1		17'h00000
+`endif
+
+// DCFGR fields
+`define OR1200_DCFGR_NDP_BITS		3:0
+`define OR1200_DCFGR_WPCI_BITS		4
+`define OR1200_DCFGR_RES1_BITS		31:5
+
+// DCFGR values
+`ifdef OR1200_DU_HWBKPTS
+`define OR1200_DCFGR_NDP		4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
+`ifdef OR1200_DU_DWCR0
+`define OR1200_DCFGR_WPCI		1'b1
+`else
+`define OR1200_DCFGR_WPCI		1'b0	// WP counters not impl.
+`endif
+`else
+`define OR1200_DCFGR_NDP		4'h0	// Zero DVR/DCR pairs
+`define OR1200_DCFGR_WPCI		1'b0	// WP counters not impl.
+`endif
+`define OR1200_DCFGR_RES1		27'd0
+
+///////////////////////////////////////////////////////////////////////////////
+// Boot Address Selection                                                    //
+//                                                                           //
+// Allows a definable boot address, potentially different to the usual reset //
+// vector to allow for power-on code to be run, if desired.                  //
+//                                                                           //
+// OR1200_BOOT_ADR should be the 32-bit address of the boot location         //
+// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2)              //
+//                                                                           //
+// For default reset behavior uncomment the settings under the "Boot 0x100"  //
+// comment below.                                                            //
+//                                                                           //
+///////////////////////////////////////////////////////////////////////////////
+// Boot from 0xf0000100
+//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
+//`define OR1200_BOOT_ADR 32'hf0000100
+// Boot from 0x100
+`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
+`define OR1200_BOOT_ADR 32'h00000100
diff --git a/systems/de2/rtl/verilog/include/orpsoc-defines.v b/systems/de2/rtl/verilog/include/orpsoc-defines.v
new file mode 100755
index 00000000..af1605e8
--- /dev/null
+++ b/systems/de2/rtl/verilog/include/orpsoc-defines.v
@@ -0,0 +1,39 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// orpsoc-defines                                               ////
+////                                                              ////
+//// Top level ORPSoC defines file                                ////
+////                                                              ////
+//// Included in toplevel and testbench                           ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+// Included modules: define to include
+`define BOOTROM
+`define OR1200_CPU
+// end of included module defines - keep this comment line here
diff --git a/systems/de2/rtl/verilog/include/timescale.v b/systems/de2/rtl/verilog/include/timescale.v
new file mode 100755
index 00000000..e66f979c
--- /dev/null
+++ b/systems/de2/rtl/verilog/include/timescale.v
@@ -0,0 +1 @@
+`timescale 1ns/1ps
diff --git a/systems/de2/rtl/verilog/include/uart_defines.v b/systems/de2/rtl/verilog/include/uart_defines.v
new file mode 100755
index 00000000..f9c567a1
--- /dev/null
+++ b/systems/de2/rtl/verilog/include/uart_defines.v
@@ -0,0 +1,250 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  uart_defines.v                                              ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the "UART 16550 compatible" project    ////
+////  http://www.opencores.org/cores/uart16550/                   ////
+////                                                              ////
+////  Documentation related to this project:                      ////
+////  - http://www.opencores.org/cores/uart16550/                 ////
+////                                                              ////
+////  Projects compatibility:                                     ////
+////  - WISHBONE                                                  ////
+////  RS232 Protocol                                              ////
+////  16550D uart (mostly supported)                              ////
+////                                                              ////
+////  Overview (main Features):                                   ////
+////  Defines of the Core                                         ////
+////                                                              ////
+////  Known problems (limits):                                    ////
+////  None                                                        ////
+////                                                              ////
+////  To Do:                                                      ////
+////  Nothing.                                                    ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - gorban@opencores.org                                  ////
+////      - Jacob Gorban                                          ////
+////      - Igor Mohor (igorm@opencores.org)                      ////
+////                                                              ////
+////  Created:        2001/05/12                                  ////
+////  Last Updated:   2001/05/17                                  ////
+////                  (See log for the revision history)          ////
+////                                                              ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000, 2001 Authors                             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.13  2003/06/11 16:37:47  gorban
+// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
+//
+// Revision 1.12  2002/07/22 23:02:23  gorban
+// Bug Fixes:
+//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+//   Problem reported by Kenny.Tung.
+//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+//  * Made FIFO's as general inferrable memory where possible.
+//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+//  * Added optional baudrate output (baud_o).
+//  This is identical to BAUDOUT* signal on 16550 chip.
+//  It outputs 16xbit_clock_rate - the divided clock.
+//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.10  2001/12/11 08:55:40  mohor
+// Scratch register define added.
+//
+// Revision 1.9  2001/12/03 21:44:29  gorban
+// Updated specification documentation.
+// Added full 32-bit data bus interface, now as default.
+// Address is 5-bit wide in 32-bit data bus mode.
+// Added wb_sel_i input to the core. It's used in the 32-bit mode.
+// Added debug interface with two 32-bit read-only registers in 32-bit mode.
+// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
+// My small test bench is modified to work with 32-bit mode.
+//
+// Revision 1.8  2001/11/26 21:38:54  gorban
+// Lots of fixes:
+// Break condition wasn't handled correctly at all.
+// LSR bits could lose their values.
+// LSR value after reset was wrong.
+// Timing of THRE interrupt signal corrected.
+// LSR bit 0 timing corrected.
+//
+// Revision 1.7  2001/08/24 21:01:12  mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.6  2001/08/23 16:05:05  mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.5  2001/05/31 20:08:01  gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.4  2001/05/21 19:12:02  gorban
+// Corrected some Linter messages.
+//
+// Revision 1.3  2001/05/17 18:34:18  gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0  2001-05-17 21:27:11+02  jacob
+// Initial revision
+//
+//
+
+// remove comments to restore to use the new version with 8 data bit interface
+// in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place
+// also, in 8-bit version there'll be no debugging features included
+// CAUTION: doesn't work with current version of OR1200
+`define DATA_BUS_WIDTH_8
+
+`ifdef DATA_BUS_WIDTH_8
+ `define UART_ADDR_WIDTH 3
+ `define UART_DATA_WIDTH 8
+`else
+ `define UART_ADDR_WIDTH 5
+ `define UART_DATA_WIDTH 32
+`endif
+
+// Uncomment this if you want your UART to have
+// 16xBaudrate output port.
+// If defined, the enable signal will be used to drive baudrate_o signal
+// It's frequency is 16xbaudrate
+
+// `define UART_HAS_BAUDRATE_OUTPUT
+
+// Register addresses
+`define UART_REG_RB	`UART_ADDR_WIDTH'd0	// receiver buffer
+`define UART_REG_TR  `UART_ADDR_WIDTH'd0	// transmitter
+`define UART_REG_IE	`UART_ADDR_WIDTH'd1	// Interrupt enable
+`define UART_REG_II  `UART_ADDR_WIDTH'd2	// Interrupt identification
+`define UART_REG_FC  `UART_ADDR_WIDTH'd2	// FIFO control
+`define UART_REG_LC	`UART_ADDR_WIDTH'd3	// Line Control
+`define UART_REG_MC	`UART_ADDR_WIDTH'd4	// Modem control
+`define UART_REG_LS  `UART_ADDR_WIDTH'd5	// Line status
+`define UART_REG_MS  `UART_ADDR_WIDTH'd6	// Modem status
+`define UART_REG_SR  `UART_ADDR_WIDTH'd7	// Scratch register
+`define UART_REG_DL1	`UART_ADDR_WIDTH'd0	// Divisor latch bytes (1-2)
+`define UART_REG_DL2	`UART_ADDR_WIDTH'd1
+
+// Interrupt Enable register bits
+`define UART_IE_RDA	0	// Received Data available interrupt
+`define UART_IE_THRE	1	// Transmitter Holding Register empty interrupt
+`define UART_IE_RLS	2	// Receiver Line Status Interrupt
+`define UART_IE_MS	3	// Modem Status Interrupt
+
+// Interrupt Identification register bits
+`define UART_II_IP	0	// Interrupt pending when 0
+`define UART_II_II	3:1	// Interrupt identification
+
+// Interrupt identification values for bits 3:1
+`define UART_II_RLS	3'b011	// Receiver Line Status
+`define UART_II_RDA	3'b010	// Receiver Data available
+`define UART_II_TI	3'b110	// Timeout Indication
+`define UART_II_THRE	3'b001	// Transmitter Holding Register empty
+`define UART_II_MS	3'b000	// Modem Status
+
+// FIFO Control Register bits
+`define UART_FC_TL	1:0	// Trigger level
+
+// FIFO trigger level values
+`define UART_FC_1		2'b00
+`define UART_FC_4		2'b01
+`define UART_FC_8		2'b10
+`define UART_FC_14	2'b11
+
+// Line Control register bits
+`define UART_LC_BITS	1:0	// bits in character
+`define UART_LC_SB	2	// stop bits
+`define UART_LC_PE	3	// parity enable
+`define UART_LC_EP	4	// even parity
+`define UART_LC_SP	5	// stick parity
+`define UART_LC_BC	6	// Break control
+`define UART_LC_DL	7	// Divisor Latch access bit
+
+// Modem Control register bits
+`define UART_MC_DTR	0
+`define UART_MC_RTS	1
+`define UART_MC_OUT1	2
+`define UART_MC_OUT2	3
+`define UART_MC_LB	4	// Loopback mode
+
+// Line Status Register bits
+`define UART_LS_DR	0	// Data ready
+`define UART_LS_OE	1	// Overrun Error
+`define UART_LS_PE	2	// Parity Error
+`define UART_LS_FE	3	// Framing Error
+`define UART_LS_BI	4	// Break interrupt
+`define UART_LS_TFE	5	// Transmit FIFO is empty
+`define UART_LS_TE	6	// Transmitter Empty indicator
+`define UART_LS_EI	7	// Error indicator
+
+// Modem Status Register bits
+`define UART_MS_DCTS	0	// Delta signals
+`define UART_MS_DDSR	1
+`define UART_MS_TERI	2
+`define UART_MS_DDCD	3
+`define UART_MS_CCTS	4	// Complement signals
+`define UART_MS_CDSR	5
+`define UART_MS_CRI	6
+`define UART_MS_CDCD	7
+
+// FIFO parameter defines
+
+`define UART_FIFO_WIDTH	8
+`define UART_FIFO_DEPTH	16
+`define UART_FIFO_POINTER_W	4
+`define UART_FIFO_COUNTER_W	5
+// receiver fifo has width 11 because it has break, parity and framing error bits
+`define UART_FIFO_REC_WIDTH  11
+
+
+`define VERBOSE_WB  0           // All activity on the WISHBONE is recorded
+`define VERBOSE_LINE_STATUS 0   // Details about the lsr (line status register)
+`define FAST_TEST   1           // 64/1024 packets are sent
+
+// Defines hard baud prescaler register - uncomment to enable
+//`define PRESCALER_PRESET_HARD
+// 115200 baud preset values
+// 20MHz: prescaler 10.8 (11, rounded up)
+//`define PRESCALER_HIGH_PRESET 8'd0
+//`define PRESCALER_LOW_PRESET 8'd11
+// 50MHz: prescaler 27.1
+//`define PRESCALER_HIGH_PRESET 8'd0
+//`define PRESCALER_LOW_PRESET 8'd27
diff --git a/systems/de2/rtl/verilog/orpsoc_top.v b/systems/de2/rtl/verilog/orpsoc_top.v
new file mode 100755
index 00000000..4975e096
--- /dev/null
+++ b/systems/de2/rtl/verilog/orpsoc_top.v
@@ -0,0 +1,705 @@
+//////////////////////////////////////////////////////////////////////
+///                                                               ////
+/// ORPSoC top for Altera de1 board                               ////
+///                                                               ////
+/// Franck Jullien, franck.jullien@gmail.com                      ////
+///                                                               ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "orpsoc-defines.v"
+
+module orpsoc_top #(
+	parameter	rom0_aw = 6,
+	parameter	uart0_aw = 3
+)
+(
+	input		sys_clk_pad_i,
+	input		rst_n_pad_i,
+
+	output	[9:0]	led_r_pad_o,
+	inout	[7:0]	gpio0_io,
+
+`ifdef SIM
+	output		tdo_pad_o,
+	input		tms_pad_i,
+	input		tck_pad_i,
+	input		tdi_pad_i,
+`endif
+
+	output	[1:0]	sdram_ba_pad_o,
+	output	[11:0]	sdram_a_pad_o,
+	output		sdram_cs_n_pad_o,
+	output		sdram_ras_pad_o,
+	output		sdram_cas_pad_o,
+	output		sdram_we_pad_o,
+	inout	[15:0]	sdram_dq_pad_io,
+	output	[1:0]	sdram_dqm_pad_o,
+	output		sdram_cke_pad_o,
+	output		sdram_clk_pad_o,
+
+	input		uart0_srx_pad_i,
+	output		uart0_stx_pad_o
+);
+
+parameter	IDCODE_VALUE = 32'h14951185;
+
+////////////////////////////////////////////////////////////////////////
+//
+// Clock and reset generation module
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	async_rst;
+wire	wb_clk, wb_rst;
+wire	dbg_tck;
+wire	sdram_clk;
+wire	sdram_rst;
+
+assign	sdram_clk_pad_o = sdram_clk;
+
+clkgen clkgen0 (
+	.sys_clk_pad_i	(sys_clk_pad_i),
+	.rst_n_pad_i	(rst_n_pad_i),
+	.async_rst_o	(async_rst),
+	.wb_clk_o	(wb_clk),
+	.wb_rst_o	(wb_rst),
+`ifdef SIM
+	.tck_pad_i	(tck_pad_i),
+	.dbg_tck_o	(dbg_tck),
+`endif
+	.sdram_clk_o	(sdram_clk),
+	.sdram_rst_o	(sdram_rst)
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// Modules interconnections
+//
+////////////////////////////////////////////////////////////////////////
+
+`include "wb_intercon.vh"
+
+`ifdef SIM
+////////////////////////////////////////////////////////////////////////
+//
+// GENERIC JTAG TAP
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	dbg_if_select;
+wire	dbg_if_tdo;
+wire	jtag_tap_tdo;
+wire	jtag_tap_shift_dr;
+wire	jtag_tap_pause_dr;
+wire	jtag_tap_update_dr;
+wire	jtag_tap_capture_dr;
+
+tap_top #(.IDCODE_VALUE(IDCODE_VALUE))
+jtag_tap0 (
+	.tdo_pad_o			(tdo_pad_o),
+	.tms_pad_i			(tms_pad_i),
+	.tck_pad_i			(dbg_tck),
+	.trst_pad_i			(async_rst),
+	.tdi_pad_i			(tdi_pad_i),
+
+	.tdo_padoe_o			(tdo_padoe_o),
+
+	.tdo_o				(jtag_tap_tdo),
+
+	.shift_dr_o			(jtag_tap_shift_dr),
+	.pause_dr_o			(jtag_tap_pause_dr),
+	.update_dr_o			(jtag_tap_update_dr),
+	.capture_dr_o			(jtag_tap_capture_dr),
+
+	.extest_select_o		(),
+	.sample_preload_select_o	(),
+	.mbist_select_o			(),
+	.debug_select_o			(dbg_if_select),
+
+
+	.bs_chain_tdi_i			(1'b0),
+	.mbist_tdi_i			(1'b0),
+	.debug_tdi_i			(dbg_if_tdo)
+);
+
+`else
+////////////////////////////////////////////////////////////////////////
+//
+// ALTERA Virtual JTAG TAP
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	dbg_if_select;
+wire	dbg_if_tdo;
+wire	jtag_tap_tdo;
+wire	jtag_tap_shift_dr;
+wire	jtag_tap_pause_dr;
+wire	jtag_tap_update_dr;
+wire	jtag_tap_capture_dr;
+
+altera_virtual_jtag jtag_tap0 (
+	.tck_o			(dbg_tck),
+	.debug_tdo_i		(dbg_if_tdo),
+	.tdi_o			(jtag_tap_tdo),
+	.test_logic_reset_o	(),
+	.run_test_idle_o	(),
+	.shift_dr_o		(jtag_tap_shift_dr),
+	.capture_dr_o		(jtag_tap_capture_dr),
+	.pause_dr_o		(jtag_tap_pause_dr),
+	.update_dr_o		(jtag_tap_update_dr),
+	.debug_select_o		(dbg_if_select)
+);
+`endif
+
+////////////////////////////////////////////////////////////////////////
+//
+// OR1K CPU
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	[31:0]	or1k_irq;
+
+wire	[31:0]	or1k_dbg_dat_i;
+wire	[31:0]	or1k_dbg_adr_i;
+wire		or1k_dbg_we_i;
+wire		or1k_dbg_stb_i;
+wire		or1k_dbg_ack_o;
+wire	[31:0]	or1k_dbg_dat_o;
+
+wire		or1k_dbg_stall_i;
+wire		or1k_dbg_ewt_i;
+wire	[3:0]	or1k_dbg_lss_o;
+wire	[1:0]	or1k_dbg_is_o;
+wire	[10:0]	or1k_dbg_wp_o;
+wire		or1k_dbg_bp_o;
+wire		or1k_dbg_rst;
+
+wire		sig_tick;
+wire		or1k_rst;
+
+assign	or1k_rst = wb_rst | or1k_dbg_rst;
+
+`ifdef OR1200_CPU
+
+or1200_top #(.boot_adr(32'hf0000100))
+or1200_top0 (
+	// Instruction bus, clocks, reset
+	.iwb_clk_i		(wb_clk),
+	.iwb_rst_i		(wb_rst),
+	.iwb_ack_i		(wb_s2m_or1k_i_ack),
+	.iwb_err_i		(wb_s2m_or1k_i_err),
+	.iwb_rty_i		(wb_s2m_or1k_i_rty),
+	.iwb_dat_i		(wb_s2m_or1k_i_dat),
+
+	.iwb_cyc_o		(wb_m2s_or1k_i_cyc),
+	.iwb_adr_o		(wb_m2s_or1k_i_adr),
+	.iwb_stb_o		(wb_m2s_or1k_i_stb),
+	.iwb_we_o		(wb_m2s_or1k_i_we),
+	.iwb_sel_o		(wb_m2s_or1k_i_sel),
+	.iwb_dat_o		(wb_m2s_or1k_i_dat),
+	.iwb_cti_o		(wb_m2s_or1k_i_cti),
+	.iwb_bte_o		(wb_m2s_or1k_i_bte),
+
+	// Data bus, clocks, reset
+	.dwb_clk_i		(wb_clk),
+	.dwb_rst_i		(wb_rst),
+	.dwb_ack_i		(wb_s2m_or1k_d_ack),
+	.dwb_err_i		(wb_s2m_or1k_d_err),
+	.dwb_rty_i		(wb_s2m_or1k_d_rty),
+	.dwb_dat_i		(wb_s2m_or1k_d_dat),
+
+	.dwb_cyc_o		(wb_m2s_or1k_d_cyc),
+	.dwb_adr_o		(wb_m2s_or1k_d_adr),
+	.dwb_stb_o		(wb_m2s_or1k_d_stb),
+	.dwb_we_o		(wb_m2s_or1k_d_we),
+	.dwb_sel_o		(wb_m2s_or1k_d_sel),
+	.dwb_dat_o		(wb_m2s_or1k_d_dat),
+	.dwb_cti_o		(wb_m2s_or1k_d_cti),
+	.dwb_bte_o		(wb_m2s_or1k_d_bte),
+
+	// Debug interface ports
+	.dbg_stall_i		(or1k_dbg_stall_i),
+	.dbg_ewt_i		(1'b0),
+	.dbg_lss_o		(or1k_dbg_lss_o),
+	.dbg_is_o		(or1k_dbg_is_o),
+	.dbg_wp_o		(or1k_dbg_wp_o),
+	.dbg_bp_o		(or1k_dbg_bp_o),
+
+	.dbg_adr_i		(or1k_dbg_adr_i),
+	.dbg_we_i		(or1k_dbg_we_i),
+	.dbg_stb_i		(or1k_dbg_stb_i),
+	.dbg_dat_i		(or1k_dbg_dat_i),
+	.dbg_dat_o		(or1k_dbg_dat_o),
+	.dbg_ack_o		(or1k_dbg_ack_o),
+
+	.pm_clksd_o		(),
+	.pm_dc_gate_o		(),
+	.pm_ic_gate_o		(),
+	.pm_dmmu_gate_o		(),
+	.pm_immu_gate_o		(),
+	.pm_tt_gate_o		(),
+	.pm_cpu_gate_o		(),
+	.pm_wakeup_o		(),
+	.pm_lvolt_o		(),
+
+	// Core clocks, resets
+	.clk_i			(wb_clk),
+	.rst_i			(or1k_rst),
+
+	.clmode_i		(2'b00),
+
+	// Interrupts
+	.pic_ints_i		(or1k_irq[30:0]),
+	.sig_tick		(sig_tick),
+
+	.pm_cpustall_i		(1'b0)
+);
+
+`else
+
+mor1kx	#(
+	.FEATURE_DEBUGUNIT		("ENABLED"),
+	.FEATURE_CMOV			("ENABLED"),
+	.FEATURE_INSTRUCTIONCACHE	("ENABLED"),
+	.OPTION_ICACHE_BLOCK_WIDTH	(5),
+	.OPTION_ICACHE_SET_WIDTH	(3),
+	.OPTION_ICACHE_WAYS		(2),
+	.OPTION_ICACHE_LIMIT_WIDTH	(32),
+	.FEATURE_IMMU			("ENABLED"),
+	.FEATURE_DATACACHE		("ENABLED"),
+	.OPTION_DCACHE_BLOCK_WIDTH	(5),
+	.OPTION_DCACHE_SET_WIDTH	(3),
+	.OPTION_DCACHE_WAYS		(2),
+	.OPTION_DCACHE_LIMIT_WIDTH	(31),
+	.FEATURE_DMMU			("ENABLED"),
+	.OPTION_PIC_TRIGGER		("LATCHED_LEVEL"),
+
+	.IBUS_WB_TYPE			("B3_REGISTERED_FEEDBACK"),
+	.DBUS_WB_TYPE			("B3_REGISTERED_FEEDBACK"),
+	.OPTION_CPU0			("CAPPUCCINO"),
+	.OPTION_RESET_PC		(32'hf0000100)
+) mor1kx0 (
+	.iwbm_adr_o			(wb_m2s_or1k_i_adr),
+	.iwbm_stb_o			(wb_m2s_or1k_i_stb),
+	.iwbm_cyc_o			(wb_m2s_or1k_i_cyc),
+	.iwbm_sel_o			(wb_m2s_or1k_i_sel),
+	.iwbm_we_o			(wb_m2s_or1k_i_we),
+	.iwbm_cti_o			(wb_m2s_or1k_i_cti),
+	.iwbm_bte_o			(wb_m2s_or1k_i_bte),
+	.iwbm_dat_o			(wb_m2s_or1k_i_dat),
+
+	.dwbm_adr_o			(wb_m2s_or1k_d_adr),
+	.dwbm_stb_o			(wb_m2s_or1k_d_stb),
+	.dwbm_cyc_o			(wb_m2s_or1k_d_cyc),
+	.dwbm_sel_o			(wb_m2s_or1k_d_sel),
+	.dwbm_we_o			(wb_m2s_or1k_d_we ),
+	.dwbm_cti_o			(wb_m2s_or1k_d_cti),
+	.dwbm_bte_o			(wb_m2s_or1k_d_bte),
+	.dwbm_dat_o			(wb_m2s_or1k_d_dat),
+
+	.clk				(wb_clk),
+	.rst				(or1k_rst),
+
+	.iwbm_err_i			(wb_s2m_or1k_i_err),
+	.iwbm_ack_i			(wb_s2m_or1k_i_ack),
+	.iwbm_dat_i			(wb_s2m_or1k_i_dat),
+	.iwbm_rty_i			(wb_s2m_or1k_i_rty),
+
+	.dwbm_err_i			(wb_s2m_or1k_d_err),
+	.dwbm_ack_i			(wb_s2m_or1k_d_ack),
+	.dwbm_dat_i			(wb_s2m_or1k_d_dat),
+	.dwbm_rty_i			(wb_s2m_or1k_d_rty),
+
+	.irq_i				(or1k_irq),
+
+	.du_addr_i			(or1k_dbg_adr_i[15:0]),
+	.du_stb_i			(or1k_dbg_stb_i),
+	.du_dat_i			(or1k_dbg_dat_i),
+	.du_we_i			(or1k_dbg_we_i),
+	.du_dat_o			(or1k_dbg_dat_o),
+	.du_ack_o			(or1k_dbg_ack_o),
+	.du_stall_i			(or1k_dbg_stall_i),
+	.du_stall_o			(or1k_dbg_bp_o)
+);
+`endif
+
+////////////////////////////////////////////////////////////////////////
+//
+// Debug Interface
+//
+////////////////////////////////////////////////////////////////////////
+
+adbg_top dbg_if0 (
+	// OR1K interface
+	.cpu0_clk_i	(wb_clk),
+	.cpu0_rst_o	(or1k_dbg_rst),
+	.cpu0_addr_o	(or1k_dbg_adr_i),
+	.cpu0_data_o	(or1k_dbg_dat_i),
+	.cpu0_stb_o	(or1k_dbg_stb_i),
+	.cpu0_we_o	(or1k_dbg_we_i),
+	.cpu0_data_i	(or1k_dbg_dat_o),
+	.cpu0_ack_i	(or1k_dbg_ack_o),
+	.cpu0_stall_o	(or1k_dbg_stall_i),
+	.cpu0_bp_i	(or1k_dbg_bp_o),
+
+	// TAP interface
+	.tck_i		(dbg_tck),
+	.tdi_i		(jtag_tap_tdo),
+	.tdo_o		(dbg_if_tdo),
+	.rst_i		(wb_rst),
+	.capture_dr_i	(jtag_tap_capture_dr),
+	.shift_dr_i	(jtag_tap_shift_dr),
+	.pause_dr_i	(jtag_tap_pause_dr),
+	.update_dr_i	(jtag_tap_update_dr),
+	.debug_select_i	(dbg_if_select),
+
+	// Wishbone debug master
+	.wb_clk_i	(wb_clk),
+	.wb_dat_i	(wb_s2m_dbg_dat),
+	.wb_ack_i	(wb_s2m_dbg_ack),
+	.wb_err_i	(wb_s2m_dbg_err),
+
+	.wb_adr_o	(wb_m2s_dbg_adr),
+	.wb_dat_o	(wb_m2s_dbg_dat),
+	.wb_cyc_o	(wb_m2s_dbg_cyc),
+	.wb_stb_o	(wb_m2s_dbg_stb),
+	.wb_sel_o	(wb_m2s_dbg_sel),
+	.wb_we_o	(wb_m2s_dbg_we),
+	.wb_cti_o	(wb_m2s_dbg_cti),
+	.wb_bte_o	(wb_m2s_dbg_bte)
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// ROM
+//
+////////////////////////////////////////////////////////////////////////
+
+assign	wb_s2m_rom0_err = 1'b0;
+assign	wb_s2m_rom0_rty = 1'b0;
+
+`ifdef BOOTROM
+rom #(.ADDR_WIDTH(rom0_aw))
+rom0 (
+	.wb_clk		(wb_clk),
+	.wb_rst		(wb_rst),
+	.wb_adr_i	(wb_m2s_rom0_adr[(rom0_aw + 2) - 1 : 2]),
+	.wb_cyc_i	(wb_m2s_rom0_cyc),
+	.wb_stb_i	(wb_m2s_rom0_stb),
+	.wb_cti_i	(wb_m2s_rom0_cti),
+	.wb_bte_i	(wb_m2s_rom0_bte),
+	.wb_dat_o	(wb_s2m_rom0_dat),
+	.wb_ack_o	(wb_s2m_rom0_ack)
+);
+`else
+assign	wb_s2m_rom0_dat_o = 0;
+assign	wb_s2m_rom0_ack_o = 0;
+`endif
+
+////////////////////////////////////////////////////////////////////////
+//
+// SDRAM Memory Controller
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	[15:0]	sdram_dq_i;
+wire	[15:0]	sdram_dq_o;
+wire		sdram_dq_oe;
+
+assign	sdram_dq_i = sdram_dq_pad_io;
+assign	sdram_dq_pad_io = sdram_dq_oe ? sdram_dq_o : 16'bz;
+assign	sdram_clk_pad_o = sdram_clk;
+
+assign	wb_s2m_sdram_ibus_err = 0;
+assign	wb_s2m_sdram_ibus_rty = 0;
+
+assign	wb_s2m_sdram_dbus_err = 0;
+assign	wb_s2m_sdram_dbus_rty = 0;
+
+wb_sdram_ctrl #(
+`ifdef ICARUS_SIM
+	.TECHNOLOGY			("GENERIC"),
+`else
+	.TECHNOLOGY			("ALTERA"),
+`endif
+	.CLK_FREQ_MHZ			(100),	// sdram_clk freq in MHZ
+`ifdef SIM
+	.POWERUP_DELAY			(1),	// power up delay in us
+`endif
+	.WB_PORTS			(2),	// Number of wishbone ports
+	.BUF_WIDTH			(3),
+	.BURST_LENGTH			(8),
+	.ROW_WIDTH			(12),	// Row width
+	.COL_WIDTH			(8),	// Column width
+	.BA_WIDTH			(2),	// Ba width
+	.tCAC				(3),	// CAS Latency
+	.tRAC				(5),	// RAS Latency
+	.tRP				(3),	// Command Period (PRE to ACT)
+	.tRC				(7),	// Command Period (REF to REF / ACT to ACT)
+	.tMRD				(2)	// Mode Register Set To Command Delay time
+)
+
+wb_sdram_ctrl0 (
+	// External SDRAM interface
+	.ba_pad_o	(sdram_ba_pad_o[1:0]),
+	.a_pad_o	(sdram_a_pad_o[11:0]),
+	.cs_n_pad_o	(sdram_cs_n_pad_o),
+	.ras_pad_o	(sdram_ras_pad_o),
+	.cas_pad_o	(sdram_cas_pad_o),
+	.we_pad_o	(sdram_we_pad_o),
+	.dq_i		(sdram_dq_i[15:0]),
+	.dq_o		(sdram_dq_o[15:0]),
+	.dqm_pad_o	(sdram_dqm_pad_o[1:0]),
+	.dq_oe		(sdram_dq_oe),
+	.cke_pad_o	(sdram_cke_pad_o),
+
+	.sdram_clk	(sdram_clk),
+	.sdram_rst	(sdram_rst),
+
+	.wb_clk		(wb_clk),
+	.wb_rst		(wb_rst),
+
+	.wb_adr_i	({wb_m2s_sdram_ibus_adr, wb_m2s_sdram_dbus_adr}),
+	.wb_stb_i	({wb_m2s_sdram_ibus_stb, wb_m2s_sdram_dbus_stb}),
+	.wb_cyc_i	({wb_m2s_sdram_ibus_cyc, wb_m2s_sdram_dbus_cyc}),
+	.wb_cti_i	({wb_m2s_sdram_ibus_cti, wb_m2s_sdram_dbus_cti}),
+	.wb_bte_i	({wb_m2s_sdram_ibus_bte, wb_m2s_sdram_dbus_bte}),
+	.wb_we_i	({wb_m2s_sdram_ibus_we,  wb_m2s_sdram_dbus_we }),
+	.wb_sel_i	({wb_m2s_sdram_ibus_sel, wb_m2s_sdram_dbus_sel}),
+	.wb_dat_i	({wb_m2s_sdram_ibus_dat, wb_m2s_sdram_dbus_dat}),
+	.wb_dat_o	({wb_s2m_sdram_ibus_dat, wb_s2m_sdram_dbus_dat}),
+	.wb_ack_o	({wb_s2m_sdram_ibus_ack, wb_s2m_sdram_dbus_ack})
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// UART0
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	uart0_irq;
+
+wire [31:0]	wb8_m2s_uart0_adr;
+wire [1:0]	wb8_m2s_uart0_bte;
+wire [2:0]	wb8_m2s_uart0_cti;
+wire		wb8_m2s_uart0_cyc;
+wire [7:0]	wb8_m2s_uart0_dat;
+wire		wb8_m2s_uart0_stb;
+wire		wb8_m2s_uart0_we;
+wire [7:0] 	wb8_s2m_uart0_dat;
+wire		wb8_s2m_uart0_ack;
+wire		wb8_s2m_uart0_err;
+wire		wb8_s2m_uart0_rty;
+
+assign	wb8_s2m_uart0_err = 0;
+assign	wb8_s2m_uart0_rty = 0;
+
+uart_top uart16550_0 (
+	// Wishbone slave interface
+	.wb_clk_i	(wb_clk),
+	.wb_rst_i	(wb_rst),
+	.wb_adr_i	(wb8_m2s_uart0_adr[uart0_aw-1:0]),
+	.wb_dat_i	(wb8_m2s_uart0_dat),
+	.wb_we_i	(wb8_m2s_uart0_we),
+	.wb_stb_i	(wb8_m2s_uart0_stb),
+	.wb_cyc_i	(wb8_m2s_uart0_cyc),
+	.wb_sel_i	(4'b0), // Not used in 8-bit mode
+	.wb_dat_o	(wb8_s2m_uart0_dat),
+	.wb_ack_o	(wb8_s2m_uart0_ack),
+
+	// Outputs
+	.int_o		(uart0_irq),
+	.stx_pad_o	(uart0_stx_pad_o),
+	.rts_pad_o	(),
+	.dtr_pad_o	(),
+
+	// Inputs
+	.srx_pad_i	(uart0_srx_pad_i),
+	.cts_pad_i	(1'b0),
+	.dsr_pad_i	(1'b0),
+	.ri_pad_i	(1'b0),
+	.dcd_pad_i	(1'b0)
+);
+
+// 32-bit to 8-bit wishbone bus resize
+wb_data_resize wb_data_resize_uart0 (
+	// Wishbone Master interface
+	.wbm_adr_i	(wb_m2s_uart0_adr),
+	.wbm_dat_i	(wb_m2s_uart0_dat),
+	.wbm_sel_i	(wb_m2s_uart0_sel),
+	.wbm_we_i	(wb_m2s_uart0_we ),
+	.wbm_cyc_i	(wb_m2s_uart0_cyc),
+	.wbm_stb_i	(wb_m2s_uart0_stb),
+	.wbm_cti_i	(wb_m2s_uart0_cti),
+	.wbm_bte_i	(wb_m2s_uart0_bte),
+	.wbm_dat_o	(wb_s2m_uart0_dat),
+	.wbm_ack_o	(wb_s2m_uart0_ack),
+	.wbm_err_o	(wb_s2m_uart0_err),
+	.wbm_rty_o	(wb_s2m_uart0_rty),
+
+	// Wishbone Slave interface
+	.wbs_adr_o	(wb8_m2s_uart0_adr),
+	.wbs_dat_o	(wb8_m2s_uart0_dat),
+	.wbs_we_o 	(wb8_m2s_uart0_we ),
+	.wbs_cyc_o	(wb8_m2s_uart0_cyc),
+	.wbs_stb_o	(wb8_m2s_uart0_stb),
+	.wbs_cti_o	(wb8_m2s_uart0_cti),
+	.wbs_bte_o	(wb8_m2s_uart0_bte),
+	.wbs_dat_i	(wb8_s2m_uart0_dat),
+	.wbs_ack_i	(wb8_s2m_uart0_ack),
+	.wbs_err_i	(wb8_s2m_uart0_err),
+	.wbs_rty_i	(wb8_s2m_uart0_rty)
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// GPIO 0
+//
+////////////////////////////////////////////////////////////////////////
+
+wire [7:0]	gpio0_in;
+wire [7:0]	gpio0_out;
+wire [7:0]	gpio0_dir;
+
+wire [31:0]	wb8_m2s_gpio0_adr;
+wire [1:0]	wb8_m2s_gpio0_bte;
+wire [2:0]	wb8_m2s_gpio0_cti;
+wire		wb8_m2s_gpio0_cyc;
+wire [7:0]	wb8_m2s_gpio0_dat;
+wire		wb8_m2s_gpio0_stb;
+wire		wb8_m2s_gpio0_we;
+wire [7:0] 	wb8_s2m_gpio0_dat;
+wire		wb8_s2m_gpio0_ack;
+wire		wb8_s2m_gpio0_err;
+wire		wb8_s2m_gpio0_rty;
+
+// Tristate logic for IO
+// 0 = input, 1 = output
+genvar                    i;
+generate
+	for (i = 0; i < 8; i = i+1) begin: gpio0_tris
+		assign gpio0_io[i] = gpio0_dir[i] ? gpio0_out[i] : 1'bz;
+		assign gpio0_in[i] = gpio0_dir[i] ? gpio0_out[i] : gpio0_io[i];
+	end
+endgenerate
+
+gpio gpio0 (
+	// GPIO bus
+	.gpio_i		(gpio0_in),
+	.gpio_o		(gpio0_out),
+	.gpio_dir_o	(gpio0_dir),
+
+	// Wishbone slave interface
+	.wb_adr_i	(wb8_m2s_gpio0_adr[0]),
+	.wb_dat_i	(wb8_m2s_gpio0_dat),
+	.wb_we_i	(wb8_m2s_gpio0_we),
+	.wb_cyc_i	(wb8_m2s_gpio0_cyc),
+	.wb_stb_i	(wb8_m2s_gpio0_stb),
+	.wb_cti_i	(wb8_m2s_gpio0_cti),
+	.wb_bte_i	(wb8_m2s_gpio0_bte),
+	.wb_dat_o	(wb8_s2m_gpio0_dat),
+	.wb_ack_o	(wb8_s2m_gpio0_ack),
+	.wb_err_o	(wb8_s2m_gpio0_err),
+	.wb_rty_o	(wb8_s2m_gpio0_rty),
+
+	.wb_clk		(wb_clk),
+	.wb_rst		(wb_rst)
+);
+
+// 32-bit to 8-bit wishbone bus resize
+wb_data_resize wb_data_resize_gpio0 (
+	// Wishbone Master interface
+	.wbm_adr_i	(wb_m2s_gpio0_adr),
+	.wbm_dat_i	(wb_m2s_gpio0_dat),
+	.wbm_sel_i	(wb_m2s_gpio0_sel),
+	.wbm_we_i	(wb_m2s_gpio0_we ),
+	.wbm_cyc_i	(wb_m2s_gpio0_cyc),
+	.wbm_stb_i	(wb_m2s_gpio0_stb),
+	.wbm_cti_i	(wb_m2s_gpio0_cti),
+	.wbm_bte_i	(wb_m2s_gpio0_bte),
+	.wbm_dat_o	(wb_s2m_gpio0_dat),
+	.wbm_ack_o	(wb_s2m_gpio0_ack),
+	.wbm_err_o	(wb_s2m_gpio0_err),
+	.wbm_rty_o	(wb_s2m_gpio0_rty),
+
+	// Wishbone Slave interface
+	.wbs_adr_o	(wb8_m2s_gpio0_adr),
+	.wbs_dat_o	(wb8_m2s_gpio0_dat),
+	.wbs_we_o	(wb8_m2s_gpio0_we ),
+	.wbs_cyc_o	(wb8_m2s_gpio0_cyc),
+	.wbs_stb_o	(wb8_m2s_gpio0_stb),
+	.wbs_cti_o	(wb8_m2s_gpio0_cti),
+	.wbs_bte_o	(wb8_m2s_gpio0_bte),
+	.wbs_dat_i	(wb8_s2m_gpio0_dat),
+	.wbs_ack_i	(wb8_s2m_gpio0_ack),
+	.wbs_err_i	(wb8_s2m_gpio0_err),
+	.wbs_rty_i	(wb8_s2m_gpio0_rty)
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// Interrupt assignment
+//
+////////////////////////////////////////////////////////////////////////
+
+assign or1k_irq[0] = 0; // Non-maskable inside OR1K
+assign or1k_irq[1] = 0; // Non-maskable inside OR1K
+assign or1k_irq[2] = uart0_irq;
+assign or1k_irq[3] = 0;
+assign or1k_irq[4] = 0;
+assign or1k_irq[5] = 0;
+assign or1k_irq[6] = 0;
+assign or1k_irq[7] = 0;
+assign or1k_irq[8] = 0;
+assign or1k_irq[9] = 0;
+assign or1k_irq[10] = 0;
+assign or1k_irq[11] = 0;
+assign or1k_irq[12] = 0;
+assign or1k_irq[13] = 0;
+assign or1k_irq[14] = 0;
+assign or1k_irq[15] = 0;
+assign or1k_irq[16] = 0;
+assign or1k_irq[17] = 0;
+assign or1k_irq[18] = 0;
+assign or1k_irq[19] = 0;
+assign or1k_irq[20] = 0;
+assign or1k_irq[21] = 0;
+assign or1k_irq[22] = 0;
+assign or1k_irq[23] = 0;
+assign or1k_irq[24] = 0;
+assign or1k_irq[25] = 0;
+assign or1k_irq[26] = 0;
+assign or1k_irq[27] = 0;
+assign or1k_irq[28] = 0;
+assign or1k_irq[29] = 0;
+assign or1k_irq[30] = 0;
+assign or1k_irq[31] = 0;
+
+endmodule // orpsoc_top
+
+
diff --git a/systems/de2/rtl/verilog/rom.v b/systems/de2/rtl/verilog/rom.v
new file mode 100755
index 00000000..b653029c
--- /dev/null
+++ b/systems/de2/rtl/verilog/rom.v
@@ -0,0 +1,127 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  ROM                                                         ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Michael Unneback (unneback@opencores.org)             ////
+////      - Julius Baxter    (julius@opencores.org)               ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2009 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+module rom #(
+	parameter ADDR_WIDTH = 5,
+	parameter B3_BURST   = 0
+)
+(
+	input					wb_clk,
+	input					wb_rst,
+	input	[(ADDR_WIDTH + 2) - 1:2]	wb_adr_i,
+	input					wb_stb_i,
+	input					wb_cyc_i,
+	input		[2:0]			wb_cti_i,
+	input		[1:0]			wb_bte_i,
+	output reg	[31:0]			wb_dat_o,
+	output reg				wb_ack_o
+);
+
+reg [ADDR_WIDTH-1:0]	adr;
+
+always @ (posedge wb_clk or posedge wb_rst)
+if (wb_rst)
+	wb_dat_o <= 32'h15000000;
+else
+	case (adr)
+	// Zero r0 and jump to 0x00000100
+	0 : wb_dat_o <= 32'h18000000;
+	1 : wb_dat_o <= 32'hA8200000;
+	2 : wb_dat_o <= 32'hA8C00100;
+	3 : wb_dat_o <= 32'h44003000;
+	4 : wb_dat_o <= 32'h15000000;
+	default: wb_dat_o <= 32'h00000000;
+	endcase // case (wb_adr_i)
+
+generate
+if (B3_BURST) begin : gen_B3_BURST
+	reg	wb_stb_i_r;
+	reg	new_access_r;
+	reg	burst_r;
+
+	wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
+	wire new_access = (wb_stb_i & !wb_stb_i_r);
+	wire new_burst = (burst & !burst_r);
+
+	always @(posedge wb_clk) begin
+	new_access_r <= new_access;
+	burst_r <= burst;
+	wb_stb_i_r <= wb_stb_i;
+	end
+
+	always @(posedge wb_clk)
+	if (wb_rst)
+		adr <= 0;
+	else if (new_access)
+		// New access, register address, ack a cycle later
+		adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2];
+		else if (burst) begin
+			if (wb_cti_i == 3'b010)
+				case (wb_bte_i)
+				2'b00: adr <= adr + 1;
+				2'b01: adr[1:0] <= adr[1:0] + 1;
+				2'b10: adr[2:0] <= adr[2:0] + 1;
+				2'b11: adr[3:0] <= adr[3:0] + 1;
+				endcase // case (wb_bte_i)
+			else
+				adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2];
+		end // if (burst)
+
+
+	always @(posedge wb_clk)
+	if (wb_rst)
+		wb_ack_o <= 0;
+		else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
+			wb_ack_o <= 0;
+		else if (wb_stb_i & ((!burst & !new_access & new_access_r) |
+			(burst & burst_r)))
+			wb_ack_o <= 1;
+		else
+			wb_ack_o <= 0;
+
+end else begin
+	always @(wb_adr_i)
+	adr <= wb_adr_i;
+
+	always @ (posedge wb_clk or posedge wb_rst)
+	if (wb_rst)
+		wb_ack_o <= 1'b0;
+	else
+		wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
+end
+
+endgenerate
+
+endmodule
diff --git a/systems/de2/rtl/verilog/wb_intercon.v b/systems/de2/rtl/verilog/wb_intercon.v
new file mode 100755
index 00000000..aa04cde6
--- /dev/null
+++ b/systems/de2/rtl/verilog/wb_intercon.v
@@ -0,0 +1,360 @@
+module wb_intercon
+   (input         wb_clk_i,
+    input         wb_rst_i,
+    input  [31:0] wb_or1k_i_adr_i,
+    input  [31:0] wb_or1k_i_dat_i,
+    input   [3:0] wb_or1k_i_sel_i,
+    input         wb_or1k_i_we_i,
+    input         wb_or1k_i_cyc_i,
+    input         wb_or1k_i_stb_i,
+    input   [2:0] wb_or1k_i_cti_i,
+    input   [1:0] wb_or1k_i_bte_i,
+    output [31:0] wb_or1k_i_dat_o,
+    output        wb_or1k_i_ack_o,
+    output        wb_or1k_i_err_o,
+    output        wb_or1k_i_rty_o,
+    input  [31:0] wb_or1k_d_adr_i,
+    input  [31:0] wb_or1k_d_dat_i,
+    input   [3:0] wb_or1k_d_sel_i,
+    input         wb_or1k_d_we_i,
+    input         wb_or1k_d_cyc_i,
+    input         wb_or1k_d_stb_i,
+    input   [2:0] wb_or1k_d_cti_i,
+    input   [1:0] wb_or1k_d_bte_i,
+    output [31:0] wb_or1k_d_dat_o,
+    output        wb_or1k_d_ack_o,
+    output        wb_or1k_d_err_o,
+    output        wb_or1k_d_rty_o,
+    input  [31:0] wb_dbg_adr_i,
+    input  [31:0] wb_dbg_dat_i,
+    input   [3:0] wb_dbg_sel_i,
+    input         wb_dbg_we_i,
+    input         wb_dbg_cyc_i,
+    input         wb_dbg_stb_i,
+    input   [2:0] wb_dbg_cti_i,
+    input   [1:0] wb_dbg_bte_i,
+    output [31:0] wb_dbg_dat_o,
+    output        wb_dbg_ack_o,
+    output        wb_dbg_err_o,
+    output        wb_dbg_rty_o,
+    output [31:0] wb_uart0_adr_o,
+    output [31:0] wb_uart0_dat_o,
+    output  [3:0] wb_uart0_sel_o,
+    output        wb_uart0_we_o,
+    output        wb_uart0_cyc_o,
+    output        wb_uart0_stb_o,
+    output  [2:0] wb_uart0_cti_o,
+    output  [1:0] wb_uart0_bte_o,
+    input  [31:0] wb_uart0_dat_i,
+    input         wb_uart0_ack_i,
+    input         wb_uart0_err_i,
+    input         wb_uart0_rty_i,
+    output [31:0] wb_sdram_dbus_adr_o,
+    output [31:0] wb_sdram_dbus_dat_o,
+    output  [3:0] wb_sdram_dbus_sel_o,
+    output        wb_sdram_dbus_we_o,
+    output        wb_sdram_dbus_cyc_o,
+    output        wb_sdram_dbus_stb_o,
+    output  [2:0] wb_sdram_dbus_cti_o,
+    output  [1:0] wb_sdram_dbus_bte_o,
+    input  [31:0] wb_sdram_dbus_dat_i,
+    input         wb_sdram_dbus_ack_i,
+    input         wb_sdram_dbus_err_i,
+    input         wb_sdram_dbus_rty_i,
+    output [31:0] wb_gpio0_adr_o,
+    output [31:0] wb_gpio0_dat_o,
+    output  [3:0] wb_gpio0_sel_o,
+    output        wb_gpio0_we_o,
+    output        wb_gpio0_cyc_o,
+    output        wb_gpio0_stb_o,
+    output  [2:0] wb_gpio0_cti_o,
+    output  [1:0] wb_gpio0_bte_o,
+    input  [31:0] wb_gpio0_dat_i,
+    input         wb_gpio0_ack_i,
+    input         wb_gpio0_err_i,
+    input         wb_gpio0_rty_i,
+    output [31:0] wb_rom0_adr_o,
+    output [31:0] wb_rom0_dat_o,
+    output  [3:0] wb_rom0_sel_o,
+    output        wb_rom0_we_o,
+    output        wb_rom0_cyc_o,
+    output        wb_rom0_stb_o,
+    output  [2:0] wb_rom0_cti_o,
+    output  [1:0] wb_rom0_bte_o,
+    input  [31:0] wb_rom0_dat_i,
+    input         wb_rom0_ack_i,
+    input         wb_rom0_err_i,
+    input         wb_rom0_rty_i,
+    output [31:0] wb_sdram_ibus_adr_o,
+    output [31:0] wb_sdram_ibus_dat_o,
+    output  [3:0] wb_sdram_ibus_sel_o,
+    output        wb_sdram_ibus_we_o,
+    output        wb_sdram_ibus_cyc_o,
+    output        wb_sdram_ibus_stb_o,
+    output  [2:0] wb_sdram_ibus_cti_o,
+    output  [1:0] wb_sdram_ibus_bte_o,
+    input  [31:0] wb_sdram_ibus_dat_i,
+    input         wb_sdram_ibus_ack_i,
+    input         wb_sdram_ibus_err_i,
+    input         wb_sdram_ibus_rty_i);
+
+wire [31:0] wb_m2s_or1k_d_sdram_dbus_adr;
+wire [31:0] wb_m2s_or1k_d_sdram_dbus_dat;
+wire  [3:0] wb_m2s_or1k_d_sdram_dbus_sel;
+wire        wb_m2s_or1k_d_sdram_dbus_we;
+wire        wb_m2s_or1k_d_sdram_dbus_cyc;
+wire        wb_m2s_or1k_d_sdram_dbus_stb;
+wire  [2:0] wb_m2s_or1k_d_sdram_dbus_cti;
+wire  [1:0] wb_m2s_or1k_d_sdram_dbus_bte;
+wire [31:0] wb_s2m_or1k_d_sdram_dbus_dat;
+wire        wb_s2m_or1k_d_sdram_dbus_ack;
+wire        wb_s2m_or1k_d_sdram_dbus_err;
+wire        wb_s2m_or1k_d_sdram_dbus_rty;
+wire [31:0] wb_m2s_or1k_d_uart0_adr;
+wire [31:0] wb_m2s_or1k_d_uart0_dat;
+wire  [3:0] wb_m2s_or1k_d_uart0_sel;
+wire        wb_m2s_or1k_d_uart0_we;
+wire        wb_m2s_or1k_d_uart0_cyc;
+wire        wb_m2s_or1k_d_uart0_stb;
+wire  [2:0] wb_m2s_or1k_d_uart0_cti;
+wire  [1:0] wb_m2s_or1k_d_uart0_bte;
+wire [31:0] wb_s2m_or1k_d_uart0_dat;
+wire        wb_s2m_or1k_d_uart0_ack;
+wire        wb_s2m_or1k_d_uart0_err;
+wire        wb_s2m_or1k_d_uart0_rty;
+wire [31:0] wb_m2s_or1k_d_gpio0_adr;
+wire [31:0] wb_m2s_or1k_d_gpio0_dat;
+wire  [3:0] wb_m2s_or1k_d_gpio0_sel;
+wire        wb_m2s_or1k_d_gpio0_we;
+wire        wb_m2s_or1k_d_gpio0_cyc;
+wire        wb_m2s_or1k_d_gpio0_stb;
+wire  [2:0] wb_m2s_or1k_d_gpio0_cti;
+wire  [1:0] wb_m2s_or1k_d_gpio0_bte;
+wire [31:0] wb_s2m_or1k_d_gpio0_dat;
+wire        wb_s2m_or1k_d_gpio0_ack;
+wire        wb_s2m_or1k_d_gpio0_err;
+wire        wb_s2m_or1k_d_gpio0_rty;
+wire [31:0] wb_m2s_dbg_sdram_dbus_adr;
+wire [31:0] wb_m2s_dbg_sdram_dbus_dat;
+wire  [3:0] wb_m2s_dbg_sdram_dbus_sel;
+wire        wb_m2s_dbg_sdram_dbus_we;
+wire        wb_m2s_dbg_sdram_dbus_cyc;
+wire        wb_m2s_dbg_sdram_dbus_stb;
+wire  [2:0] wb_m2s_dbg_sdram_dbus_cti;
+wire  [1:0] wb_m2s_dbg_sdram_dbus_bte;
+wire [31:0] wb_s2m_dbg_sdram_dbus_dat;
+wire        wb_s2m_dbg_sdram_dbus_ack;
+wire        wb_s2m_dbg_sdram_dbus_err;
+wire        wb_s2m_dbg_sdram_dbus_rty;
+wire [31:0] wb_m2s_dbg_uart0_adr;
+wire [31:0] wb_m2s_dbg_uart0_dat;
+wire  [3:0] wb_m2s_dbg_uart0_sel;
+wire        wb_m2s_dbg_uart0_we;
+wire        wb_m2s_dbg_uart0_cyc;
+wire        wb_m2s_dbg_uart0_stb;
+wire  [2:0] wb_m2s_dbg_uart0_cti;
+wire  [1:0] wb_m2s_dbg_uart0_bte;
+wire [31:0] wb_s2m_dbg_uart0_dat;
+wire        wb_s2m_dbg_uart0_ack;
+wire        wb_s2m_dbg_uart0_err;
+wire        wb_s2m_dbg_uart0_rty;
+wire [31:0] wb_m2s_dbg_gpio0_adr;
+wire [31:0] wb_m2s_dbg_gpio0_dat;
+wire  [3:0] wb_m2s_dbg_gpio0_sel;
+wire        wb_m2s_dbg_gpio0_we;
+wire        wb_m2s_dbg_gpio0_cyc;
+wire        wb_m2s_dbg_gpio0_stb;
+wire  [2:0] wb_m2s_dbg_gpio0_cti;
+wire  [1:0] wb_m2s_dbg_gpio0_bte;
+wire [31:0] wb_s2m_dbg_gpio0_dat;
+wire        wb_s2m_dbg_gpio0_ack;
+wire        wb_s2m_dbg_gpio0_err;
+wire        wb_s2m_dbg_gpio0_rty;
+
+wb_mux
+  #(.num_slaves (2),
+    .MATCH_ADDR ({32'h00000000, 32'hf0000100}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffc0}))
+ wb_mux_or1k_i
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_or1k_i_adr_i),
+    .wbm_dat_i (wb_or1k_i_dat_i),
+    .wbm_sel_i (wb_or1k_i_sel_i),
+    .wbm_we_i  (wb_or1k_i_we_i),
+    .wbm_cyc_i (wb_or1k_i_cyc_i),
+    .wbm_stb_i (wb_or1k_i_stb_i),
+    .wbm_cti_i (wb_or1k_i_cti_i),
+    .wbm_bte_i (wb_or1k_i_bte_i),
+    .wbm_dat_o (wb_or1k_i_dat_o),
+    .wbm_ack_o (wb_or1k_i_ack_o),
+    .wbm_err_o (wb_or1k_i_err_o),
+    .wbm_rty_o (wb_or1k_i_rty_o),
+    .wbs_adr_o ({wb_sdram_ibus_adr_o, wb_rom0_adr_o}),
+    .wbs_dat_o ({wb_sdram_ibus_dat_o, wb_rom0_dat_o}),
+    .wbs_sel_o ({wb_sdram_ibus_sel_o, wb_rom0_sel_o}),
+    .wbs_we_o  ({wb_sdram_ibus_we_o, wb_rom0_we_o}),
+    .wbs_cyc_o ({wb_sdram_ibus_cyc_o, wb_rom0_cyc_o}),
+    .wbs_stb_o ({wb_sdram_ibus_stb_o, wb_rom0_stb_o}),
+    .wbs_cti_o ({wb_sdram_ibus_cti_o, wb_rom0_cti_o}),
+    .wbs_bte_o ({wb_sdram_ibus_bte_o, wb_rom0_bte_o}),
+    .wbs_dat_i ({wb_sdram_ibus_dat_i, wb_rom0_dat_i}),
+    .wbs_ack_i ({wb_sdram_ibus_ack_i, wb_rom0_ack_i}),
+    .wbs_err_i ({wb_sdram_ibus_err_i, wb_rom0_err_i}),
+    .wbs_rty_i ({wb_sdram_ibus_rty_i, wb_rom0_rty_i}));
+
+wb_mux
+  #(.num_slaves (3),
+    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
+ wb_mux_or1k_d
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_or1k_d_adr_i),
+    .wbm_dat_i (wb_or1k_d_dat_i),
+    .wbm_sel_i (wb_or1k_d_sel_i),
+    .wbm_we_i  (wb_or1k_d_we_i),
+    .wbm_cyc_i (wb_or1k_d_cyc_i),
+    .wbm_stb_i (wb_or1k_d_stb_i),
+    .wbm_cti_i (wb_or1k_d_cti_i),
+    .wbm_bte_i (wb_or1k_d_bte_i),
+    .wbm_dat_o (wb_or1k_d_dat_o),
+    .wbm_ack_o (wb_or1k_d_ack_o),
+    .wbm_err_o (wb_or1k_d_err_o),
+    .wbm_rty_o (wb_or1k_d_rty_o),
+    .wbs_adr_o ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_or1k_d_uart0_adr, wb_m2s_or1k_d_gpio0_adr}),
+    .wbs_dat_o ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_or1k_d_uart0_dat, wb_m2s_or1k_d_gpio0_dat}),
+    .wbs_sel_o ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_or1k_d_uart0_sel, wb_m2s_or1k_d_gpio0_sel}),
+    .wbs_we_o  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_or1k_d_uart0_we, wb_m2s_or1k_d_gpio0_we}),
+    .wbs_cyc_o ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_or1k_d_uart0_cyc, wb_m2s_or1k_d_gpio0_cyc}),
+    .wbs_stb_o ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_or1k_d_uart0_stb, wb_m2s_or1k_d_gpio0_stb}),
+    .wbs_cti_o ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_or1k_d_uart0_cti, wb_m2s_or1k_d_gpio0_cti}),
+    .wbs_bte_o ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_or1k_d_uart0_bte, wb_m2s_or1k_d_gpio0_bte}),
+    .wbs_dat_i ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_or1k_d_uart0_dat, wb_s2m_or1k_d_gpio0_dat}),
+    .wbs_ack_i ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_or1k_d_uart0_ack, wb_s2m_or1k_d_gpio0_ack}),
+    .wbs_err_i ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_or1k_d_uart0_err, wb_s2m_or1k_d_gpio0_err}),
+    .wbs_rty_i ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_or1k_d_uart0_rty, wb_s2m_or1k_d_gpio0_rty}));
+
+wb_mux
+  #(.num_slaves (3),
+    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
+ wb_mux_dbg
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_dbg_adr_i),
+    .wbm_dat_i (wb_dbg_dat_i),
+    .wbm_sel_i (wb_dbg_sel_i),
+    .wbm_we_i  (wb_dbg_we_i),
+    .wbm_cyc_i (wb_dbg_cyc_i),
+    .wbm_stb_i (wb_dbg_stb_i),
+    .wbm_cti_i (wb_dbg_cti_i),
+    .wbm_bte_i (wb_dbg_bte_i),
+    .wbm_dat_o (wb_dbg_dat_o),
+    .wbm_ack_o (wb_dbg_ack_o),
+    .wbm_err_o (wb_dbg_err_o),
+    .wbm_rty_o (wb_dbg_rty_o),
+    .wbs_adr_o ({wb_m2s_dbg_sdram_dbus_adr, wb_m2s_dbg_uart0_adr, wb_m2s_dbg_gpio0_adr}),
+    .wbs_dat_o ({wb_m2s_dbg_sdram_dbus_dat, wb_m2s_dbg_uart0_dat, wb_m2s_dbg_gpio0_dat}),
+    .wbs_sel_o ({wb_m2s_dbg_sdram_dbus_sel, wb_m2s_dbg_uart0_sel, wb_m2s_dbg_gpio0_sel}),
+    .wbs_we_o  ({wb_m2s_dbg_sdram_dbus_we, wb_m2s_dbg_uart0_we, wb_m2s_dbg_gpio0_we}),
+    .wbs_cyc_o ({wb_m2s_dbg_sdram_dbus_cyc, wb_m2s_dbg_uart0_cyc, wb_m2s_dbg_gpio0_cyc}),
+    .wbs_stb_o ({wb_m2s_dbg_sdram_dbus_stb, wb_m2s_dbg_uart0_stb, wb_m2s_dbg_gpio0_stb}),
+    .wbs_cti_o ({wb_m2s_dbg_sdram_dbus_cti, wb_m2s_dbg_uart0_cti, wb_m2s_dbg_gpio0_cti}),
+    .wbs_bte_o ({wb_m2s_dbg_sdram_dbus_bte, wb_m2s_dbg_uart0_bte, wb_m2s_dbg_gpio0_bte}),
+    .wbs_dat_i ({wb_s2m_dbg_sdram_dbus_dat, wb_s2m_dbg_uart0_dat, wb_s2m_dbg_gpio0_dat}),
+    .wbs_ack_i ({wb_s2m_dbg_sdram_dbus_ack, wb_s2m_dbg_uart0_ack, wb_s2m_dbg_gpio0_ack}),
+    .wbs_err_i ({wb_s2m_dbg_sdram_dbus_err, wb_s2m_dbg_uart0_err, wb_s2m_dbg_gpio0_err}),
+    .wbs_rty_i ({wb_s2m_dbg_sdram_dbus_rty, wb_s2m_dbg_uart0_rty, wb_s2m_dbg_gpio0_rty}));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_uart0
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_uart0_adr, wb_m2s_dbg_uart0_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_uart0_dat, wb_m2s_dbg_uart0_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_uart0_sel, wb_m2s_dbg_uart0_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_uart0_we, wb_m2s_dbg_uart0_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_uart0_cyc, wb_m2s_dbg_uart0_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_uart0_stb, wb_m2s_dbg_uart0_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_uart0_cti, wb_m2s_dbg_uart0_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_uart0_bte, wb_m2s_dbg_uart0_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_uart0_dat, wb_s2m_dbg_uart0_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}),
+    .wbs_adr_o (wb_uart0_adr_o),
+    .wbs_dat_o (wb_uart0_dat_o),
+    .wbs_sel_o (wb_uart0_sel_o),
+    .wbs_we_o  (wb_uart0_we_o),
+    .wbs_cyc_o (wb_uart0_cyc_o),
+    .wbs_stb_o (wb_uart0_stb_o),
+    .wbs_cti_o (wb_uart0_cti_o),
+    .wbs_bte_o (wb_uart0_bte_o),
+    .wbs_dat_i (wb_uart0_dat_i),
+    .wbs_ack_i (wb_uart0_ack_i),
+    .wbs_err_i (wb_uart0_err_i),
+    .wbs_rty_i (wb_uart0_rty_i));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_sdram_dbus
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_dbg_sdram_dbus_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_dbg_sdram_dbus_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_dbg_sdram_dbus_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_dbg_sdram_dbus_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_dbg_sdram_dbus_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_dbg_sdram_dbus_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_dbg_sdram_dbus_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_dbg_sdram_dbus_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_dbg_sdram_dbus_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_dbg_sdram_dbus_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_dbg_sdram_dbus_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_dbg_sdram_dbus_rty}),
+    .wbs_adr_o (wb_sdram_dbus_adr_o),
+    .wbs_dat_o (wb_sdram_dbus_dat_o),
+    .wbs_sel_o (wb_sdram_dbus_sel_o),
+    .wbs_we_o  (wb_sdram_dbus_we_o),
+    .wbs_cyc_o (wb_sdram_dbus_cyc_o),
+    .wbs_stb_o (wb_sdram_dbus_stb_o),
+    .wbs_cti_o (wb_sdram_dbus_cti_o),
+    .wbs_bte_o (wb_sdram_dbus_bte_o),
+    .wbs_dat_i (wb_sdram_dbus_dat_i),
+    .wbs_ack_i (wb_sdram_dbus_ack_i),
+    .wbs_err_i (wb_sdram_dbus_err_i),
+    .wbs_rty_i (wb_sdram_dbus_rty_i));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_gpio0
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}),
+    .wbs_adr_o (wb_gpio0_adr_o),
+    .wbs_dat_o (wb_gpio0_dat_o),
+    .wbs_sel_o (wb_gpio0_sel_o),
+    .wbs_we_o  (wb_gpio0_we_o),
+    .wbs_cyc_o (wb_gpio0_cyc_o),
+    .wbs_stb_o (wb_gpio0_stb_o),
+    .wbs_cti_o (wb_gpio0_cti_o),
+    .wbs_bte_o (wb_gpio0_bte_o),
+    .wbs_dat_i (wb_gpio0_dat_i),
+    .wbs_ack_i (wb_gpio0_ack_i),
+    .wbs_err_i (wb_gpio0_err_i),
+    .wbs_rty_i (wb_gpio0_rty_i));
+
+endmodule
diff --git a/systems/de2/rtl/verilog/wb_intercon.vh b/systems/de2/rtl/verilog/wb_intercon.vh
new file mode 100755
index 00000000..e81420ee
--- /dev/null
+++ b/systems/de2/rtl/verilog/wb_intercon.vh
@@ -0,0 +1,197 @@
+wire [31:0] wb_m2s_or1k_i_adr;
+wire [31:0] wb_m2s_or1k_i_dat;
+wire  [3:0] wb_m2s_or1k_i_sel;
+wire        wb_m2s_or1k_i_we;
+wire        wb_m2s_or1k_i_cyc;
+wire        wb_m2s_or1k_i_stb;
+wire  [2:0] wb_m2s_or1k_i_cti;
+wire  [1:0] wb_m2s_or1k_i_bte;
+wire [31:0] wb_s2m_or1k_i_dat;
+wire        wb_s2m_or1k_i_ack;
+wire        wb_s2m_or1k_i_err;
+wire        wb_s2m_or1k_i_rty;
+wire [31:0] wb_m2s_or1k_d_adr;
+wire [31:0] wb_m2s_or1k_d_dat;
+wire  [3:0] wb_m2s_or1k_d_sel;
+wire        wb_m2s_or1k_d_we;
+wire        wb_m2s_or1k_d_cyc;
+wire        wb_m2s_or1k_d_stb;
+wire  [2:0] wb_m2s_or1k_d_cti;
+wire  [1:0] wb_m2s_or1k_d_bte;
+wire [31:0] wb_s2m_or1k_d_dat;
+wire        wb_s2m_or1k_d_ack;
+wire        wb_s2m_or1k_d_err;
+wire        wb_s2m_or1k_d_rty;
+wire [31:0] wb_m2s_dbg_adr;
+wire [31:0] wb_m2s_dbg_dat;
+wire  [3:0] wb_m2s_dbg_sel;
+wire        wb_m2s_dbg_we;
+wire        wb_m2s_dbg_cyc;
+wire        wb_m2s_dbg_stb;
+wire  [2:0] wb_m2s_dbg_cti;
+wire  [1:0] wb_m2s_dbg_bte;
+wire [31:0] wb_s2m_dbg_dat;
+wire        wb_s2m_dbg_ack;
+wire        wb_s2m_dbg_err;
+wire        wb_s2m_dbg_rty;
+wire [31:0] wb_m2s_uart0_adr;
+wire [31:0] wb_m2s_uart0_dat;
+wire  [3:0] wb_m2s_uart0_sel;
+wire        wb_m2s_uart0_we;
+wire        wb_m2s_uart0_cyc;
+wire        wb_m2s_uart0_stb;
+wire  [2:0] wb_m2s_uart0_cti;
+wire  [1:0] wb_m2s_uart0_bte;
+wire [31:0] wb_s2m_uart0_dat;
+wire        wb_s2m_uart0_ack;
+wire        wb_s2m_uart0_err;
+wire        wb_s2m_uart0_rty;
+wire [31:0] wb_m2s_sdram_dbus_adr;
+wire [31:0] wb_m2s_sdram_dbus_dat;
+wire  [3:0] wb_m2s_sdram_dbus_sel;
+wire        wb_m2s_sdram_dbus_we;
+wire        wb_m2s_sdram_dbus_cyc;
+wire        wb_m2s_sdram_dbus_stb;
+wire  [2:0] wb_m2s_sdram_dbus_cti;
+wire  [1:0] wb_m2s_sdram_dbus_bte;
+wire [31:0] wb_s2m_sdram_dbus_dat;
+wire        wb_s2m_sdram_dbus_ack;
+wire        wb_s2m_sdram_dbus_err;
+wire        wb_s2m_sdram_dbus_rty;
+wire [31:0] wb_m2s_gpio0_adr;
+wire [31:0] wb_m2s_gpio0_dat;
+wire  [3:0] wb_m2s_gpio0_sel;
+wire        wb_m2s_gpio0_we;
+wire        wb_m2s_gpio0_cyc;
+wire        wb_m2s_gpio0_stb;
+wire  [2:0] wb_m2s_gpio0_cti;
+wire  [1:0] wb_m2s_gpio0_bte;
+wire [31:0] wb_s2m_gpio0_dat;
+wire        wb_s2m_gpio0_ack;
+wire        wb_s2m_gpio0_err;
+wire        wb_s2m_gpio0_rty;
+wire [31:0] wb_m2s_rom0_adr;
+wire [31:0] wb_m2s_rom0_dat;
+wire  [3:0] wb_m2s_rom0_sel;
+wire        wb_m2s_rom0_we;
+wire        wb_m2s_rom0_cyc;
+wire        wb_m2s_rom0_stb;
+wire  [2:0] wb_m2s_rom0_cti;
+wire  [1:0] wb_m2s_rom0_bte;
+wire [31:0] wb_s2m_rom0_dat;
+wire        wb_s2m_rom0_ack;
+wire        wb_s2m_rom0_err;
+wire        wb_s2m_rom0_rty;
+wire [31:0] wb_m2s_sdram_ibus_adr;
+wire [31:0] wb_m2s_sdram_ibus_dat;
+wire  [3:0] wb_m2s_sdram_ibus_sel;
+wire        wb_m2s_sdram_ibus_we;
+wire        wb_m2s_sdram_ibus_cyc;
+wire        wb_m2s_sdram_ibus_stb;
+wire  [2:0] wb_m2s_sdram_ibus_cti;
+wire  [1:0] wb_m2s_sdram_ibus_bte;
+wire [31:0] wb_s2m_sdram_ibus_dat;
+wire        wb_s2m_sdram_ibus_ack;
+wire        wb_s2m_sdram_ibus_err;
+wire        wb_s2m_sdram_ibus_rty;
+
+wb_intercon wb_intercon0
+   (.wb_clk_i            (wb_clk),
+    .wb_rst_i            (wb_rst),
+    .wb_or1k_i_adr_i     (wb_m2s_or1k_i_adr),
+    .wb_or1k_i_dat_i     (wb_m2s_or1k_i_dat),
+    .wb_or1k_i_sel_i     (wb_m2s_or1k_i_sel),
+    .wb_or1k_i_we_i      (wb_m2s_or1k_i_we),
+    .wb_or1k_i_cyc_i     (wb_m2s_or1k_i_cyc),
+    .wb_or1k_i_stb_i     (wb_m2s_or1k_i_stb),
+    .wb_or1k_i_cti_i     (wb_m2s_or1k_i_cti),
+    .wb_or1k_i_bte_i     (wb_m2s_or1k_i_bte),
+    .wb_or1k_i_dat_o     (wb_s2m_or1k_i_dat),
+    .wb_or1k_i_ack_o     (wb_s2m_or1k_i_ack),
+    .wb_or1k_i_err_o     (wb_s2m_or1k_i_err),
+    .wb_or1k_i_rty_o     (wb_s2m_or1k_i_rty),
+    .wb_or1k_d_adr_i     (wb_m2s_or1k_d_adr),
+    .wb_or1k_d_dat_i     (wb_m2s_or1k_d_dat),
+    .wb_or1k_d_sel_i     (wb_m2s_or1k_d_sel),
+    .wb_or1k_d_we_i      (wb_m2s_or1k_d_we),
+    .wb_or1k_d_cyc_i     (wb_m2s_or1k_d_cyc),
+    .wb_or1k_d_stb_i     (wb_m2s_or1k_d_stb),
+    .wb_or1k_d_cti_i     (wb_m2s_or1k_d_cti),
+    .wb_or1k_d_bte_i     (wb_m2s_or1k_d_bte),
+    .wb_or1k_d_dat_o     (wb_s2m_or1k_d_dat),
+    .wb_or1k_d_ack_o     (wb_s2m_or1k_d_ack),
+    .wb_or1k_d_err_o     (wb_s2m_or1k_d_err),
+    .wb_or1k_d_rty_o     (wb_s2m_or1k_d_rty),
+    .wb_dbg_adr_i        (wb_m2s_dbg_adr),
+    .wb_dbg_dat_i        (wb_m2s_dbg_dat),
+    .wb_dbg_sel_i        (wb_m2s_dbg_sel),
+    .wb_dbg_we_i         (wb_m2s_dbg_we),
+    .wb_dbg_cyc_i        (wb_m2s_dbg_cyc),
+    .wb_dbg_stb_i        (wb_m2s_dbg_stb),
+    .wb_dbg_cti_i        (wb_m2s_dbg_cti),
+    .wb_dbg_bte_i        (wb_m2s_dbg_bte),
+    .wb_dbg_dat_o        (wb_s2m_dbg_dat),
+    .wb_dbg_ack_o        (wb_s2m_dbg_ack),
+    .wb_dbg_err_o        (wb_s2m_dbg_err),
+    .wb_dbg_rty_o        (wb_s2m_dbg_rty),
+    .wb_uart0_adr_o      (wb_m2s_uart0_adr),
+    .wb_uart0_dat_o      (wb_m2s_uart0_dat),
+    .wb_uart0_sel_o      (wb_m2s_uart0_sel),
+    .wb_uart0_we_o       (wb_m2s_uart0_we),
+    .wb_uart0_cyc_o      (wb_m2s_uart0_cyc),
+    .wb_uart0_stb_o      (wb_m2s_uart0_stb),
+    .wb_uart0_cti_o      (wb_m2s_uart0_cti),
+    .wb_uart0_bte_o      (wb_m2s_uart0_bte),
+    .wb_uart0_dat_i      (wb_s2m_uart0_dat),
+    .wb_uart0_ack_i      (wb_s2m_uart0_ack),
+    .wb_uart0_err_i      (wb_s2m_uart0_err),
+    .wb_uart0_rty_i      (wb_s2m_uart0_rty),
+    .wb_sdram_dbus_adr_o (wb_m2s_sdram_dbus_adr),
+    .wb_sdram_dbus_dat_o (wb_m2s_sdram_dbus_dat),
+    .wb_sdram_dbus_sel_o (wb_m2s_sdram_dbus_sel),
+    .wb_sdram_dbus_we_o  (wb_m2s_sdram_dbus_we),
+    .wb_sdram_dbus_cyc_o (wb_m2s_sdram_dbus_cyc),
+    .wb_sdram_dbus_stb_o (wb_m2s_sdram_dbus_stb),
+    .wb_sdram_dbus_cti_o (wb_m2s_sdram_dbus_cti),
+    .wb_sdram_dbus_bte_o (wb_m2s_sdram_dbus_bte),
+    .wb_sdram_dbus_dat_i (wb_s2m_sdram_dbus_dat),
+    .wb_sdram_dbus_ack_i (wb_s2m_sdram_dbus_ack),
+    .wb_sdram_dbus_err_i (wb_s2m_sdram_dbus_err),
+    .wb_sdram_dbus_rty_i (wb_s2m_sdram_dbus_rty),
+    .wb_gpio0_adr_o      (wb_m2s_gpio0_adr),
+    .wb_gpio0_dat_o      (wb_m2s_gpio0_dat),
+    .wb_gpio0_sel_o      (wb_m2s_gpio0_sel),
+    .wb_gpio0_we_o       (wb_m2s_gpio0_we),
+    .wb_gpio0_cyc_o      (wb_m2s_gpio0_cyc),
+    .wb_gpio0_stb_o      (wb_m2s_gpio0_stb),
+    .wb_gpio0_cti_o      (wb_m2s_gpio0_cti),
+    .wb_gpio0_bte_o      (wb_m2s_gpio0_bte),
+    .wb_gpio0_dat_i      (wb_s2m_gpio0_dat),
+    .wb_gpio0_ack_i      (wb_s2m_gpio0_ack),
+    .wb_gpio0_err_i      (wb_s2m_gpio0_err),
+    .wb_gpio0_rty_i      (wb_s2m_gpio0_rty),
+    .wb_rom0_adr_o       (wb_m2s_rom0_adr),
+    .wb_rom0_dat_o       (wb_m2s_rom0_dat),
+    .wb_rom0_sel_o       (wb_m2s_rom0_sel),
+    .wb_rom0_we_o        (wb_m2s_rom0_we),
+    .wb_rom0_cyc_o       (wb_m2s_rom0_cyc),
+    .wb_rom0_stb_o       (wb_m2s_rom0_stb),
+    .wb_rom0_cti_o       (wb_m2s_rom0_cti),
+    .wb_rom0_bte_o       (wb_m2s_rom0_bte),
+    .wb_rom0_dat_i       (wb_s2m_rom0_dat),
+    .wb_rom0_ack_i       (wb_s2m_rom0_ack),
+    .wb_rom0_err_i       (wb_s2m_rom0_err),
+    .wb_rom0_rty_i       (wb_s2m_rom0_rty),
+    .wb_sdram_ibus_adr_o (wb_m2s_sdram_ibus_adr),
+    .wb_sdram_ibus_dat_o (wb_m2s_sdram_ibus_dat),
+    .wb_sdram_ibus_sel_o (wb_m2s_sdram_ibus_sel),
+    .wb_sdram_ibus_we_o  (wb_m2s_sdram_ibus_we),
+    .wb_sdram_ibus_cyc_o (wb_m2s_sdram_ibus_cyc),
+    .wb_sdram_ibus_stb_o (wb_m2s_sdram_ibus_stb),
+    .wb_sdram_ibus_cti_o (wb_m2s_sdram_ibus_cti),
+    .wb_sdram_ibus_bte_o (wb_m2s_sdram_ibus_bte),
+    .wb_sdram_ibus_dat_i (wb_s2m_sdram_ibus_dat),
+    .wb_sdram_ibus_ack_i (wb_s2m_sdram_ibus_ack),
+    .wb_sdram_ibus_err_i (wb_s2m_sdram_ibus_err),
+    .wb_sdram_ibus_rty_i (wb_s2m_sdram_ibus_rty));
+
diff --git a/systems/de2/scripts/build_summary b/systems/de2/scripts/build_summary
new file mode 100755
index 00000000..07bb1a6f
--- /dev/null
+++ b/systems/de2/scripts/build_summary
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+FITTER_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nr "; Fitter Summary" | gawk '{print $1}' FS=":")
+FITTER_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nr "; Fitter Settings" | gawk '{print $1}' FS=":")
+
+FITTER_REPORT_START=$(($FITTER_REPORT_START - 1))
+FITTER_REPORT_END=$(($FITTER_REPORT_END - 4))
+
+echo -e "\033[31m"
+sed -n ${FITTER_REPORT_START},${FITTER_REPORT_END}p ${BUILD_ROOT}/bld-quartus/de2.fit.rpt
+
+
+FMAX_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nr "; Slow Model Fmax Summary" | gawk '{print $1}' FS=":")
+FMAX_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nr "This panel reports FMAX" | gawk '{print $1}' FS=":")
+
+FMAX_REPORT_START=$(($FMAX_REPORT_START - 1))
+FMAX_REPORT_END=$(($FMAX_REPORT_END - 1))
+
+echo
+sed -n ${FMAX_REPORT_START},${FMAX_REPORT_END}p ${BUILD_ROOT}/bld-quartus/de2.sta.rpt
+echo -e "\033[0m"

From 0ce4e02005909fea57423984048dd52033c403b4 Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Wed, 5 Mar 2014 17:56:54 +0700
Subject: [PATCH 03/12] Readme updated

---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index 089a305a..710eda9c 100644
--- a/README.md
+++ b/README.md
@@ -2,3 +2,4 @@ orpsoc-cores
 ============
 
 Core description files for ORPSoCv3.
+Support for Altera DE2 board added (alpha, written by Tran Cong Nam).

From 35d07c2328f8a249e9c221c9394bd9c763482e38 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Wed, 5 Mar 2014 22:24:10 +0100
Subject: [PATCH 04/12] Remove generic system

The generic system has been broken for a long time and only adds
confusion. It has been more or less replaced with or1200-generic
---
 systems/generic/bench/orpsoc_tb.v             |   66 -
 systems/generic/bench/uart_decoder.v          |   93 -
 systems/generic/generic.core                  |   34 -
 systems/generic/generic.system                |    3 -
 systems/generic/rtl/verilog/clkgen.v          |  118 --
 .../rtl/verilog/include/or1200_defines.v      | 1824 -----------------
 .../rtl/verilog/include/orpsoc-defines.v      |   42 -
 .../rtl/verilog/include/orpsoc-params.v       |   95 -
 .../generic/rtl/verilog/include/timescale.v   |    1 -
 .../rtl/verilog/include/uart_defines.v        |  250 ---
 systems/generic/rtl/verilog/intgen.v          |   70 -
 systems/generic/rtl/verilog/orpsoc_top.v      |  780 -------
 systems/generic/rtl/verilog/rom.v             |  126 --
 13 files changed, 3502 deletions(-)
 delete mode 100644 systems/generic/bench/orpsoc_tb.v
 delete mode 100644 systems/generic/bench/uart_decoder.v
 delete mode 100644 systems/generic/generic.core
 delete mode 100644 systems/generic/generic.system
 delete mode 100644 systems/generic/rtl/verilog/clkgen.v
 delete mode 100644 systems/generic/rtl/verilog/include/or1200_defines.v
 delete mode 100644 systems/generic/rtl/verilog/include/orpsoc-defines.v
 delete mode 100644 systems/generic/rtl/verilog/include/orpsoc-params.v
 delete mode 100644 systems/generic/rtl/verilog/include/timescale.v
 delete mode 100644 systems/generic/rtl/verilog/include/uart_defines.v
 delete mode 100644 systems/generic/rtl/verilog/intgen.v
 delete mode 100644 systems/generic/rtl/verilog/orpsoc_top.v
 delete mode 100644 systems/generic/rtl/verilog/rom.v

diff --git a/systems/generic/bench/orpsoc_tb.v b/systems/generic/bench/orpsoc_tb.v
deleted file mode 100644
index fae0c270..00000000
--- a/systems/generic/bench/orpsoc_tb.v
+++ /dev/null
@@ -1,66 +0,0 @@
-`include "timescale.v"
-
-module orpsoc_tb;
-
-   reg clk   = 0;
-   reg rst_n = 1;
-
-   always
-     #5 clk <= ~clk;
-
-   initial begin
-      #100 rst_n <= 0;
-      #200 rst_n <= 1;
-   end
-
-   vlog_tb_utils vlog_tb_utils0();
-
-   integer mem_words;
-   integer i;
-   reg [31:0] mem_word;
-   reg [1023:0] elf_file;
-
-   initial begin
-      if($value$plusargs("elf_load=%s", elf_file)) begin
-	 $elf_load_file(elf_file);
-      
-	 mem_words = $elf_get_size/4;
-	 for(i=0; i < mem_words; i = i+1)
-	   orpsoc_tb.dut.ram_wb0.ram_wb_b3_0.mem[i] = $elf_read_32(i*4);
-      end else
-	$display("No ELF file specified");
-   end
-   
-   reg enable_jtag_vpi;
-   initial enable_jtag_vpi = $test$plusargs("enable_jtag_vpi");
-   
-   jtag_vpi jtag_vpi0
-     (.tms       (tms),
-      .tck       (tck),
-      .tdi       (tdi),
-      .tdo       (tdo),
-      .enable    (enable_jtag_vpi),
-      .init_done (orpsoc_tb.dut.wb_rst));
-
-   orpsoc_top dut
-     (.clk_pad_i   (clk),
-      .rst_n_pad_i (rst_n),
-      //JTAG interface
-      .tms_pad_i(tms),
-      .tck_pad_i(tck),
-      .tdi_pad_i(tdi),
-      .tdo_pad_o(tdo),
-      //UART interface
-      .uart0_srx_pad_i(uart),
-      .uart0_stx_pad_o(uart));
-
-   or1200_monitor i_monitor();
-
-   //FIXME: Get correct baud rate from parameter
-   uart_decoder
-     #(.uart_baudrate_period_ns(8680/2))
-   uart_decoder0
-     (.clk(clk),
-      .uart_tx(uart));
-   
-endmodule
diff --git a/systems/generic/bench/uart_decoder.v b/systems/generic/bench/uart_decoder.v
deleted file mode 100644
index 8046c3db..00000000
--- a/systems/generic/bench/uart_decoder.v
+++ /dev/null
@@ -1,93 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  ORPSoC Testbench UART Decoder                               ////
-////                                                              ////
-////  Description                                                 ////
-////  ORPSoC Testbench UART output decoder                        ////
-////                                                              ////
-////  To Do:                                                      ////
-////                                                              ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - jb, jb@orsoc.se                                       ////
-////                                                              ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-
-// Receieves and decodes 8-bit,  1 stop bit, no parity UART signals.
-`timescale 1ns/1ns
-module uart_decoder(clk, uart_tx);
-
-   input clk;   
-   input uart_tx;
-
-   // Default baud of 115200, period (ns)
-   parameter uart_baudrate_period_ns = 8680; 
-
-   // Something to trigger the task
-   always @(posedge clk)
-     uart_decoder;
-   
-   task uart_decoder;
-      reg [7:0] tx_byte;
-      begin
-	 while (uart_tx !== 1'b1)
-	   @(uart_tx); 
-	 // Wait for start bit
-	 while (uart_tx !== 1'b0)
-           @(uart_tx);
-	 #(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
-	 tx_byte[0] = uart_tx;
-	 #uart_baudrate_period_ns;
-	 tx_byte[1] = uart_tx;
-	 #uart_baudrate_period_ns;
-	 tx_byte[2] = uart_tx;
-	 #uart_baudrate_period_ns;
-	 tx_byte[3] = uart_tx;
-	 #uart_baudrate_period_ns;
-	 tx_byte[4] = uart_tx;
-	 #uart_baudrate_period_ns;
-	 tx_byte[5] = uart_tx;
-	 #uart_baudrate_period_ns;
-	 tx_byte[6] = uart_tx;
-	 #uart_baudrate_period_ns;
-	 tx_byte[7] = uart_tx;
-	 #uart_baudrate_period_ns;
-	 //Check for stop bit
-	 if (uart_tx !== 1'b1)
-	   begin
-	      // Wait for return to idle
-	      while (uart_tx !== 1'b1)
-		@(uart_tx);
-	   end
-	 // display the char
-	 $write("%c", tx_byte);
-      end
-   endtask // user_uart_read_byte
-
-endmodule // uart_decoder
diff --git a/systems/generic/generic.core b/systems/generic/generic.core
deleted file mode 100644
index 63fbd072..00000000
--- a/systems/generic/generic.core
+++ /dev/null
@@ -1,34 +0,0 @@
-CAPI=1
-[main]
-depend = 
- adv_debug_sys
- dbg
- jtag_tap
- jtag_vpi
- or1200
- elf-loader
- ram_wb
- uart16550
- vlog_tb_utils
- wb_utils
-
-simulators =
- icarus
- modelsim
-
-[verilog]
-src_files = 
- rtl/verilog/clkgen.v
- rtl/verilog/intgen.v
- rtl/verilog/rom.v
- rtl/verilog/orpsoc_top.v
-include_files =
- rtl/verilog/include/or1200_defines.v
- rtl/verilog/include/orpsoc-defines.v
- rtl/verilog/include/orpsoc-params.v
- rtl/verilog/include/timescale.v
- rtl/verilog/include/uart_defines.v
-
-tb_src_files = 
- bench/uart_decoder.v
- bench/orpsoc_tb.v
diff --git a/systems/generic/generic.system b/systems/generic/generic.system
deleted file mode 100644
index 1e024e79..00000000
--- a/systems/generic/generic.system
+++ /dev/null
@@ -1,3 +0,0 @@
-SAPI=1
-[main]
-description = "Generic technology independent OpenRISC system
diff --git a/systems/generic/rtl/verilog/clkgen.v b/systems/generic/rtl/verilog/clkgen.v
deleted file mode 100644
index d4606b00..00000000
--- a/systems/generic/rtl/verilog/clkgen.v
+++ /dev/null
@@ -1,118 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//
-// clkgen
-//
-// Handles clock and reset generation for rest of design
-//
-//
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-//
-// A simple implementation for the main generic ORPSoC simulations
-//
-
-`include "timescale.v"
-`include "orpsoc-defines.v"
-
-module clkgen
-  (
-   // Main clocks in, depending on board
-   clk_pad_i,
-
-   // Input reset - through a buffer, asynchronous
-   async_rst_o,
-   // Wishbone clock and reset out  
-   wb_clk_o,
-   wb_rst_o,
-
-   // JTAG clock
-`ifdef JTAG_DEBUG
-   tck_pad_i,
-   dbg_tck_o,
-`endif      
-
-   // Asynchronous, active low reset in
-   rst_n_pad_i
-   
-   );
-
-   input clk_pad_i;
-   
-   output async_rst_o;
-   
-   output wb_rst_o;
-   output wb_clk_o;
-
-`ifdef JTAG_DEBUG
-   input  tck_pad_i;
-   output dbg_tck_o;
-`endif      
-   
-   // Asynchronous, active low reset (pushbutton, typically)
-   input  rst_n_pad_i;
-   
-   // First, deal with the asychronous reset
-   wire   async_rst_n;
-
-   // An input buffer is usually instantiated here
-   assign async_rst_n = rst_n_pad_i;
-   
-   // Everyone likes active-high reset signals...
-   assign async_rst_o = ~async_rst_n;
-   
-`ifdef JTAG_DEBUG
-   assign dbg_tck_o = tck_pad_i;
-`endif
-
-   //
-   // Declare synchronous reset wires here
-   //
-   
-   // An active-low synchronous reset signal (usually a PLL lock signal)
-   wire   sync_rst_n;
-   assign sync_rst_n  = async_rst_n; // Pretend it's somehow synchronous now
-
-
-   // Here we just assign "board" clock (really test) to wishbone clock
-   assign wb_clk_o = clk_pad_i;
-   
-   //
-   // Reset generation
-   //
-   //
-
-   // Reset generation for wishbone
-   reg [15:0] 	   wb_rst_shr;
-   always @(posedge wb_clk_o or posedge async_rst_o)
-     if (async_rst_o)
-       wb_rst_shr <= 16'hffff;
-     else
-       wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
-   
-   assign wb_rst_o = wb_rst_shr[15];
-   
-endmodule // clkgen
diff --git a/systems/generic/rtl/verilog/include/or1200_defines.v b/systems/generic/rtl/verilog/include/or1200_defines.v
deleted file mode 100644
index bdfcc838..00000000
--- a/systems/generic/rtl/verilog/include/or1200_defines.v
+++ /dev/null
@@ -1,1824 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  OR1200's definitions                                        ////
-////                                                              ////
-////  This file is part of the OpenRISC 1200 project              ////
-////  http://opencores.org/project,or1k                           ////
-////                                                              ////
-////  Description                                                 ////
-////  Defines for the OR1200 core                                 ////
-////                                                              ////
-////  To Do:                                                      ////
-////   - add parameters that are missing                          ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Damjan Lampret, lampret@opencores.org                 ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-//
-// $Log: or1200_defines.v,v $
-// Revision 2.0  2010/06/30 11:00:00  ORSoC
-// Minor update: 
-// Defines added, bugs fixed. 
-
-//
-// Dump VCD
-//
-//`define OR1200_VCD_DUMP
-
-//
-// Generate debug messages during simulation
-//
-//`define OR1200_VERBOSE
-
-//  `define OR1200_ASIC
-////////////////////////////////////////////////////////
-//
-// Typical configuration for an ASIC
-//
-`ifdef OR1200_ASIC
-
-//
-// Target ASIC memories
-//
-//`define OR1200_ARTISAN_SSP
-//`define OR1200_ARTISAN_SDP
-//`define OR1200_ARTISAN_STP
-`define OR1200_VIRTUALSILICON_SSP
-//`define OR1200_VIRTUALSILICON_STP_T1
-//`define OR1200_VIRTUALSILICON_STP_T2
-
-//
-// Do not implement Data cache
-//
-//`define OR1200_NO_DC
-
-//
-// Do not implement Insn cache
-//
-//`define OR1200_NO_IC
-
-//
-// Do not implement Data MMU
-//
-//`define OR1200_NO_DMMU
-
-//
-// Do not implement Insn MMU
-//
-//`define OR1200_NO_IMMU
-
-//
-// Select between ASIC optimized and generic multiplier
-//
-//`define OR1200_ASIC_MULTP2_32X32
-`define OR1200_GENERIC_MULTP2_32X32
-
-//
-// Size/type of insn/data cache if implemented
-//
-// `define OR1200_IC_1W_512B
-// `define OR1200_IC_1W_4KB
-`define OR1200_IC_1W_8KB
-// `define OR1200_DC_1W_4KB
-`define OR1200_DC_1W_8KB
-
-`else
-
-
-/////////////////////////////////////////////////////////
-//
-// Typical configuration for an FPGA
-//
-
-//
-// Target FPGA memories
-//
-//`define OR1200_ALTERA_LPM
-//`define OR1200_XILINX_RAMB16
-//`define OR1200_XILINX_RAMB4
-//`define OR1200_XILINX_RAM32X1D
-//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
-// Generic models should infer RAM blocks at synthesis time (not only effects 
-// single port ram.)
-`define OR1200_GENERIC
-
-//
-// Do not implement Data cache
-//
-//`define OR1200_NO_DC
-
-//
-// Do not implement Insn cache
-//
-//`define OR1200_NO_IC
-
-//
-// Do not implement Data MMU
-//
-//`define OR1200_NO_DMMU
-
-//
-// Do not implement Insn MMU
-//
-//`define OR1200_NO_IMMU
-
-//
-// Select between ASIC and generic multiplier
-//
-// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
-//
-//`define OR1200_ASIC_MULTP2_32X32
-`define OR1200_GENERIC_MULTP2_32X32
-
-//
-// Size/type of insn/data cache if implemented
-// (consider available FPGA memory resources)
-//
-//`define OR1200_IC_1W_512B
-`define OR1200_IC_1W_4KB
-//`define OR1200_IC_1W_8KB
-//`define OR1200_IC_1W_16KB
-//`define OR1200_IC_1W_32KB
-`define OR1200_DC_1W_4KB
-//`define OR1200_DC_1W_8KB
-//`define OR1200_DC_1W_16KB
-//`define OR1200_DC_1W_32KB
-
-`endif
-
-
-//////////////////////////////////////////////////////////
-//
-// Do not change below unless you know what you are doing
-//
-
-//
-// Reset active low
-//
-//`define OR1200_RST_ACT_LOW
-
-//
-// Enable RAM BIST
-//
-// At the moment this only works for Virtual Silicon
-// single port RAMs. For other RAMs it has not effect.
-// Special wrapper for VS RAMs needs to be provided
-// with scan flops to facilitate bist scan.
-//
-//`define OR1200_BIST
-
-//
-// Register OR1200 WISHBONE outputs
-// (must be defined/enabled)
-//
-`define OR1200_REGISTERED_OUTPUTS
-
-//
-// Register OR1200 WISHBONE inputs
-//
-// (must be undefined/disabled)
-//
-//`define OR1200_REGISTERED_INPUTS
-
-//
-// Disable bursts if they are not supported by the
-// memory subsystem (only affect cache line fill)
-//
-//`define OR1200_NO_BURSTS
-//
-
-//
-// WISHBONE retry counter range
-//
-// 2^value range for retry counter. Retry counter
-// is activated whenever *wb_rty_i is asserted and
-// until retry counter expires, corresponding
-// WISHBONE interface is deactivated.
-//
-// To disable retry counters and *wb_rty_i all together,
-// undefine this macro.
-//
-//`define OR1200_WB_RETRY 7
-
-//
-// WISHBONE Consecutive Address Burst
-//
-// This was used prior to WISHBONE B3 specification
-// to identify bursts. It is no longer needed but
-// remains enabled for compatibility with old designs.
-//
-// To remove *wb_cab_o ports undefine this macro.
-//
-//`define OR1200_WB_CAB
-
-//
-// WISHBONE B3 compatible interface
-//
-// This follows the WISHBONE B3 specification.
-// It is not enabled by default because most
-// designs still don't use WB b3.
-//
-// To enable *wb_cti_o/*wb_bte_o ports,
-// define this macro.
-//
-`define OR1200_WB_B3
-
-//
-// LOG all WISHBONE accesses
-//
-`define OR1200_LOG_WB_ACCESS
-
-//
-// Enable additional synthesis directives if using
-// _Synopsys_ synthesis tool
-//
-//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
-
-//
-// Enables default statement in some case blocks
-// and disables Synopsys synthesis directive full_case
-//
-// By default it is enabled. When disabled it
-// can increase clock frequency.
-//
-`define OR1200_CASE_DEFAULT
-
-//
-// Operand width / register file address width
-//
-// (DO NOT CHANGE)
-//
-`define OR1200_OPERAND_WIDTH		32
-`define OR1200_REGFILE_ADDR_WIDTH	5
-
-//
-// l.add/l.addi/l.and and optional l.addc/l.addic
-// also set (compare) flag when result of their
-// operation equals zero
-//
-// At the time of writing this, default or32
-// C/C++ compiler doesn't generate code that
-// would benefit from this optimization.
-//
-// By default this optimization is disabled to
-// save area.
-//
-//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
-
-//
-// Implement l.addc/l.addic instructions
-//
-// By default implementation of l.addc/l.addic
-// instructions is enabled in case you need them.
-// If you don't use them, then disable implementation
-// to save area.
-//
-`define OR1200_IMPL_ADDC
-
-//
-// Implement l.sub instruction
-//
-// By default implementation of l.sub instructions
-// is enabled to be compliant with the simulator.
-// If you don't use carry bit, then disable
-// implementation to save area.
-//
-`define OR1200_IMPL_SUB
-
-//
-// Implement carry bit SR[CY]
-//
-//
-// By default implementation of SR[CY] is enabled
-// to be compliant with the simulator. However SR[CY]
-// is explicitly only used by l.addc/l.addic/l.sub
-// instructions and if these three insns are not
-// implemented there is not much point having SR[CY].
-//
-`define OR1200_IMPL_CY
-
-//
-// Implement carry bit SR[OV]
-//
-// Compiler doesn't use this, but other code may like
-// to.
-//
-`define OR1200_IMPL_OV
-
-//
-// Implement carry bit SR[OVE]
-//
-// Overflow interrupt indicator. When enabled, SR[OV] flag
-// does not remain asserted after exception.
-//
-`define OR1200_IMPL_OVE
-
-
-//
-// Implement rotate in the ALU
-//
-// At the time of writing this, or32
-// C/C++ compiler doesn't generate rotate
-// instructions. However or32 assembler
-// can assemble code that uses rotate insn.
-// This means that rotate instructions
-// must be used manually inserted.
-//
-// By default implementation of rotate
-// is disabled to save area and increase
-// clock frequency.
-//
-//`define OR1200_IMPL_ALU_ROTATE
-
-//
-// Type of ALU compare to implement
-//
-// Try to find which synthesizes with
-// most efficient logic use or highest speed.
-//
-//`define OR1200_IMPL_ALU_COMP1
-//`define OR1200_IMPL_ALU_COMP2
-`define OR1200_IMPL_ALU_COMP3
-
-//
-// Implement Find First/Last '1'
-//
-`define OR1200_IMPL_ALU_FFL1
-
-//
-// Implement l.cust5 ALU instruction
-//
-//`define OR1200_IMPL_ALU_CUST5
-
-//
-// Implement l.extXs and l.extXz instructions
-//
-`define OR1200_IMPL_ALU_EXT
-
-//
-// Implement multiplier
-//
-// By default multiplier is implemented
-//
-`define OR1200_MULT_IMPLEMENTED
-
-//
-// Implement multiply-and-accumulate
-//
-// By default MAC is implemented. To
-// implement MAC, multiplier (non-serial) needs to be
-// implemented.
-//
-`define OR1200_MAC_IMPLEMENTED
-
-//
-// Implement optional l.div/l.divu instructions
-//
-// By default divide instructions are not implemented
-// to save area.
-//
-//
-`define OR1200_DIV_IMPLEMENTED
-
-//
-// Serial multiplier.
-//
-//`define OR1200_MULT_SERIAL
-
-//
-// Serial divider.
-// Uncomment to use a serial divider, otherwise will
-// be a generic parallel implementation.
-//
-`define OR1200_DIV_SERIAL
-
-//
-// Implement HW Single Precision FPU
-//
-`define OR1200_FPU_IMPLEMENTED
-
-//
-// Clock ratio RISC clock versus WB clock
-//
-// If you plan to run WB:RISC clock fixed to 1:1, disable
-// both defines
-//
-// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
-// and use clmode to set ratio
-//
-// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
-// clmode to set ratio
-//
-//`define OR1200_CLKDIV_2_SUPPORTED
-//`define OR1200_CLKDIV_4_SUPPORTED
-
-//
-// Type of register file RAM
-//
-// Memory macro w/ two ports (see or1200_tpram_32x32.v)
-//`define OR1200_RFRAM_TWOPORT
-//
-// Memory macro dual port (see or1200_dpram.v)
-`define OR1200_RFRAM_DUALPORT
-
-//
-// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
-//`define OR1200_RFRAM_GENERIC
-//  Generic register file supports - 16 registers 
-`ifdef OR1200_RFRAM_GENERIC
-//    `define OR1200_RFRAM_16REG
-`endif
-
-//
-// Type of mem2reg aligner to implement.
-//
-// Once OR1200_IMPL_MEM2REG2 yielded faster
-// circuit, however with today tools it will
-// most probably give you slower circuit.
-//
-`define OR1200_IMPL_MEM2REG1
-//`define OR1200_IMPL_MEM2REG2
-
-//
-// Reset value and event
-//
-`ifdef OR1200_RST_ACT_LOW
-  `define OR1200_RST_VALUE      (1'b0)
-  `define OR1200_RST_EVENT      negedge
-`else
-  `define OR1200_RST_VALUE      (1'b1)
-  `define OR1200_RST_EVENT      posedge
-`endif
-
-//
-// ALUOPs
-//
-`define OR1200_ALUOP_WIDTH	5
-`define OR1200_ALUOP_NOP	5'b0_0100
-/* LS-nibble encodings correspond to bits [3:0] of instruction */
-`define OR1200_ALUOP_ADD	5'b0_0000 // 0
-`define OR1200_ALUOP_ADDC	5'b0_0001 // 1
-`define OR1200_ALUOP_SUB	5'b0_0010 // 2
-`define OR1200_ALUOP_AND	5'b0_0011 // 3
-`define OR1200_ALUOP_OR		5'b0_0100 // 4
-`define OR1200_ALUOP_XOR	5'b0_0101 // 5
-`define OR1200_ALUOP_MUL	5'b0_0110 // 6
-`define OR1200_ALUOP_RESERVED	5'b0_0111 // 7
-`define OR1200_ALUOP_SHROT	5'b0_1000 // 8
-`define OR1200_ALUOP_DIV	5'b0_1001 // 9
-`define OR1200_ALUOP_DIVU	5'b0_1010 // a
-`define OR1200_ALUOP_MULU	5'b0_1011 // b
-`define OR1200_ALUOP_EXTHB	5'b0_1100 // c
-`define OR1200_ALUOP_EXTW	5'b0_1101 // d
-`define OR1200_ALUOP_CMOV	5'b0_1110 // e
-`define OR1200_ALUOP_FFL1	5'b0_1111 // f
-
-/* Values sent to ALU from decode unit - not defined by ISA */
-`define OR1200_ALUOP_COMP       5'b1_0000 // Comparison
-`define OR1200_ALUOP_MOVHI      5'b1_0001 // Move-high
-`define OR1200_ALUOP_CUST5	5'b1_0010 // l.cust5
-
-// ALU instructions second opcode field
-`define OR1200_ALUOP2_POS	9:6
-`define OR1200_ALUOP2_WIDTH	4
-
-//
-// MACOPs
-//
-`define OR1200_MACOP_WIDTH	3
-`define OR1200_MACOP_NOP	3'b000
-`define OR1200_MACOP_MAC	3'b001
-`define OR1200_MACOP_MSB	3'b010
-
-//
-// Shift/rotate ops
-//
-`define OR1200_SHROTOP_WIDTH	4
-`define OR1200_SHROTOP_NOP	4'd0
-`define OR1200_SHROTOP_SLL	4'd0
-`define OR1200_SHROTOP_SRL	4'd1
-`define OR1200_SHROTOP_SRA	4'd2
-`define OR1200_SHROTOP_ROR	4'd3
-
-//
-// Zero/Sign Extend ops
-//
-`define OR1200_EXTHBOP_WIDTH      4
-`define OR1200_EXTHBOP_BS         4'h1
-`define OR1200_EXTHBOP_HS         4'h0
-`define OR1200_EXTHBOP_BZ         4'h3
-`define OR1200_EXTHBOP_HZ         4'h2
-`define OR1200_EXTWOP_WIDTH       4
-`define OR1200_EXTWOP_WS          4'h0
-`define OR1200_EXTWOP_WZ          4'h1
-
-// Execution cycles per instruction
-`define OR1200_MULTICYCLE_WIDTH	3
-`define OR1200_ONE_CYCLE		3'd0
-`define OR1200_TWO_CYCLES		3'd1
-
-// Execution control which will "wait on" a module to finish
-`define OR1200_WAIT_ON_WIDTH 2
-`define OR1200_WAIT_ON_NOTHING    `OR1200_WAIT_ON_WIDTH'd0
-`define OR1200_WAIT_ON_MULTMAC    `OR1200_WAIT_ON_WIDTH'd1
-`define OR1200_WAIT_ON_FPU        `OR1200_WAIT_ON_WIDTH'd2
-`define OR1200_WAIT_ON_MTSPR      `OR1200_WAIT_ON_WIDTH'd3
-
-
-// Operand MUX selects
-`define OR1200_SEL_WIDTH		2
-`define OR1200_SEL_RF			2'd0
-`define OR1200_SEL_IMM			2'd1
-`define OR1200_SEL_EX_FORW		2'd2
-`define OR1200_SEL_WB_FORW		2'd3
-
-//
-// BRANCHOPs
-//
-`define OR1200_BRANCHOP_WIDTH		3
-`define OR1200_BRANCHOP_NOP		3'd0
-`define OR1200_BRANCHOP_J		3'd1
-`define OR1200_BRANCHOP_JR		3'd2
-`define OR1200_BRANCHOP_BAL		3'd3
-`define OR1200_BRANCHOP_BF		3'd4
-`define OR1200_BRANCHOP_BNF		3'd5
-`define OR1200_BRANCHOP_RFE		3'd6
-
-//
-// LSUOPs
-//
-// Bit 0: sign extend
-// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
-// Bit 3: 0 load, 1 store
-`define OR1200_LSUOP_WIDTH		4
-`define OR1200_LSUOP_NOP		4'b0000
-`define OR1200_LSUOP_LBZ		4'b0010
-`define OR1200_LSUOP_LBS		4'b0011
-`define OR1200_LSUOP_LHZ		4'b0100
-`define OR1200_LSUOP_LHS		4'b0101
-`define OR1200_LSUOP_LWZ		4'b0110
-`define OR1200_LSUOP_LWS		4'b0111
-`define OR1200_LSUOP_LD			4'b0001
-`define OR1200_LSUOP_SD			4'b1000
-`define OR1200_LSUOP_SB			4'b1010
-`define OR1200_LSUOP_SH			4'b1100
-`define OR1200_LSUOP_SW			4'b1110
-
-// Number of bits of load/store EA precalculated in ID stage
-// for balancing ID and EX stages.
-//
-// Valid range: 2,3,...,30,31
-`define OR1200_LSUEA_PRECALC		2
-
-// FETCHOPs
-`define OR1200_FETCHOP_WIDTH		1
-`define OR1200_FETCHOP_NOP		1'b0
-`define OR1200_FETCHOP_LW		1'b1
-
-//
-// Register File Write-Back OPs
-//
-// Bit 0: register file write enable
-// Bits 3-1: write-back mux selects
-//
-`define OR1200_RFWBOP_WIDTH		4
-`define OR1200_RFWBOP_NOP		4'b0000
-`define OR1200_RFWBOP_ALU		3'b000
-`define OR1200_RFWBOP_LSU		3'b001
-`define OR1200_RFWBOP_SPRS		3'b010
-`define OR1200_RFWBOP_LR		3'b011
-`define OR1200_RFWBOP_FPU		3'b100
-
-// Compare instructions
-`define OR1200_COP_SFEQ       3'b000
-`define OR1200_COP_SFNE       3'b001
-`define OR1200_COP_SFGT       3'b010
-`define OR1200_COP_SFGE       3'b011
-`define OR1200_COP_SFLT       3'b100
-`define OR1200_COP_SFLE       3'b101
-`define OR1200_COP_X          3'b111
-`define OR1200_SIGNED_COMPARE 'd3
-`define OR1200_COMPOP_WIDTH	4
-
-//
-// FP OPs
-//
-// MSbit indicates FPU operation valid
-//
-`define OR1200_FPUOP_WIDTH	8
-// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
-`define OR1200_FPUOP_CYCLES 3'd4
-// FP instruction is double precision if bit 4 is set. We're a 32-bit 
-// implementation thus do not support double precision FP 
-`define OR1200_FPUOP_DOUBLE_BIT 4
-`define OR1200_FPUOP_ADD  8'b0000_0000
-`define OR1200_FPUOP_SUB  8'b0000_0001
-`define OR1200_FPUOP_MUL  8'b0000_0010
-`define OR1200_FPUOP_DIV  8'b0000_0011
-`define OR1200_FPUOP_ITOF 8'b0000_0100
-`define OR1200_FPUOP_FTOI 8'b0000_0101
-`define OR1200_FPUOP_REM  8'b0000_0110
-`define OR1200_FPUOP_RESERVED  8'b0000_0111
-// FP Compare instructions
-`define OR1200_FPCOP_SFEQ 8'b0000_1000
-`define OR1200_FPCOP_SFNE 8'b0000_1001
-`define OR1200_FPCOP_SFGT 8'b0000_1010
-`define OR1200_FPCOP_SFGE 8'b0000_1011
-`define OR1200_FPCOP_SFLT 8'b0000_1100
-`define OR1200_FPCOP_SFLE 8'b0000_1101
-
-//
-// TAGs for instruction bus
-//
-`define OR1200_ITAG_IDLE	4'h0	// idle bus
-`define	OR1200_ITAG_NI		4'h1	// normal insn
-`define OR1200_ITAG_BE		4'hb	// Bus error exception
-`define OR1200_ITAG_PE		4'hc	// Page fault exception
-`define OR1200_ITAG_TE		4'hd	// TLB miss exception
-
-//
-// TAGs for data bus
-//
-`define OR1200_DTAG_IDLE	4'h0	// idle bus
-`define	OR1200_DTAG_ND		4'h1	// normal data
-`define OR1200_DTAG_AE		4'ha	// Alignment exception
-`define OR1200_DTAG_BE		4'hb	// Bus error exception
-`define OR1200_DTAG_PE		4'hc	// Page fault exception
-`define OR1200_DTAG_TE		4'hd	// TLB miss exception
-
-
-//////////////////////////////////////////////
-//
-// ORBIS32 ISA specifics
-//
-
-// SHROT_OP position in machine word
-`define OR1200_SHROTOP_POS		7:6
-
-//
-// Instruction opcode groups (basic)
-//
-`define OR1200_OR32_J                 6'b000000
-`define OR1200_OR32_JAL               6'b000001
-`define OR1200_OR32_BNF               6'b000011
-`define OR1200_OR32_BF                6'b000100
-`define OR1200_OR32_NOP               6'b000101
-`define OR1200_OR32_MOVHI             6'b000110
-`define OR1200_OR32_MACRC             6'b000110
-`define OR1200_OR32_XSYNC             6'b001000
-`define OR1200_OR32_RFE               6'b001001
-/* */
-`define OR1200_OR32_JR                6'b010001
-`define OR1200_OR32_JALR              6'b010010
-`define OR1200_OR32_MACI              6'b010011
-/* */
-`define OR1200_OR32_LWZ               6'b100001
-`define OR1200_OR32_LWS               6'b100010
-`define OR1200_OR32_LBZ               6'b100011
-`define OR1200_OR32_LBS               6'b100100
-`define OR1200_OR32_LHZ               6'b100101
-`define OR1200_OR32_LHS               6'b100110
-`define OR1200_OR32_ADDI              6'b100111
-`define OR1200_OR32_ADDIC             6'b101000
-`define OR1200_OR32_ANDI              6'b101001
-`define OR1200_OR32_ORI               6'b101010
-`define OR1200_OR32_XORI              6'b101011
-`define OR1200_OR32_MULI              6'b101100
-`define OR1200_OR32_MFSPR             6'b101101
-`define OR1200_OR32_SH_ROTI 	      6'b101110
-`define OR1200_OR32_SFXXI             6'b101111
-/* */
-`define OR1200_OR32_MTSPR             6'b110000
-`define OR1200_OR32_MACMSB            6'b110001
-`define OR1200_OR32_FLOAT             6'b110010
-/* */
-`define OR1200_OR32_SW                6'b110101
-`define OR1200_OR32_SB                6'b110110
-`define OR1200_OR32_SH                6'b110111
-`define OR1200_OR32_ALU               6'b111000
-`define OR1200_OR32_SFXX              6'b111001
-`define OR1200_OR32_CUST5             6'b111100
-
-/////////////////////////////////////////////////////
-//
-// Exceptions
-//
-
-//
-// Exception vectors per OR1K architecture:
-// 0xPPPPP100 - reset
-// 0xPPPPP200 - bus error
-// ... etc
-// where P represents exception prefix.
-//
-// Exception vectors can be customized as per
-// the following formula:
-// 0xPPPPPNVV - exception N
-//
-// P represents exception prefix
-// N represents exception N
-// VV represents length of the individual vector space,
-//   usually it is 8 bits wide and starts with all bits zero
-//
-
-//
-// PPPPP and VV parts
-//
-// Sum of these two defines needs to be 28
-//
-`define OR1200_EXCEPT_EPH0_P    20'h00000
-`define OR1200_EXCEPT_EPH1_P    20'hF0000
-`define OR1200_EXCEPT_V		    8'h00
-
-//
-// N part width
-//
-`define OR1200_EXCEPT_WIDTH 4
-
-//
-// Definition of exception vectors
-//
-// To avoid implementation of a certain exception,
-// simply comment out corresponding line
-//
-`define OR1200_EXCEPT_UNUSED		`OR1200_EXCEPT_WIDTH'hf
-`define OR1200_EXCEPT_TRAP		`OR1200_EXCEPT_WIDTH'he
-`define OR1200_EXCEPT_FLOAT		`OR1200_EXCEPT_WIDTH'hd
-`define OR1200_EXCEPT_SYSCALL		`OR1200_EXCEPT_WIDTH'hc
-`define OR1200_EXCEPT_RANGE		`OR1200_EXCEPT_WIDTH'hb
-`define OR1200_EXCEPT_ITLBMISS		`OR1200_EXCEPT_WIDTH'ha
-`define OR1200_EXCEPT_DTLBMISS		`OR1200_EXCEPT_WIDTH'h9
-`define OR1200_EXCEPT_INT		`OR1200_EXCEPT_WIDTH'h8
-`define OR1200_EXCEPT_ILLEGAL		`OR1200_EXCEPT_WIDTH'h7
-`define OR1200_EXCEPT_ALIGN		`OR1200_EXCEPT_WIDTH'h6
-`define OR1200_EXCEPT_TICK		`OR1200_EXCEPT_WIDTH'h5
-`define OR1200_EXCEPT_IPF		`OR1200_EXCEPT_WIDTH'h4
-`define OR1200_EXCEPT_DPF		`OR1200_EXCEPT_WIDTH'h3
-`define OR1200_EXCEPT_BUSERR		`OR1200_EXCEPT_WIDTH'h2
-`define OR1200_EXCEPT_RESET		`OR1200_EXCEPT_WIDTH'h1
-`define OR1200_EXCEPT_NONE		`OR1200_EXCEPT_WIDTH'h0
-
-
-/////////////////////////////////////////////////////
-//
-// SPR groups
-//
-
-// Bits that define the group
-`define OR1200_SPR_GROUP_BITS	15:11
-
-// Width of the group bits
-`define OR1200_SPR_GROUP_WIDTH 	5
-
-// Bits that define offset inside the group
-`define OR1200_SPR_OFS_BITS 10:0
-
-// List of groups
-`define OR1200_SPR_GROUP_SYS	5'd00
-`define OR1200_SPR_GROUP_DMMU	5'd01
-`define OR1200_SPR_GROUP_IMMU	5'd02
-`define OR1200_SPR_GROUP_DC	5'd03
-`define OR1200_SPR_GROUP_IC	5'd04
-`define OR1200_SPR_GROUP_MAC	5'd05
-`define OR1200_SPR_GROUP_DU	5'd06
-`define OR1200_SPR_GROUP_PM	5'd08
-`define OR1200_SPR_GROUP_PIC	5'd09
-`define OR1200_SPR_GROUP_TT	5'd10
-`define OR1200_SPR_GROUP_FPU    5'd11
-
-/////////////////////////////////////////////////////
-//
-// System group
-//
-
-//
-// System registers
-//
-`define OR1200_SPR_CFGR		7'd0
-`define OR1200_SPR_RF		6'd32	// 1024 >> 5
-`define OR1200_SPR_NPC		11'd16
-`define OR1200_SPR_SR		11'd17
-`define OR1200_SPR_PPC		11'd18
-`define OR1200_SPR_FPCSR        11'd20
-`define OR1200_SPR_EPCR		11'd32
-`define OR1200_SPR_EEAR		11'd48
-`define OR1200_SPR_ESR		11'd64
-
-//
-// SR bits
-//
-`define OR1200_SR_WIDTH 17
-`define OR1200_SR_SM   0
-`define OR1200_SR_TEE  1
-`define OR1200_SR_IEE  2
-`define OR1200_SR_DCE  3
-`define OR1200_SR_ICE  4
-`define OR1200_SR_DME  5
-`define OR1200_SR_IME  6
-`define OR1200_SR_LEE  7
-`define OR1200_SR_CE   8
-`define OR1200_SR_F    9
-`define OR1200_SR_CY   10	// Optional
-`define OR1200_SR_OV   11	// Optional
-`define OR1200_SR_OVE  12	// Optional
-`define OR1200_SR_DSX  13	// Unused
-`define OR1200_SR_EPH  14
-`define OR1200_SR_FO   15
-`define OR1200_SR_TED  16
-`define OR1200_SR_CID  31:28	// Unimplemented
-
-//
-// Bits that define offset inside the group
-//
-`define OR1200_SPROFS_BITS 10:0
-
-//
-// Default Exception Prefix
-//
-// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
-// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
-//
-`define OR1200_SR_EPH_DEF	1'b0
-
-
-//
-// FPCSR bits
-//
-`define OR1200_FPCSR_WIDTH 12
-`define OR1200_FPCSR_FPEE  0
-`define OR1200_FPCSR_RM    2:1
-`define OR1200_FPCSR_OVF   3
-`define OR1200_FPCSR_UNF   4
-`define OR1200_FPCSR_SNF   5
-`define OR1200_FPCSR_QNF   6
-`define OR1200_FPCSR_ZF    7
-`define OR1200_FPCSR_IXF   8
-`define OR1200_FPCSR_IVF   9
-`define OR1200_FPCSR_INF   10
-`define OR1200_FPCSR_DZF   11
-`define OR1200_FPCSR_RES   31:12
-
-/////////////////////////////////////////////////////
-//
-// Power Management (PM)
-//
-
-// Define it if you want PM implemented
-//`define OR1200_PM_IMPLEMENTED
-
-// Bit positions inside PMR (don't change)
-`define OR1200_PM_PMR_SDF 3:0
-`define OR1200_PM_PMR_DME 4
-`define OR1200_PM_PMR_SME 5
-`define OR1200_PM_PMR_DCGE 6
-`define OR1200_PM_PMR_UNUSED 31:7
-
-// PMR offset inside PM group of registers
-`define OR1200_PM_OFS_PMR 11'b0
-
-// PM group
-`define OR1200_SPRGRP_PM 5'd8
-
-// Define if PMR can be read/written at any address inside PM group
-`define OR1200_PM_PARTIAL_DECODING
-
-// Define if reading PMR is allowed
-`define OR1200_PM_READREGS
-
-// Define if unused PMR bits should be zero
-`define OR1200_PM_UNUSED_ZERO
-
-
-/////////////////////////////////////////////////////
-//
-// Debug Unit (DU)
-//
-
-// Define it if you want DU implemented
-`define OR1200_DU_IMPLEMENTED
-
-//
-// Define if you want HW Breakpoints
-// (if HW breakpoints are not implemented
-// only default software trapping is
-// possible with l.trap insn - this is
-// however already enough for use
-// with or32 gdb)
-//
-//`define OR1200_DU_HWBKPTS
-
-// Number of DVR/DCR pairs if HW breakpoints enabled
-//	Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
-//	DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
-`define OR1200_DU_DVRDCR_PAIRS 8
-
-// Define if you want trace buffer
-//	(for now only available for Xilinx Virtex FPGAs)
-//`define OR1200_DU_TB_IMPLEMENTED
-
-
-//
-// Address offsets of DU registers inside DU group
-//
-// To not implement a register, doq not define its address
-//
-`ifdef OR1200_DU_HWBKPTS
-`define OR1200_DU_DVR0		11'd0
-`define OR1200_DU_DVR1		11'd1
-`define OR1200_DU_DVR2		11'd2
-`define OR1200_DU_DVR3		11'd3
-`define OR1200_DU_DVR4		11'd4
-`define OR1200_DU_DVR5		11'd5
-`define OR1200_DU_DVR6		11'd6
-`define OR1200_DU_DVR7		11'd7
-`define OR1200_DU_DCR0		11'd8
-`define OR1200_DU_DCR1		11'd9
-`define OR1200_DU_DCR2		11'd10
-`define OR1200_DU_DCR3		11'd11
-`define OR1200_DU_DCR4		11'd12
-`define OR1200_DU_DCR5		11'd13
-`define OR1200_DU_DCR6		11'd14
-`define OR1200_DU_DCR7		11'd15
-`endif
-`define OR1200_DU_DMR1		11'd16
-`ifdef OR1200_DU_HWBKPTS
-`define OR1200_DU_DMR2		11'd17
-`define OR1200_DU_DWCR0		11'd18
-`define OR1200_DU_DWCR1		11'd19
-`endif
-`define OR1200_DU_DSR		11'd20
-`define OR1200_DU_DRR		11'd21
-`ifdef OR1200_DU_TB_IMPLEMENTED
-`define OR1200_DU_TBADR		11'h0ff
-`define OR1200_DU_TBIA		11'h1??
-`define OR1200_DU_TBIM		11'h2??
-`define OR1200_DU_TBAR		11'h3??
-`define OR1200_DU_TBTS		11'h4??
-`endif
-
-// Position of offset bits inside SPR address
-`define OR1200_DUOFS_BITS	10:0
-
-// DCR bits
-`define OR1200_DU_DCR_DP	0
-`define OR1200_DU_DCR_CC	3:1
-`define OR1200_DU_DCR_SC	4
-`define OR1200_DU_DCR_CT	7:5
-
-// DMR1 bits
-`define OR1200_DU_DMR1_CW0	1:0
-`define OR1200_DU_DMR1_CW1	3:2
-`define OR1200_DU_DMR1_CW2	5:4
-`define OR1200_DU_DMR1_CW3	7:6
-`define OR1200_DU_DMR1_CW4	9:8
-`define OR1200_DU_DMR1_CW5	11:10
-`define OR1200_DU_DMR1_CW6	13:12
-`define OR1200_DU_DMR1_CW7	15:14
-`define OR1200_DU_DMR1_CW8	17:16
-`define OR1200_DU_DMR1_CW9	19:18
-`define OR1200_DU_DMR1_CW10	21:20
-`define OR1200_DU_DMR1_ST	22
-`define OR1200_DU_DMR1_BT	23
-`define OR1200_DU_DMR1_DXFW	24
-`define OR1200_DU_DMR1_ETE	25
-
-// DMR2 bits
-`define OR1200_DU_DMR2_WCE0	0
-`define OR1200_DU_DMR2_WCE1	1
-`define OR1200_DU_DMR2_AWTC	12:2
-`define OR1200_DU_DMR2_WGB	23:13
-
-// DWCR bits
-`define OR1200_DU_DWCR_COUNT	15:0
-`define OR1200_DU_DWCR_MATCH	31:16
-
-// DSR bits
-`define OR1200_DU_DSR_WIDTH	14
-`define OR1200_DU_DSR_RSTE	0
-`define OR1200_DU_DSR_BUSEE	1
-`define OR1200_DU_DSR_DPFE	2
-`define OR1200_DU_DSR_IPFE	3
-`define OR1200_DU_DSR_TTE	4
-`define OR1200_DU_DSR_AE	5
-`define OR1200_DU_DSR_IIE	6
-`define OR1200_DU_DSR_IE	7
-`define OR1200_DU_DSR_DME	8
-`define OR1200_DU_DSR_IME	9
-`define OR1200_DU_DSR_RE	10
-`define OR1200_DU_DSR_SCE	11
-`define OR1200_DU_DSR_FPE	12
-`define OR1200_DU_DSR_TE	13
-
-// DRR bits
-`define OR1200_DU_DRR_RSTE	0
-`define OR1200_DU_DRR_BUSEE	1
-`define OR1200_DU_DRR_DPFE	2
-`define OR1200_DU_DRR_IPFE	3
-`define OR1200_DU_DRR_TTE	4
-`define OR1200_DU_DRR_AE	5
-`define OR1200_DU_DRR_IIE	6
-`define OR1200_DU_DRR_IE	7
-`define OR1200_DU_DRR_DME	8
-`define OR1200_DU_DRR_IME	9
-`define OR1200_DU_DRR_RE	10
-`define OR1200_DU_DRR_SCE	11
-`define OR1200_DU_DRR_FPE	12
-`define OR1200_DU_DRR_TE	13
-
-// Define if reading DU regs is allowed
-`define OR1200_DU_READREGS
-
-// Define if unused DU registers bits should be zero
-`define OR1200_DU_UNUSED_ZERO
-
-// Define if IF/LSU status is not needed by devel i/f
-`define OR1200_DU_STATUS_UNIMPLEMENTED
-
-/////////////////////////////////////////////////////
-//
-// Programmable Interrupt Controller (PIC)
-//
-
-// Define it if you want PIC implemented
-`define OR1200_PIC_IMPLEMENTED
-
-// Define number of interrupt inputs (2-31)
-`define OR1200_PIC_INTS 20
-
-// Address offsets of PIC registers inside PIC group
-`define OR1200_PIC_OFS_PICMR 2'd0
-`define OR1200_PIC_OFS_PICSR 2'd2
-
-// Position of offset bits inside SPR address
-`define OR1200_PICOFS_BITS 1:0
-
-// Define if you want these PIC registers to be implemented
-`define OR1200_PIC_PICMR
-`define OR1200_PIC_PICSR
-
-// Define if reading PIC registers is allowed
-`define OR1200_PIC_READREGS
-
-// Define if unused PIC register bits should be zero
-`define OR1200_PIC_UNUSED_ZERO
-
-
-/////////////////////////////////////////////////////
-//
-// Tick Timer (TT)
-//
-
-// Define it if you want TT implemented
-`define OR1200_TT_IMPLEMENTED
-
-// Address offsets of TT registers inside TT group
-`define OR1200_TT_OFS_TTMR 1'd0
-`define OR1200_TT_OFS_TTCR 1'd1
-
-// Position of offset bits inside SPR group
-`define OR1200_TTOFS_BITS 0
-
-// Define if you want these TT registers to be implemented
-`define OR1200_TT_TTMR
-`define OR1200_TT_TTCR
-
-// TTMR bits
-`define OR1200_TT_TTMR_TP 27:0
-`define OR1200_TT_TTMR_IP 28
-`define OR1200_TT_TTMR_IE 29
-`define OR1200_TT_TTMR_M 31:30
-
-// Define if reading TT registers is allowed
-`define OR1200_TT_READREGS
-
-
-//////////////////////////////////////////////
-//
-// MAC
-//
-`define OR1200_MAC_ADDR		0	// MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
-`define OR1200_MAC_SPR_WE		// Define if MACLO/MACHI are SPR writable
-
-//
-// Shift {MACHI,MACLO} into destination register when executing l.macrc
-//
-// According to architecture manual there is no shift, so default value is 0.
-// However the implementation has deviated in this from the arch manual and had
-// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
-// (if using libmad fixed point library). Shifts are no longer default setup, 
-// but if you need to remain backward compatible, define your shift bits, which
-// were normally
-// dest_GPR = {MACHI,MACLO}[59:28]
-`define OR1200_MAC_SHIFTBY	0	// 0 = According to arch manual, 28 = obsolete backward compatibility
-
-
-//////////////////////////////////////////////
-//
-// Data MMU (DMMU)
-//
-
-//
-// Address that selects between TLB TR and MR
-//
-`define OR1200_DTLB_TM_ADDR	7
-
-//
-// DTLBMR fields
-//
-`define	OR1200_DTLBMR_V_BITS	0
-`define	OR1200_DTLBMR_CID_BITS	4:1
-`define	OR1200_DTLBMR_RES_BITS	11:5
-`define OR1200_DTLBMR_VPN_BITS	31:13
-
-//
-// DTLBTR fields
-//
-`define	OR1200_DTLBTR_CC_BITS	0
-`define	OR1200_DTLBTR_CI_BITS	1
-`define	OR1200_DTLBTR_WBC_BITS	2
-`define	OR1200_DTLBTR_WOM_BITS	3
-`define	OR1200_DTLBTR_A_BITS	4
-`define	OR1200_DTLBTR_D_BITS	5
-`define	OR1200_DTLBTR_URE_BITS	6
-`define	OR1200_DTLBTR_UWE_BITS	7
-`define	OR1200_DTLBTR_SRE_BITS	8
-`define	OR1200_DTLBTR_SWE_BITS	9
-`define	OR1200_DTLBTR_RES_BITS	11:10
-`define OR1200_DTLBTR_PPN_BITS	31:13
-
-//
-// DTLB configuration
-//
-`define	OR1200_DMMU_PS		13					// 13 for 8KB page size
-`define	OR1200_DTLB_INDXW	6					// 6 for 64 entry DTLB	7 for 128 entries
-`define OR1200_DTLB_INDXL	`OR1200_DMMU_PS				// 13			13
-`define OR1200_DTLB_INDXH	`OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1	// 18			19
-`define	OR1200_DTLB_INDX	`OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL	// 18:13		19:13
-`define OR1200_DTLB_TAGW	32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS	// 13			12
-`define OR1200_DTLB_TAGL	`OR1200_DTLB_INDXH+1			// 19			20
-`define	OR1200_DTLB_TAG		31:`OR1200_DTLB_TAGL			// 31:19		31:20
-`define	OR1200_DTLBMRW		`OR1200_DTLB_TAGW+1			// +1 because of V bit
-`define	OR1200_DTLBTRW		32-`OR1200_DMMU_PS+5			// +5 because of protection bits and CI
-
-//
-// Cache inhibit while DMMU is not enabled/implemented
-//
-// cache inhibited 0GB-4GB		1'b1
-// cache inhibited 0GB-2GB		!dcpu_adr_i[31]
-// cache inhibited 0GB-1GB 2GB-3GB	!dcpu_adr_i[30]
-// cache inhibited 1GB-2GB 3GB-4GB	dcpu_adr_i[30]
-// cache inhibited 2GB-4GB (default)	dcpu_adr_i[31]
-// cached 0GB-4GB			1'b0
-//
-`define OR1200_DMMU_CI			dcpu_adr_i[31]
-
-
-//////////////////////////////////////////////
-//
-// Insn MMU (IMMU)
-//
-
-//
-// Address that selects between TLB TR and MR
-//
-`define OR1200_ITLB_TM_ADDR	7
-
-//
-// ITLBMR fields
-//
-`define	OR1200_ITLBMR_V_BITS	0
-`define	OR1200_ITLBMR_CID_BITS	4:1
-`define	OR1200_ITLBMR_RES_BITS	11:5
-`define OR1200_ITLBMR_VPN_BITS	31:13
-
-//
-// ITLBTR fields
-//
-`define	OR1200_ITLBTR_CC_BITS	0
-`define	OR1200_ITLBTR_CI_BITS	1
-`define	OR1200_ITLBTR_WBC_BITS	2
-`define	OR1200_ITLBTR_WOM_BITS	3
-`define	OR1200_ITLBTR_A_BITS	4
-`define	OR1200_ITLBTR_D_BITS	5
-`define	OR1200_ITLBTR_SXE_BITS	6
-`define	OR1200_ITLBTR_UXE_BITS	7
-`define	OR1200_ITLBTR_RES_BITS	11:8
-`define OR1200_ITLBTR_PPN_BITS	31:13
-
-//
-// ITLB configuration
-//
-`define	OR1200_IMMU_PS		13					// 13 for 8KB page size
-`define	OR1200_ITLB_INDXW	6					// 6 for 64 entry ITLB	7 for 128 entries
-`define OR1200_ITLB_INDXL	`OR1200_IMMU_PS				// 13			13
-`define OR1200_ITLB_INDXH	`OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1	// 18			19
-`define	OR1200_ITLB_INDX	`OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL	// 18:13		19:13
-`define OR1200_ITLB_TAGW	32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS	// 13			12
-`define OR1200_ITLB_TAGL	`OR1200_ITLB_INDXH+1			// 19			20
-`define	OR1200_ITLB_TAG		31:`OR1200_ITLB_TAGL			// 31:19		31:20
-`define	OR1200_ITLBMRW		`OR1200_ITLB_TAGW+1			// +1 because of V bit
-`define	OR1200_ITLBTRW		32-`OR1200_IMMU_PS+3			// +3 because of protection bits and CI
-
-//
-// Cache inhibit while IMMU is not enabled/implemented
-// Note: all combinations that use icpu_adr_i cause async loop
-//
-// cache inhibited 0GB-4GB		1'b1
-// cache inhibited 0GB-2GB		!icpu_adr_i[31]
-// cache inhibited 0GB-1GB 2GB-3GB	!icpu_adr_i[30]
-// cache inhibited 1GB-2GB 3GB-4GB	icpu_adr_i[30]
-// cache inhibited 2GB-4GB (default)	icpu_adr_i[31]
-// cached 0GB-4GB			1'b0
-//
-`define OR1200_IMMU_CI			1'b0
-
-
-/////////////////////////////////////////////////
-//
-// Insn cache (IC)
-//
-
-// 4 for 16 byte line, 5 for 32 byte lines.
-`ifdef OR1200_IC_1W_32KB
- `define OR1200_ICLS		5
-`else
- `define OR1200_ICLS		4
-`endif
-
-//
-// IC configurations
-//
-`ifdef OR1200_IC_1W_512B
-`define OR1200_ICSIZE                   9                       // 512
-`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 7
-`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 8
-`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 9
-`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS // 5
-`define OR1200_ICTAG_W                  24
-`endif
-`ifdef OR1200_IC_1W_4KB
-`define OR1200_ICSIZE			12			// 4096
-`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 10
-`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 11
-`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 12
-`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 8
-`define	OR1200_ICTAG_W			21
-`endif
-`ifdef OR1200_IC_1W_8KB
-`define OR1200_ICSIZE			13			// 8192
-`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 11
-`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 12
-`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 13
-`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 9
-`define	OR1200_ICTAG_W			20
-`endif
-`ifdef OR1200_IC_1W_16KB
-`define OR1200_ICSIZE			14			// 16384
-`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 12
-`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 13
-`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 14
-`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 10
-`define	OR1200_ICTAG_W			19
-`endif
-`ifdef OR1200_IC_1W_32KB
-`define OR1200_ICSIZE			15			// 32768
-`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 13
-`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 14
-`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 14
-`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 10
-`define	OR1200_ICTAG_W			18
-`endif
-
-
-/////////////////////////////////////////////////
-//
-// Data cache (DC)
-//
-
-// 4 for 16 bytes, 5 for 32 bytes
-`ifdef OR1200_DC_1W_32KB
- `define OR1200_DCLS		5
-`else
- `define OR1200_DCLS		4
-`endif
-
-// Define to enable default behavior of cache as write through
-// Turning this off enabled write back statergy
-//
-`define OR1200_DC_WRITETHROUGH
-
-// Define to enable stores from the stack not doing writethrough.
-// EXPERIMENTAL
-//`define OR1200_DC_NOSTACKWRITETHROUGH
-
-// Data cache SPR definitions
-`define OR1200_SPRGRP_DC_ADR_WIDTH 3
-// Data cache group SPR addresses
-`define OR1200_SPRGRP_DC_DCCR		3'd0 // Not implemented
-`define OR1200_SPRGRP_DC_DCBPR		3'd1 // Not implemented
-`define OR1200_SPRGRP_DC_DCBFR		3'd2
-`define OR1200_SPRGRP_DC_DCBIR		3'd3
-`define OR1200_SPRGRP_DC_DCBWR		3'd4 // Not implemented
-`define OR1200_SPRGRP_DC_DCBLR		3'd5 // Not implemented
-
-//
-// DC configurations
-//
-`ifdef OR1200_DC_1W_4KB
-`define OR1200_DCSIZE			12			// 4096
-`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 10
-`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 11
-`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 12
-`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 8
-`define	OR1200_DCTAG_W			21
-`endif
-`ifdef OR1200_DC_1W_8KB
-`define OR1200_DCSIZE			13			// 8192
-`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 11
-`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 12
-`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 13
-`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 9
-`define	OR1200_DCTAG_W			20
-`endif
-`ifdef OR1200_DC_1W_16KB
-`define OR1200_DCSIZE			14			// 16384
-`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 12
-`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 13
-`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 14
-`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 10
-`define	OR1200_DCTAG_W			19
-`endif
-`ifdef OR1200_DC_1W_32KB
-`define OR1200_DCSIZE			15			// 32768
-`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 13
-`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 14
-`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 15
-`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 10
-`define	OR1200_DCTAG_W			18
-`endif
-
-
-/////////////////////////////////////////////////
-//
-// Store buffer (SB)
-//
-
-//
-// Store buffer
-//
-// It will improve performance by "caching" CPU stores
-// using store buffer. This is most important for function
-// prologues because DC can only work in write though mode
-// and all stores would have to complete external WB writes
-// to memory.
-// Store buffer is between DC and data BIU.
-// All stores will be stored into store buffer and immediately
-// completed by the CPU, even though actual external writes
-// will be performed later. As a consequence store buffer masks
-// all data bus errors related to stores (data bus errors
-// related to loads are delivered normally).
-// All pending CPU loads will wait until store buffer is empty to
-// ensure strict memory model. Right now this is necessary because
-// we don't make destinction between cached and cache inhibited
-// address space, so we simply empty store buffer until loads
-// can begin.
-//
-// It makes design a bit bigger, depending what is the number of
-// entries in SB FIFO. Number of entries can be changed further
-// down.
-//
-//`define OR1200_SB_IMPLEMENTED
-
-//
-// Number of store buffer entries
-//
-// Verified number of entries are 4 and 8 entries
-// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
-// always match 2**OR1200_SB_LOG.
-// To disable store buffer, undefine
-// OR1200_SB_IMPLEMENTED.
-//
-`define OR1200_SB_LOG		2	// 2 or 3
-`define OR1200_SB_ENTRIES	4	// 4 or 8
-
-
-/////////////////////////////////////////////////
-//
-// Quick Embedded Memory (QMEM)
-//
-
-//
-// Quick Embedded Memory
-//
-// Instantiation of dedicated insn/data memory (RAM or ROM).
-// Insn fetch has effective throughput 1insn / clock cycle.
-// Data load takes two clock cycles / access, data store
-// takes 1 clock cycle / access (if there is no insn fetch)).
-// Memory instantiation is shared between insn and data,
-// meaning if insn fetch are performed, data load/store
-// performance will be lower.
-//
-// Main reason for QMEM is to put some time critical functions
-// into this memory and to have predictable and fast access
-// to these functions. (soft fpu, context switch, exception
-// handlers, stack, etc)
-//
-// It makes design a bit bigger and slower. QMEM sits behind
-// IMMU/DMMU so all addresses are physical (so the MMUs can be
-// used with QMEM and QMEM is seen by the CPU just like any other
-// memory in the system). IC/DC are sitting behind QMEM so the
-// whole design timing might be worse with QMEM implemented.
-//
-//`define OR1200_QMEM_IMPLEMENTED
-
-//
-// Base address and mask of QMEM
-//
-// Base address defines first address of QMEM. Mask defines
-// QMEM range in address space. Actual size of QMEM is however
-// determined with instantiated RAM/ROM. However bigger
-// mask will reserve more address space for QMEM, but also
-// make design faster, while more tight mask will take
-// less address space but also make design slower. If
-// instantiated RAM/ROM is smaller than space reserved with
-// the mask, instatiated RAM/ROM will also be shadowed
-// at higher addresses in reserved space.
-//
-`define OR1200_QMEM_IADDR	32'h0080_0000
-`define OR1200_QMEM_IMASK	32'hfff0_0000 // Max QMEM size 1MB
-`define OR1200_QMEM_DADDR	32'h0080_0000
-`define OR1200_QMEM_DMASK	32'hfff0_0000 // Max QMEM size 1MB
-
-//
-// QMEM interface byte-select capability
-//
-// To enable qmem_sel* ports, define this macro.
-//
-//`define OR1200_QMEM_BSEL
-
-//
-// QMEM interface acknowledge
-//
-// To enable qmem_ack port, define this macro.
-//
-//`define OR1200_QMEM_ACK
-
-/////////////////////////////////////////////////////
-//
-// VR, UPR and Configuration Registers
-//
-//
-// VR, UPR and configuration registers are optional. If 
-// implemented, operating system can automatically figure
-// out how to use the processor because it knows 
-// what units are available in the processor and how they
-// are configured.
-//
-// This section must be last in or1200_defines.v file so
-// that all units are already configured and thus
-// configuration registers are properly set.
-// 
-
-// Define if you want configuration registers implemented
-`define OR1200_CFGR_IMPLEMENTED
-
-// Define if you want full address decode inside SYS group
-`define OR1200_SYS_FULL_DECODE
-
-// Offsets of VR, UPR and CFGR registers
-`define OR1200_SPRGRP_SYS_VR		4'h0
-`define OR1200_SPRGRP_SYS_UPR		4'h1
-`define OR1200_SPRGRP_SYS_CPUCFGR	4'h2
-`define OR1200_SPRGRP_SYS_DMMUCFGR	4'h3
-`define OR1200_SPRGRP_SYS_IMMUCFGR	4'h4
-`define OR1200_SPRGRP_SYS_DCCFGR	4'h5
-`define OR1200_SPRGRP_SYS_ICCFGR	4'h6
-`define OR1200_SPRGRP_SYS_DCFGR	4'h7
-
-// VR fields
-`define OR1200_VR_REV_BITS		5:0
-`define OR1200_VR_RES1_BITS		15:6
-`define OR1200_VR_CFG_BITS		23:16
-`define OR1200_VR_VER_BITS		31:24
-
-// VR values
-`define OR1200_VR_REV			6'h08
-`define OR1200_VR_RES1			10'h000
-`define OR1200_VR_CFG			8'h00
-`define OR1200_VR_VER			8'h12
-
-// UPR fields
-`define OR1200_UPR_UP_BITS		0
-`define OR1200_UPR_DCP_BITS		1
-`define OR1200_UPR_ICP_BITS		2
-`define OR1200_UPR_DMP_BITS		3
-`define OR1200_UPR_IMP_BITS		4
-`define OR1200_UPR_MP_BITS		5
-`define OR1200_UPR_DUP_BITS		6
-`define OR1200_UPR_PCUP_BITS		7
-`define OR1200_UPR_PMP_BITS		8
-`define OR1200_UPR_PICP_BITS		9
-`define OR1200_UPR_TTP_BITS		10
-`define OR1200_UPR_FPP_BITS		11
-`define OR1200_UPR_RES1_BITS		23:12
-`define OR1200_UPR_CUP_BITS		31:24
-
-// UPR values
-`define OR1200_UPR_UP			1'b1
-`ifdef OR1200_NO_DC
-`define OR1200_UPR_DCP			1'b0
-`else
-`define OR1200_UPR_DCP			1'b1
-`endif
-`ifdef OR1200_NO_IC
-`define OR1200_UPR_ICP			1'b0
-`else
-`define OR1200_UPR_ICP			1'b1
-`endif
-`ifdef OR1200_NO_DMMU
-`define OR1200_UPR_DMP			1'b0
-`else
-`define OR1200_UPR_DMP			1'b1
-`endif
-`ifdef OR1200_NO_IMMU
-`define OR1200_UPR_IMP			1'b0
-`else
-`define OR1200_UPR_IMP			1'b1
-`endif
-`ifdef OR1200_MAC_IMPLEMENTED
-`define OR1200_UPR_MP			1'b1
-`else
-`define OR1200_UPR_MP			1'b0
-`endif
-`ifdef OR1200_DU_IMPLEMENTED
-`define OR1200_UPR_DUP			1'b1
-`else
-`define OR1200_UPR_DUP			1'b0
-`endif
-`define OR1200_UPR_PCUP			1'b0	// Performance counters not present
-`ifdef OR1200_PM_IMPLEMENTED
-`define OR1200_UPR_PMP			1'b1
-`else
-`define OR1200_UPR_PMP			1'b0
-`endif
-`ifdef OR1200_PIC_IMPLEMENTED
-`define OR1200_UPR_PICP			1'b1
-`else
-`define OR1200_UPR_PICP			1'b0
-`endif
-`ifdef OR1200_TT_IMPLEMENTED
-`define OR1200_UPR_TTP			1'b1
-`else
-`define OR1200_UPR_TTP			1'b0
-`endif
-`ifdef OR1200_FPU_IMPLEMENTED
-`define OR1200_UPR_FPP			1'b1
-`else
-`define OR1200_UPR_FPP			1'b0
-`endif
-`define OR1200_UPR_RES1			12'h000
-`define OR1200_UPR_CUP			8'h00
-
-// CPUCFGR fields
-`define OR1200_CPUCFGR_NSGF_BITS	3:0
-`define OR1200_CPUCFGR_HGF_BITS     4
-`define OR1200_CPUCFGR_OB32S_BITS	5
-`define OR1200_CPUCFGR_OB64S_BITS	6
-`define OR1200_CPUCFGR_OF32S_BITS	7
-`define OR1200_CPUCFGR_OF64S_BITS	8
-`define OR1200_CPUCFGR_OV64S_BITS	9
-`define OR1200_CPUCFGR_RES1_BITS	31:10
-
-// CPUCFGR values
-`define OR1200_CPUCFGR_NSGF		    4'h0
-`ifdef OR1200_RFRAM_16REG
-    `define OR1200_CPUCFGR_HGF  		1'b1
-`else
-    `define OR1200_CPUCFGR_HGF  		1'b0
-`endif
-`define OR1200_CPUCFGR_OB32S		1'b1
-`define OR1200_CPUCFGR_OB64S		1'b0
-`ifdef OR1200_FPU_IMPLEMENTED
- `define OR1200_CPUCFGR_OF32S		1'b1
-`else
- `define OR1200_CPUCFGR_OF32S		1'b0
-`endif
-
-`define OR1200_CPUCFGR_OF64S		1'b0
-`define OR1200_CPUCFGR_OV64S		1'b0
-`define OR1200_CPUCFGR_RES1		22'h000000
-
-// DMMUCFGR fields
-`define OR1200_DMMUCFGR_NTW_BITS	1:0
-`define OR1200_DMMUCFGR_NTS_BITS	4:2
-`define OR1200_DMMUCFGR_NAE_BITS	7:5
-`define OR1200_DMMUCFGR_CRI_BITS	8
-`define OR1200_DMMUCFGR_PRI_BITS	9
-`define OR1200_DMMUCFGR_TEIRI_BITS	10
-`define OR1200_DMMUCFGR_HTR_BITS	11
-`define OR1200_DMMUCFGR_RES1_BITS	31:12
-
-// DMMUCFGR values
-`ifdef OR1200_NO_DMMU
-`define OR1200_DMMUCFGR_NTW		2'h0	// Irrelevant
-`define OR1200_DMMUCFGR_NTS		3'h0	// Irrelevant
-`define OR1200_DMMUCFGR_NAE		3'h0	// Irrelevant
-`define OR1200_DMMUCFGR_CRI		1'b0	// Irrelevant
-`define OR1200_DMMUCFGR_PRI		1'b0	// Irrelevant
-`define OR1200_DMMUCFGR_TEIRI		1'b0	// Irrelevant
-`define OR1200_DMMUCFGR_HTR		1'b0	// Irrelevant
-`define OR1200_DMMUCFGR_RES1		20'h00000
-`else
-`define OR1200_DMMUCFGR_NTW		2'h0	// 1 TLB way
-`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW	// Num TLB sets
-`define OR1200_DMMUCFGR_NAE		3'h0	// No ATB entries
-`define OR1200_DMMUCFGR_CRI		1'b0	// No control register
-`define OR1200_DMMUCFGR_PRI		1'b0	// No protection reg
-`define OR1200_DMMUCFGR_TEIRI		1'b0	// TLB entry inv reg NOT impl.
-`define OR1200_DMMUCFGR_HTR		1'b0	// No HW TLB reload
-`define OR1200_DMMUCFGR_RES1		20'h00000
-`endif
-
-// IMMUCFGR fields
-`define OR1200_IMMUCFGR_NTW_BITS	1:0
-`define OR1200_IMMUCFGR_NTS_BITS	4:2
-`define OR1200_IMMUCFGR_NAE_BITS	7:5
-`define OR1200_IMMUCFGR_CRI_BITS	8
-`define OR1200_IMMUCFGR_PRI_BITS	9
-`define OR1200_IMMUCFGR_TEIRI_BITS	10
-`define OR1200_IMMUCFGR_HTR_BITS	11
-`define OR1200_IMMUCFGR_RES1_BITS	31:12
-
-// IMMUCFGR values
-`ifdef OR1200_NO_IMMU
-`define OR1200_IMMUCFGR_NTW		2'h0	// Irrelevant
-`define OR1200_IMMUCFGR_NTS		3'h0	// Irrelevant
-`define OR1200_IMMUCFGR_NAE		3'h0	// Irrelevant
-`define OR1200_IMMUCFGR_CRI		1'b0	// Irrelevant
-`define OR1200_IMMUCFGR_PRI		1'b0	// Irrelevant
-`define OR1200_IMMUCFGR_TEIRI		1'b0	// Irrelevant
-`define OR1200_IMMUCFGR_HTR		1'b0	// Irrelevant
-`define OR1200_IMMUCFGR_RES1		20'h00000
-`else
-`define OR1200_IMMUCFGR_NTW		2'h0	// 1 TLB way
-`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW	// Num TLB sets
-`define OR1200_IMMUCFGR_NAE		3'h0	// No ATB entry
-`define OR1200_IMMUCFGR_CRI		1'b0	// No control reg
-`define OR1200_IMMUCFGR_PRI		1'b0	// No protection reg
-`define OR1200_IMMUCFGR_TEIRI		1'b0	// TLB entry inv reg NOT impl
-`define OR1200_IMMUCFGR_HTR		1'b0	// No HW TLB reload
-`define OR1200_IMMUCFGR_RES1		20'h00000
-`endif
-
-// DCCFGR fields
-`define OR1200_DCCFGR_NCW_BITS		2:0
-`define OR1200_DCCFGR_NCS_BITS		6:3
-`define OR1200_DCCFGR_CBS_BITS		7
-`define OR1200_DCCFGR_CWS_BITS		8
-`define OR1200_DCCFGR_CCRI_BITS		9
-`define OR1200_DCCFGR_CBIRI_BITS	10
-`define OR1200_DCCFGR_CBPRI_BITS	11
-`define OR1200_DCCFGR_CBLRI_BITS	12
-`define OR1200_DCCFGR_CBFRI_BITS	13
-`define OR1200_DCCFGR_CBWBRI_BITS	14
-`define OR1200_DCCFGR_RES1_BITS	31:15
-
-// DCCFGR values
-`ifdef OR1200_NO_DC
-`define OR1200_DCCFGR_NCW		3'h0	// Irrelevant
-`define OR1200_DCCFGR_NCS		4'h0	// Irrelevant
-`define OR1200_DCCFGR_CBS		1'b0	// Irrelevant
-`define OR1200_DCCFGR_CWS		1'b0	// Irrelevant
-`define OR1200_DCCFGR_CCRI		1'b0	// Irrelevant
-`define OR1200_DCCFGR_CBIRI		1'b0	// Irrelevant
-`define OR1200_DCCFGR_CBPRI		1'b0	// Irrelevant
-`define OR1200_DCCFGR_CBLRI		1'b0	// Irrelevant
-`define OR1200_DCCFGR_CBFRI		1'b0	// Irrelevant
-`define OR1200_DCCFGR_CBWBRI		1'b0	// Irrelevant
-`define OR1200_DCCFGR_RES1		17'h00000
-`else
-`define OR1200_DCCFGR_NCW		3'h0	// 1 cache way
-`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)	// Num cache sets
-`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
-`ifdef OR1200_DC_WRITETHROUGH
- `define OR1200_DCCFGR_CWS		1'b0	// Write-through strategy
-`else
- `define OR1200_DCCFGR_CWS		1'b1	// Write-back strategy
-`endif
-`define OR1200_DCCFGR_CCRI		1'b1	// Cache control reg impl.
-`define OR1200_DCCFGR_CBIRI		1'b1	// Cache block inv reg impl.
-`define OR1200_DCCFGR_CBPRI		1'b0	// Cache block prefetch reg not impl.
-`define OR1200_DCCFGR_CBLRI		1'b0	// Cache block lock reg not impl.
-`define OR1200_DCCFGR_CBFRI		1'b1	// Cache block flush reg impl.
-`ifdef OR1200_DC_WRITETHROUGH
- `define OR1200_DCCFGR_CBWBRI		1'b0	// Cache block WB reg not impl.
-`else
- `define OR1200_DCCFGR_CBWBRI		1'b1	// Cache block WB reg impl.
-`endif
-`define OR1200_DCCFGR_RES1		17'h00000
-`endif
-
-// ICCFGR fields
-`define OR1200_ICCFGR_NCW_BITS		2:0
-`define OR1200_ICCFGR_NCS_BITS		6:3
-`define OR1200_ICCFGR_CBS_BITS		7
-`define OR1200_ICCFGR_CWS_BITS		8
-`define OR1200_ICCFGR_CCRI_BITS		9
-`define OR1200_ICCFGR_CBIRI_BITS	10
-`define OR1200_ICCFGR_CBPRI_BITS	11
-`define OR1200_ICCFGR_CBLRI_BITS	12
-`define OR1200_ICCFGR_CBFRI_BITS	13
-`define OR1200_ICCFGR_CBWBRI_BITS	14
-`define OR1200_ICCFGR_RES1_BITS	31:15
-
-// ICCFGR values
-`ifdef OR1200_NO_IC
-`define OR1200_ICCFGR_NCW		3'h0	// Irrelevant
-`define OR1200_ICCFGR_NCS 		4'h0	// Irrelevant
-`define OR1200_ICCFGR_CBS 		1'b0	// Irrelevant
-`define OR1200_ICCFGR_CWS		1'b0	// Irrelevant
-`define OR1200_ICCFGR_CCRI		1'b0	// Irrelevant
-`define OR1200_ICCFGR_CBIRI		1'b0	// Irrelevant
-`define OR1200_ICCFGR_CBPRI		1'b0	// Irrelevant
-`define OR1200_ICCFGR_CBLRI		1'b0	// Irrelevant
-`define OR1200_ICCFGR_CBFRI		1'b0	// Irrelevant
-`define OR1200_ICCFGR_CBWBRI		1'b0	// Irrelevant
-`define OR1200_ICCFGR_RES1		17'h00000
-`else
-`define OR1200_ICCFGR_NCW		3'h0	// 1 cache way
-`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)	// Num cache sets
-`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1	// 16 byte cache block
-`define OR1200_ICCFGR_CWS		1'b0	// Irrelevant
-`define OR1200_ICCFGR_CCRI		1'b1	// Cache control reg impl.
-`define OR1200_ICCFGR_CBIRI		1'b1	// Cache block inv reg impl.
-`define OR1200_ICCFGR_CBPRI		1'b0	// Cache block prefetch reg not impl.
-`define OR1200_ICCFGR_CBLRI		1'b0	// Cache block lock reg not impl.
-`define OR1200_ICCFGR_CBFRI		1'b1	// Cache block flush reg impl.
-`define OR1200_ICCFGR_CBWBRI		1'b0	// Irrelevant
-`define OR1200_ICCFGR_RES1		17'h00000
-`endif
-
-// DCFGR fields
-`define OR1200_DCFGR_NDP_BITS		3:0
-`define OR1200_DCFGR_WPCI_BITS		4
-`define OR1200_DCFGR_RES1_BITS		31:5
-
-// DCFGR values
-`ifdef OR1200_DU_HWBKPTS
-`define OR1200_DCFGR_NDP		4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
-`ifdef OR1200_DU_DWCR0
-`define OR1200_DCFGR_WPCI		1'b1
-`else
-`define OR1200_DCFGR_WPCI		1'b0	// WP counters not impl.
-`endif
-`else
-`define OR1200_DCFGR_NDP		4'h0	// Zero DVR/DCR pairs
-`define OR1200_DCFGR_WPCI		1'b0	// WP counters not impl.
-`endif
-`define OR1200_DCFGR_RES1		27'd0
-
-///////////////////////////////////////////////////////////////////////////////
-// Boot Address Selection                                                    //
-//                                                                           //
-// Allows a definable boot address, potentially different to the usual reset //
-// vector to allow for power-on code to be run, if desired.                  //
-//                                                                           //
-// OR1200_BOOT_ADR should be the 32-bit address of the boot location         //
-// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2)              //
-//                                                                           //
-// For default reset behavior uncomment the settings under the "Boot 0x100"  //
-// comment below.                                                            //
-//                                                                           //
-///////////////////////////////////////////////////////////////////////////////
-// Boot from 0xf0000100
-//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
-//`define OR1200_BOOT_ADR 32'hf0000100
-// Boot from 0x100
- `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
- `define OR1200_BOOT_ADR 32'h00000100
diff --git a/systems/generic/rtl/verilog/include/orpsoc-defines.v b/systems/generic/rtl/verilog/include/orpsoc-defines.v
deleted file mode 100644
index 57c5c497..00000000
--- a/systems/generic/rtl/verilog/include/orpsoc-defines.v
+++ /dev/null
@@ -1,42 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// orpsoc-defines                                               ////
-////                                                              ////
-//// Top level ORPSoC defines file                                ////
-////                                                              ////
-//// Included in toplevel and testbench                           ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-
-// Included modules: define to include
-`define JTAG_DEBUG
-`define UART0
-`define RAM_WB
-`define INTGEN
-`define BOOTROM
-// end of included module defines - keep this comment line here
diff --git a/systems/generic/rtl/verilog/include/orpsoc-params.v b/systems/generic/rtl/verilog/include/orpsoc-params.v
deleted file mode 100644
index daf74eab..00000000
--- a/systems/generic/rtl/verilog/include/orpsoc-params.v
+++ /dev/null
@@ -1,95 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// orpsoc-params                                                ////
-////                                                              ////
-//// Top level ORPSoC parameters file                             ////
-////                                                              ////
-//// Included in toplevel and testbench                           ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-
-///////////////////////////
-//                       //
-// Peripheral parameters //
-//                       //
-///////////////////////////
-
-// UART 0 params
-parameter uart0_wb_adr = 8'h90;
-parameter uart0_aw = 3;
-
-// Interrupt generator (intgen) params
-parameter intgen_wb_adr = 8'he1;
-parameter intgen_addr_width = 1;
-
-// ROM
-parameter rom0_dw = 32;
-parameter rom0_aw = 6;
-
-//////////////////////////////////////////////////////
-//                                                  //
-// Wishbone bus parameters                          //
-//                                                  //
-//////////////////////////////////////////////////////
-
-////////////////////////
-//                    //
-// Arbiter parameters //
-//                    // 
-////////////////////////
-
-parameter wb_dw = 32; // Default Wishbone full word width
-parameter wb_aw = 32; // Default Wishbone full address width
-
-///////////////////////////
-//                       //
-// Instruction bus       //
-//                       //
-///////////////////////////
-
-parameter ibus_slaves = 2;
-parameter rom0_slave_nr     = 0;
-parameter mc0_ibus_slave_nr = 1;
-
-///////////////////////////
-//                       //
-// Data bus              //
-//                       //
-///////////////////////////
-parameter dbus_slaves = 2;
-parameter mc0_dbus_slave_nr = 0;
-parameter bbus_slave_nr = 1;
-
-///////////////////////////////
-//                           //
-// Byte-wide peripheral bus  //
-//                           //
-///////////////////////////////
-parameter bbus_slaves = 2;
-parameter uart_slave_nr = 0;
-parameter intgen_slave_nr = 1;
diff --git a/systems/generic/rtl/verilog/include/timescale.v b/systems/generic/rtl/verilog/include/timescale.v
deleted file mode 100644
index ff200d44..00000000
--- a/systems/generic/rtl/verilog/include/timescale.v
+++ /dev/null
@@ -1 +0,0 @@
-`timescale 1ns/10ps
diff --git a/systems/generic/rtl/verilog/include/uart_defines.v b/systems/generic/rtl/verilog/include/uart_defines.v
deleted file mode 100644
index d67b3b4a..00000000
--- a/systems/generic/rtl/verilog/include/uart_defines.v
+++ /dev/null
@@ -1,250 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  uart_defines.v                                              ////
-////                                                              ////
-////                                                              ////
-////  This file is part of the "UART 16550 compatible" project    ////
-////  http://www.opencores.org/cores/uart16550/                   ////
-////                                                              ////
-////  Documentation related to this project:                      ////
-////  - http://www.opencores.org/cores/uart16550/                 ////
-////                                                              ////
-////  Projects compatibility:                                     ////
-////  - WISHBONE                                                  ////
-////  RS232 Protocol                                              ////
-////  16550D uart (mostly supported)                              ////
-////                                                              ////
-////  Overview (main Features):                                   ////
-////  Defines of the Core                                         ////
-////                                                              ////
-////  Known problems (limits):                                    ////
-////  None                                                        ////
-////                                                              ////
-////  To Do:                                                      ////
-////  Nothing.                                                    ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - gorban@opencores.org                                  ////
-////      - Jacob Gorban                                          ////
-////      - Igor Mohor (igorm@opencores.org)                      ////
-////                                                              ////
-////  Created:        2001/05/12                                  ////
-////  Last Updated:   2001/05/17                                  ////
-////                  (See log for the revision history)          ////
-////                                                              ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2000, 2001 Authors                             ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.13  2003/06/11 16:37:47  gorban
-// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
-//
-// Revision 1.12  2002/07/22 23:02:23  gorban
-// Bug Fixes:
-//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-//   Problem reported by Kenny.Tung.
-//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-//  * Made FIFO's as general inferrable memory where possible.
-//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-//  * Added optional baudrate output (baud_o).
-//  This is identical to BAUDOUT* signal on 16550 chip.
-//  It outputs 16xbit_clock_rate - the divided clock.
-//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-// Revision 1.10  2001/12/11 08:55:40  mohor
-// Scratch register define added.
-//
-// Revision 1.9  2001/12/03 21:44:29  gorban
-// Updated specification documentation.
-// Added full 32-bit data bus interface, now as default.
-// Address is 5-bit wide in 32-bit data bus mode.
-// Added wb_sel_i input to the core. It's used in the 32-bit mode.
-// Added debug interface with two 32-bit read-only registers in 32-bit mode.
-// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
-// My small test bench is modified to work with 32-bit mode.
-//
-// Revision 1.8  2001/11/26 21:38:54  gorban
-// Lots of fixes:
-// Break condition wasn't handled correctly at all.
-// LSR bits could lose their values.
-// LSR value after reset was wrong.
-// Timing of THRE interrupt signal corrected.
-// LSR bit 0 timing corrected.
-//
-// Revision 1.7  2001/08/24 21:01:12  mohor
-// Things connected to parity changed.
-// Clock devider changed.
-//
-// Revision 1.6  2001/08/23 16:05:05  mohor
-// Stop bit bug fixed.
-// Parity bug fixed.
-// WISHBONE read cycle bug fixed,
-// OE indicator (Overrun Error) bug fixed.
-// PE indicator (Parity Error) bug fixed.
-// Register read bug fixed.
-//
-// Revision 1.5  2001/05/31 20:08:01  gorban
-// FIFO changes and other corrections.
-//
-// Revision 1.4  2001/05/21 19:12:02  gorban
-// Corrected some Linter messages.
-//
-// Revision 1.3  2001/05/17 18:34:18  gorban
-// First 'stable' release. Should be sythesizable now. Also added new header.
-//
-// Revision 1.0  2001-05-17 21:27:11+02  jacob
-// Initial revision
-//
-//
-
-// remove comments to restore to use the new version with 8 data bit interface
-// in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place
-// also, in 8-bit version there'll be no debugging features included
-// CAUTION: doesn't work with current version of OR1200
-`define DATA_BUS_WIDTH_8
-
-`ifdef DATA_BUS_WIDTH_8
- `define UART_ADDR_WIDTH 3
- `define UART_DATA_WIDTH 8
-`else
- `define UART_ADDR_WIDTH 5
- `define UART_DATA_WIDTH 32
-`endif
-
-// Uncomment this if you want your UART to have
-// 16xBaudrate output port.
-// If defined, the enable signal will be used to drive baudrate_o signal
-// It's frequency is 16xbaudrate
-
-// `define UART_HAS_BAUDRATE_OUTPUT
-
-// Register addresses
-`define UART_REG_RB	`UART_ADDR_WIDTH'd0	// receiver buffer
-`define UART_REG_TR  `UART_ADDR_WIDTH'd0	// transmitter
-`define UART_REG_IE	`UART_ADDR_WIDTH'd1	// Interrupt enable
-`define UART_REG_II  `UART_ADDR_WIDTH'd2	// Interrupt identification
-`define UART_REG_FC  `UART_ADDR_WIDTH'd2	// FIFO control
-`define UART_REG_LC	`UART_ADDR_WIDTH'd3	// Line Control
-`define UART_REG_MC	`UART_ADDR_WIDTH'd4	// Modem control
-`define UART_REG_LS  `UART_ADDR_WIDTH'd5	// Line status
-`define UART_REG_MS  `UART_ADDR_WIDTH'd6	// Modem status
-`define UART_REG_SR  `UART_ADDR_WIDTH'd7	// Scratch register
-`define UART_REG_DL1	`UART_ADDR_WIDTH'd0	// Divisor latch bytes (1-2)
-`define UART_REG_DL2	`UART_ADDR_WIDTH'd1
-
-// Interrupt Enable register bits
-`define UART_IE_RDA	0	// Received Data available interrupt
-`define UART_IE_THRE	1	// Transmitter Holding Register empty interrupt
-`define UART_IE_RLS	2	// Receiver Line Status Interrupt
-`define UART_IE_MS	3	// Modem Status Interrupt
-
-// Interrupt Identification register bits
-`define UART_II_IP	0	// Interrupt pending when 0
-`define UART_II_II	3:1	// Interrupt identification
-
-// Interrupt identification values for bits 3:1
-`define UART_II_RLS	3'b011	// Receiver Line Status
-`define UART_II_RDA	3'b010	// Receiver Data available
-`define UART_II_TI	3'b110	// Timeout Indication
-`define UART_II_THRE	3'b001	// Transmitter Holding Register empty
-`define UART_II_MS	3'b000	// Modem Status
-
-// FIFO Control Register bits
-`define UART_FC_TL	1:0	// Trigger level
-
-// FIFO trigger level values
-`define UART_FC_1		2'b00
-`define UART_FC_4		2'b01
-`define UART_FC_8		2'b10
-`define UART_FC_14	2'b11
-
-// Line Control register bits
-`define UART_LC_BITS	1:0	// bits in character
-`define UART_LC_SB	2	// stop bits
-`define UART_LC_PE	3	// parity enable
-`define UART_LC_EP	4	// even parity
-`define UART_LC_SP	5	// stick parity
-`define UART_LC_BC	6	// Break control
-`define UART_LC_DL	7	// Divisor Latch access bit
-
-// Modem Control register bits
-`define UART_MC_DTR	0
-`define UART_MC_RTS	1
-`define UART_MC_OUT1	2
-`define UART_MC_OUT2	3
-`define UART_MC_LB	4	// Loopback mode
-
-// Line Status Register bits
-`define UART_LS_DR	0	// Data ready
-`define UART_LS_OE	1	// Overrun Error
-`define UART_LS_PE	2	// Parity Error
-`define UART_LS_FE	3	// Framing Error
-`define UART_LS_BI	4	// Break interrupt
-`define UART_LS_TFE	5	// Transmit FIFO is empty
-`define UART_LS_TE	6	// Transmitter Empty indicator
-`define UART_LS_EI	7	// Error indicator
-
-// Modem Status Register bits
-`define UART_MS_DCTS	0	// Delta signals
-`define UART_MS_DDSR	1
-`define UART_MS_TERI	2
-`define UART_MS_DDCD	3
-`define UART_MS_CCTS	4	// Complement signals
-`define UART_MS_CDSR	5
-`define UART_MS_CRI	6
-`define UART_MS_CDCD	7
-
-// FIFO parameter defines
-
-`define UART_FIFO_WIDTH	8
-`define UART_FIFO_DEPTH	16
-`define UART_FIFO_POINTER_W	4
-`define UART_FIFO_COUNTER_W	5
-// receiver fifo has width 11 because it has break, parity and framing error bits
-`define UART_FIFO_REC_WIDTH  11
-
-
-`define VERBOSE_WB  0           // All activity on the WISHBONE is recorded
-`define VERBOSE_LINE_STATUS 0   // Details about the lsr (line status register)
-`define FAST_TEST   1           // 64/1024 packets are sent
-
-// Defines hard baud prescaler register - uncomment to enable
-`define PRESCALER_PRESET_HARD
-// 115200 baud preset values
-// 20MHz: prescaler 10.8 (11, rounded up)
-//`define PRESCALER_HIGH_PRESET 8'd0
-//`define PRESCALER_LOW_PRESET 8'd11
-// 50MHz: prescaler 27.1
-`define PRESCALER_HIGH_PRESET 8'd0
-`define PRESCALER_LOW_PRESET 8'd27
diff --git a/systems/generic/rtl/verilog/intgen.v b/systems/generic/rtl/verilog/intgen.v
deleted file mode 100644
index 3caf8a26..00000000
--- a/systems/generic/rtl/verilog/intgen.v
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- *
- * Interrupt generation module
- * 
- * A counter is loaded with a value over the Wishbone bus interface, which then
- * counts down and issues an interrupt when the value is 1
- * 
- * 
- * Register 0 - write only - counter value
- * 
- * Register 1 - read/write - interrupt status/clear
- * 
- */
-
-module intgen(
-	      clk_i,
-	      rst_i,
-	      wb_adr_i,
-	      wb_cyc_i,
-	      wb_stb_i,
-	      wb_dat_i,
-	      wb_we_i,
-	      wb_ack_o,
-	      wb_dat_o,
-
-	      irq_o
-	      );
-
-
-   input clk_i;
-   input rst_i;
-   
-   input wb_adr_i;
-   input wb_cyc_i;
-   input wb_stb_i;
-   input [7:0] wb_dat_i;
-   input       wb_we_i;
-   output      wb_ack_o;
-   output [7:0] wb_dat_o;
-   
-   output reg 	irq_o;
-   
-   reg [7:0] 	counter;
-
-   always @(posedge clk_i or posedge rst_i)
-     if (rst_i)
-       counter <= 0;
-     else if (wb_stb_i & wb_cyc_i & wb_we_i & !wb_adr_i)
-       // Write to adress 0 loads counter
-       counter <= wb_dat_i;
-     else if (|counter)
-       counter <= counter - 1;
-   
-   always @(posedge clk_i or posedge rst_i)
-     if (rst_i)
-       irq_o <= 0;
-     else if (wb_stb_i & wb_cyc_i & wb_we_i & wb_adr_i)
-       // Clear on write to reg 1
-       irq_o <= 0;
-     else if (counter==8'd1)
-       irq_o <= 1;
-
-   assign wb_ack_o = wb_stb_i & wb_cyc_i;
-   assign wb_dat_o = (wb_adr_i) ? {7'd0,irq_o} : counter;
-   
-endmodule // intgen
-
-       
-
-   
\ No newline at end of file
diff --git a/systems/generic/rtl/verilog/orpsoc_top.v b/systems/generic/rtl/verilog/orpsoc_top.v
deleted file mode 100644
index db9b2017..00000000
--- a/systems/generic/rtl/verilog/orpsoc_top.v
+++ /dev/null
@@ -1,780 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-///                                                               //// 
-/// ORPSoC top level                                              ////
-///                                                               ////
-/// Define I/O ports, instantiate modules                         ////
-///                                                               ////
-/// Julius Baxter, julius@opencores.org                           ////
-///                                                               ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-
-`include "orpsoc-defines.v"
-
-module orpsoc_top
-  (
-   input  clk_pad_i,
-   input  rst_n_pad_i,
-   //JTAG Interface
-   output tdo_pad_o,
-   input  tms_pad_i,
-   input  tck_pad_i,
-   input  tdi_pad_i,
-   //UART Interface
-   input  uart0_srx_pad_i,
-   output uart0_stx_pad_o
-    );
-
-`include "orpsoc-params.v"   
-
-   parameter IDCODE_VALUE=32'h14951185;
-   ////////////////////////////////////////////////////////////////////////
-   //
-   // Clock and reset generation module
-   // 
-   ////////////////////////////////////////////////////////////////////////
-
-   wire   async_rst;
-   wire   wb_clk, wb_rst;
-   wire   dbg_tck;
-   
-   clkgen clkgen0
-     (
-      .clk_pad_i   (clk_pad_i),
-      .rst_n_pad_i (rst_n_pad_i),
-      .async_rst_o (async_rst),
-      //Wishbone clocks
-      .wb_clk_o    (wb_clk),
-      .wb_rst_o    (wb_rst),
-      //JTAG clocks
-      .tck_pad_i   (tck_pad_i),
-      .dbg_tck_o   (dbg_tck));
-
-   // OR1200 instruction bus wires
-   wire [wb_aw-1:0] 	      wb_or1200_i_adr;
-   wire [wb_dw-1:0] 	      wb_or1200_i_dat;
-   wire [3:0] 		      wb_or1200_i_sel;
-   wire 		      wb_or1200_i_we;
-   wire 		      wb_or1200_i_cyc;
-   wire 		      wb_or1200_i_stb;
-   wire [2:0] 		      wb_or1200_i_cti;
-   wire [1:0] 		      wb_or1200_i_bte;
-   
-   wire [wb_dw-1:0] 	      wb_or1200_i_sdt;   
-   wire 		      wb_or1200_i_ack;
-   wire 		      wb_or1200_i_err;
-   wire 		      wb_or1200_i_rty;
-
-   // OR1200 data bus wires   
-   wire [wb_aw-1:0] 	      wb_or1200_d_adr;
-   wire [wb_dw-1:0] 	      wb_or1200_d_dat;
-   wire [3:0] 		      wb_or1200_d_sel;
-   wire 		      wb_or1200_d_we;
-   wire 		      wb_or1200_d_cyc;
-   wire 		      wb_or1200_d_stb;
-   wire [2:0] 		      wb_or1200_d_cti;
-   wire [1:0] 		      wb_or1200_d_bte;
-   
-   wire [wb_dw-1:0] 	      wb_or1200_d_sdt;   
-   wire 		      wb_or1200_d_ack;
-   wire 		      wb_or1200_d_err;
-   wire 		      wb_or1200_d_rty;   
-
-   // Debug interface bus wires   
-   wire [wb_aw-1:0] 	      wb_dbg_adr;
-   wire [wb_dw-1:0] 	      wb_dbg_dat;
-   wire [3:0] 		      wb_dbg_sel;
-   wire 		      wb_dbg_we;
-   wire 		      wb_dbg_cyc;
-   wire 		      wb_dbg_stb;
-   wire [2:0] 		      wb_dbg_cti;
-   wire [1:0] 		      wb_dbg_bte;
-   
-   wire [wb_dw-1:0] 	      wb_dbg_sdt;
-   wire 		      wb_dbg_ack;
-   wire 		      wb_dbg_err;
-   wire 		      wb_dbg_rty;
-
-   wire [wb_aw-1:0] 	      wbm_dbus_adr;
-   wire [wb_dw-1:0] 	      wbm_dbus_dat;
-   wire [3:0] 		      wbm_dbus_sel;
-   wire 		      wbm_dbus_we;
-   wire 		      wbm_dbus_cyc;
-   wire 		      wbm_dbus_stb;
-   wire [2:0] 		      wbm_dbus_cti;
-   wire [1:0] 		      wbm_dbus_bte;
-   
-   wire [wb_dw-1:0] 	      wbm_dbus_sdt;   
-   wire 		      wbm_dbus_ack;
-   wire 		      wbm_dbus_err;
-   wire 		      wbm_dbus_rty;
-
-   // Byte bus bridge master signals
-   wire [wb_dw-1:0] 	      wb_bbus_sdt;   
-   wire 		      wb_bbus_ack;
-   wire 		      wb_bbus_err;
-   wire 		      wb_bbus_rty;   
-
-   // Instruction bus slave wires //
-   
-   // rom0 instruction bus wires
-   wire [31:0] wb_rom0_sdt;   
-   wire        wb_rom0_ack;
-   wire        wb_rom0_err;
-   wire        wb_rom0_rty;   
-   // mc0 instruction bus wires
-   wire [31:0] wb_mc0_ibus_sdt;
-   wire        wb_mc0_ibus_ack;
-   wire        wb_mc0_ibus_err;
-   wire        wb_mc0_ibus_rty;
-   // mc0 data bus wires
-   wire [31:0] wb_mc0_dbus_sdt;
-   wire        wb_mc0_dbus_ack;
-   wire        wb_mc0_dbus_err;
-   wire        wb_mc0_dbus_rty;
-   
-   // Data bus slave wires //
-   
-   // uart0 wires
-   wire [7:0]  wb_uart_sdt;   
-   wire        wb_uart_ack;
-   wire        wb_uart_err;
-   wire        wb_uart_rty;   
-   // intgen wires
-   wire [7:0] 			     wb_intgen_sdt;
-   wire 			     wb_intgen_ack;
-   wire 			     wb_intgen_err;
-   wire 			     wb_intgen_rty;
-
-   wire [ibus_slaves-1:0] ibus_slave_sel =
-	      {wb_or1200_i_adr[31:28] != 4'hf,
-	       wb_or1200_i_adr[31:28] == 4'hf};
-   
-
-   wire [31:0] 		  wb_ibus_adr;
-   wire [31:0] 		  wb_ibus_dat;
-   wire [3:0] 		  wb_ibus_sel;
-   wire 		  wb_ibus_we;
-   wire [ibus_slaves-1:0] wb_ibus_cyc;
-   wire [ibus_slaves-1:0] wb_ibus_stb;
-   wire [2:0] 		  wb_ibus_cti;
-   wire [1:0] 		  wb_ibus_bte;
-   
-   
-   //
-   // Wishbone instruction bus arbiter
-   //
-   wb_mux wb_mux_ibus
-     (.wb_clk      (wb_clk),
-      .wb_rst      (wb_rst),
-      .slave_sel_i (ibus_slave_sel),
-    // Master Interface
-      .wbm_adr_i   (wb_or1200_i_adr),
-      .wbm_dat_i   (wb_or1200_i_dat),
-      .wbm_sel_i   (wb_or1200_i_sel),
-      .wbm_we_i    (wb_or1200_i_we),
-      .wbm_cyc_i   (wb_or1200_i_cyc),
-      .wbm_stb_i   (wb_or1200_i_stb),
-      .wbm_cti_i   (wb_or1200_i_cti),
-      .wbm_bte_i   (wb_or1200_i_bte),
-      .wbm_sdt_o   (wb_or1200_i_sdt),
-      .wbm_ack_o   (wb_or1200_i_ack),
-      .wbm_err_o   (wb_or1200_i_err),
-      .wbm_rty_o   (wb_or1200_i_rty), 
-      //Slave interface
-      .wbs_adr_o   (wb_ibus_adr),
-      .wbs_dat_o   (wb_ibus_dat),
-      .wbs_sel_o   (wb_ibus_sel), 
-      .wbs_we_o    (wb_ibus_we),
-      .wbs_cyc_o   (wb_ibus_cyc),
-      .wbs_stb_o   (wb_ibus_stb),
-      .wbs_cti_o   (wb_ibus_cti),
-      .wbs_bte_o   (wb_ibus_bte),
-      .wbs_sdt_i   ({wb_mc0_ibus_sdt, wb_rom0_sdt}),
-      .wbs_ack_i   ({wb_mc0_ibus_ack, wb_rom0_ack}),
-      .wbs_err_i   ({wb_mc0_ibus_err, wb_rom0_err}),
-      .wbs_rty_i   ({wb_mc0_ibus_rty, wb_rom0_rty}));
-      
-
-   wb_arbiter wb_arbiter_dbus
-     (.wb_clk      (wb_clk),
-      .wb_rst      (wb_rst),
-    // Master Interface
-      .wbm_adr_i   ({wb_dbg_adr, wb_or1200_d_adr}),
-      .wbm_dat_i   ({wb_dbg_dat, wb_or1200_d_dat}),
-      .wbm_sel_i   ({wb_dbg_sel, wb_or1200_d_sel}),
-      .wbm_we_i    ({wb_dbg_we , wb_or1200_d_we }),
-      .wbm_cyc_i   ({wb_dbg_cyc, wb_or1200_d_cyc}),
-      .wbm_stb_i   ({wb_dbg_stb, wb_or1200_d_stb}),
-      .wbm_cti_i   ({wb_dbg_cti, wb_or1200_d_cti}),
-      .wbm_bte_i   ({wb_dbg_bte, wb_or1200_d_bte}),
-      .wbm_sdt_o   ({wb_dbg_sdt, wb_or1200_d_sdt}),
-      .wbm_ack_o   ({wb_dbg_ack, wb_or1200_d_ack}),
-      .wbm_err_o   ({wb_dbg_err, wb_or1200_d_err}),
-      .wbm_rty_o   ({wb_dbg_rty, wb_or1200_d_rty}), 
-      //Slave interface
-      .wbs_adr_o   (wbm_dbus_adr),
-      .wbs_dat_o   (wbm_dbus_dat),
-      .wbs_sel_o   (wbm_dbus_sel), 
-      .wbs_we_o    (wbm_dbus_we),
-      .wbs_cyc_o   (wbm_dbus_cyc),
-      .wbs_stb_o   (wbm_dbus_stb),
-      .wbs_cti_o   (wbm_dbus_cti),
-      .wbs_bte_o   (wbm_dbus_bte),
-      .wbs_sdt_i   (wbm_dbus_sdt),
-      .wbs_ack_i   (wbm_dbus_ack),
-      .wbs_err_i   (wbm_dbus_err),
-      .wbs_rty_i   (wbm_dbus_rty));
-
-   wire [dbus_slaves-1:0] dbus_slave_sel =
-			  {wbm_dbus_adr[31:28] != 4'h0,
-			   wbm_dbus_adr[31:28] == 4'h0};
-
-   wire [31:0] 		  wb_dbus_adr;
-   wire [31:0] 		  wb_dbus_dat;
-   wire [3:0] 		  wb_dbus_sel;
-   wire 		  wb_dbus_we;
-   wire [ibus_slaves-1:0] wb_dbus_cyc;
-   wire [ibus_slaves-1:0] wb_dbus_stb;
-   wire [2:0] 		  wb_dbus_cti;
-   wire [1:0] 		  wb_dbus_bte;
-
-   //
-   // Wishbone data bus multiplexer
-   //
-   wb_mux wb_mux_dbus
-     (.wb_clk      (wb_clk),
-      .wb_rst      (wb_rst),
-      .slave_sel_i (dbus_slave_sel),
-      // Master Interface
-      .wbm_adr_i   (wbm_dbus_adr),
-      .wbm_dat_i   (wbm_dbus_dat),
-      .wbm_sel_i   (wbm_dbus_sel),
-      .wbm_we_i    (wbm_dbus_we),
-      .wbm_cyc_i   (wbm_dbus_cyc),
-      .wbm_stb_i   (wbm_dbus_stb),
-      .wbm_cti_i   (wbm_dbus_cti),
-      .wbm_bte_i   (wbm_dbus_bte),
-      .wbm_sdt_o   (wbm_dbus_sdt),
-      .wbm_ack_o   (wbm_dbus_ack),
-      .wbm_err_o   (wbm_dbus_err),
-      .wbm_rty_o   (wbm_dbus_rty), 
-      //Slave interface
-      .wbs_adr_o   (wb_dbus_adr),
-      .wbs_dat_o   (wb_dbus_dat),
-      .wbs_sel_o   (wb_dbus_sel), 
-      .wbs_we_o    (wb_dbus_we),
-      .wbs_cyc_o   (wb_dbus_cyc),
-      .wbs_stb_o   (wb_dbus_stb),
-      .wbs_cti_o   (wb_dbus_cti),
-      .wbs_bte_o   (wb_dbus_bte),
-      .wbs_sdt_i   ({wb_bbus_sdt, wb_mc0_dbus_sdt}),
-      .wbs_ack_i   ({wb_bbus_ack, wb_mc0_dbus_ack}),
-      .wbs_err_i   ({wb_bbus_err, wb_mc0_dbus_err}),
-      .wbs_rty_i   ({wb_bbus_rty, wb_mc0_dbus_rty}));
-
-
-   wire [bbus_slaves-1:0] bbus_slave_sel =
-			  {wb_or1200_d_adr[31:24] == 8'he1,
-			   wb_or1200_d_adr[31:24] == 8'h90};
-
-   wire [31:0] 		  wb_bbus_adr;
-   wire [7:0] 		  wb_bbus_dat;
-   wire [3:0] 		  wb_bbus_sel;
-   wire 		  wb_bbus_we;
-   wire [bbus_slaves-1:0] wb_bbus_cyc;
-   wire [bbus_slaves-1:0] wb_bbus_stb;
-   wire [2:0] 		  wb_bbus_cti;
-   wire [1:0] 		  wb_bbus_bte;
-
-   //
-   // Wishbone byte-wide bus arbiter
-   //   
-   wb_mux
-     #(.sdw(8))
-   wb_mux_bbus
-     (.wb_clk      (wb_clk),
-      .wb_rst      (wb_rst),
-      .slave_sel_i (bbus_slave_sel),
-      //Master interface
-      .wbm_adr_i   (wb_dbus_adr),
-      .wbm_dat_i   (wb_dbus_dat),
-      .wbm_sel_i   (wb_dbus_sel),
-      .wbm_we_i    (wb_dbus_we ),
-      .wbm_cyc_i   (wb_dbus_cyc[bbus_slave_nr]),
-      .wbm_stb_i   (wb_dbus_stb[bbus_slave_nr]),
-      .wbm_cti_i   (wb_dbus_cti),
-      .wbm_bte_i   (wb_dbus_bte),
-      .wbm_sdt_o   (wb_bbus_sdt),
-      .wbm_ack_o   (wb_bbus_ack),
-      .wbm_err_o   (wb_bbus_err),
-      .wbm_rty_o   (wb_bbus_rty),
-      //Slave interface
-      .wbs_adr_o   (wb_bbus_adr),
-      .wbs_dat_o   (wb_bbus_dat),
-      .wbs_sel_o   (           ),
-      .wbs_we_o    (wb_bbus_we ),
-      .wbs_cyc_o   (wb_bbus_cyc),
-      .wbs_stb_o   (wb_bbus_stb),
-      .wbs_cti_o   (wb_bbus_cti),
-      .wbs_bte_o   (wb_bbus_bte),
-      .wbs_sdt_i   ({wb_intgen_sdt, wb_uart_sdt}),
-      .wbs_ack_i   ({wb_intgen_ack, wb_uart_ack}),
-      .wbs_err_i   ({wb_intgen_err, wb_uart_err}),
-      .wbs_rty_i   ({wb_intgen_rty, wb_uart_rty}));
-
-   ////////////////////////////////////////////////////////////////////////
-   //
-   // JTAG TAP
-   // 
-   ////////////////////////////////////////////////////////////////////////
-
-   wire 				  dbg_if_select;   
-   wire 				  dbg_if_tdo;
-   wire 				  jtag_tap_tdo;   
-   wire 				  jtag_tap_shift_dr, jtag_tap_pause_dr, 
-					  jtag_tap_update_dr, jtag_tap_capture_dr;
-
-   tap_top #(.IDCODE_VALUE(IDCODE_VALUE)) jtag_tap0
-     (
-      // Ports to pads
-      .tdo_pad_o			(tdo_pad_o),
-      .tms_pad_i			(tms_pad_i),
-      .tck_pad_i			(dbg_tck),
-      .trst_pad_i			(async_rst),
-      .tdi_pad_i			(tdi_pad_i),
-      
-      .tdo_padoe_o			(),
-      
-      .tdo_o				(jtag_tap_tdo),
-
-      .shift_dr_o			(jtag_tap_shift_dr),
-      .pause_dr_o			(jtag_tap_pause_dr),
-      .update_dr_o			(jtag_tap_update_dr),
-      .capture_dr_o			(jtag_tap_capture_dr),
-      
-      .extest_select_o			(),
-      .sample_preload_select_o		(),
-      .mbist_select_o			(),
-      .debug_select_o			(dbg_if_select),
-
-      
-      .bs_chain_tdi_i			(1'b0),
-      .mbist_tdi_i			(1'b0),
-      .debug_tdi_i			(dbg_if_tdo)
-      
-      );
-   
-   ////////////////////////////////////////////////////////////////////////
-   //
-   // or1200
-   // 
-   ////////////////////////////////////////////////////////////////////////
-
-   wire [19:0] 				  or1200_pic_ints;
-
-   wire [31:0] 				  or1200_dbg_dat_i;
-   wire [31:0] 				  or1200_dbg_adr_i;
-   wire 				  or1200_dbg_we_i;
-   wire 				  or1200_dbg_stb_i;
-   wire 				  or1200_dbg_ack_o;
-   wire [31:0] 				  or1200_dbg_dat_o;
-   
-   wire 				  or1200_dbg_stall_i;
-   wire 				  or1200_dbg_ewt_i;
-   wire [3:0] 				  or1200_dbg_lss_o;
-   wire [1:0] 				  or1200_dbg_is_o;
-   wire [10:0] 				  or1200_dbg_wp_o;
-   wire 				  or1200_dbg_bp_o;
-   wire 				  or1200_dbg_rst;   
-   
-   wire 				  sig_tick;
-   wire or1200_rst = wb_rst | or1200_dbg_rst;
-
-   or1200_top #(.boot_adr(32'hf0000000)) or1200_top0
-       (
-	// Instruction bus, clocks, reset
-	.iwb_clk_i			(wb_clk),
-	.iwb_rst_i			(wb_rst),
-	.iwb_ack_i			(wb_or1200_i_ack),
-	.iwb_err_i			(wb_or1200_i_err),
-	.iwb_rty_i			(wb_or1200_i_rty),
-	.iwb_dat_i			(wb_or1200_i_sdt),
-	
-	.iwb_cyc_o			(wb_or1200_i_cyc),
-	.iwb_adr_o			(wb_or1200_i_adr),
-	.iwb_stb_o			(wb_or1200_i_stb),
-	.iwb_we_o			(wb_or1200_i_we),
-	.iwb_sel_o			(wb_or1200_i_sel),
-	.iwb_dat_o			(wb_or1200_i_dat),
-	.iwb_cti_o			(wb_or1200_i_cti),
-	.iwb_bte_o			(wb_or1200_i_bte),
-	
-	// Data bus, clocks, reset            
-	.dwb_clk_i			(wb_clk),
-	.dwb_rst_i			(wb_rst),
-	.dwb_ack_i			(wb_or1200_d_ack),
-	.dwb_err_i			(wb_or1200_d_err),
-	.dwb_rty_i			(wb_or1200_d_rty),
-	.dwb_dat_i			(wb_or1200_d_sdt),
-
-	.dwb_cyc_o			(wb_or1200_d_cyc),
-	.dwb_adr_o			(wb_or1200_d_adr),
-	.dwb_stb_o			(wb_or1200_d_stb),
-	.dwb_we_o			(wb_or1200_d_we),
-	.dwb_sel_o			(wb_or1200_d_sel),
-	.dwb_dat_o			(wb_or1200_d_dat),
-	.dwb_cti_o			(wb_or1200_d_cti),
-	.dwb_bte_o			(wb_or1200_d_bte),
-	
-	// Debug interface ports
-	.dbg_stall_i			(or1200_dbg_stall_i),
-	//.dbg_ewt_i			(or1200_dbg_ewt_i),
-	.dbg_ewt_i			(1'b0),
-	.dbg_lss_o			(or1200_dbg_lss_o),
-	.dbg_is_o			(or1200_dbg_is_o),
-	.dbg_wp_o			(or1200_dbg_wp_o),
-	.dbg_bp_o			(or1200_dbg_bp_o),
-
-	.dbg_adr_i			(or1200_dbg_adr_i),      
-	.dbg_we_i			(or1200_dbg_we_i ), 
-	.dbg_stb_i			(or1200_dbg_stb_i),          
-	.dbg_dat_i			(or1200_dbg_dat_i),
-	.dbg_dat_o			(or1200_dbg_dat_o),
-	.dbg_ack_o			(or1200_dbg_ack_o),
-	
-	.pm_clksd_o			(),
-	.pm_dc_gate_o			(),
-	.pm_ic_gate_o			(),
-	.pm_dmmu_gate_o			(),
-	.pm_immu_gate_o			(),
-	.pm_tt_gate_o			(),
-	.pm_cpu_gate_o			(),
-	.pm_wakeup_o			(),
-	.pm_lvolt_o			(),
-
-	// Core clocks, resets
-	.clk_i				(wb_clk),
-	.rst_i				(or1200_rst),
-	
-	.clmode_i			(2'b00),
-	// Interrupts      
-	.pic_ints_i			(or1200_pic_ints),
-	.sig_tick(sig_tick),
-	/*
-	 .mbist_so_o			(),
-	 .mbist_si_i			(0),
-	 .mbist_ctrl_i			(0),
-	 */
-
-	.pm_cpustall_i			(1'b0)
-
-	);
-   
-   ////////////////////////////////////////////////////////////////////////
-
-
-   ////////////////////////////////////////////////////////////////////////
-   //
-   // OR1200 Debug Interface
-   // 
-   ////////////////////////////////////////////////////////////////////////
-/*   
-   dbg_top dbg_if0
-     (
-      // OR1200 interface
-      .cpu0_clk_i			(wb_clk),
-      .cpu0_rst_o			(or1200_dbg_rst),      
-      .cpu0_addr_o			(or1200_dbg_adr_i),
-      .cpu0_data_o			(or1200_dbg_dat_i),
-      .cpu0_stb_o			(or1200_dbg_stb_i),
-      .cpu0_we_o			(or1200_dbg_we_i),
-      .cpu0_data_i			(or1200_dbg_dat_o),
-      .cpu0_ack_i			(or1200_dbg_ack_o),      
-
-
-      .cpu0_stall_o			(or1200_dbg_stall_i),
-      .cpu0_bp_i			(or1200_dbg_bp_o),      
-      
-      // TAP interface
-      .tck_i				(dbg_tck),
-      .tdi_i				(jtag_tap_tdo),
-      .tdo_o				(dbg_if_tdo),      
-      .rst_i				(wb_rst),
-      .shift_dr_i			(jtag_tap_shift_dr),
-      .pause_dr_i			(jtag_tap_pause_dr),
-      .update_dr_i			(jtag_tap_update_dr),
-      .debug_select_i			(dbg_if_select),
-
-      // Wishbone debug master
-      .wb_clk_i				(wb_clk),
-      .wb_dat_i				(wb_dbg_sdt),
-      .wb_ack_i				(wb_dbg_ack),
-      .wb_err_i				(wb_dbg_err),
-      .wb_adr_o				(wb_dbg_adr),
-      .wb_dat_o				(wb_dbg_dat),
-      .wb_cyc_o				(wb_dbg_cyc),
-      .wb_stb_o				(wb_dbg_stb),
-      .wb_sel_o				(wb_dbg_sel),
-      .wb_we_o				(wb_dbg_we ),
-      .wb_cti_o				(wb_dbg_cti),
-      .wb_cab_o                         (),
-      .wb_bte_o				(wb_dbg_bte)
-      );
-*/
-  adbg_top dbg_if0
-     (
-      // OR1200 interface
-      .cpu0_clk_i	(wb_clk),
-      .cpu0_rst_o	(or1200_dbg_rst),
-      .cpu0_addr_o	(or1200_dbg_adr_i),
-      .cpu0_data_o	(or1200_dbg_dat_i),
-      .cpu0_stb_o	(or1200_dbg_stb_i),
-      .cpu0_we_o	(or1200_dbg_we_i),
-      .cpu0_data_i	(or1200_dbg_dat_o),
-      .cpu0_ack_i	(or1200_dbg_ack_o),
-      .cpu0_stall_o	(or1200_dbg_stall_i),
-      .cpu0_bp_i	(or1200_dbg_bp_o),
-
-      // TAP interface
-      .tck_i	(dbg_tck),
-      .tdi_i	(jtag_tap_tdo),
-      .tdo_o	(dbg_if_tdo),
-      .rst_i	(wb_rst),
-      .capture_dr_i (jtag_tap_capture_dr),
-      .shift_dr_i	(jtag_tap_shift_dr),
-      .pause_dr_i	(jtag_tap_pause_dr),
-      .update_dr_i	(jtag_tap_update_dr),
-      .debug_select_i	(dbg_if_select),
-
-      // Wishbone debug master
-      .wb_clk_i	(wb_clk),
-      .wb_dat_i	(wb_dbg_sdt),
-      .wb_ack_i	(wb_dbg_ack),
-      .wb_err_i	(wb_dbg_err),
-
-      .wb_adr_o	(wb_dbg_adr),
-      .wb_dat_o	(wb_dbg_dat),
-      .wb_cyc_o	(wb_dbg_cyc),
-      .wb_stb_o	(wb_dbg_stb),
-      .wb_sel_o	(wb_dbg_sel),
-      .wb_we_o	(wb_dbg_we ),
-      .wb_cti_o	(wb_dbg_cti),
-      .wb_bte_o	(wb_dbg_bte)
-     );
-
-   ////////////////////////////////////////////////////////////////////////
-   //
-   // ROM
-   // 
-   ////////////////////////////////////////////////////////////////////////
-`ifdef BOOTROM   
-   rom
-     #(.addr_width(rom0_aw))
-   rom0
-     (
-      .wb_clk				(wb_clk),
-      .wb_rst				(wb_rst),
-      .wb_adr_i				(wb_ibus_adr[(rom0_aw+2)-1:2]),
-      .wb_cyc_i				(wb_ibus_cyc[rom0_slave_nr]),
-      .wb_stb_i				(wb_ibus_stb[rom0_slave_nr]),
-      .wb_cti_i				(wb_ibus_cti),
-      .wb_bte_i				(wb_ibus_bte),
-      .wb_dat_o				(wb_rom0_sdt),
-      .wb_ack_o				(wb_rom0_ack));
-`else // !`ifdef BOOTROM
-   assign wb_rom0_dat_o = 0;
-   assign wb_rom0_ack_o = 0;
-`endif // !`ifdef BOOTROM
-   assign wb_rom0_err = 1'b0;
-   assign wb_rom0_rty = 1'b0;
-
-   ////////////////////////////////////////////////////////////////////////
-
-   ////////////////////////////////////////////////////////////////////////
-   //
-   // Generic main RAM
-   // 
-   ////////////////////////////////////////////////////////////////////////
-
-   ram_wb #(.aw(wb_aw),
-	    .dw(wb_dw),
-	    .mem_size_bytes(8192*1024), // 8MB
-	    .mem_adr_width(23)) // log2(8192*1024)
-   ram_wb0
-     (
-      // Wishbone slave interface 0
-      .wbm0_dat_i			(wb_ibus_dat),
-      .wbm0_adr_i			(wb_ibus_adr),
-      .wbm0_sel_i			(wb_ibus_sel),
-      .wbm0_cti_i			(wb_ibus_cti),
-      .wbm0_bte_i			(wb_ibus_bte),
-      .wbm0_we_i			(wb_ibus_we ),
-      .wbm0_cyc_i			(wb_ibus_cyc[mc0_ibus_slave_nr]),
-      .wbm0_stb_i			(wb_ibus_stb[mc0_ibus_slave_nr]),
-      .wbm0_dat_o			(wb_mc0_ibus_sdt),
-      .wbm0_ack_o			(wb_mc0_ibus_ack),
-      .wbm0_err_o                       (wb_mc0_ibus_err),
-      .wbm0_rty_o                       (wb_mc0_ibus_rty),
-      // Wishbone slave interface 1
-      .wbm1_dat_i			(wb_dbus_dat),
-      .wbm1_adr_i			(wb_dbus_adr),
-      .wbm1_sel_i			(wb_dbus_sel),
-      .wbm1_cti_i			(wb_dbus_cti),
-      .wbm1_bte_i			(wb_dbus_bte),
-      .wbm1_we_i			(wb_dbus_we),
-      .wbm1_cyc_i			(wb_dbus_cyc[mc0_dbus_slave_nr]),
-      .wbm1_stb_i			(wb_dbus_stb[mc0_dbus_slave_nr]),
-      .wbm1_dat_o			(wb_mc0_dbus_sdt),
-      .wbm1_ack_o			(wb_mc0_dbus_ack),
-      .wbm1_err_o                       (wb_mc0_dbus_err),
-      .wbm1_rty_o                       (wb_mc0_dbus_rty),
-      // Wishbone slave interface 2
-      .wbm2_dat_i			(32'd0),
-      .wbm2_adr_i			(32'd0),
-      .wbm2_sel_i			(4'd0),
-      .wbm2_cti_i			(3'd0),
-      .wbm2_bte_i			(2'd0),
-      .wbm2_we_i			(1'd0),
-      .wbm2_cyc_i			(1'd0),
-      .wbm2_stb_i			(1'd0),
-      .wbm2_dat_o			(),
-      .wbm2_ack_o			(),
-      .wbm2_err_o                       (),
-      .wbm2_rty_o                       (),
-      // Clock, reset
-      .wb_clk_i				(wb_clk),
-      .wb_rst_i				(wb_rst));
-
-   ////////////////////////////////////////////////////////////////////////
-   //
-   // UART0
-   // 
-   ////////////////////////////////////////////////////////////////////////
-
-   wire        uart0_irq;
-
-   assign wb_uart_err = 0;
-   assign wb_uart_rty = 0;
-   
-   uart_top uart16550_0
-     (
-      // Wishbone slave interface
-      .wb_clk_i				(wb_clk),
-      .wb_rst_i				(wb_rst),
-      .wb_adr_i				(wb_bbus_adr[uart0_aw-1:0]),
-      .wb_dat_i				(wb_bbus_dat),
-      .wb_we_i				(wb_bbus_we),
-      .wb_stb_i				(wb_bbus_stb[uart_slave_nr]),
-      .wb_cyc_i				(wb_bbus_cyc[uart_slave_nr]),
-      .wb_sel_i				(),
-      .wb_dat_o				(wb_uart_sdt),
-      .wb_ack_o				(wb_uart_ack),
-
-      .int_o				(uart0_irq),
-      .stx_pad_o			(uart0_stx_pad_o),
-      .rts_pad_o			(),
-      .dtr_pad_o			(),
-      //      .baud_o				(),
-      // Inputs
-      .srx_pad_i			(uart0_srx_pad_i),
-      .cts_pad_i			(1'b0),
-      .dsr_pad_i			(1'b0),
-      .ri_pad_i				(1'b0),
-      .dcd_pad_i			(1'b0));
-
-`ifdef INTGEN
-
-   wire        intgen_irq;
-
-   intgen intgen0
-     (
-      .clk_i                           (wb_clk),
-      .rst_i                           (wb_rst),
-      .wb_adr_i                        (wb_bbus_adr[intgen_addr_width-1:0]),
-      .wb_dat_i                        (wb_bbus_dat),
-      .wb_we_i                         (wb_bbus_we ),
-      .wb_cyc_i                        (wb_bbus_cyc[intgen_slave_nr]),
-      .wb_stb_i                        (wb_bbus_stb[intgen_slave_nr]),
-      .wb_ack_o                        (wb_intgen_ack),
-      .wb_dat_o                        (wb_intgen_sdt),
-      
-      .irq_o                           (intgen_irq)
-      );
-
-`endif //  `ifdef INTGEN
-   assign wb_intgen_err = 0;
-   assign wb_intgen_rty = 0;
-   
-   
-   ////////////////////////////////////////////////////////////////////////
-   //
-   // OR1200 Interrupt assignment
-   // 
-   ////////////////////////////////////////////////////////////////////////
-   
-   assign or1200_pic_ints[0] = 0; // Non-maskable inside OR1200
-   assign or1200_pic_ints[1] = 0; // Non-maskable inside OR1200
-`ifdef UART0
-   assign or1200_pic_ints[2] = uart0_irq;
-`else   
-   assign or1200_pic_ints[2] = 0;
-`endif
-   assign or1200_pic_ints[3] = 0;
-   assign or1200_pic_ints[4] = 0;
-   assign or1200_pic_ints[5] = 0;
-`ifdef SPI0
-   assign or1200_pic_ints[6] = spi0_irq;
-`else   
-   assign or1200_pic_ints[6] = 0;
-`endif
-   assign or1200_pic_ints[7] = 0;
-   assign or1200_pic_ints[8] = 0;
-   assign or1200_pic_ints[9] = 0;
-   assign or1200_pic_ints[10] = 0;
-   assign or1200_pic_ints[11] = 0;
-   assign or1200_pic_ints[12] = 0;
-   assign or1200_pic_ints[13] = 0;
-   assign or1200_pic_ints[14] = 0;
-   assign or1200_pic_ints[15] = 0;
-   assign or1200_pic_ints[16] = 0;
-   assign or1200_pic_ints[17] = 0;
-   assign or1200_pic_ints[18] = 0;
-`ifdef INTGEN
-   assign or1200_pic_ints[19] = intgen_irq;
-`else
-   assign or1200_pic_ints[19] = 0;
-`endif
-   
-endmodule // top
-
-// Local Variables:
-// verilog-library-directories:("." "../arbiter" "../uart16550" "../or1200" "../dbg_if" "../jtag_tap" "../rom" "../simple_spi" )
-// verilog-library-files:()
-// verilog-library-extensions:(".v" ".h")
-// End:
-
diff --git a/systems/generic/rtl/verilog/rom.v b/systems/generic/rtl/verilog/rom.v
deleted file mode 100644
index af1b6ddc..00000000
--- a/systems/generic/rtl/verilog/rom.v
+++ /dev/null
@@ -1,126 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  ROM                                                         ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Michael Unneback (unneback@opencores.org)             ////
-////      - Julius Baxter    (julius@opencores.org)               ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2009 Authors                                   ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-
-module rom
-  #(parameter addr_width = 5,
-    parameter b3_burst   = 0)
-   (
-    input 		       wb_clk,
-    input 		       wb_rst,
-    input [(addr_width+2)-1:2] wb_adr_i,
-    input 		       wb_stb_i,
-    input 		       wb_cyc_i,
-    input [2:0] 	       wb_cti_i,
-    input [1:0] 	       wb_bte_i,
-    output reg [31:0] 	       wb_dat_o,
-    output reg 		       wb_ack_o);
-   
-   reg [addr_width-1:0] 	    adr;
-
-   always @ (posedge wb_clk or posedge wb_rst)
-     if (wb_rst)
-       wb_dat_o <= 32'h15000000;
-     else
-       case (adr)
-	 // Zero r0 and jump to 0x00000100
-	 0 : wb_dat_o <= 32'h18000000;
-	 1 : wb_dat_o <= 32'hA8200000;
-	 2 : wb_dat_o <= 32'hA8C00100;
-	 3 : wb_dat_o <= 32'h44003000;
-	 4 : wb_dat_o <= 32'h15000000;
-	 
-	 default:
-	   wb_dat_o <= 32'h00000000;
-       endcase // case (wb_adr_i)
-
-generate
-if(b3_burst) begin : gen_b3_burst
-   reg 				    wb_stb_i_r;
-   reg 				    new_access_r;   
-   reg 				    burst_r;
-	 
-   wire burst      = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
-   wire new_access = (wb_stb_i & !wb_stb_i_r);
-   wire new_burst  = (burst & !burst_r);
-
-   always @(posedge wb_clk) begin
-     new_access_r <= new_access;
-     burst_r      <= burst;
-     wb_stb_i_r   <= wb_stb_i;
-   end
-   
-   
-   always @(posedge wb_clk)
-     if (wb_rst)
-       adr <= 0;
-     else if (new_access)
-       // New access, register address, ack a cycle later
-       adr <= wb_adr_i[(addr_width+2)-1:2];
-     else if (burst) begin
-	if (wb_cti_i == 3'b010)
-	  case (wb_bte_i)
-	    2'b00: adr <= adr + 1;
-	    2'b01: adr[1:0] <= adr[1:0] + 1;
-	    2'b10: adr[2:0] <= adr[2:0] + 1;
-	    2'b11: adr[3:0] <= adr[3:0] + 1;
-	  endcase // case (wb_bte_i)
-	else
-	  adr <= wb_adr_i[(addr_width+2)-1:2];
-     end // if (burst)
-   
-   
-   always @(posedge wb_clk)
-     if (wb_rst)
-       wb_ack_o <= 0;
-     else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
-       wb_ack_o <= 0;
-     else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r)))
-       wb_ack_o <= 1;
-     else
-       wb_ack_o <= 0;
-
-     end else begin
-	always @(wb_adr_i)
-	  adr <= wb_adr_i;
-	
-	always @ (posedge wb_clk or posedge wb_rst)
-	  if (wb_rst)
-	    wb_ack_o <= 1'b0;
-	  else
-	    wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
-	
-     end
-endgenerate   
-endmodule 

From 19aea758114d2c5d0925fd197c20640f4be82659 Mon Sep 17 00:00:00 2001
From: Franck Jullien <franck.jullien@gmail.com>
Date: Wed, 5 Mar 2014 22:24:15 +0100
Subject: [PATCH 05/12] elf-loader: add missing headers in vpi_wrapper.c

No error while using Icarus but Modelsim complains.

Add missing stdlib.h and ctype.h required for NULL, free() and
isspace().

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
---
 cores/elf-loader/vpi_wrapper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/cores/elf-loader/vpi_wrapper.c b/cores/elf-loader/vpi_wrapper.c
index d5be84a4..b43e7dbf 100644
--- a/cores/elf-loader/vpi_wrapper.c
+++ b/cores/elf-loader/vpi_wrapper.c
@@ -1,3 +1,5 @@
+#include <stdlib.h>
+#include <ctype.h>
 #include <vpi_user.h>
 #include "elf-loader.h"
 

From ea54794395d1783a0ff020451677b2aa7a81ddce Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Wed, 5 Mar 2014 16:22:35 +0700
Subject: [PATCH 06/12] Minor change

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index cefa9312..089a305a 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
 orpsoc-cores
 ============
 
-Core description files for ORPSoCv3
+Core description files for ORPSoCv3.

From 5625f1bc7b800616d67ea58580b17dbc29d2ca57 Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Wed, 5 Mar 2014 17:51:59 +0700
Subject: [PATCH 07/12] system: add Altera DE2 board support (alpha, need more
 testing, originally written by Tran Cong Nam

---
 systems/de2/backend/rtl/verilog/pll.v         |  377 ++++
 systems/de2/data/de2.sdc                      |    8 +
 systems/de2/data/options.tcl                  |   17 +
 systems/de2/data/pinmap.tcl                   |  208 ++
 systems/de2/data/wb_intercon.conf             |   43 +
 systems/de2/de2.core                          |   44 +
 systems/de2/de2.system                        |   15 +
 systems/de2/rtl/verilog/clkgen.v              |  128 ++
 .../de2/rtl/verilog/include/or1200_defines.v  | 1824 +++++++++++++++++
 .../de2/rtl/verilog/include/orpsoc-defines.v  |   39 +
 systems/de2/rtl/verilog/include/timescale.v   |    1 +
 .../de2/rtl/verilog/include/uart_defines.v    |  250 +++
 systems/de2/rtl/verilog/orpsoc_top.v          |  705 +++++++
 systems/de2/rtl/verilog/rom.v                 |  127 ++
 systems/de2/rtl/verilog/wb_intercon.v         |  360 ++++
 systems/de2/rtl/verilog/wb_intercon.vh        |  197 ++
 systems/de2/scripts/build_summary             |   21 +
 17 files changed, 4364 insertions(+)
 create mode 100755 systems/de2/backend/rtl/verilog/pll.v
 create mode 100755 systems/de2/data/de2.sdc
 create mode 100755 systems/de2/data/options.tcl
 create mode 100755 systems/de2/data/pinmap.tcl
 create mode 100755 systems/de2/data/wb_intercon.conf
 create mode 100755 systems/de2/de2.core
 create mode 100755 systems/de2/de2.system
 create mode 100755 systems/de2/rtl/verilog/clkgen.v
 create mode 100755 systems/de2/rtl/verilog/include/or1200_defines.v
 create mode 100755 systems/de2/rtl/verilog/include/orpsoc-defines.v
 create mode 100755 systems/de2/rtl/verilog/include/timescale.v
 create mode 100755 systems/de2/rtl/verilog/include/uart_defines.v
 create mode 100755 systems/de2/rtl/verilog/orpsoc_top.v
 create mode 100755 systems/de2/rtl/verilog/rom.v
 create mode 100755 systems/de2/rtl/verilog/wb_intercon.v
 create mode 100755 systems/de2/rtl/verilog/wb_intercon.vh
 create mode 100755 systems/de2/scripts/build_summary

diff --git a/systems/de2/backend/rtl/verilog/pll.v b/systems/de2/backend/rtl/verilog/pll.v
new file mode 100755
index 00000000..c3f34d76
--- /dev/null
+++ b/systems/de2/backend/rtl/verilog/pll.v
@@ -0,0 +1,377 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.0 Build 157 04/27/2011 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	areset,
+	inclk0,
+	c0,
+	c1,
+	c2,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  c2;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [5:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire7 = 1'h0;
+	wire [2:2] sub_wire4 = sub_wire0[2:2];
+	wire [0:0] sub_wire3 = sub_wire0[0:0];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  c0 = sub_wire3;
+	wire  c2 = sub_wire4;
+	wire  sub_wire5 = inclk0;
+	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire6),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 2,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 1,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 1,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk2_divide_by = 5,
+		altpll_component.clk2_duty_cycle = 50,
+		altpll_component.clk2_multiply_by = 1,
+		altpll_component.clk2_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.gate_lock_signal = "NO",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.invalid_lock_multiplier = 5,
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_USED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "5"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "10.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/systems/de2/data/de2.sdc b/systems/de2/data/de2.sdc
new file mode 100755
index 00000000..aad4ab21
--- /dev/null
+++ b/systems/de2/data/de2.sdc
@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "sys_clk_pad_i" -period 20.000ns [get_ports {sys_clk_pad_i}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
diff --git a/systems/de2/data/options.tcl b/systems/de2/data/options.tcl
new file mode 100755
index 00000000..2b66c97e
--- /dev/null
+++ b/systems/de2/data/options.tcl
@@ -0,0 +1,17 @@
+# See Cyclone II FPGA Family Errata, needed for ddual-port dual-clock mode M4K
+# (http://www.altera.com/support/kdb/solutions/fb27180.html)
+
+set_parameter -name CYCLONEII_SAFE_WRITE  "VERIFIED_SAFE"
+
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS_INPUT_TRI_STATED"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+
+# Make it pass STA
+
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
diff --git a/systems/de2/data/pinmap.tcl b/systems/de2/data/pinmap.tcl
new file mode 100755
index 00000000..440485a2
--- /dev/null
+++ b/systems/de2/data/pinmap.tcl
@@ -0,0 +1,208 @@
+# Clock / Reset
+
+set_location_assignment PIN_G26 -to rst_n_pad_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pad_i
+set_location_assignment PIN_N2 -to sys_clk_pad_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i
+
+# SD card
+#set_location_assignment PIN_V20 -to sd_clk_pad_o
+  
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_clk_pad_o
+#set_location_assignment PIN_Y20 -to sd_cmd_pad_o
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_cmd_pad_o
+#set_location_assignment PIN_W20 -to sd_dat_pad_i
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_dat_pad_i
+#set_location_assignment PIN_U20 -to sd_dat3_pad_o
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_dat3_pad_o
+
+# UART
+set_location_assignment PIN_C25 -to uart0_srx_pad_i
+   
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i
+set_location_assignment PIN_B25 -to uart0_stx_pad_o
+  
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o
+
+# SDRAM
+set_location_assignment PIN_T6 -to sdram_a_pad_o[0]
+      
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[0]
+set_location_assignment PIN_V4 -to sdram_a_pad_o[1]
+       
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[1]
+set_location_assignment PIN_V3 -to sdram_a_pad_o[2]
+       
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[2]
+set_location_assignment PIN_W2 -to sdram_a_pad_o[3]
+      
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[3]
+set_location_assignment PIN_W1 -to sdram_a_pad_o[4]
+     	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[4]
+set_location_assignment PIN_U6 -to sdram_a_pad_o[5]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[5]
+set_location_assignment PIN_U7 -to sdram_a_pad_o[6]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[6]
+set_location_assignment PIN_U5 -to sdram_a_pad_o[7]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[7]
+set_location_assignment PIN_W4 -to sdram_a_pad_o[8]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[8]
+set_location_assignment PIN_W3 -to sdram_a_pad_o[9]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[9]
+set_location_assignment PIN_Y1 -to sdram_a_pad_o[10]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[10]
+set_location_assignment PIN_V5 -to sdram_a_pad_o[11]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[11]
+
+set_location_assignment PIN_V6 -to sdram_dq_pad_io[0]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[0]
+set_location_assignment PIN_AA2 -to sdram_dq_pad_io[1]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[1]
+set_location_assignment PIN_AA1 -to sdram_dq_pad_io[2]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[2]
+set_location_assignment PIN_Y3 -to sdram_dq_pad_io[3]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[3]
+set_location_assignment PIN_Y4 -to sdram_dq_pad_io[4]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[4]
+set_location_assignment PIN_R8 -to sdram_dq_pad_io[5]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[5]
+set_location_assignment PIN_T8 -to sdram_dq_pad_io[6]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[6]
+set_location_assignment PIN_V7 -to sdram_dq_pad_io[7]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[7]
+set_location_assignment PIN_W6 -to sdram_dq_pad_io[8]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[8]
+set_location_assignment PIN_AB2 -to sdram_dq_pad_io[9]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[9]
+set_location_assignment PIN_AB1 -to sdram_dq_pad_io[10]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[10]
+set_location_assignment PIN_AA4 -to sdram_dq_pad_io[11]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[11]
+set_location_assignment PIN_AA3 -to sdram_dq_pad_io[12]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[12]
+set_location_assignment PIN_AC2 -to sdram_dq_pad_io[13]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[13]
+set_location_assignment PIN_AC1 -to sdram_dq_pad_io[14]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[14]
+set_location_assignment PIN_AA5 -to sdram_dq_pad_io[15]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[15]
+
+set_location_assignment PIN_AD2 -to sdram_dqm_pad_o[0]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[0]
+set_location_assignment PIN_Y5 -to sdram_dqm_pad_o[1]
+	
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[1]
+
+set_location_assignment PIN_AE2 -to sdram_ba_pad_o[0]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[0]
+set_location_assignment PIN_AE3 -to sdram_ba_pad_o[1]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[1]
+
+set_location_assignment PIN_AB3 -to sdram_cas_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cas_pad_o
+
+set_location_assignment PIN_AA6 -to sdram_cke_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cke_pad_o
+
+set_location_assignment PIN_AC3 -to sdram_cs_n_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cs_n_pad_o
+
+set_location_assignment PIN_AB4 -to sdram_ras_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ras_pad_o
+
+set_location_assignment PIN_AD3 -to sdram_we_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_we_pad_o
+
+set_location_assignment PIN_AA7 -to sdram_clk_pad_o
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_clk_pad_o
+
+# RED LED
+set_location_assignment PIN_AE23 -to led_r_pad_o[0]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[0]
+set_location_assignment PIN_AF23 -to led_r_pad_o[1]
+			
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[1]
+set_location_assignment PIN_AB21 -to led_r_pad_o[2]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[2]
+set_location_assignment PIN_AC22 -to led_r_pad_o[3]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[3]
+set_location_assignment PIN_AD22 -to led_r_pad_o[4]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[4]
+set_location_assignment PIN_AD23 -to led_r_pad_o[5]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[5]
+set_location_assignment PIN_AD21 -to led_r_pad_o[6]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[6]
+set_location_assignment PIN_AC21 -to led_r_pad_o[7]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[7]
+set_location_assignment PIN_AA14 -to led_r_pad_o[8]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[8]
+set_location_assignment PIN_Y13 -to led_r_pad_o[9]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[9]
+
+# GREEN LED
+set_location_assignment PIN_AE22 -to gpio0_io[0]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[0]
+set_location_assignment PIN_AF22 -to gpio0_io[1]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[1]
+set_location_assignment PIN_W19 -to gpio0_io[2]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[2]
+set_location_assignment PIN_V18 -to gpio0_io[3]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[3]
+set_location_assignment PIN_U18 -to gpio0_io[4]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[4]
+set_location_assignment PIN_U17 -to gpio0_io[5]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[5]
+set_location_assignment PIN_AA20 -to gpio0_io[6]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[6]
+set_location_assignment PIN_Y18 -to gpio0_io[7]
+		
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[7]
diff --git a/systems/de2/data/wb_intercon.conf b/systems/de2/data/wb_intercon.conf
new file mode 100755
index 00000000..0fe144fc
--- /dev/null
+++ b/systems/de2/data/wb_intercon.conf
@@ -0,0 +1,43 @@
+; or1k instruction bus master
+[master or1k_i]
+slaves =
+ sdram_ibus
+ rom0
+
+; or1k data bus master
+[master or1k_d]
+slaves =
+ sdram_dbus
+ uart0
+ gpio0
+
+; debug master
+[master dbg]
+slaves =
+ sdram_dbus
+ uart0
+ gpio0
+
+[slave uart0]
+datawidth=8
+offset=0x90000000
+size=32
+
+[slave gpio0]
+datawidth=8
+offset=0x91000000
+size=2
+
+[slave rom0]
+offset=0xf0000100
+size=64
+
+; SDRAM
+; Have several ports with buffering features,
+; so we split each port into a seperate slave
+[slave sdram_dbus]
+offset=0
+size=0x2000000 ; 32MB
+[slave sdram_ibus]
+offset=0
+size=0x2000000 ; 32MB
diff --git a/systems/de2/de2.core b/systems/de2/de2.core
new file mode 100755
index 00000000..918bf988
--- /dev/null
+++ b/systems/de2/de2.core
@@ -0,0 +1,44 @@
+CAPI=1
+[main]
+depend =
+ jtag_tap
+ wb_intercon
+ adv_debug_sys
+ or1200
+ uart16550
+ or1k-elf-loader
+ vlog_tb_utils
+ jtag_vpi
+ wiredelay
+ wb_sdram_ctrl
+ mor1kx
+ mt48lc16m16a2
+ gpio
+ altera_virtual_jtag
+
+simulators =
+ icarus
+ modelsim
+
+[verilog]
+src_files = 
+ rtl/verilog/clkgen.v
+ rtl/verilog/orpsoc_top.v
+ backend/rtl/verilog/pll.v
+ rtl/verilog/rom.v
+ rtl/verilog/wb_intercon.v
+
+
+include_files =
+ rtl/verilog/include/or1200_defines.v
+ rtl/verilog/include/orpsoc-defines.v
+ rtl/verilog/include/timescale.v
+ rtl/verilog/include/uart_defines.v
+ rtl/verilog/wb_intercon.vh
+
+[icarus]
+iverilog_options = -DICARUS_SIM -DSIM
+
+[modelsim]
+vlog_options = +define+SIM +define+MODELSIM_SIM
+vsim_options = -L altera_mf_ver -L altera_mf
diff --git a/systems/de2/de2.system b/systems/de2/de2.system
new file mode 100755
index 00000000..7d48909b
--- /dev/null
+++ b/systems/de2/de2.system
@@ -0,0 +1,15 @@
+SAPI=1
+[main]
+name = de2
+description = "Altera de2 board OpenRISC system"
+
+backend = quartus
+
+[quartus]
+family = "Cyclone II"
+device = EP2C35F672C6
+sdc_files = data/de2.sdc
+tcl_files = data/pinmap.tcl
+            data/options.tcl
+
+
diff --git a/systems/de2/rtl/verilog/clkgen.v b/systems/de2/rtl/verilog/clkgen.v
new file mode 100755
index 00000000..08dd6278
--- /dev/null
+++ b/systems/de2/rtl/verilog/clkgen.v
@@ -0,0 +1,128 @@
+//////////////////////////////////////////////////////////////////////
+//
+// clkgen
+//
+// Handles clock and reset generation for rest of design
+//
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+`include "orpsoc-defines.v"
+
+module clkgen
+(
+	// Main clocks in, depending on board
+	input	sys_clk_pad_i,
+	// Asynchronous, active low reset in
+	input	rst_n_pad_i,
+	// Input reset - through a buffer, asynchronous
+	output	async_rst_o,
+
+	// Wishbone clock and reset out
+	output	wb_clk_o,
+	output	wb_rst_o,
+
+	// JTAG clock
+`ifdef SIM
+	input	tck_pad_i,
+	output	dbg_tck_o,
+`endif
+
+	// Main memory clocks
+	output	sdram_clk_o,
+	output	sdram_rst_o
+);
+
+// First, deal with the asychronous reset
+wire	async_rst;
+wire	async_rst_n;
+
+assign	async_rst_n  = rst_n_pad_i;
+assign	async_rst  = ~async_rst_n;
+
+// Everyone likes active-high reset signals...
+assign	async_rst_o = ~async_rst_n;
+
+`ifdef SIM
+assign	dbg_tck_o = tck_pad_i;
+`endif
+
+//
+// Declare synchronous reset wires here
+//
+
+// An active-low synchronous reset signal (usually a PLL lock signal)
+wire	sync_rst_n;
+
+wire	pll_lock;
+
+`ifndef SIM
+pll pll0 (
+	.areset	(async_rst),
+	.inclk0	(sys_clk_pad_i),
+	.c0	(sdram_clk_o),
+	.c1	(wb_clk_o),
+	.locked	(pll_lock)
+);
+`else
+assign sdram_clk_o = sys_clk_pad_i;
+assign wb_clk_o = sys_clk_pad_i;
+assign pll_lock = 1'b1;
+`endif
+
+assign sync_rst_n = pll_lock;
+
+//
+// Reset generation
+//
+//
+
+// Reset generation for wishbone
+reg [15:0]	wb_rst_shr;
+
+always @(posedge wb_clk_o or posedge async_rst)
+	if (async_rst)
+		wb_rst_shr <= 16'hffff;
+	else
+		wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
+
+assign wb_rst_o = wb_rst_shr[15];
+
+// Reset generation for SDRAM controller
+reg [15:0]	sdram_rst_shr;
+
+always @(posedge sdram_clk_o or posedge async_rst)
+	if (async_rst)
+		sdram_rst_shr <= 16'hffff;
+	else
+		sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};
+
+assign sdram_rst_o = sdram_rst_shr[15];
+
+endmodule // clkgen
diff --git a/systems/de2/rtl/verilog/include/or1200_defines.v b/systems/de2/rtl/verilog/include/or1200_defines.v
new file mode 100755
index 00000000..840f66f6
--- /dev/null
+++ b/systems/de2/rtl/verilog/include/or1200_defines.v
@@ -0,0 +1,1824 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  OR1200's definitions                                        ////
+////                                                              ////
+////  This file is part of the OpenRISC 1200 project              ////
+////  http://opencores.org/project,or1k                           ////
+////                                                              ////
+////  Description                                                 ////
+////  Defines for the OR1200 core                                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////   - add parameters that are missing                          ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Damjan Lampret, lampret@opencores.org                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Log: or1200_defines.v,v $
+// Revision 2.0  2010/06/30 11:00:00  ORSoC
+// Minor update: 
+// Defines added, bugs fixed. 
+
+//
+// Dump VCD
+//
+//`define OR1200_VCD_DUMP
+
+//
+// Generate debug messages during simulation
+//
+//`define OR1200_VERBOSE
+
+//  `define OR1200_ASIC
+////////////////////////////////////////////////////////
+//
+// Typical configuration for an ASIC
+//
+`ifdef OR1200_ASIC
+
+//
+// Target ASIC memories
+//
+//`define OR1200_ARTISAN_SSP
+//`define OR1200_ARTISAN_SDP
+//`define OR1200_ARTISAN_STP
+`define OR1200_VIRTUALSILICON_SSP
+//`define OR1200_VIRTUALSILICON_STP_T1
+//`define OR1200_VIRTUALSILICON_STP_T2
+
+//
+// Do not implement Data cache
+//
+//`define OR1200_NO_DC
+
+//
+// Do not implement Insn cache
+//
+//`define OR1200_NO_IC
+
+//
+// Do not implement Data MMU
+//
+//`define OR1200_NO_DMMU
+
+//
+// Do not implement Insn MMU
+//
+//`define OR1200_NO_IMMU
+
+//
+// Select between ASIC optimized and generic multiplier
+//
+//`define OR1200_ASIC_MULTP2_32X32
+`define OR1200_GENERIC_MULTP2_32X32
+
+//
+// Size/type of insn/data cache if implemented
+//
+// `define OR1200_IC_1W_512B
+// `define OR1200_IC_1W_4KB
+`define OR1200_IC_1W_8KB
+// `define OR1200_DC_1W_4KB
+`define OR1200_DC_1W_8KB
+
+`else
+
+
+/////////////////////////////////////////////////////////
+//
+// Typical configuration for an FPGA
+//
+
+//
+// Target FPGA memories
+//
+`define OR1200_ALTERA_LPM
+//`define OR1200_XILINX_RAMB16
+//`define OR1200_XILINX_RAMB4
+//`define OR1200_XILINX_RAM32X1D
+//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
+// Generic models should infer RAM blocks at synthesis time (not only effects 
+// single port ram.)
+//`define OR1200_GENERIC
+
+//
+// Do not implement Data cache
+//
+//`define OR1200_NO_DC
+
+//
+// Do not implement Insn cache
+//
+//`define OR1200_NO_IC
+
+//
+// Do not implement Data MMU
+//
+//`define OR1200_NO_DMMU
+
+//
+// Do not implement Insn MMU
+//
+//`define OR1200_NO_IMMU
+
+//
+// Select between ASIC and generic multiplier
+//
+// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
+//
+//`define OR1200_ASIC_MULTP2_32X32
+`define OR1200_GENERIC_MULTP2_32X32
+
+//
+// Size/type of insn/data cache if implemented
+// (consider available FPGA memory resources)
+//
+//`define OR1200_IC_1W_512B
+`define OR1200_IC_1W_4KB
+//`define OR1200_IC_1W_8KB
+//`define OR1200_IC_1W_16KB
+//`define OR1200_IC_1W_32KB
+`define OR1200_DC_1W_4KB
+//`define OR1200_DC_1W_8KB
+//`define OR1200_DC_1W_16KB
+//`define OR1200_DC_1W_32KB
+
+`endif
+
+
+//////////////////////////////////////////////////////////
+//
+// Do not change below unless you know what you are doing
+//
+
+//
+// Reset active low
+//
+//`define OR1200_RST_ACT_LOW
+
+//
+// Enable RAM BIST
+//
+// At the moment this only works for Virtual Silicon
+// single port RAMs. For other RAMs it has not effect.
+// Special wrapper for VS RAMs needs to be provided
+// with scan flops to facilitate bist scan.
+//
+//`define OR1200_BIST
+
+//
+// Register OR1200 WISHBONE outputs
+// (must be defined/enabled)
+//
+`define OR1200_REGISTERED_OUTPUTS
+
+//
+// Register OR1200 WISHBONE inputs
+//
+// (must be undefined/disabled)
+//
+//`define OR1200_REGISTERED_INPUTS
+
+//
+// Disable bursts if they are not supported by the
+// memory subsystem (only affect cache line fill)
+//
+//`define OR1200_NO_BURSTS
+//
+
+//
+// WISHBONE retry counter range
+//
+// 2^value range for retry counter. Retry counter
+// is activated whenever *wb_rty_i is asserted and
+// until retry counter expires, corresponding
+// WISHBONE interface is deactivated.
+//
+// To disable retry counters and *wb_rty_i all together,
+// undefine this macro.
+//
+//`define OR1200_WB_RETRY 7
+
+//
+// WISHBONE Consecutive Address Burst
+//
+// This was used prior to WISHBONE B3 specification
+// to identify bursts. It is no longer needed but
+// remains enabled for compatibility with old designs.
+//
+// To remove *wb_cab_o ports undefine this macro.
+//
+//`define OR1200_WB_CAB
+
+//
+// WISHBONE B3 compatible interface
+//
+// This follows the WISHBONE B3 specification.
+// It is not enabled by default because most
+// designs still don't use WB b3.
+//
+// To enable *wb_cti_o/*wb_bte_o ports,
+// define this macro.
+//
+`define OR1200_WB_B3
+
+//
+// LOG all WISHBONE accesses
+//
+`define OR1200_LOG_WB_ACCESS
+
+//
+// Enable additional synthesis directives if using
+// _Synopsys_ synthesis tool
+//
+//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
+
+//
+// Enables default statement in some case blocks
+// and disables Synopsys synthesis directive full_case
+//
+// By default it is enabled. When disabled it
+// can increase clock frequency.
+//
+`define OR1200_CASE_DEFAULT
+
+//
+// Operand width / register file address width
+//
+// (DO NOT CHANGE)
+//
+`define OR1200_OPERAND_WIDTH		32
+`define OR1200_REGFILE_ADDR_WIDTH	5
+
+//
+// l.add/l.addi/l.and and optional l.addc/l.addic
+// also set (compare) flag when result of their
+// operation equals zero
+//
+// At the time of writing this, default or32
+// C/C++ compiler doesn't generate code that
+// would benefit from this optimization.
+//
+// By default this optimization is disabled to
+// save area.
+//
+//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
+
+//
+// Implement l.addc/l.addic instructions
+//
+// By default implementation of l.addc/l.addic
+// instructions is enabled in case you need them.
+// If you don't use them, then disable implementation
+// to save area.
+//
+//`define OR1200_IMPL_ADDC
+
+//
+// Implement l.sub instruction
+//
+// By default implementation of l.sub instructions
+// is enabled to be compliant with the simulator.
+// If you don't use carry bit, then disable
+// implementation to save area.
+//
+`define OR1200_IMPL_SUB
+
+//
+// Implement carry bit SR[CY]
+//
+//
+// By default implementation of SR[CY] is enabled
+// to be compliant with the simulator. However SR[CY]
+// is explicitly only used by l.addc/l.addic/l.sub
+// instructions and if these three insns are not
+// implemented there is not much point having SR[CY].
+//
+//`define OR1200_IMPL_CY
+
+//
+// Implement carry bit SR[OV]
+//
+// Compiler doesn't use this, but other code may like
+// to.
+//
+//`define OR1200_IMPL_OV
+
+//
+// Implement carry bit SR[OVE]
+//
+// Overflow interrupt indicator. When enabled, SR[OV] flag
+// does not remain asserted after exception.
+//
+//`define OR1200_IMPL_OVE
+
+
+//
+// Implement rotate in the ALU
+//
+// At the time of writing this, or32
+// C/C++ compiler doesn't generate rotate
+// instructions. However or32 assembler
+// can assemble code that uses rotate insn.
+// This means that rotate instructions
+// must be used manually inserted.
+//
+// By default implementation of rotate
+// is disabled to save area and increase
+// clock frequency.
+//
+//`define OR1200_IMPL_ALU_ROTATE
+
+//
+// Type of ALU compare to implement
+//
+// Try either one to find what yields
+// higher clock frequencyin your case.
+//
+//`define OR1200_IMPL_ALU_COMP1
+`define OR1200_IMPL_ALU_COMP2
+//`define OR1200_IMPL_ALU_COMP3
+
+//
+// Implement Find First/Last '1'
+//
+`define OR1200_IMPL_ALU_FFL1
+
+//
+// Implement l.cust5 ALU instruction
+//
+//`define OR1200_IMPL_ALU_CUST5
+
+//
+// Implement l.extXs and l.extXz instructions
+//
+//`define OR1200_IMPL_ALU_EXT
+
+//
+// Implement multiplier
+//
+// By default multiplier is implemented
+//
+`define OR1200_MULT_IMPLEMENTED
+
+//
+// Implement multiply-and-accumulate
+//
+// By default MAC is implemented. To
+// implement MAC, multiplier (non-serial) needs to be
+// implemented.
+//
+//`define OR1200_MAC_IMPLEMENTED
+
+//
+// Implement optional l.div/l.divu instructions
+//
+// By default divide instructions are not implemented
+// to save area.
+//
+//
+`define OR1200_DIV_IMPLEMENTED
+
+//
+// Serial multiplier.
+//
+`define OR1200_MULT_SERIAL
+
+//
+// Serial divider.
+// Uncomment to use a serial divider, otherwise will
+// be a generic parallel implementation.
+//
+`define OR1200_DIV_SERIAL
+
+//
+// Implement HW Single Precision FPU
+//
+//`define OR1200_FPU_IMPLEMENTED
+
+//
+// Clock ratio RISC clock versus WB clock
+//
+// If you plan to run WB:RISC clock fixed to 1:1, disable
+// both defines
+//
+// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
+// and use clmode to set ratio
+//
+// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
+// clmode to set ratio
+//
+//`define OR1200_CLKDIV_2_SUPPORTED
+//`define OR1200_CLKDIV_4_SUPPORTED
+
+//
+// Type of register file RAM
+//
+// Memory macro w/ two ports (see or1200_tpram_32x32.v)
+//`define OR1200_RFRAM_TWOPORT
+//
+// Memory macro dual port (see or1200_dpram.v)
+`define OR1200_RFRAM_DUALPORT
+
+//
+// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
+//`define OR1200_RFRAM_GENERIC
+//  Generic register file supports - 16 registers 
+`ifdef OR1200_RFRAM_GENERIC
+//    `define OR1200_RFRAM_16REG
+`endif
+
+//
+// Type of mem2reg aligner to implement.
+//
+// Once OR1200_IMPL_MEM2REG2 yielded faster
+// circuit, however with today tools it will
+// most probably give you slower circuit.
+//
+`define OR1200_IMPL_MEM2REG1
+//`define OR1200_IMPL_MEM2REG2
+
+//
+// Reset value and event
+//
+`ifdef OR1200_RST_ACT_LOW
+  `define OR1200_RST_VALUE      (1'b0)
+  `define OR1200_RST_EVENT      negedge
+`else
+  `define OR1200_RST_VALUE      (1'b1)
+  `define OR1200_RST_EVENT      posedge
+`endif
+
+//
+// ALUOPs
+//
+`define OR1200_ALUOP_WIDTH	5
+`define OR1200_ALUOP_NOP	5'b0_0100
+/* LS-nibble encodings correspond to bits [3:0] of instruction */
+`define OR1200_ALUOP_ADD	5'b0_0000 // 0
+`define OR1200_ALUOP_ADDC	5'b0_0001 // 1
+`define OR1200_ALUOP_SUB	5'b0_0010 // 2
+`define OR1200_ALUOP_AND	5'b0_0011 // 3
+`define OR1200_ALUOP_OR		5'b0_0100 // 4
+`define OR1200_ALUOP_XOR	5'b0_0101 // 5
+`define OR1200_ALUOP_MUL	5'b0_0110 // 6
+`define OR1200_ALUOP_RESERVED	5'b0_0111 // 7
+`define OR1200_ALUOP_SHROT	5'b0_1000 // 8
+`define OR1200_ALUOP_DIV	5'b0_1001 // 9
+`define OR1200_ALUOP_DIVU	5'b0_1010 // a
+`define OR1200_ALUOP_MULU	5'b0_1011 // b
+`define OR1200_ALUOP_EXTHB	5'b0_1100 // c
+`define OR1200_ALUOP_EXTW	5'b0_1101 // d
+`define OR1200_ALUOP_CMOV	5'b0_1110 // e
+`define OR1200_ALUOP_FFL1	5'b0_1111 // f
+
+/* Values sent to ALU from decode unit - not defined by ISA */
+`define OR1200_ALUOP_COMP       5'b1_0000 // Comparison
+`define OR1200_ALUOP_MOVHI      5'b1_0001 // Move-high
+`define OR1200_ALUOP_CUST5	5'b1_0010 // l.cust5
+
+// ALU instructions second opcode field
+`define OR1200_ALUOP2_POS	9:6
+`define OR1200_ALUOP2_WIDTH	4
+
+//
+// MACOPs
+//
+`define OR1200_MACOP_WIDTH	3
+`define OR1200_MACOP_NOP	3'b000
+`define OR1200_MACOP_MAC	3'b001
+`define OR1200_MACOP_MSB	3'b010
+
+//
+// Shift/rotate ops
+//
+`define OR1200_SHROTOP_WIDTH	4
+`define OR1200_SHROTOP_NOP	4'd0
+`define OR1200_SHROTOP_SLL	4'd0
+`define OR1200_SHROTOP_SRL	4'd1
+`define OR1200_SHROTOP_SRA	4'd2
+`define OR1200_SHROTOP_ROR	4'd3
+
+//
+// Zero/Sign Extend ops
+//
+`define OR1200_EXTHBOP_WIDTH      4
+`define OR1200_EXTHBOP_BS         4'h1
+`define OR1200_EXTHBOP_HS         4'h0
+`define OR1200_EXTHBOP_BZ         4'h3
+`define OR1200_EXTHBOP_HZ         4'h2
+`define OR1200_EXTWOP_WIDTH       4
+`define OR1200_EXTWOP_WS          4'h0
+`define OR1200_EXTWOP_WZ          4'h1
+
+// Execution cycles per instruction
+`define OR1200_MULTICYCLE_WIDTH	3
+`define OR1200_ONE_CYCLE		3'd0
+`define OR1200_TWO_CYCLES		3'd1
+
+// Execution control which will "wait on" a module to finish
+`define OR1200_WAIT_ON_WIDTH 2
+`define OR1200_WAIT_ON_NOTHING    `OR1200_WAIT_ON_WIDTH'd0
+`define OR1200_WAIT_ON_MULTMAC    `OR1200_WAIT_ON_WIDTH'd1
+`define OR1200_WAIT_ON_FPU        `OR1200_WAIT_ON_WIDTH'd2
+`define OR1200_WAIT_ON_MTSPR      `OR1200_WAIT_ON_WIDTH'd3
+
+
+// Operand MUX selects
+`define OR1200_SEL_WIDTH		2
+`define OR1200_SEL_RF			2'd0
+`define OR1200_SEL_IMM			2'd1
+`define OR1200_SEL_EX_FORW		2'd2
+`define OR1200_SEL_WB_FORW		2'd3
+
+//
+// BRANCHOPs
+//
+`define OR1200_BRANCHOP_WIDTH		3
+`define OR1200_BRANCHOP_NOP		3'd0
+`define OR1200_BRANCHOP_J		3'd1
+`define OR1200_BRANCHOP_JR		3'd2
+`define OR1200_BRANCHOP_BAL		3'd3
+`define OR1200_BRANCHOP_BF		3'd4
+`define OR1200_BRANCHOP_BNF		3'd5
+`define OR1200_BRANCHOP_RFE		3'd6
+
+//
+// LSUOPs
+//
+// Bit 0: sign extend
+// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
+// Bit 3: 0 load, 1 store
+`define OR1200_LSUOP_WIDTH		4
+`define OR1200_LSUOP_NOP		4'b0000
+`define OR1200_LSUOP_LBZ		4'b0010
+`define OR1200_LSUOP_LBS		4'b0011
+`define OR1200_LSUOP_LHZ		4'b0100
+`define OR1200_LSUOP_LHS		4'b0101
+`define OR1200_LSUOP_LWZ		4'b0110
+`define OR1200_LSUOP_LWS		4'b0111
+`define OR1200_LSUOP_LD			4'b0001
+`define OR1200_LSUOP_SD			4'b1000
+`define OR1200_LSUOP_SB			4'b1010
+`define OR1200_LSUOP_SH			4'b1100
+`define OR1200_LSUOP_SW			4'b1110
+
+// Number of bits of load/store EA precalculated in ID stage
+// for balancing ID and EX stages.
+//
+// Valid range: 2,3,...,30,31
+`define OR1200_LSUEA_PRECALC		2
+
+// FETCHOPs
+`define OR1200_FETCHOP_WIDTH		1
+`define OR1200_FETCHOP_NOP		1'b0
+`define OR1200_FETCHOP_LW		1'b1
+
+//
+// Register File Write-Back OPs
+//
+// Bit 0: register file write enable
+// Bits 3-1: write-back mux selects
+//
+`define OR1200_RFWBOP_WIDTH		4
+`define OR1200_RFWBOP_NOP		4'b0000
+`define OR1200_RFWBOP_ALU		3'b000
+`define OR1200_RFWBOP_LSU		3'b001
+`define OR1200_RFWBOP_SPRS		3'b010
+`define OR1200_RFWBOP_LR		3'b011
+`define OR1200_RFWBOP_FPU		3'b100
+
+// Compare instructions
+`define OR1200_COP_SFEQ       3'b000
+`define OR1200_COP_SFNE       3'b001
+`define OR1200_COP_SFGT       3'b010
+`define OR1200_COP_SFGE       3'b011
+`define OR1200_COP_SFLT       3'b100
+`define OR1200_COP_SFLE       3'b101
+`define OR1200_COP_X          3'b111
+`define OR1200_SIGNED_COMPARE 'd3
+`define OR1200_COMPOP_WIDTH	4
+
+//
+// FP OPs
+//
+// MSbit indicates FPU operation valid
+//
+`define OR1200_FPUOP_WIDTH	8
+// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
+`define OR1200_FPUOP_CYCLES 3'd4
+// FP instruction is double precision if bit 4 is set. We're a 32-bit 
+// implementation thus do not support double precision FP 
+`define OR1200_FPUOP_DOUBLE_BIT 4
+`define OR1200_FPUOP_ADD  8'b0000_0000
+`define OR1200_FPUOP_SUB  8'b0000_0001
+`define OR1200_FPUOP_MUL  8'b0000_0010
+`define OR1200_FPUOP_DIV  8'b0000_0011
+`define OR1200_FPUOP_ITOF 8'b0000_0100
+`define OR1200_FPUOP_FTOI 8'b0000_0101
+`define OR1200_FPUOP_REM  8'b0000_0110
+`define OR1200_FPUOP_RESERVED  8'b0000_0111
+// FP Compare instructions
+`define OR1200_FPCOP_SFEQ 8'b0000_1000
+`define OR1200_FPCOP_SFNE 8'b0000_1001
+`define OR1200_FPCOP_SFGT 8'b0000_1010
+`define OR1200_FPCOP_SFGE 8'b0000_1011
+`define OR1200_FPCOP_SFLT 8'b0000_1100
+`define OR1200_FPCOP_SFLE 8'b0000_1101
+
+//
+// TAGs for instruction bus
+//
+`define OR1200_ITAG_IDLE	4'h0	// idle bus
+`define	OR1200_ITAG_NI		4'h1	// normal insn
+`define OR1200_ITAG_BE		4'hb	// Bus error exception
+`define OR1200_ITAG_PE		4'hc	// Page fault exception
+`define OR1200_ITAG_TE		4'hd	// TLB miss exception
+
+//
+// TAGs for data bus
+//
+`define OR1200_DTAG_IDLE	4'h0	// idle bus
+`define	OR1200_DTAG_ND		4'h1	// normal data
+`define OR1200_DTAG_AE		4'ha	// Alignment exception
+`define OR1200_DTAG_BE		4'hb	// Bus error exception
+`define OR1200_DTAG_PE		4'hc	// Page fault exception
+`define OR1200_DTAG_TE		4'hd	// TLB miss exception
+
+
+//////////////////////////////////////////////
+//
+// ORBIS32 ISA specifics
+//
+
+// SHROT_OP position in machine word
+`define OR1200_SHROTOP_POS		7:6
+
+//
+// Instruction opcode groups (basic)
+//
+`define OR1200_OR32_J                 6'b000000
+`define OR1200_OR32_JAL               6'b000001
+`define OR1200_OR32_BNF               6'b000011
+`define OR1200_OR32_BF                6'b000100
+`define OR1200_OR32_NOP               6'b000101
+`define OR1200_OR32_MOVHI             6'b000110
+`define OR1200_OR32_MACRC             6'b000110
+`define OR1200_OR32_XSYNC             6'b001000
+`define OR1200_OR32_RFE               6'b001001
+/* */
+`define OR1200_OR32_JR                6'b010001
+`define OR1200_OR32_JALR              6'b010010
+`define OR1200_OR32_MACI              6'b010011
+/* */
+`define OR1200_OR32_LWZ               6'b100001
+`define OR1200_OR32_LWS               6'b100010
+`define OR1200_OR32_LBZ               6'b100011
+`define OR1200_OR32_LBS               6'b100100
+`define OR1200_OR32_LHZ               6'b100101
+`define OR1200_OR32_LHS               6'b100110
+`define OR1200_OR32_ADDI              6'b100111
+`define OR1200_OR32_ADDIC             6'b101000
+`define OR1200_OR32_ANDI              6'b101001
+`define OR1200_OR32_ORI               6'b101010
+`define OR1200_OR32_XORI              6'b101011
+`define OR1200_OR32_MULI              6'b101100
+`define OR1200_OR32_MFSPR             6'b101101
+`define OR1200_OR32_SH_ROTI 	      6'b101110
+`define OR1200_OR32_SFXXI             6'b101111
+/* */
+`define OR1200_OR32_MTSPR             6'b110000
+`define OR1200_OR32_MACMSB            6'b110001
+`define OR1200_OR32_FLOAT             6'b110010
+/* */
+`define OR1200_OR32_SW                6'b110101
+`define OR1200_OR32_SB                6'b110110
+`define OR1200_OR32_SH                6'b110111
+`define OR1200_OR32_ALU               6'b111000
+`define OR1200_OR32_SFXX              6'b111001
+`define OR1200_OR32_CUST5             6'b111100
+
+/////////////////////////////////////////////////////
+//
+// Exceptions
+//
+
+//
+// Exception vectors per OR1K architecture:
+// 0xPPPPP100 - reset
+// 0xPPPPP200 - bus error
+// ... etc
+// where P represents exception prefix.
+//
+// Exception vectors can be customized as per
+// the following formula:
+// 0xPPPPPNVV - exception N
+//
+// P represents exception prefix
+// N represents exception N
+// VV represents length of the individual vector space,
+//   usually it is 8 bits wide and starts with all bits zero
+//
+
+//
+// PPPPP and VV parts
+//
+// Sum of these two defines needs to be 28
+//
+`define OR1200_EXCEPT_EPH0_P    20'h00000
+`define OR1200_EXCEPT_EPH1_P    20'hF0000
+`define OR1200_EXCEPT_V		    8'h00
+
+//
+// N part width
+//
+`define OR1200_EXCEPT_WIDTH 4
+
+//
+// Definition of exception vectors
+//
+// To avoid implementation of a certain exception,
+// simply comment out corresponding line
+//
+`define OR1200_EXCEPT_UNUSED		`OR1200_EXCEPT_WIDTH'hf
+`define OR1200_EXCEPT_TRAP		`OR1200_EXCEPT_WIDTH'he
+`define OR1200_EXCEPT_FLOAT		`OR1200_EXCEPT_WIDTH'hd
+`define OR1200_EXCEPT_SYSCALL		`OR1200_EXCEPT_WIDTH'hc
+`define OR1200_EXCEPT_RANGE		`OR1200_EXCEPT_WIDTH'hb
+`define OR1200_EXCEPT_ITLBMISS		`OR1200_EXCEPT_WIDTH'ha
+`define OR1200_EXCEPT_DTLBMISS		`OR1200_EXCEPT_WIDTH'h9
+`define OR1200_EXCEPT_INT		`OR1200_EXCEPT_WIDTH'h8
+`define OR1200_EXCEPT_ILLEGAL		`OR1200_EXCEPT_WIDTH'h7
+`define OR1200_EXCEPT_ALIGN		`OR1200_EXCEPT_WIDTH'h6
+`define OR1200_EXCEPT_TICK		`OR1200_EXCEPT_WIDTH'h5
+`define OR1200_EXCEPT_IPF		`OR1200_EXCEPT_WIDTH'h4
+`define OR1200_EXCEPT_DPF		`OR1200_EXCEPT_WIDTH'h3
+`define OR1200_EXCEPT_BUSERR		`OR1200_EXCEPT_WIDTH'h2
+`define OR1200_EXCEPT_RESET		`OR1200_EXCEPT_WIDTH'h1
+`define OR1200_EXCEPT_NONE		`OR1200_EXCEPT_WIDTH'h0
+
+
+/////////////////////////////////////////////////////
+//
+// SPR groups
+//
+
+// Bits that define the group
+`define OR1200_SPR_GROUP_BITS	15:11
+
+// Width of the group bits
+`define OR1200_SPR_GROUP_WIDTH 	5
+
+// Bits that define offset inside the group
+`define OR1200_SPR_OFS_BITS 10:0
+
+// List of groups
+`define OR1200_SPR_GROUP_SYS	5'd00
+`define OR1200_SPR_GROUP_DMMU	5'd01
+`define OR1200_SPR_GROUP_IMMU	5'd02
+`define OR1200_SPR_GROUP_DC	5'd03
+`define OR1200_SPR_GROUP_IC	5'd04
+`define OR1200_SPR_GROUP_MAC	5'd05
+`define OR1200_SPR_GROUP_DU	5'd06
+`define OR1200_SPR_GROUP_PM	5'd08
+`define OR1200_SPR_GROUP_PIC	5'd09
+`define OR1200_SPR_GROUP_TT	5'd10
+`define OR1200_SPR_GROUP_FPU    5'd11
+
+/////////////////////////////////////////////////////
+//
+// System group
+//
+
+//
+// System registers
+//
+`define OR1200_SPR_CFGR		7'd0
+`define OR1200_SPR_RF		6'd32	// 1024 >> 5
+`define OR1200_SPR_NPC		11'd16
+`define OR1200_SPR_SR		11'd17
+`define OR1200_SPR_PPC		11'd18
+`define OR1200_SPR_FPCSR        11'd20
+`define OR1200_SPR_EPCR		11'd32
+`define OR1200_SPR_EEAR		11'd48
+`define OR1200_SPR_ESR		11'd64
+
+//
+// SR bits
+//
+`define OR1200_SR_WIDTH 17
+`define OR1200_SR_SM   0
+`define OR1200_SR_TEE  1
+`define OR1200_SR_IEE  2
+`define OR1200_SR_DCE  3
+`define OR1200_SR_ICE  4
+`define OR1200_SR_DME  5
+`define OR1200_SR_IME  6
+`define OR1200_SR_LEE  7
+`define OR1200_SR_CE   8
+`define OR1200_SR_F    9
+`define OR1200_SR_CY   10	// Optional
+`define OR1200_SR_OV   11	// Optional
+`define OR1200_SR_OVE  12	// Optional
+`define OR1200_SR_DSX  13	// Unused
+`define OR1200_SR_EPH  14
+`define OR1200_SR_FO   15
+`define OR1200_SR_TED  16
+`define OR1200_SR_CID  31:28	// Unimplemented
+
+//
+// Bits that define offset inside the group
+//
+`define OR1200_SPROFS_BITS 10:0
+
+//
+// Default Exception Prefix
+//
+// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
+// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
+//
+`define OR1200_SR_EPH_DEF	1'b0
+
+
+//
+// FPCSR bits
+//
+`define OR1200_FPCSR_WIDTH 12
+`define OR1200_FPCSR_FPEE  0
+`define OR1200_FPCSR_RM    2:1
+`define OR1200_FPCSR_OVF   3
+`define OR1200_FPCSR_UNF   4
+`define OR1200_FPCSR_SNF   5
+`define OR1200_FPCSR_QNF   6
+`define OR1200_FPCSR_ZF    7
+`define OR1200_FPCSR_IXF   8
+`define OR1200_FPCSR_IVF   9
+`define OR1200_FPCSR_INF   10
+`define OR1200_FPCSR_DZF   11
+`define OR1200_FPCSR_RES   31:12
+
+/////////////////////////////////////////////////////
+//
+// Power Management (PM)
+//
+
+// Define it if you want PM implemented
+//`define OR1200_PM_IMPLEMENTED
+
+// Bit positions inside PMR (don't change)
+`define OR1200_PM_PMR_SDF 3:0
+`define OR1200_PM_PMR_DME 4
+`define OR1200_PM_PMR_SME 5
+`define OR1200_PM_PMR_DCGE 6
+`define OR1200_PM_PMR_UNUSED 31:7
+
+// PMR offset inside PM group of registers
+`define OR1200_PM_OFS_PMR 11'b0
+
+// PM group
+`define OR1200_SPRGRP_PM 5'd8
+
+// Define if PMR can be read/written at any address inside PM group
+`define OR1200_PM_PARTIAL_DECODING
+
+// Define if reading PMR is allowed
+`define OR1200_PM_READREGS
+
+// Define if unused PMR bits should be zero
+`define OR1200_PM_UNUSED_ZERO
+
+
+/////////////////////////////////////////////////////
+//
+// Debug Unit (DU)
+//
+
+// Define it if you want DU implemented
+`define OR1200_DU_IMPLEMENTED
+
+//
+// Define if you want HW Breakpoints
+// (if HW breakpoints are not implemented
+// only default software trapping is
+// possible with l.trap insn - this is
+// however already enough for use
+// with or32 gdb)
+//
+//`define OR1200_DU_HWBKPTS
+
+// Number of DVR/DCR pairs if HW breakpoints enabled
+//	Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
+//	DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
+`define OR1200_DU_DVRDCR_PAIRS 8
+
+// Define if you want trace buffer
+//	(for now only available for Xilinx Virtex FPGAs)
+//`define OR1200_DU_TB_IMPLEMENTED
+
+
+//
+// Address offsets of DU registers inside DU group
+//
+// To not implement a register, doq not define its address
+//
+`ifdef OR1200_DU_HWBKPTS
+`define OR1200_DU_DVR0		11'd0
+`define OR1200_DU_DVR1		11'd1
+`define OR1200_DU_DVR2		11'd2
+`define OR1200_DU_DVR3		11'd3
+`define OR1200_DU_DVR4		11'd4
+`define OR1200_DU_DVR5		11'd5
+`define OR1200_DU_DVR6		11'd6
+`define OR1200_DU_DVR7		11'd7
+`define OR1200_DU_DCR0		11'd8
+`define OR1200_DU_DCR1		11'd9
+`define OR1200_DU_DCR2		11'd10
+`define OR1200_DU_DCR3		11'd11
+`define OR1200_DU_DCR4		11'd12
+`define OR1200_DU_DCR5		11'd13
+`define OR1200_DU_DCR6		11'd14
+`define OR1200_DU_DCR7		11'd15
+`endif
+`define OR1200_DU_DMR1		11'd16
+`ifdef OR1200_DU_HWBKPTS
+`define OR1200_DU_DMR2		11'd17
+`define OR1200_DU_DWCR0		11'd18
+`define OR1200_DU_DWCR1		11'd19
+`endif
+`define OR1200_DU_DSR		11'd20
+`define OR1200_DU_DRR		11'd21
+`ifdef OR1200_DU_TB_IMPLEMENTED
+`define OR1200_DU_TBADR		11'h0ff
+`define OR1200_DU_TBIA		11'h1??
+`define OR1200_DU_TBIM		11'h2??
+`define OR1200_DU_TBAR		11'h3??
+`define OR1200_DU_TBTS		11'h4??
+`endif
+
+// Position of offset bits inside SPR address
+`define OR1200_DUOFS_BITS	10:0
+
+// DCR bits
+`define OR1200_DU_DCR_DP	0
+`define OR1200_DU_DCR_CC	3:1
+`define OR1200_DU_DCR_SC	4
+`define OR1200_DU_DCR_CT	7:5
+
+// DMR1 bits
+`define OR1200_DU_DMR1_CW0	1:0
+`define OR1200_DU_DMR1_CW1	3:2
+`define OR1200_DU_DMR1_CW2	5:4
+`define OR1200_DU_DMR1_CW3	7:6
+`define OR1200_DU_DMR1_CW4	9:8
+`define OR1200_DU_DMR1_CW5	11:10
+`define OR1200_DU_DMR1_CW6	13:12
+`define OR1200_DU_DMR1_CW7	15:14
+`define OR1200_DU_DMR1_CW8	17:16
+`define OR1200_DU_DMR1_CW9	19:18
+`define OR1200_DU_DMR1_CW10	21:20
+`define OR1200_DU_DMR1_ST	22
+`define OR1200_DU_DMR1_BT	23
+`define OR1200_DU_DMR1_DXFW	24
+`define OR1200_DU_DMR1_ETE	25
+
+// DMR2 bits
+`define OR1200_DU_DMR2_WCE0	0
+`define OR1200_DU_DMR2_WCE1	1
+`define OR1200_DU_DMR2_AWTC	12:2
+`define OR1200_DU_DMR2_WGB	23:13
+
+// DWCR bits
+`define OR1200_DU_DWCR_COUNT	15:0
+`define OR1200_DU_DWCR_MATCH	31:16
+
+// DSR bits
+`define OR1200_DU_DSR_WIDTH	14
+`define OR1200_DU_DSR_RSTE	0
+`define OR1200_DU_DSR_BUSEE	1
+`define OR1200_DU_DSR_DPFE	2
+`define OR1200_DU_DSR_IPFE	3
+`define OR1200_DU_DSR_TTE	4
+`define OR1200_DU_DSR_AE	5
+`define OR1200_DU_DSR_IIE	6
+`define OR1200_DU_DSR_IE	7
+`define OR1200_DU_DSR_DME	8
+`define OR1200_DU_DSR_IME	9
+`define OR1200_DU_DSR_RE	10
+`define OR1200_DU_DSR_SCE	11
+`define OR1200_DU_DSR_FPE	12
+`define OR1200_DU_DSR_TE	13
+
+// DRR bits
+`define OR1200_DU_DRR_RSTE	0
+`define OR1200_DU_DRR_BUSEE	1
+`define OR1200_DU_DRR_DPFE	2
+`define OR1200_DU_DRR_IPFE	3
+`define OR1200_DU_DRR_TTE	4
+`define OR1200_DU_DRR_AE	5
+`define OR1200_DU_DRR_IIE	6
+`define OR1200_DU_DRR_IE	7
+`define OR1200_DU_DRR_DME	8
+`define OR1200_DU_DRR_IME	9
+`define OR1200_DU_DRR_RE	10
+`define OR1200_DU_DRR_SCE	11
+`define OR1200_DU_DRR_FPE	12
+`define OR1200_DU_DRR_TE	13
+
+// Define if reading DU regs is allowed
+`define OR1200_DU_READREGS
+
+// Define if unused DU registers bits should be zero
+`define OR1200_DU_UNUSED_ZERO
+
+// Define if IF/LSU status is not needed by devel i/f
+`define OR1200_DU_STATUS_UNIMPLEMENTED
+
+/////////////////////////////////////////////////////
+//
+// Programmable Interrupt Controller (PIC)
+//
+
+// Define it if you want PIC implemented
+`define OR1200_PIC_IMPLEMENTED
+
+// Define number of interrupt inputs (2-31)
+`define OR1200_PIC_INTS 31
+
+// Address offsets of PIC registers inside PIC group
+`define OR1200_PIC_OFS_PICMR 2'd0
+`define OR1200_PIC_OFS_PICSR 2'd2
+
+// Position of offset bits inside SPR address
+`define OR1200_PICOFS_BITS 1:0
+
+// Define if you want these PIC registers to be implemented
+`define OR1200_PIC_PICMR
+`define OR1200_PIC_PICSR
+
+// Define if reading PIC registers is allowed
+`define OR1200_PIC_READREGS
+
+// Define if unused PIC register bits should be zero
+`define OR1200_PIC_UNUSED_ZERO
+
+
+/////////////////////////////////////////////////////
+//
+// Tick Timer (TT)
+//
+
+// Define it if you want TT implemented
+`define OR1200_TT_IMPLEMENTED
+
+// Address offsets of TT registers inside TT group
+`define OR1200_TT_OFS_TTMR 1'd0
+`define OR1200_TT_OFS_TTCR 1'd1
+
+// Position of offset bits inside SPR group
+`define OR1200_TTOFS_BITS 0
+
+// Define if you want these TT registers to be implemented
+`define OR1200_TT_TTMR
+`define OR1200_TT_TTCR
+
+// TTMR bits
+`define OR1200_TT_TTMR_TP 27:0
+`define OR1200_TT_TTMR_IP 28
+`define OR1200_TT_TTMR_IE 29
+`define OR1200_TT_TTMR_M 31:30
+
+// Define if reading TT registers is allowed
+`define OR1200_TT_READREGS
+
+
+//////////////////////////////////////////////
+//
+// MAC
+//
+`define OR1200_MAC_ADDR		0	// MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
+`define OR1200_MAC_SPR_WE		// Define if MACLO/MACHI are SPR writable
+
+//
+// Shift {MACHI,MACLO} into destination register when executing l.macrc
+//
+// According to architecture manual there is no shift, so default value is 0.
+// However the implementation has deviated in this from the arch manual and had
+// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
+// (if using libmad fixed point library). Shifts are no longer default setup, 
+// but if you need to remain backward compatible, define your shift bits, which
+// were normally
+// dest_GPR = {MACHI,MACLO}[59:28]
+`define OR1200_MAC_SHIFTBY	0	// 0 = According to arch manual, 28 = obsolete backward compatibility
+
+
+//////////////////////////////////////////////
+//
+// Data MMU (DMMU)
+//
+
+//
+// Address that selects between TLB TR and MR
+//
+`define OR1200_DTLB_TM_ADDR	7
+
+//
+// DTLBMR fields
+//
+`define	OR1200_DTLBMR_V_BITS	0
+`define	OR1200_DTLBMR_CID_BITS	4:1
+`define	OR1200_DTLBMR_RES_BITS	11:5
+`define OR1200_DTLBMR_VPN_BITS	31:13
+
+//
+// DTLBTR fields
+//
+`define	OR1200_DTLBTR_CC_BITS	0
+`define	OR1200_DTLBTR_CI_BITS	1
+`define	OR1200_DTLBTR_WBC_BITS	2
+`define	OR1200_DTLBTR_WOM_BITS	3
+`define	OR1200_DTLBTR_A_BITS	4
+`define	OR1200_DTLBTR_D_BITS	5
+`define	OR1200_DTLBTR_URE_BITS	6
+`define	OR1200_DTLBTR_UWE_BITS	7
+`define	OR1200_DTLBTR_SRE_BITS	8
+`define	OR1200_DTLBTR_SWE_BITS	9
+`define	OR1200_DTLBTR_RES_BITS	11:10
+`define OR1200_DTLBTR_PPN_BITS	31:13
+
+//
+// DTLB configuration
+//
+`define	OR1200_DMMU_PS		13					// 13 for 8KB page size
+`define	OR1200_DTLB_INDXW	6					// 6 for 64 entry DTLB	7 for 128 entries
+`define OR1200_DTLB_INDXL	`OR1200_DMMU_PS				// 13			13
+`define OR1200_DTLB_INDXH	`OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1	// 18			19
+`define	OR1200_DTLB_INDX	`OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL	// 18:13		19:13
+`define OR1200_DTLB_TAGW	32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS	// 13			12
+`define OR1200_DTLB_TAGL	`OR1200_DTLB_INDXH+1			// 19			20
+`define	OR1200_DTLB_TAG		31:`OR1200_DTLB_TAGL			// 31:19		31:20
+`define	OR1200_DTLBMRW		`OR1200_DTLB_TAGW+1			// +1 because of V bit
+`define	OR1200_DTLBTRW		32-`OR1200_DMMU_PS+5			// +5 because of protection bits and CI
+
+//
+// Cache inhibit while DMMU is not enabled/implemented
+//
+// cache inhibited 0GB-4GB		1'b1
+// cache inhibited 0GB-2GB		!dcpu_adr_i[31]
+// cache inhibited 0GB-1GB 2GB-3GB	!dcpu_adr_i[30]
+// cache inhibited 1GB-2GB 3GB-4GB	dcpu_adr_i[30]
+// cache inhibited 2GB-4GB (default)	dcpu_adr_i[31]
+// cached 0GB-4GB			1'b0
+//
+`define OR1200_DMMU_CI			dcpu_adr_i[31]
+
+
+//////////////////////////////////////////////
+//
+// Insn MMU (IMMU)
+//
+
+//
+// Address that selects between TLB TR and MR
+//
+`define OR1200_ITLB_TM_ADDR	7
+
+//
+// ITLBMR fields
+//
+`define	OR1200_ITLBMR_V_BITS	0
+`define	OR1200_ITLBMR_CID_BITS	4:1
+`define	OR1200_ITLBMR_RES_BITS	11:5
+`define OR1200_ITLBMR_VPN_BITS	31:13
+
+//
+// ITLBTR fields
+//
+`define	OR1200_ITLBTR_CC_BITS	0
+`define	OR1200_ITLBTR_CI_BITS	1
+`define	OR1200_ITLBTR_WBC_BITS	2
+`define	OR1200_ITLBTR_WOM_BITS	3
+`define	OR1200_ITLBTR_A_BITS	4
+`define	OR1200_ITLBTR_D_BITS	5
+`define	OR1200_ITLBTR_SXE_BITS	6
+`define	OR1200_ITLBTR_UXE_BITS	7
+`define	OR1200_ITLBTR_RES_BITS	11:8
+`define OR1200_ITLBTR_PPN_BITS	31:13
+
+//
+// ITLB configuration
+//
+`define	OR1200_IMMU_PS		13					// 13 for 8KB page size
+`define	OR1200_ITLB_INDXW	6					// 6 for 64 entry ITLB	7 for 128 entries
+`define OR1200_ITLB_INDXL	`OR1200_IMMU_PS				// 13			13
+`define OR1200_ITLB_INDXH	`OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1	// 18			19
+`define	OR1200_ITLB_INDX	`OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL	// 18:13		19:13
+`define OR1200_ITLB_TAGW	32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS	// 13			12
+`define OR1200_ITLB_TAGL	`OR1200_ITLB_INDXH+1			// 19			20
+`define	OR1200_ITLB_TAG		31:`OR1200_ITLB_TAGL			// 31:19		31:20
+`define	OR1200_ITLBMRW		`OR1200_ITLB_TAGW+1			// +1 because of V bit
+`define	OR1200_ITLBTRW		32-`OR1200_IMMU_PS+3			// +3 because of protection bits and CI
+
+//
+// Cache inhibit while IMMU is not enabled/implemented
+// Note: all combinations that use icpu_adr_i cause async loop
+//
+// cache inhibited 0GB-4GB		1'b1
+// cache inhibited 0GB-2GB		!icpu_adr_i[31]
+// cache inhibited 0GB-1GB 2GB-3GB	!icpu_adr_i[30]
+// cache inhibited 1GB-2GB 3GB-4GB	icpu_adr_i[30]
+// cache inhibited 2GB-4GB (default)	icpu_adr_i[31]
+// cached 0GB-4GB			1'b0
+//
+`define OR1200_IMMU_CI			1'b0
+
+
+/////////////////////////////////////////////////
+//
+// Insn cache (IC)
+//
+
+// 4 for 16 byte line, 5 for 32 byte lines.
+`ifdef OR1200_IC_1W_32KB
+ `define OR1200_ICLS		5
+`else
+ `define OR1200_ICLS		4
+`endif
+
+//
+// IC configurations
+//
+`ifdef OR1200_IC_1W_512B
+`define OR1200_ICSIZE                   9                       // 512
+`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 7
+`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 8
+`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 9
+`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS // 5
+`define OR1200_ICTAG_W                  24
+`endif
+`ifdef OR1200_IC_1W_4KB
+`define OR1200_ICSIZE			12			// 4096
+`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 10
+`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 11
+`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 12
+`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 8
+`define	OR1200_ICTAG_W			21
+`endif
+`ifdef OR1200_IC_1W_8KB
+`define OR1200_ICSIZE			13			// 8192
+`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 11
+`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 12
+`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 13
+`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 9
+`define	OR1200_ICTAG_W			20
+`endif
+`ifdef OR1200_IC_1W_16KB
+`define OR1200_ICSIZE			14			// 16384
+`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 12
+`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 13
+`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 14
+`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 10
+`define	OR1200_ICTAG_W			19
+`endif
+`ifdef OR1200_IC_1W_32KB
+`define OR1200_ICSIZE			15			// 32768
+`define OR1200_ICINDX			`OR1200_ICSIZE-2	// 13
+`define OR1200_ICINDXH			`OR1200_ICSIZE-1	// 14
+`define OR1200_ICTAGL			`OR1200_ICINDXH+1	// 14
+`define	OR1200_ICTAG			`OR1200_ICSIZE-`OR1200_ICLS	// 10
+`define	OR1200_ICTAG_W			18
+`endif
+
+
+/////////////////////////////////////////////////
+//
+// Data cache (DC)
+//
+
+// 4 for 16 bytes, 5 for 32 bytes
+`ifdef OR1200_DC_1W_32KB
+ `define OR1200_DCLS		5
+`else
+ `define OR1200_DCLS		4
+`endif
+
+// Define to enable default behavior of cache as write through
+// Turning this off enabled write back statergy
+//
+`define OR1200_DC_WRITETHROUGH
+
+// Define to enable stores from the stack not doing writethrough.
+// EXPERIMENTAL
+//`define OR1200_DC_NOSTACKWRITETHROUGH
+
+// Data cache SPR definitions
+`define OR1200_SPRGRP_DC_ADR_WIDTH 3
+// Data cache group SPR addresses
+`define OR1200_SPRGRP_DC_DCCR		3'd0 // Not implemented
+`define OR1200_SPRGRP_DC_DCBPR		3'd1 // Not implemented
+`define OR1200_SPRGRP_DC_DCBFR		3'd2
+`define OR1200_SPRGRP_DC_DCBIR		3'd3
+`define OR1200_SPRGRP_DC_DCBWR		3'd4 // Not implemented
+`define OR1200_SPRGRP_DC_DCBLR		3'd5 // Not implemented
+
+//
+// DC configurations
+//
+`ifdef OR1200_DC_1W_4KB
+`define OR1200_DCSIZE			12			// 4096
+`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 10
+`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 11
+`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 12
+`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 8
+`define	OR1200_DCTAG_W			21
+`endif
+`ifdef OR1200_DC_1W_8KB
+`define OR1200_DCSIZE			13			// 8192
+`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 11
+`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 12
+`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 13
+`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 9
+`define	OR1200_DCTAG_W			20
+`endif
+`ifdef OR1200_DC_1W_16KB
+`define OR1200_DCSIZE			14			// 16384
+`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 12
+`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 13
+`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 14
+`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 10
+`define	OR1200_DCTAG_W			19
+`endif
+`ifdef OR1200_DC_1W_32KB
+`define OR1200_DCSIZE			15			// 32768
+`define OR1200_DCINDX			`OR1200_DCSIZE-2	// 13
+`define OR1200_DCINDXH			`OR1200_DCSIZE-1	// 14
+`define OR1200_DCTAGL			`OR1200_DCINDXH+1	// 15
+`define	OR1200_DCTAG			`OR1200_DCSIZE-`OR1200_DCLS	// 10
+`define	OR1200_DCTAG_W			18
+`endif
+
+
+/////////////////////////////////////////////////
+//
+// Store buffer (SB)
+//
+
+//
+// Store buffer
+//
+// It will improve performance by "caching" CPU stores
+// using store buffer. This is most important for function
+// prologues because DC can only work in write though mode
+// and all stores would have to complete external WB writes
+// to memory.
+// Store buffer is between DC and data BIU.
+// All stores will be stored into store buffer and immediately
+// completed by the CPU, even though actual external writes
+// will be performed later. As a consequence store buffer masks
+// all data bus errors related to stores (data bus errors
+// related to loads are delivered normally).
+// All pending CPU loads will wait until store buffer is empty to
+// ensure strict memory model. Right now this is necessary because
+// we don't make destinction between cached and cache inhibited
+// address space, so we simply empty store buffer until loads
+// can begin.
+//
+// It makes design a bit bigger, depending what is the number of
+// entries in SB FIFO. Number of entries can be changed further
+// down.
+//
+//`define OR1200_SB_IMPLEMENTED
+
+//
+// Number of store buffer entries
+//
+// Verified number of entries are 4 and 8 entries
+// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
+// always match 2**OR1200_SB_LOG.
+// To disable store buffer, undefine
+// OR1200_SB_IMPLEMENTED.
+//
+`define OR1200_SB_LOG		2	// 2 or 3
+`define OR1200_SB_ENTRIES	4	// 4 or 8
+
+
+/////////////////////////////////////////////////
+//
+// Quick Embedded Memory (QMEM)
+//
+
+//
+// Quick Embedded Memory
+//
+// Instantiation of dedicated insn/data memory (RAM or ROM).
+// Insn fetch has effective throughput 1insn / clock cycle.
+// Data load takes two clock cycles / access, data store
+// takes 1 clock cycle / access (if there is no insn fetch)).
+// Memory instantiation is shared between insn and data,
+// meaning if insn fetch are performed, data load/store
+// performance will be lower.
+//
+// Main reason for QMEM is to put some time critical functions
+// into this memory and to have predictable and fast access
+// to these functions. (soft fpu, context switch, exception
+// handlers, stack, etc)
+//
+// It makes design a bit bigger and slower. QMEM sits behind
+// IMMU/DMMU so all addresses are physical (so the MMUs can be
+// used with QMEM and QMEM is seen by the CPU just like any other
+// memory in the system). IC/DC are sitting behind QMEM so the
+// whole design timing might be worse with QMEM implemented.
+//
+//`define OR1200_QMEM_IMPLEMENTED
+
+//
+// Base address and mask of QMEM
+//
+// Base address defines first address of QMEM. Mask defines
+// QMEM range in address space. Actual size of QMEM is however
+// determined with instantiated RAM/ROM. However bigger
+// mask will reserve more address space for QMEM, but also
+// make design faster, while more tight mask will take
+// less address space but also make design slower. If
+// instantiated RAM/ROM is smaller than space reserved with
+// the mask, instatiated RAM/ROM will also be shadowed
+// at higher addresses in reserved space.
+//
+`define OR1200_QMEM_IADDR	32'h0080_0000
+`define OR1200_QMEM_IMASK	32'hfff0_0000 // Max QMEM size 1MB
+`define OR1200_QMEM_DADDR	32'h0080_0000
+`define OR1200_QMEM_DMASK	32'hfff0_0000 // Max QMEM size 1MB
+
+//
+// QMEM interface byte-select capability
+//
+// To enable qmem_sel* ports, define this macro.
+//
+//`define OR1200_QMEM_BSEL
+
+//
+// QMEM interface acknowledge
+//
+// To enable qmem_ack port, define this macro.
+//
+//`define OR1200_QMEM_ACK
+
+/////////////////////////////////////////////////////
+//
+// VR, UPR and Configuration Registers
+//
+//
+// VR, UPR and configuration registers are optional. If 
+// implemented, operating system can automatically figure
+// out how to use the processor because it knows 
+// what units are available in the processor and how they
+// are configured.
+//
+// This section must be last in or1200_defines.v file so
+// that all units are already configured and thus
+// configuration registers are properly set.
+// 
+
+// Define if you want configuration registers implemented
+`define OR1200_CFGR_IMPLEMENTED
+
+// Define if you want full address decode inside SYS group
+`define OR1200_SYS_FULL_DECODE
+
+// Offsets of VR, UPR and CFGR registers
+`define OR1200_SPRGRP_SYS_VR		4'h0
+`define OR1200_SPRGRP_SYS_UPR		4'h1
+`define OR1200_SPRGRP_SYS_CPUCFGR	4'h2
+`define OR1200_SPRGRP_SYS_DMMUCFGR	4'h3
+`define OR1200_SPRGRP_SYS_IMMUCFGR	4'h4
+`define OR1200_SPRGRP_SYS_DCCFGR	4'h5
+`define OR1200_SPRGRP_SYS_ICCFGR	4'h6
+`define OR1200_SPRGRP_SYS_DCFGR	4'h7
+
+// VR fields
+`define OR1200_VR_REV_BITS		5:0
+`define OR1200_VR_RES1_BITS		15:6
+`define OR1200_VR_CFG_BITS		23:16
+`define OR1200_VR_VER_BITS		31:24
+
+// VR values
+`define OR1200_VR_REV			6'h08
+`define OR1200_VR_RES1			10'h000
+`define OR1200_VR_CFG			8'h00
+`define OR1200_VR_VER			8'h12
+
+// UPR fields
+`define OR1200_UPR_UP_BITS		0
+`define OR1200_UPR_DCP_BITS		1
+`define OR1200_UPR_ICP_BITS		2
+`define OR1200_UPR_DMP_BITS		3
+`define OR1200_UPR_IMP_BITS		4
+`define OR1200_UPR_MP_BITS		5
+`define OR1200_UPR_DUP_BITS		6
+`define OR1200_UPR_PCUP_BITS		7
+`define OR1200_UPR_PMP_BITS		8
+`define OR1200_UPR_PICP_BITS		9
+`define OR1200_UPR_TTP_BITS		10
+`define OR1200_UPR_FPP_BITS		11
+`define OR1200_UPR_RES1_BITS		23:12
+`define OR1200_UPR_CUP_BITS		31:24
+
+// UPR values
+`define OR1200_UPR_UP			1'b1
+`ifdef OR1200_NO_DC
+`define OR1200_UPR_DCP			1'b0
+`else
+`define OR1200_UPR_DCP			1'b1
+`endif
+`ifdef OR1200_NO_IC
+`define OR1200_UPR_ICP			1'b0
+`else
+`define OR1200_UPR_ICP			1'b1
+`endif
+`ifdef OR1200_NO_DMMU
+`define OR1200_UPR_DMP			1'b0
+`else
+`define OR1200_UPR_DMP			1'b1
+`endif
+`ifdef OR1200_NO_IMMU
+`define OR1200_UPR_IMP			1'b0
+`else
+`define OR1200_UPR_IMP			1'b1
+`endif
+`ifdef OR1200_MAC_IMPLEMENTED
+`define OR1200_UPR_MP			1'b1
+`else
+`define OR1200_UPR_MP			1'b0
+`endif
+`ifdef OR1200_DU_IMPLEMENTED
+`define OR1200_UPR_DUP			1'b1
+`else
+`define OR1200_UPR_DUP			1'b0
+`endif
+`define OR1200_UPR_PCUP			1'b0	// Performance counters not present
+`ifdef OR1200_PM_IMPLEMENTED
+`define OR1200_UPR_PMP			1'b1
+`else
+`define OR1200_UPR_PMP			1'b0
+`endif
+`ifdef OR1200_PIC_IMPLEMENTED
+`define OR1200_UPR_PICP			1'b1
+`else
+`define OR1200_UPR_PICP			1'b0
+`endif
+`ifdef OR1200_TT_IMPLEMENTED
+`define OR1200_UPR_TTP			1'b1
+`else
+`define OR1200_UPR_TTP			1'b0
+`endif
+`ifdef OR1200_FPU_IMPLEMENTED
+`define OR1200_UPR_FPP			1'b1
+`else
+`define OR1200_UPR_FPP			1'b0
+`endif
+`define OR1200_UPR_RES1			12'h000
+`define OR1200_UPR_CUP			8'h00
+
+// CPUCFGR fields
+`define OR1200_CPUCFGR_NSGF_BITS	3:0
+`define OR1200_CPUCFGR_HGF_BITS     4
+`define OR1200_CPUCFGR_OB32S_BITS	5
+`define OR1200_CPUCFGR_OB64S_BITS	6
+`define OR1200_CPUCFGR_OF32S_BITS	7
+`define OR1200_CPUCFGR_OF64S_BITS	8
+`define OR1200_CPUCFGR_OV64S_BITS	9
+`define OR1200_CPUCFGR_RES1_BITS	31:10
+
+// CPUCFGR values
+`define OR1200_CPUCFGR_NSGF		    4'h0
+`ifdef OR1200_RFRAM_16REG
+    `define OR1200_CPUCFGR_HGF  		1'b1
+`else
+    `define OR1200_CPUCFGR_HGF  		1'b0
+`endif
+`define OR1200_CPUCFGR_OB32S		1'b1
+`define OR1200_CPUCFGR_OB64S		1'b0
+`ifdef OR1200_FPU_IMPLEMENTED
+ `define OR1200_CPUCFGR_OF32S		1'b1
+`else
+ `define OR1200_CPUCFGR_OF32S		1'b0
+`endif
+
+`define OR1200_CPUCFGR_OF64S		1'b0
+`define OR1200_CPUCFGR_OV64S		1'b0
+`define OR1200_CPUCFGR_RES1		22'h000000
+
+// DMMUCFGR fields
+`define OR1200_DMMUCFGR_NTW_BITS	1:0
+`define OR1200_DMMUCFGR_NTS_BITS	4:2
+`define OR1200_DMMUCFGR_NAE_BITS	7:5
+`define OR1200_DMMUCFGR_CRI_BITS	8
+`define OR1200_DMMUCFGR_PRI_BITS	9
+`define OR1200_DMMUCFGR_TEIRI_BITS	10
+`define OR1200_DMMUCFGR_HTR_BITS	11
+`define OR1200_DMMUCFGR_RES1_BITS	31:12
+
+// DMMUCFGR values
+`ifdef OR1200_NO_DMMU
+`define OR1200_DMMUCFGR_NTW		2'h0	// Irrelevant
+`define OR1200_DMMUCFGR_NTS		3'h0	// Irrelevant
+`define OR1200_DMMUCFGR_NAE		3'h0	// Irrelevant
+`define OR1200_DMMUCFGR_CRI		1'b0	// Irrelevant
+`define OR1200_DMMUCFGR_PRI		1'b0	// Irrelevant
+`define OR1200_DMMUCFGR_TEIRI		1'b0	// Irrelevant
+`define OR1200_DMMUCFGR_HTR		1'b0	// Irrelevant
+`define OR1200_DMMUCFGR_RES1		20'h00000
+`else
+`define OR1200_DMMUCFGR_NTW		2'h0	// 1 TLB way
+`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW	// Num TLB sets
+`define OR1200_DMMUCFGR_NAE		3'h0	// No ATB entries
+`define OR1200_DMMUCFGR_CRI		1'b0	// No control register
+`define OR1200_DMMUCFGR_PRI		1'b0	// No protection reg
+`define OR1200_DMMUCFGR_TEIRI		1'b0	// TLB entry inv reg NOT impl.
+`define OR1200_DMMUCFGR_HTR		1'b0	// No HW TLB reload
+`define OR1200_DMMUCFGR_RES1		20'h00000
+`endif
+
+// IMMUCFGR fields
+`define OR1200_IMMUCFGR_NTW_BITS	1:0
+`define OR1200_IMMUCFGR_NTS_BITS	4:2
+`define OR1200_IMMUCFGR_NAE_BITS	7:5
+`define OR1200_IMMUCFGR_CRI_BITS	8
+`define OR1200_IMMUCFGR_PRI_BITS	9
+`define OR1200_IMMUCFGR_TEIRI_BITS	10
+`define OR1200_IMMUCFGR_HTR_BITS	11
+`define OR1200_IMMUCFGR_RES1_BITS	31:12
+
+// IMMUCFGR values
+`ifdef OR1200_NO_IMMU
+`define OR1200_IMMUCFGR_NTW		2'h0	// Irrelevant
+`define OR1200_IMMUCFGR_NTS		3'h0	// Irrelevant
+`define OR1200_IMMUCFGR_NAE		3'h0	// Irrelevant
+`define OR1200_IMMUCFGR_CRI		1'b0	// Irrelevant
+`define OR1200_IMMUCFGR_PRI		1'b0	// Irrelevant
+`define OR1200_IMMUCFGR_TEIRI		1'b0	// Irrelevant
+`define OR1200_IMMUCFGR_HTR		1'b0	// Irrelevant
+`define OR1200_IMMUCFGR_RES1		20'h00000
+`else
+`define OR1200_IMMUCFGR_NTW		2'h0	// 1 TLB way
+`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW	// Num TLB sets
+`define OR1200_IMMUCFGR_NAE		3'h0	// No ATB entry
+`define OR1200_IMMUCFGR_CRI		1'b0	// No control reg
+`define OR1200_IMMUCFGR_PRI		1'b0	// No protection reg
+`define OR1200_IMMUCFGR_TEIRI		1'b0	// TLB entry inv reg NOT impl
+`define OR1200_IMMUCFGR_HTR		1'b0	// No HW TLB reload
+`define OR1200_IMMUCFGR_RES1		20'h00000
+`endif
+
+// DCCFGR fields
+`define OR1200_DCCFGR_NCW_BITS		2:0
+`define OR1200_DCCFGR_NCS_BITS		6:3
+`define OR1200_DCCFGR_CBS_BITS		7
+`define OR1200_DCCFGR_CWS_BITS		8
+`define OR1200_DCCFGR_CCRI_BITS		9
+`define OR1200_DCCFGR_CBIRI_BITS	10
+`define OR1200_DCCFGR_CBPRI_BITS	11
+`define OR1200_DCCFGR_CBLRI_BITS	12
+`define OR1200_DCCFGR_CBFRI_BITS	13
+`define OR1200_DCCFGR_CBWBRI_BITS	14
+`define OR1200_DCCFGR_RES1_BITS	31:15
+
+// DCCFGR values
+`ifdef OR1200_NO_DC
+`define OR1200_DCCFGR_NCW		3'h0	// Irrelevant
+`define OR1200_DCCFGR_NCS		4'h0	// Irrelevant
+`define OR1200_DCCFGR_CBS		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CWS		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CCRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBIRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBPRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBLRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBFRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_CBWBRI		1'b0	// Irrelevant
+`define OR1200_DCCFGR_RES1		17'h00000
+`else
+`define OR1200_DCCFGR_NCW		3'h0	// 1 cache way
+`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)	// Num cache sets
+`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
+`ifdef OR1200_DC_WRITETHROUGH
+ `define OR1200_DCCFGR_CWS		1'b0	// Write-through strategy
+`else
+ `define OR1200_DCCFGR_CWS		1'b1	// Write-back strategy
+`endif
+`define OR1200_DCCFGR_CCRI		1'b1	// Cache control reg impl.
+`define OR1200_DCCFGR_CBIRI		1'b1	// Cache block inv reg impl.
+`define OR1200_DCCFGR_CBPRI		1'b0	// Cache block prefetch reg not impl.
+`define OR1200_DCCFGR_CBLRI		1'b0	// Cache block lock reg not impl.
+`define OR1200_DCCFGR_CBFRI		1'b1	// Cache block flush reg impl.
+`ifdef OR1200_DC_WRITETHROUGH
+ `define OR1200_DCCFGR_CBWBRI		1'b0	// Cache block WB reg not impl.
+`else
+ `define OR1200_DCCFGR_CBWBRI		1'b1	// Cache block WB reg impl.
+`endif
+`define OR1200_DCCFGR_RES1		17'h00000
+`endif
+
+// ICCFGR fields
+`define OR1200_ICCFGR_NCW_BITS		2:0
+`define OR1200_ICCFGR_NCS_BITS		6:3
+`define OR1200_ICCFGR_CBS_BITS		7
+`define OR1200_ICCFGR_CWS_BITS		8
+`define OR1200_ICCFGR_CCRI_BITS		9
+`define OR1200_ICCFGR_CBIRI_BITS	10
+`define OR1200_ICCFGR_CBPRI_BITS	11
+`define OR1200_ICCFGR_CBLRI_BITS	12
+`define OR1200_ICCFGR_CBFRI_BITS	13
+`define OR1200_ICCFGR_CBWBRI_BITS	14
+`define OR1200_ICCFGR_RES1_BITS	31:15
+
+// ICCFGR values
+`ifdef OR1200_NO_IC
+`define OR1200_ICCFGR_NCW		3'h0	// Irrelevant
+`define OR1200_ICCFGR_NCS 		4'h0	// Irrelevant
+`define OR1200_ICCFGR_CBS 		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CWS		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CCRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBIRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBPRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBLRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBFRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CBWBRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_RES1		17'h00000
+`else
+`define OR1200_ICCFGR_NCW		3'h0	// 1 cache way
+`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)	// Num cache sets
+`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1	// 16 byte cache block
+`define OR1200_ICCFGR_CWS		1'b0	// Irrelevant
+`define OR1200_ICCFGR_CCRI		1'b1	// Cache control reg impl.
+`define OR1200_ICCFGR_CBIRI		1'b1	// Cache block inv reg impl.
+`define OR1200_ICCFGR_CBPRI		1'b0	// Cache block prefetch reg not impl.
+`define OR1200_ICCFGR_CBLRI		1'b0	// Cache block lock reg not impl.
+`define OR1200_ICCFGR_CBFRI		1'b1	// Cache block flush reg impl.
+`define OR1200_ICCFGR_CBWBRI		1'b0	// Irrelevant
+`define OR1200_ICCFGR_RES1		17'h00000
+`endif
+
+// DCFGR fields
+`define OR1200_DCFGR_NDP_BITS		3:0
+`define OR1200_DCFGR_WPCI_BITS		4
+`define OR1200_DCFGR_RES1_BITS		31:5
+
+// DCFGR values
+`ifdef OR1200_DU_HWBKPTS
+`define OR1200_DCFGR_NDP		4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
+`ifdef OR1200_DU_DWCR0
+`define OR1200_DCFGR_WPCI		1'b1
+`else
+`define OR1200_DCFGR_WPCI		1'b0	// WP counters not impl.
+`endif
+`else
+`define OR1200_DCFGR_NDP		4'h0	// Zero DVR/DCR pairs
+`define OR1200_DCFGR_WPCI		1'b0	// WP counters not impl.
+`endif
+`define OR1200_DCFGR_RES1		27'd0
+
+///////////////////////////////////////////////////////////////////////////////
+// Boot Address Selection                                                    //
+//                                                                           //
+// Allows a definable boot address, potentially different to the usual reset //
+// vector to allow for power-on code to be run, if desired.                  //
+//                                                                           //
+// OR1200_BOOT_ADR should be the 32-bit address of the boot location         //
+// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2)              //
+//                                                                           //
+// For default reset behavior uncomment the settings under the "Boot 0x100"  //
+// comment below.                                                            //
+//                                                                           //
+///////////////////////////////////////////////////////////////////////////////
+// Boot from 0xf0000100
+//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
+//`define OR1200_BOOT_ADR 32'hf0000100
+// Boot from 0x100
+`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
+`define OR1200_BOOT_ADR 32'h00000100
diff --git a/systems/de2/rtl/verilog/include/orpsoc-defines.v b/systems/de2/rtl/verilog/include/orpsoc-defines.v
new file mode 100755
index 00000000..af1605e8
--- /dev/null
+++ b/systems/de2/rtl/verilog/include/orpsoc-defines.v
@@ -0,0 +1,39 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// orpsoc-defines                                               ////
+////                                                              ////
+//// Top level ORPSoC defines file                                ////
+////                                                              ////
+//// Included in toplevel and testbench                           ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+// Included modules: define to include
+`define BOOTROM
+`define OR1200_CPU
+// end of included module defines - keep this comment line here
diff --git a/systems/de2/rtl/verilog/include/timescale.v b/systems/de2/rtl/verilog/include/timescale.v
new file mode 100755
index 00000000..e66f979c
--- /dev/null
+++ b/systems/de2/rtl/verilog/include/timescale.v
@@ -0,0 +1 @@
+`timescale 1ns/1ps
diff --git a/systems/de2/rtl/verilog/include/uart_defines.v b/systems/de2/rtl/verilog/include/uart_defines.v
new file mode 100755
index 00000000..f9c567a1
--- /dev/null
+++ b/systems/de2/rtl/verilog/include/uart_defines.v
@@ -0,0 +1,250 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  uart_defines.v                                              ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the "UART 16550 compatible" project    ////
+////  http://www.opencores.org/cores/uart16550/                   ////
+////                                                              ////
+////  Documentation related to this project:                      ////
+////  - http://www.opencores.org/cores/uart16550/                 ////
+////                                                              ////
+////  Projects compatibility:                                     ////
+////  - WISHBONE                                                  ////
+////  RS232 Protocol                                              ////
+////  16550D uart (mostly supported)                              ////
+////                                                              ////
+////  Overview (main Features):                                   ////
+////  Defines of the Core                                         ////
+////                                                              ////
+////  Known problems (limits):                                    ////
+////  None                                                        ////
+////                                                              ////
+////  To Do:                                                      ////
+////  Nothing.                                                    ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - gorban@opencores.org                                  ////
+////      - Jacob Gorban                                          ////
+////      - Igor Mohor (igorm@opencores.org)                      ////
+////                                                              ////
+////  Created:        2001/05/12                                  ////
+////  Last Updated:   2001/05/17                                  ////
+////                  (See log for the revision history)          ////
+////                                                              ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000, 2001 Authors                             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.13  2003/06/11 16:37:47  gorban
+// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
+//
+// Revision 1.12  2002/07/22 23:02:23  gorban
+// Bug Fixes:
+//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
+//   Problem reported by Kenny.Tung.
+//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
+//
+// Improvements:
+//  * Made FIFO's as general inferrable memory where possible.
+//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
+//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
+//
+//  * Added optional baudrate output (baud_o).
+//  This is identical to BAUDOUT* signal on 16550 chip.
+//  It outputs 16xbit_clock_rate - the divided clock.
+//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
+//
+// Revision 1.10  2001/12/11 08:55:40  mohor
+// Scratch register define added.
+//
+// Revision 1.9  2001/12/03 21:44:29  gorban
+// Updated specification documentation.
+// Added full 32-bit data bus interface, now as default.
+// Address is 5-bit wide in 32-bit data bus mode.
+// Added wb_sel_i input to the core. It's used in the 32-bit mode.
+// Added debug interface with two 32-bit read-only registers in 32-bit mode.
+// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
+// My small test bench is modified to work with 32-bit mode.
+//
+// Revision 1.8  2001/11/26 21:38:54  gorban
+// Lots of fixes:
+// Break condition wasn't handled correctly at all.
+// LSR bits could lose their values.
+// LSR value after reset was wrong.
+// Timing of THRE interrupt signal corrected.
+// LSR bit 0 timing corrected.
+//
+// Revision 1.7  2001/08/24 21:01:12  mohor
+// Things connected to parity changed.
+// Clock devider changed.
+//
+// Revision 1.6  2001/08/23 16:05:05  mohor
+// Stop bit bug fixed.
+// Parity bug fixed.
+// WISHBONE read cycle bug fixed,
+// OE indicator (Overrun Error) bug fixed.
+// PE indicator (Parity Error) bug fixed.
+// Register read bug fixed.
+//
+// Revision 1.5  2001/05/31 20:08:01  gorban
+// FIFO changes and other corrections.
+//
+// Revision 1.4  2001/05/21 19:12:02  gorban
+// Corrected some Linter messages.
+//
+// Revision 1.3  2001/05/17 18:34:18  gorban
+// First 'stable' release. Should be sythesizable now. Also added new header.
+//
+// Revision 1.0  2001-05-17 21:27:11+02  jacob
+// Initial revision
+//
+//
+
+// remove comments to restore to use the new version with 8 data bit interface
+// in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place
+// also, in 8-bit version there'll be no debugging features included
+// CAUTION: doesn't work with current version of OR1200
+`define DATA_BUS_WIDTH_8
+
+`ifdef DATA_BUS_WIDTH_8
+ `define UART_ADDR_WIDTH 3
+ `define UART_DATA_WIDTH 8
+`else
+ `define UART_ADDR_WIDTH 5
+ `define UART_DATA_WIDTH 32
+`endif
+
+// Uncomment this if you want your UART to have
+// 16xBaudrate output port.
+// If defined, the enable signal will be used to drive baudrate_o signal
+// It's frequency is 16xbaudrate
+
+// `define UART_HAS_BAUDRATE_OUTPUT
+
+// Register addresses
+`define UART_REG_RB	`UART_ADDR_WIDTH'd0	// receiver buffer
+`define UART_REG_TR  `UART_ADDR_WIDTH'd0	// transmitter
+`define UART_REG_IE	`UART_ADDR_WIDTH'd1	// Interrupt enable
+`define UART_REG_II  `UART_ADDR_WIDTH'd2	// Interrupt identification
+`define UART_REG_FC  `UART_ADDR_WIDTH'd2	// FIFO control
+`define UART_REG_LC	`UART_ADDR_WIDTH'd3	// Line Control
+`define UART_REG_MC	`UART_ADDR_WIDTH'd4	// Modem control
+`define UART_REG_LS  `UART_ADDR_WIDTH'd5	// Line status
+`define UART_REG_MS  `UART_ADDR_WIDTH'd6	// Modem status
+`define UART_REG_SR  `UART_ADDR_WIDTH'd7	// Scratch register
+`define UART_REG_DL1	`UART_ADDR_WIDTH'd0	// Divisor latch bytes (1-2)
+`define UART_REG_DL2	`UART_ADDR_WIDTH'd1
+
+// Interrupt Enable register bits
+`define UART_IE_RDA	0	// Received Data available interrupt
+`define UART_IE_THRE	1	// Transmitter Holding Register empty interrupt
+`define UART_IE_RLS	2	// Receiver Line Status Interrupt
+`define UART_IE_MS	3	// Modem Status Interrupt
+
+// Interrupt Identification register bits
+`define UART_II_IP	0	// Interrupt pending when 0
+`define UART_II_II	3:1	// Interrupt identification
+
+// Interrupt identification values for bits 3:1
+`define UART_II_RLS	3'b011	// Receiver Line Status
+`define UART_II_RDA	3'b010	// Receiver Data available
+`define UART_II_TI	3'b110	// Timeout Indication
+`define UART_II_THRE	3'b001	// Transmitter Holding Register empty
+`define UART_II_MS	3'b000	// Modem Status
+
+// FIFO Control Register bits
+`define UART_FC_TL	1:0	// Trigger level
+
+// FIFO trigger level values
+`define UART_FC_1		2'b00
+`define UART_FC_4		2'b01
+`define UART_FC_8		2'b10
+`define UART_FC_14	2'b11
+
+// Line Control register bits
+`define UART_LC_BITS	1:0	// bits in character
+`define UART_LC_SB	2	// stop bits
+`define UART_LC_PE	3	// parity enable
+`define UART_LC_EP	4	// even parity
+`define UART_LC_SP	5	// stick parity
+`define UART_LC_BC	6	// Break control
+`define UART_LC_DL	7	// Divisor Latch access bit
+
+// Modem Control register bits
+`define UART_MC_DTR	0
+`define UART_MC_RTS	1
+`define UART_MC_OUT1	2
+`define UART_MC_OUT2	3
+`define UART_MC_LB	4	// Loopback mode
+
+// Line Status Register bits
+`define UART_LS_DR	0	// Data ready
+`define UART_LS_OE	1	// Overrun Error
+`define UART_LS_PE	2	// Parity Error
+`define UART_LS_FE	3	// Framing Error
+`define UART_LS_BI	4	// Break interrupt
+`define UART_LS_TFE	5	// Transmit FIFO is empty
+`define UART_LS_TE	6	// Transmitter Empty indicator
+`define UART_LS_EI	7	// Error indicator
+
+// Modem Status Register bits
+`define UART_MS_DCTS	0	// Delta signals
+`define UART_MS_DDSR	1
+`define UART_MS_TERI	2
+`define UART_MS_DDCD	3
+`define UART_MS_CCTS	4	// Complement signals
+`define UART_MS_CDSR	5
+`define UART_MS_CRI	6
+`define UART_MS_CDCD	7
+
+// FIFO parameter defines
+
+`define UART_FIFO_WIDTH	8
+`define UART_FIFO_DEPTH	16
+`define UART_FIFO_POINTER_W	4
+`define UART_FIFO_COUNTER_W	5
+// receiver fifo has width 11 because it has break, parity and framing error bits
+`define UART_FIFO_REC_WIDTH  11
+
+
+`define VERBOSE_WB  0           // All activity on the WISHBONE is recorded
+`define VERBOSE_LINE_STATUS 0   // Details about the lsr (line status register)
+`define FAST_TEST   1           // 64/1024 packets are sent
+
+// Defines hard baud prescaler register - uncomment to enable
+//`define PRESCALER_PRESET_HARD
+// 115200 baud preset values
+// 20MHz: prescaler 10.8 (11, rounded up)
+//`define PRESCALER_HIGH_PRESET 8'd0
+//`define PRESCALER_LOW_PRESET 8'd11
+// 50MHz: prescaler 27.1
+//`define PRESCALER_HIGH_PRESET 8'd0
+//`define PRESCALER_LOW_PRESET 8'd27
diff --git a/systems/de2/rtl/verilog/orpsoc_top.v b/systems/de2/rtl/verilog/orpsoc_top.v
new file mode 100755
index 00000000..4975e096
--- /dev/null
+++ b/systems/de2/rtl/verilog/orpsoc_top.v
@@ -0,0 +1,705 @@
+//////////////////////////////////////////////////////////////////////
+///                                                               ////
+/// ORPSoC top for Altera de1 board                               ////
+///                                                               ////
+/// Franck Jullien, franck.jullien@gmail.com                      ////
+///                                                               ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "orpsoc-defines.v"
+
+module orpsoc_top #(
+	parameter	rom0_aw = 6,
+	parameter	uart0_aw = 3
+)
+(
+	input		sys_clk_pad_i,
+	input		rst_n_pad_i,
+
+	output	[9:0]	led_r_pad_o,
+	inout	[7:0]	gpio0_io,
+
+`ifdef SIM
+	output		tdo_pad_o,
+	input		tms_pad_i,
+	input		tck_pad_i,
+	input		tdi_pad_i,
+`endif
+
+	output	[1:0]	sdram_ba_pad_o,
+	output	[11:0]	sdram_a_pad_o,
+	output		sdram_cs_n_pad_o,
+	output		sdram_ras_pad_o,
+	output		sdram_cas_pad_o,
+	output		sdram_we_pad_o,
+	inout	[15:0]	sdram_dq_pad_io,
+	output	[1:0]	sdram_dqm_pad_o,
+	output		sdram_cke_pad_o,
+	output		sdram_clk_pad_o,
+
+	input		uart0_srx_pad_i,
+	output		uart0_stx_pad_o
+);
+
+parameter	IDCODE_VALUE = 32'h14951185;
+
+////////////////////////////////////////////////////////////////////////
+//
+// Clock and reset generation module
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	async_rst;
+wire	wb_clk, wb_rst;
+wire	dbg_tck;
+wire	sdram_clk;
+wire	sdram_rst;
+
+assign	sdram_clk_pad_o = sdram_clk;
+
+clkgen clkgen0 (
+	.sys_clk_pad_i	(sys_clk_pad_i),
+	.rst_n_pad_i	(rst_n_pad_i),
+	.async_rst_o	(async_rst),
+	.wb_clk_o	(wb_clk),
+	.wb_rst_o	(wb_rst),
+`ifdef SIM
+	.tck_pad_i	(tck_pad_i),
+	.dbg_tck_o	(dbg_tck),
+`endif
+	.sdram_clk_o	(sdram_clk),
+	.sdram_rst_o	(sdram_rst)
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// Modules interconnections
+//
+////////////////////////////////////////////////////////////////////////
+
+`include "wb_intercon.vh"
+
+`ifdef SIM
+////////////////////////////////////////////////////////////////////////
+//
+// GENERIC JTAG TAP
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	dbg_if_select;
+wire	dbg_if_tdo;
+wire	jtag_tap_tdo;
+wire	jtag_tap_shift_dr;
+wire	jtag_tap_pause_dr;
+wire	jtag_tap_update_dr;
+wire	jtag_tap_capture_dr;
+
+tap_top #(.IDCODE_VALUE(IDCODE_VALUE))
+jtag_tap0 (
+	.tdo_pad_o			(tdo_pad_o),
+	.tms_pad_i			(tms_pad_i),
+	.tck_pad_i			(dbg_tck),
+	.trst_pad_i			(async_rst),
+	.tdi_pad_i			(tdi_pad_i),
+
+	.tdo_padoe_o			(tdo_padoe_o),
+
+	.tdo_o				(jtag_tap_tdo),
+
+	.shift_dr_o			(jtag_tap_shift_dr),
+	.pause_dr_o			(jtag_tap_pause_dr),
+	.update_dr_o			(jtag_tap_update_dr),
+	.capture_dr_o			(jtag_tap_capture_dr),
+
+	.extest_select_o		(),
+	.sample_preload_select_o	(),
+	.mbist_select_o			(),
+	.debug_select_o			(dbg_if_select),
+
+
+	.bs_chain_tdi_i			(1'b0),
+	.mbist_tdi_i			(1'b0),
+	.debug_tdi_i			(dbg_if_tdo)
+);
+
+`else
+////////////////////////////////////////////////////////////////////////
+//
+// ALTERA Virtual JTAG TAP
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	dbg_if_select;
+wire	dbg_if_tdo;
+wire	jtag_tap_tdo;
+wire	jtag_tap_shift_dr;
+wire	jtag_tap_pause_dr;
+wire	jtag_tap_update_dr;
+wire	jtag_tap_capture_dr;
+
+altera_virtual_jtag jtag_tap0 (
+	.tck_o			(dbg_tck),
+	.debug_tdo_i		(dbg_if_tdo),
+	.tdi_o			(jtag_tap_tdo),
+	.test_logic_reset_o	(),
+	.run_test_idle_o	(),
+	.shift_dr_o		(jtag_tap_shift_dr),
+	.capture_dr_o		(jtag_tap_capture_dr),
+	.pause_dr_o		(jtag_tap_pause_dr),
+	.update_dr_o		(jtag_tap_update_dr),
+	.debug_select_o		(dbg_if_select)
+);
+`endif
+
+////////////////////////////////////////////////////////////////////////
+//
+// OR1K CPU
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	[31:0]	or1k_irq;
+
+wire	[31:0]	or1k_dbg_dat_i;
+wire	[31:0]	or1k_dbg_adr_i;
+wire		or1k_dbg_we_i;
+wire		or1k_dbg_stb_i;
+wire		or1k_dbg_ack_o;
+wire	[31:0]	or1k_dbg_dat_o;
+
+wire		or1k_dbg_stall_i;
+wire		or1k_dbg_ewt_i;
+wire	[3:0]	or1k_dbg_lss_o;
+wire	[1:0]	or1k_dbg_is_o;
+wire	[10:0]	or1k_dbg_wp_o;
+wire		or1k_dbg_bp_o;
+wire		or1k_dbg_rst;
+
+wire		sig_tick;
+wire		or1k_rst;
+
+assign	or1k_rst = wb_rst | or1k_dbg_rst;
+
+`ifdef OR1200_CPU
+
+or1200_top #(.boot_adr(32'hf0000100))
+or1200_top0 (
+	// Instruction bus, clocks, reset
+	.iwb_clk_i		(wb_clk),
+	.iwb_rst_i		(wb_rst),
+	.iwb_ack_i		(wb_s2m_or1k_i_ack),
+	.iwb_err_i		(wb_s2m_or1k_i_err),
+	.iwb_rty_i		(wb_s2m_or1k_i_rty),
+	.iwb_dat_i		(wb_s2m_or1k_i_dat),
+
+	.iwb_cyc_o		(wb_m2s_or1k_i_cyc),
+	.iwb_adr_o		(wb_m2s_or1k_i_adr),
+	.iwb_stb_o		(wb_m2s_or1k_i_stb),
+	.iwb_we_o		(wb_m2s_or1k_i_we),
+	.iwb_sel_o		(wb_m2s_or1k_i_sel),
+	.iwb_dat_o		(wb_m2s_or1k_i_dat),
+	.iwb_cti_o		(wb_m2s_or1k_i_cti),
+	.iwb_bte_o		(wb_m2s_or1k_i_bte),
+
+	// Data bus, clocks, reset
+	.dwb_clk_i		(wb_clk),
+	.dwb_rst_i		(wb_rst),
+	.dwb_ack_i		(wb_s2m_or1k_d_ack),
+	.dwb_err_i		(wb_s2m_or1k_d_err),
+	.dwb_rty_i		(wb_s2m_or1k_d_rty),
+	.dwb_dat_i		(wb_s2m_or1k_d_dat),
+
+	.dwb_cyc_o		(wb_m2s_or1k_d_cyc),
+	.dwb_adr_o		(wb_m2s_or1k_d_adr),
+	.dwb_stb_o		(wb_m2s_or1k_d_stb),
+	.dwb_we_o		(wb_m2s_or1k_d_we),
+	.dwb_sel_o		(wb_m2s_or1k_d_sel),
+	.dwb_dat_o		(wb_m2s_or1k_d_dat),
+	.dwb_cti_o		(wb_m2s_or1k_d_cti),
+	.dwb_bte_o		(wb_m2s_or1k_d_bte),
+
+	// Debug interface ports
+	.dbg_stall_i		(or1k_dbg_stall_i),
+	.dbg_ewt_i		(1'b0),
+	.dbg_lss_o		(or1k_dbg_lss_o),
+	.dbg_is_o		(or1k_dbg_is_o),
+	.dbg_wp_o		(or1k_dbg_wp_o),
+	.dbg_bp_o		(or1k_dbg_bp_o),
+
+	.dbg_adr_i		(or1k_dbg_adr_i),
+	.dbg_we_i		(or1k_dbg_we_i),
+	.dbg_stb_i		(or1k_dbg_stb_i),
+	.dbg_dat_i		(or1k_dbg_dat_i),
+	.dbg_dat_o		(or1k_dbg_dat_o),
+	.dbg_ack_o		(or1k_dbg_ack_o),
+
+	.pm_clksd_o		(),
+	.pm_dc_gate_o		(),
+	.pm_ic_gate_o		(),
+	.pm_dmmu_gate_o		(),
+	.pm_immu_gate_o		(),
+	.pm_tt_gate_o		(),
+	.pm_cpu_gate_o		(),
+	.pm_wakeup_o		(),
+	.pm_lvolt_o		(),
+
+	// Core clocks, resets
+	.clk_i			(wb_clk),
+	.rst_i			(or1k_rst),
+
+	.clmode_i		(2'b00),
+
+	// Interrupts
+	.pic_ints_i		(or1k_irq[30:0]),
+	.sig_tick		(sig_tick),
+
+	.pm_cpustall_i		(1'b0)
+);
+
+`else
+
+mor1kx	#(
+	.FEATURE_DEBUGUNIT		("ENABLED"),
+	.FEATURE_CMOV			("ENABLED"),
+	.FEATURE_INSTRUCTIONCACHE	("ENABLED"),
+	.OPTION_ICACHE_BLOCK_WIDTH	(5),
+	.OPTION_ICACHE_SET_WIDTH	(3),
+	.OPTION_ICACHE_WAYS		(2),
+	.OPTION_ICACHE_LIMIT_WIDTH	(32),
+	.FEATURE_IMMU			("ENABLED"),
+	.FEATURE_DATACACHE		("ENABLED"),
+	.OPTION_DCACHE_BLOCK_WIDTH	(5),
+	.OPTION_DCACHE_SET_WIDTH	(3),
+	.OPTION_DCACHE_WAYS		(2),
+	.OPTION_DCACHE_LIMIT_WIDTH	(31),
+	.FEATURE_DMMU			("ENABLED"),
+	.OPTION_PIC_TRIGGER		("LATCHED_LEVEL"),
+
+	.IBUS_WB_TYPE			("B3_REGISTERED_FEEDBACK"),
+	.DBUS_WB_TYPE			("B3_REGISTERED_FEEDBACK"),
+	.OPTION_CPU0			("CAPPUCCINO"),
+	.OPTION_RESET_PC		(32'hf0000100)
+) mor1kx0 (
+	.iwbm_adr_o			(wb_m2s_or1k_i_adr),
+	.iwbm_stb_o			(wb_m2s_or1k_i_stb),
+	.iwbm_cyc_o			(wb_m2s_or1k_i_cyc),
+	.iwbm_sel_o			(wb_m2s_or1k_i_sel),
+	.iwbm_we_o			(wb_m2s_or1k_i_we),
+	.iwbm_cti_o			(wb_m2s_or1k_i_cti),
+	.iwbm_bte_o			(wb_m2s_or1k_i_bte),
+	.iwbm_dat_o			(wb_m2s_or1k_i_dat),
+
+	.dwbm_adr_o			(wb_m2s_or1k_d_adr),
+	.dwbm_stb_o			(wb_m2s_or1k_d_stb),
+	.dwbm_cyc_o			(wb_m2s_or1k_d_cyc),
+	.dwbm_sel_o			(wb_m2s_or1k_d_sel),
+	.dwbm_we_o			(wb_m2s_or1k_d_we ),
+	.dwbm_cti_o			(wb_m2s_or1k_d_cti),
+	.dwbm_bte_o			(wb_m2s_or1k_d_bte),
+	.dwbm_dat_o			(wb_m2s_or1k_d_dat),
+
+	.clk				(wb_clk),
+	.rst				(or1k_rst),
+
+	.iwbm_err_i			(wb_s2m_or1k_i_err),
+	.iwbm_ack_i			(wb_s2m_or1k_i_ack),
+	.iwbm_dat_i			(wb_s2m_or1k_i_dat),
+	.iwbm_rty_i			(wb_s2m_or1k_i_rty),
+
+	.dwbm_err_i			(wb_s2m_or1k_d_err),
+	.dwbm_ack_i			(wb_s2m_or1k_d_ack),
+	.dwbm_dat_i			(wb_s2m_or1k_d_dat),
+	.dwbm_rty_i			(wb_s2m_or1k_d_rty),
+
+	.irq_i				(or1k_irq),
+
+	.du_addr_i			(or1k_dbg_adr_i[15:0]),
+	.du_stb_i			(or1k_dbg_stb_i),
+	.du_dat_i			(or1k_dbg_dat_i),
+	.du_we_i			(or1k_dbg_we_i),
+	.du_dat_o			(or1k_dbg_dat_o),
+	.du_ack_o			(or1k_dbg_ack_o),
+	.du_stall_i			(or1k_dbg_stall_i),
+	.du_stall_o			(or1k_dbg_bp_o)
+);
+`endif
+
+////////////////////////////////////////////////////////////////////////
+//
+// Debug Interface
+//
+////////////////////////////////////////////////////////////////////////
+
+adbg_top dbg_if0 (
+	// OR1K interface
+	.cpu0_clk_i	(wb_clk),
+	.cpu0_rst_o	(or1k_dbg_rst),
+	.cpu0_addr_o	(or1k_dbg_adr_i),
+	.cpu0_data_o	(or1k_dbg_dat_i),
+	.cpu0_stb_o	(or1k_dbg_stb_i),
+	.cpu0_we_o	(or1k_dbg_we_i),
+	.cpu0_data_i	(or1k_dbg_dat_o),
+	.cpu0_ack_i	(or1k_dbg_ack_o),
+	.cpu0_stall_o	(or1k_dbg_stall_i),
+	.cpu0_bp_i	(or1k_dbg_bp_o),
+
+	// TAP interface
+	.tck_i		(dbg_tck),
+	.tdi_i		(jtag_tap_tdo),
+	.tdo_o		(dbg_if_tdo),
+	.rst_i		(wb_rst),
+	.capture_dr_i	(jtag_tap_capture_dr),
+	.shift_dr_i	(jtag_tap_shift_dr),
+	.pause_dr_i	(jtag_tap_pause_dr),
+	.update_dr_i	(jtag_tap_update_dr),
+	.debug_select_i	(dbg_if_select),
+
+	// Wishbone debug master
+	.wb_clk_i	(wb_clk),
+	.wb_dat_i	(wb_s2m_dbg_dat),
+	.wb_ack_i	(wb_s2m_dbg_ack),
+	.wb_err_i	(wb_s2m_dbg_err),
+
+	.wb_adr_o	(wb_m2s_dbg_adr),
+	.wb_dat_o	(wb_m2s_dbg_dat),
+	.wb_cyc_o	(wb_m2s_dbg_cyc),
+	.wb_stb_o	(wb_m2s_dbg_stb),
+	.wb_sel_o	(wb_m2s_dbg_sel),
+	.wb_we_o	(wb_m2s_dbg_we),
+	.wb_cti_o	(wb_m2s_dbg_cti),
+	.wb_bte_o	(wb_m2s_dbg_bte)
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// ROM
+//
+////////////////////////////////////////////////////////////////////////
+
+assign	wb_s2m_rom0_err = 1'b0;
+assign	wb_s2m_rom0_rty = 1'b0;
+
+`ifdef BOOTROM
+rom #(.ADDR_WIDTH(rom0_aw))
+rom0 (
+	.wb_clk		(wb_clk),
+	.wb_rst		(wb_rst),
+	.wb_adr_i	(wb_m2s_rom0_adr[(rom0_aw + 2) - 1 : 2]),
+	.wb_cyc_i	(wb_m2s_rom0_cyc),
+	.wb_stb_i	(wb_m2s_rom0_stb),
+	.wb_cti_i	(wb_m2s_rom0_cti),
+	.wb_bte_i	(wb_m2s_rom0_bte),
+	.wb_dat_o	(wb_s2m_rom0_dat),
+	.wb_ack_o	(wb_s2m_rom0_ack)
+);
+`else
+assign	wb_s2m_rom0_dat_o = 0;
+assign	wb_s2m_rom0_ack_o = 0;
+`endif
+
+////////////////////////////////////////////////////////////////////////
+//
+// SDRAM Memory Controller
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	[15:0]	sdram_dq_i;
+wire	[15:0]	sdram_dq_o;
+wire		sdram_dq_oe;
+
+assign	sdram_dq_i = sdram_dq_pad_io;
+assign	sdram_dq_pad_io = sdram_dq_oe ? sdram_dq_o : 16'bz;
+assign	sdram_clk_pad_o = sdram_clk;
+
+assign	wb_s2m_sdram_ibus_err = 0;
+assign	wb_s2m_sdram_ibus_rty = 0;
+
+assign	wb_s2m_sdram_dbus_err = 0;
+assign	wb_s2m_sdram_dbus_rty = 0;
+
+wb_sdram_ctrl #(
+`ifdef ICARUS_SIM
+	.TECHNOLOGY			("GENERIC"),
+`else
+	.TECHNOLOGY			("ALTERA"),
+`endif
+	.CLK_FREQ_MHZ			(100),	// sdram_clk freq in MHZ
+`ifdef SIM
+	.POWERUP_DELAY			(1),	// power up delay in us
+`endif
+	.WB_PORTS			(2),	// Number of wishbone ports
+	.BUF_WIDTH			(3),
+	.BURST_LENGTH			(8),
+	.ROW_WIDTH			(12),	// Row width
+	.COL_WIDTH			(8),	// Column width
+	.BA_WIDTH			(2),	// Ba width
+	.tCAC				(3),	// CAS Latency
+	.tRAC				(5),	// RAS Latency
+	.tRP				(3),	// Command Period (PRE to ACT)
+	.tRC				(7),	// Command Period (REF to REF / ACT to ACT)
+	.tMRD				(2)	// Mode Register Set To Command Delay time
+)
+
+wb_sdram_ctrl0 (
+	// External SDRAM interface
+	.ba_pad_o	(sdram_ba_pad_o[1:0]),
+	.a_pad_o	(sdram_a_pad_o[11:0]),
+	.cs_n_pad_o	(sdram_cs_n_pad_o),
+	.ras_pad_o	(sdram_ras_pad_o),
+	.cas_pad_o	(sdram_cas_pad_o),
+	.we_pad_o	(sdram_we_pad_o),
+	.dq_i		(sdram_dq_i[15:0]),
+	.dq_o		(sdram_dq_o[15:0]),
+	.dqm_pad_o	(sdram_dqm_pad_o[1:0]),
+	.dq_oe		(sdram_dq_oe),
+	.cke_pad_o	(sdram_cke_pad_o),
+
+	.sdram_clk	(sdram_clk),
+	.sdram_rst	(sdram_rst),
+
+	.wb_clk		(wb_clk),
+	.wb_rst		(wb_rst),
+
+	.wb_adr_i	({wb_m2s_sdram_ibus_adr, wb_m2s_sdram_dbus_adr}),
+	.wb_stb_i	({wb_m2s_sdram_ibus_stb, wb_m2s_sdram_dbus_stb}),
+	.wb_cyc_i	({wb_m2s_sdram_ibus_cyc, wb_m2s_sdram_dbus_cyc}),
+	.wb_cti_i	({wb_m2s_sdram_ibus_cti, wb_m2s_sdram_dbus_cti}),
+	.wb_bte_i	({wb_m2s_sdram_ibus_bte, wb_m2s_sdram_dbus_bte}),
+	.wb_we_i	({wb_m2s_sdram_ibus_we,  wb_m2s_sdram_dbus_we }),
+	.wb_sel_i	({wb_m2s_sdram_ibus_sel, wb_m2s_sdram_dbus_sel}),
+	.wb_dat_i	({wb_m2s_sdram_ibus_dat, wb_m2s_sdram_dbus_dat}),
+	.wb_dat_o	({wb_s2m_sdram_ibus_dat, wb_s2m_sdram_dbus_dat}),
+	.wb_ack_o	({wb_s2m_sdram_ibus_ack, wb_s2m_sdram_dbus_ack})
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// UART0
+//
+////////////////////////////////////////////////////////////////////////
+
+wire	uart0_irq;
+
+wire [31:0]	wb8_m2s_uart0_adr;
+wire [1:0]	wb8_m2s_uart0_bte;
+wire [2:0]	wb8_m2s_uart0_cti;
+wire		wb8_m2s_uart0_cyc;
+wire [7:0]	wb8_m2s_uart0_dat;
+wire		wb8_m2s_uart0_stb;
+wire		wb8_m2s_uart0_we;
+wire [7:0] 	wb8_s2m_uart0_dat;
+wire		wb8_s2m_uart0_ack;
+wire		wb8_s2m_uart0_err;
+wire		wb8_s2m_uart0_rty;
+
+assign	wb8_s2m_uart0_err = 0;
+assign	wb8_s2m_uart0_rty = 0;
+
+uart_top uart16550_0 (
+	// Wishbone slave interface
+	.wb_clk_i	(wb_clk),
+	.wb_rst_i	(wb_rst),
+	.wb_adr_i	(wb8_m2s_uart0_adr[uart0_aw-1:0]),
+	.wb_dat_i	(wb8_m2s_uart0_dat),
+	.wb_we_i	(wb8_m2s_uart0_we),
+	.wb_stb_i	(wb8_m2s_uart0_stb),
+	.wb_cyc_i	(wb8_m2s_uart0_cyc),
+	.wb_sel_i	(4'b0), // Not used in 8-bit mode
+	.wb_dat_o	(wb8_s2m_uart0_dat),
+	.wb_ack_o	(wb8_s2m_uart0_ack),
+
+	// Outputs
+	.int_o		(uart0_irq),
+	.stx_pad_o	(uart0_stx_pad_o),
+	.rts_pad_o	(),
+	.dtr_pad_o	(),
+
+	// Inputs
+	.srx_pad_i	(uart0_srx_pad_i),
+	.cts_pad_i	(1'b0),
+	.dsr_pad_i	(1'b0),
+	.ri_pad_i	(1'b0),
+	.dcd_pad_i	(1'b0)
+);
+
+// 32-bit to 8-bit wishbone bus resize
+wb_data_resize wb_data_resize_uart0 (
+	// Wishbone Master interface
+	.wbm_adr_i	(wb_m2s_uart0_adr),
+	.wbm_dat_i	(wb_m2s_uart0_dat),
+	.wbm_sel_i	(wb_m2s_uart0_sel),
+	.wbm_we_i	(wb_m2s_uart0_we ),
+	.wbm_cyc_i	(wb_m2s_uart0_cyc),
+	.wbm_stb_i	(wb_m2s_uart0_stb),
+	.wbm_cti_i	(wb_m2s_uart0_cti),
+	.wbm_bte_i	(wb_m2s_uart0_bte),
+	.wbm_dat_o	(wb_s2m_uart0_dat),
+	.wbm_ack_o	(wb_s2m_uart0_ack),
+	.wbm_err_o	(wb_s2m_uart0_err),
+	.wbm_rty_o	(wb_s2m_uart0_rty),
+
+	// Wishbone Slave interface
+	.wbs_adr_o	(wb8_m2s_uart0_adr),
+	.wbs_dat_o	(wb8_m2s_uart0_dat),
+	.wbs_we_o 	(wb8_m2s_uart0_we ),
+	.wbs_cyc_o	(wb8_m2s_uart0_cyc),
+	.wbs_stb_o	(wb8_m2s_uart0_stb),
+	.wbs_cti_o	(wb8_m2s_uart0_cti),
+	.wbs_bte_o	(wb8_m2s_uart0_bte),
+	.wbs_dat_i	(wb8_s2m_uart0_dat),
+	.wbs_ack_i	(wb8_s2m_uart0_ack),
+	.wbs_err_i	(wb8_s2m_uart0_err),
+	.wbs_rty_i	(wb8_s2m_uart0_rty)
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// GPIO 0
+//
+////////////////////////////////////////////////////////////////////////
+
+wire [7:0]	gpio0_in;
+wire [7:0]	gpio0_out;
+wire [7:0]	gpio0_dir;
+
+wire [31:0]	wb8_m2s_gpio0_adr;
+wire [1:0]	wb8_m2s_gpio0_bte;
+wire [2:0]	wb8_m2s_gpio0_cti;
+wire		wb8_m2s_gpio0_cyc;
+wire [7:0]	wb8_m2s_gpio0_dat;
+wire		wb8_m2s_gpio0_stb;
+wire		wb8_m2s_gpio0_we;
+wire [7:0] 	wb8_s2m_gpio0_dat;
+wire		wb8_s2m_gpio0_ack;
+wire		wb8_s2m_gpio0_err;
+wire		wb8_s2m_gpio0_rty;
+
+// Tristate logic for IO
+// 0 = input, 1 = output
+genvar                    i;
+generate
+	for (i = 0; i < 8; i = i+1) begin: gpio0_tris
+		assign gpio0_io[i] = gpio0_dir[i] ? gpio0_out[i] : 1'bz;
+		assign gpio0_in[i] = gpio0_dir[i] ? gpio0_out[i] : gpio0_io[i];
+	end
+endgenerate
+
+gpio gpio0 (
+	// GPIO bus
+	.gpio_i		(gpio0_in),
+	.gpio_o		(gpio0_out),
+	.gpio_dir_o	(gpio0_dir),
+
+	// Wishbone slave interface
+	.wb_adr_i	(wb8_m2s_gpio0_adr[0]),
+	.wb_dat_i	(wb8_m2s_gpio0_dat),
+	.wb_we_i	(wb8_m2s_gpio0_we),
+	.wb_cyc_i	(wb8_m2s_gpio0_cyc),
+	.wb_stb_i	(wb8_m2s_gpio0_stb),
+	.wb_cti_i	(wb8_m2s_gpio0_cti),
+	.wb_bte_i	(wb8_m2s_gpio0_bte),
+	.wb_dat_o	(wb8_s2m_gpio0_dat),
+	.wb_ack_o	(wb8_s2m_gpio0_ack),
+	.wb_err_o	(wb8_s2m_gpio0_err),
+	.wb_rty_o	(wb8_s2m_gpio0_rty),
+
+	.wb_clk		(wb_clk),
+	.wb_rst		(wb_rst)
+);
+
+// 32-bit to 8-bit wishbone bus resize
+wb_data_resize wb_data_resize_gpio0 (
+	// Wishbone Master interface
+	.wbm_adr_i	(wb_m2s_gpio0_adr),
+	.wbm_dat_i	(wb_m2s_gpio0_dat),
+	.wbm_sel_i	(wb_m2s_gpio0_sel),
+	.wbm_we_i	(wb_m2s_gpio0_we ),
+	.wbm_cyc_i	(wb_m2s_gpio0_cyc),
+	.wbm_stb_i	(wb_m2s_gpio0_stb),
+	.wbm_cti_i	(wb_m2s_gpio0_cti),
+	.wbm_bte_i	(wb_m2s_gpio0_bte),
+	.wbm_dat_o	(wb_s2m_gpio0_dat),
+	.wbm_ack_o	(wb_s2m_gpio0_ack),
+	.wbm_err_o	(wb_s2m_gpio0_err),
+	.wbm_rty_o	(wb_s2m_gpio0_rty),
+
+	// Wishbone Slave interface
+	.wbs_adr_o	(wb8_m2s_gpio0_adr),
+	.wbs_dat_o	(wb8_m2s_gpio0_dat),
+	.wbs_we_o	(wb8_m2s_gpio0_we ),
+	.wbs_cyc_o	(wb8_m2s_gpio0_cyc),
+	.wbs_stb_o	(wb8_m2s_gpio0_stb),
+	.wbs_cti_o	(wb8_m2s_gpio0_cti),
+	.wbs_bte_o	(wb8_m2s_gpio0_bte),
+	.wbs_dat_i	(wb8_s2m_gpio0_dat),
+	.wbs_ack_i	(wb8_s2m_gpio0_ack),
+	.wbs_err_i	(wb8_s2m_gpio0_err),
+	.wbs_rty_i	(wb8_s2m_gpio0_rty)
+);
+
+////////////////////////////////////////////////////////////////////////
+//
+// Interrupt assignment
+//
+////////////////////////////////////////////////////////////////////////
+
+assign or1k_irq[0] = 0; // Non-maskable inside OR1K
+assign or1k_irq[1] = 0; // Non-maskable inside OR1K
+assign or1k_irq[2] = uart0_irq;
+assign or1k_irq[3] = 0;
+assign or1k_irq[4] = 0;
+assign or1k_irq[5] = 0;
+assign or1k_irq[6] = 0;
+assign or1k_irq[7] = 0;
+assign or1k_irq[8] = 0;
+assign or1k_irq[9] = 0;
+assign or1k_irq[10] = 0;
+assign or1k_irq[11] = 0;
+assign or1k_irq[12] = 0;
+assign or1k_irq[13] = 0;
+assign or1k_irq[14] = 0;
+assign or1k_irq[15] = 0;
+assign or1k_irq[16] = 0;
+assign or1k_irq[17] = 0;
+assign or1k_irq[18] = 0;
+assign or1k_irq[19] = 0;
+assign or1k_irq[20] = 0;
+assign or1k_irq[21] = 0;
+assign or1k_irq[22] = 0;
+assign or1k_irq[23] = 0;
+assign or1k_irq[24] = 0;
+assign or1k_irq[25] = 0;
+assign or1k_irq[26] = 0;
+assign or1k_irq[27] = 0;
+assign or1k_irq[28] = 0;
+assign or1k_irq[29] = 0;
+assign or1k_irq[30] = 0;
+assign or1k_irq[31] = 0;
+
+endmodule // orpsoc_top
+
+
diff --git a/systems/de2/rtl/verilog/rom.v b/systems/de2/rtl/verilog/rom.v
new file mode 100755
index 00000000..b653029c
--- /dev/null
+++ b/systems/de2/rtl/verilog/rom.v
@@ -0,0 +1,127 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  ROM                                                         ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Michael Unneback (unneback@opencores.org)             ////
+////      - Julius Baxter    (julius@opencores.org)               ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2009 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+module rom #(
+	parameter ADDR_WIDTH = 5,
+	parameter B3_BURST   = 0
+)
+(
+	input					wb_clk,
+	input					wb_rst,
+	input	[(ADDR_WIDTH + 2) - 1:2]	wb_adr_i,
+	input					wb_stb_i,
+	input					wb_cyc_i,
+	input		[2:0]			wb_cti_i,
+	input		[1:0]			wb_bte_i,
+	output reg	[31:0]			wb_dat_o,
+	output reg				wb_ack_o
+);
+
+reg [ADDR_WIDTH-1:0]	adr;
+
+always @ (posedge wb_clk or posedge wb_rst)
+if (wb_rst)
+	wb_dat_o <= 32'h15000000;
+else
+	case (adr)
+	// Zero r0 and jump to 0x00000100
+	0 : wb_dat_o <= 32'h18000000;
+	1 : wb_dat_o <= 32'hA8200000;
+	2 : wb_dat_o <= 32'hA8C00100;
+	3 : wb_dat_o <= 32'h44003000;
+	4 : wb_dat_o <= 32'h15000000;
+	default: wb_dat_o <= 32'h00000000;
+	endcase // case (wb_adr_i)
+
+generate
+if (B3_BURST) begin : gen_B3_BURST
+	reg	wb_stb_i_r;
+	reg	new_access_r;
+	reg	burst_r;
+
+	wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
+	wire new_access = (wb_stb_i & !wb_stb_i_r);
+	wire new_burst = (burst & !burst_r);
+
+	always @(posedge wb_clk) begin
+	new_access_r <= new_access;
+	burst_r <= burst;
+	wb_stb_i_r <= wb_stb_i;
+	end
+
+	always @(posedge wb_clk)
+	if (wb_rst)
+		adr <= 0;
+	else if (new_access)
+		// New access, register address, ack a cycle later
+		adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2];
+		else if (burst) begin
+			if (wb_cti_i == 3'b010)
+				case (wb_bte_i)
+				2'b00: adr <= adr + 1;
+				2'b01: adr[1:0] <= adr[1:0] + 1;
+				2'b10: adr[2:0] <= adr[2:0] + 1;
+				2'b11: adr[3:0] <= adr[3:0] + 1;
+				endcase // case (wb_bte_i)
+			else
+				adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2];
+		end // if (burst)
+
+
+	always @(posedge wb_clk)
+	if (wb_rst)
+		wb_ack_o <= 0;
+		else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
+			wb_ack_o <= 0;
+		else if (wb_stb_i & ((!burst & !new_access & new_access_r) |
+			(burst & burst_r)))
+			wb_ack_o <= 1;
+		else
+			wb_ack_o <= 0;
+
+end else begin
+	always @(wb_adr_i)
+	adr <= wb_adr_i;
+
+	always @ (posedge wb_clk or posedge wb_rst)
+	if (wb_rst)
+		wb_ack_o <= 1'b0;
+	else
+		wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
+end
+
+endgenerate
+
+endmodule
diff --git a/systems/de2/rtl/verilog/wb_intercon.v b/systems/de2/rtl/verilog/wb_intercon.v
new file mode 100755
index 00000000..aa04cde6
--- /dev/null
+++ b/systems/de2/rtl/verilog/wb_intercon.v
@@ -0,0 +1,360 @@
+module wb_intercon
+   (input         wb_clk_i,
+    input         wb_rst_i,
+    input  [31:0] wb_or1k_i_adr_i,
+    input  [31:0] wb_or1k_i_dat_i,
+    input   [3:0] wb_or1k_i_sel_i,
+    input         wb_or1k_i_we_i,
+    input         wb_or1k_i_cyc_i,
+    input         wb_or1k_i_stb_i,
+    input   [2:0] wb_or1k_i_cti_i,
+    input   [1:0] wb_or1k_i_bte_i,
+    output [31:0] wb_or1k_i_dat_o,
+    output        wb_or1k_i_ack_o,
+    output        wb_or1k_i_err_o,
+    output        wb_or1k_i_rty_o,
+    input  [31:0] wb_or1k_d_adr_i,
+    input  [31:0] wb_or1k_d_dat_i,
+    input   [3:0] wb_or1k_d_sel_i,
+    input         wb_or1k_d_we_i,
+    input         wb_or1k_d_cyc_i,
+    input         wb_or1k_d_stb_i,
+    input   [2:0] wb_or1k_d_cti_i,
+    input   [1:0] wb_or1k_d_bte_i,
+    output [31:0] wb_or1k_d_dat_o,
+    output        wb_or1k_d_ack_o,
+    output        wb_or1k_d_err_o,
+    output        wb_or1k_d_rty_o,
+    input  [31:0] wb_dbg_adr_i,
+    input  [31:0] wb_dbg_dat_i,
+    input   [3:0] wb_dbg_sel_i,
+    input         wb_dbg_we_i,
+    input         wb_dbg_cyc_i,
+    input         wb_dbg_stb_i,
+    input   [2:0] wb_dbg_cti_i,
+    input   [1:0] wb_dbg_bte_i,
+    output [31:0] wb_dbg_dat_o,
+    output        wb_dbg_ack_o,
+    output        wb_dbg_err_o,
+    output        wb_dbg_rty_o,
+    output [31:0] wb_uart0_adr_o,
+    output [31:0] wb_uart0_dat_o,
+    output  [3:0] wb_uart0_sel_o,
+    output        wb_uart0_we_o,
+    output        wb_uart0_cyc_o,
+    output        wb_uart0_stb_o,
+    output  [2:0] wb_uart0_cti_o,
+    output  [1:0] wb_uart0_bte_o,
+    input  [31:0] wb_uart0_dat_i,
+    input         wb_uart0_ack_i,
+    input         wb_uart0_err_i,
+    input         wb_uart0_rty_i,
+    output [31:0] wb_sdram_dbus_adr_o,
+    output [31:0] wb_sdram_dbus_dat_o,
+    output  [3:0] wb_sdram_dbus_sel_o,
+    output        wb_sdram_dbus_we_o,
+    output        wb_sdram_dbus_cyc_o,
+    output        wb_sdram_dbus_stb_o,
+    output  [2:0] wb_sdram_dbus_cti_o,
+    output  [1:0] wb_sdram_dbus_bte_o,
+    input  [31:0] wb_sdram_dbus_dat_i,
+    input         wb_sdram_dbus_ack_i,
+    input         wb_sdram_dbus_err_i,
+    input         wb_sdram_dbus_rty_i,
+    output [31:0] wb_gpio0_adr_o,
+    output [31:0] wb_gpio0_dat_o,
+    output  [3:0] wb_gpio0_sel_o,
+    output        wb_gpio0_we_o,
+    output        wb_gpio0_cyc_o,
+    output        wb_gpio0_stb_o,
+    output  [2:0] wb_gpio0_cti_o,
+    output  [1:0] wb_gpio0_bte_o,
+    input  [31:0] wb_gpio0_dat_i,
+    input         wb_gpio0_ack_i,
+    input         wb_gpio0_err_i,
+    input         wb_gpio0_rty_i,
+    output [31:0] wb_rom0_adr_o,
+    output [31:0] wb_rom0_dat_o,
+    output  [3:0] wb_rom0_sel_o,
+    output        wb_rom0_we_o,
+    output        wb_rom0_cyc_o,
+    output        wb_rom0_stb_o,
+    output  [2:0] wb_rom0_cti_o,
+    output  [1:0] wb_rom0_bte_o,
+    input  [31:0] wb_rom0_dat_i,
+    input         wb_rom0_ack_i,
+    input         wb_rom0_err_i,
+    input         wb_rom0_rty_i,
+    output [31:0] wb_sdram_ibus_adr_o,
+    output [31:0] wb_sdram_ibus_dat_o,
+    output  [3:0] wb_sdram_ibus_sel_o,
+    output        wb_sdram_ibus_we_o,
+    output        wb_sdram_ibus_cyc_o,
+    output        wb_sdram_ibus_stb_o,
+    output  [2:0] wb_sdram_ibus_cti_o,
+    output  [1:0] wb_sdram_ibus_bte_o,
+    input  [31:0] wb_sdram_ibus_dat_i,
+    input         wb_sdram_ibus_ack_i,
+    input         wb_sdram_ibus_err_i,
+    input         wb_sdram_ibus_rty_i);
+
+wire [31:0] wb_m2s_or1k_d_sdram_dbus_adr;
+wire [31:0] wb_m2s_or1k_d_sdram_dbus_dat;
+wire  [3:0] wb_m2s_or1k_d_sdram_dbus_sel;
+wire        wb_m2s_or1k_d_sdram_dbus_we;
+wire        wb_m2s_or1k_d_sdram_dbus_cyc;
+wire        wb_m2s_or1k_d_sdram_dbus_stb;
+wire  [2:0] wb_m2s_or1k_d_sdram_dbus_cti;
+wire  [1:0] wb_m2s_or1k_d_sdram_dbus_bte;
+wire [31:0] wb_s2m_or1k_d_sdram_dbus_dat;
+wire        wb_s2m_or1k_d_sdram_dbus_ack;
+wire        wb_s2m_or1k_d_sdram_dbus_err;
+wire        wb_s2m_or1k_d_sdram_dbus_rty;
+wire [31:0] wb_m2s_or1k_d_uart0_adr;
+wire [31:0] wb_m2s_or1k_d_uart0_dat;
+wire  [3:0] wb_m2s_or1k_d_uart0_sel;
+wire        wb_m2s_or1k_d_uart0_we;
+wire        wb_m2s_or1k_d_uart0_cyc;
+wire        wb_m2s_or1k_d_uart0_stb;
+wire  [2:0] wb_m2s_or1k_d_uart0_cti;
+wire  [1:0] wb_m2s_or1k_d_uart0_bte;
+wire [31:0] wb_s2m_or1k_d_uart0_dat;
+wire        wb_s2m_or1k_d_uart0_ack;
+wire        wb_s2m_or1k_d_uart0_err;
+wire        wb_s2m_or1k_d_uart0_rty;
+wire [31:0] wb_m2s_or1k_d_gpio0_adr;
+wire [31:0] wb_m2s_or1k_d_gpio0_dat;
+wire  [3:0] wb_m2s_or1k_d_gpio0_sel;
+wire        wb_m2s_or1k_d_gpio0_we;
+wire        wb_m2s_or1k_d_gpio0_cyc;
+wire        wb_m2s_or1k_d_gpio0_stb;
+wire  [2:0] wb_m2s_or1k_d_gpio0_cti;
+wire  [1:0] wb_m2s_or1k_d_gpio0_bte;
+wire [31:0] wb_s2m_or1k_d_gpio0_dat;
+wire        wb_s2m_or1k_d_gpio0_ack;
+wire        wb_s2m_or1k_d_gpio0_err;
+wire        wb_s2m_or1k_d_gpio0_rty;
+wire [31:0] wb_m2s_dbg_sdram_dbus_adr;
+wire [31:0] wb_m2s_dbg_sdram_dbus_dat;
+wire  [3:0] wb_m2s_dbg_sdram_dbus_sel;
+wire        wb_m2s_dbg_sdram_dbus_we;
+wire        wb_m2s_dbg_sdram_dbus_cyc;
+wire        wb_m2s_dbg_sdram_dbus_stb;
+wire  [2:0] wb_m2s_dbg_sdram_dbus_cti;
+wire  [1:0] wb_m2s_dbg_sdram_dbus_bte;
+wire [31:0] wb_s2m_dbg_sdram_dbus_dat;
+wire        wb_s2m_dbg_sdram_dbus_ack;
+wire        wb_s2m_dbg_sdram_dbus_err;
+wire        wb_s2m_dbg_sdram_dbus_rty;
+wire [31:0] wb_m2s_dbg_uart0_adr;
+wire [31:0] wb_m2s_dbg_uart0_dat;
+wire  [3:0] wb_m2s_dbg_uart0_sel;
+wire        wb_m2s_dbg_uart0_we;
+wire        wb_m2s_dbg_uart0_cyc;
+wire        wb_m2s_dbg_uart0_stb;
+wire  [2:0] wb_m2s_dbg_uart0_cti;
+wire  [1:0] wb_m2s_dbg_uart0_bte;
+wire [31:0] wb_s2m_dbg_uart0_dat;
+wire        wb_s2m_dbg_uart0_ack;
+wire        wb_s2m_dbg_uart0_err;
+wire        wb_s2m_dbg_uart0_rty;
+wire [31:0] wb_m2s_dbg_gpio0_adr;
+wire [31:0] wb_m2s_dbg_gpio0_dat;
+wire  [3:0] wb_m2s_dbg_gpio0_sel;
+wire        wb_m2s_dbg_gpio0_we;
+wire        wb_m2s_dbg_gpio0_cyc;
+wire        wb_m2s_dbg_gpio0_stb;
+wire  [2:0] wb_m2s_dbg_gpio0_cti;
+wire  [1:0] wb_m2s_dbg_gpio0_bte;
+wire [31:0] wb_s2m_dbg_gpio0_dat;
+wire        wb_s2m_dbg_gpio0_ack;
+wire        wb_s2m_dbg_gpio0_err;
+wire        wb_s2m_dbg_gpio0_rty;
+
+wb_mux
+  #(.num_slaves (2),
+    .MATCH_ADDR ({32'h00000000, 32'hf0000100}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffc0}))
+ wb_mux_or1k_i
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_or1k_i_adr_i),
+    .wbm_dat_i (wb_or1k_i_dat_i),
+    .wbm_sel_i (wb_or1k_i_sel_i),
+    .wbm_we_i  (wb_or1k_i_we_i),
+    .wbm_cyc_i (wb_or1k_i_cyc_i),
+    .wbm_stb_i (wb_or1k_i_stb_i),
+    .wbm_cti_i (wb_or1k_i_cti_i),
+    .wbm_bte_i (wb_or1k_i_bte_i),
+    .wbm_dat_o (wb_or1k_i_dat_o),
+    .wbm_ack_o (wb_or1k_i_ack_o),
+    .wbm_err_o (wb_or1k_i_err_o),
+    .wbm_rty_o (wb_or1k_i_rty_o),
+    .wbs_adr_o ({wb_sdram_ibus_adr_o, wb_rom0_adr_o}),
+    .wbs_dat_o ({wb_sdram_ibus_dat_o, wb_rom0_dat_o}),
+    .wbs_sel_o ({wb_sdram_ibus_sel_o, wb_rom0_sel_o}),
+    .wbs_we_o  ({wb_sdram_ibus_we_o, wb_rom0_we_o}),
+    .wbs_cyc_o ({wb_sdram_ibus_cyc_o, wb_rom0_cyc_o}),
+    .wbs_stb_o ({wb_sdram_ibus_stb_o, wb_rom0_stb_o}),
+    .wbs_cti_o ({wb_sdram_ibus_cti_o, wb_rom0_cti_o}),
+    .wbs_bte_o ({wb_sdram_ibus_bte_o, wb_rom0_bte_o}),
+    .wbs_dat_i ({wb_sdram_ibus_dat_i, wb_rom0_dat_i}),
+    .wbs_ack_i ({wb_sdram_ibus_ack_i, wb_rom0_ack_i}),
+    .wbs_err_i ({wb_sdram_ibus_err_i, wb_rom0_err_i}),
+    .wbs_rty_i ({wb_sdram_ibus_rty_i, wb_rom0_rty_i}));
+
+wb_mux
+  #(.num_slaves (3),
+    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
+ wb_mux_or1k_d
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_or1k_d_adr_i),
+    .wbm_dat_i (wb_or1k_d_dat_i),
+    .wbm_sel_i (wb_or1k_d_sel_i),
+    .wbm_we_i  (wb_or1k_d_we_i),
+    .wbm_cyc_i (wb_or1k_d_cyc_i),
+    .wbm_stb_i (wb_or1k_d_stb_i),
+    .wbm_cti_i (wb_or1k_d_cti_i),
+    .wbm_bte_i (wb_or1k_d_bte_i),
+    .wbm_dat_o (wb_or1k_d_dat_o),
+    .wbm_ack_o (wb_or1k_d_ack_o),
+    .wbm_err_o (wb_or1k_d_err_o),
+    .wbm_rty_o (wb_or1k_d_rty_o),
+    .wbs_adr_o ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_or1k_d_uart0_adr, wb_m2s_or1k_d_gpio0_adr}),
+    .wbs_dat_o ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_or1k_d_uart0_dat, wb_m2s_or1k_d_gpio0_dat}),
+    .wbs_sel_o ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_or1k_d_uart0_sel, wb_m2s_or1k_d_gpio0_sel}),
+    .wbs_we_o  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_or1k_d_uart0_we, wb_m2s_or1k_d_gpio0_we}),
+    .wbs_cyc_o ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_or1k_d_uart0_cyc, wb_m2s_or1k_d_gpio0_cyc}),
+    .wbs_stb_o ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_or1k_d_uart0_stb, wb_m2s_or1k_d_gpio0_stb}),
+    .wbs_cti_o ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_or1k_d_uart0_cti, wb_m2s_or1k_d_gpio0_cti}),
+    .wbs_bte_o ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_or1k_d_uart0_bte, wb_m2s_or1k_d_gpio0_bte}),
+    .wbs_dat_i ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_or1k_d_uart0_dat, wb_s2m_or1k_d_gpio0_dat}),
+    .wbs_ack_i ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_or1k_d_uart0_ack, wb_s2m_or1k_d_gpio0_ack}),
+    .wbs_err_i ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_or1k_d_uart0_err, wb_s2m_or1k_d_gpio0_err}),
+    .wbs_rty_i ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_or1k_d_uart0_rty, wb_s2m_or1k_d_gpio0_rty}));
+
+wb_mux
+  #(.num_slaves (3),
+    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
+ wb_mux_dbg
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_dbg_adr_i),
+    .wbm_dat_i (wb_dbg_dat_i),
+    .wbm_sel_i (wb_dbg_sel_i),
+    .wbm_we_i  (wb_dbg_we_i),
+    .wbm_cyc_i (wb_dbg_cyc_i),
+    .wbm_stb_i (wb_dbg_stb_i),
+    .wbm_cti_i (wb_dbg_cti_i),
+    .wbm_bte_i (wb_dbg_bte_i),
+    .wbm_dat_o (wb_dbg_dat_o),
+    .wbm_ack_o (wb_dbg_ack_o),
+    .wbm_err_o (wb_dbg_err_o),
+    .wbm_rty_o (wb_dbg_rty_o),
+    .wbs_adr_o ({wb_m2s_dbg_sdram_dbus_adr, wb_m2s_dbg_uart0_adr, wb_m2s_dbg_gpio0_adr}),
+    .wbs_dat_o ({wb_m2s_dbg_sdram_dbus_dat, wb_m2s_dbg_uart0_dat, wb_m2s_dbg_gpio0_dat}),
+    .wbs_sel_o ({wb_m2s_dbg_sdram_dbus_sel, wb_m2s_dbg_uart0_sel, wb_m2s_dbg_gpio0_sel}),
+    .wbs_we_o  ({wb_m2s_dbg_sdram_dbus_we, wb_m2s_dbg_uart0_we, wb_m2s_dbg_gpio0_we}),
+    .wbs_cyc_o ({wb_m2s_dbg_sdram_dbus_cyc, wb_m2s_dbg_uart0_cyc, wb_m2s_dbg_gpio0_cyc}),
+    .wbs_stb_o ({wb_m2s_dbg_sdram_dbus_stb, wb_m2s_dbg_uart0_stb, wb_m2s_dbg_gpio0_stb}),
+    .wbs_cti_o ({wb_m2s_dbg_sdram_dbus_cti, wb_m2s_dbg_uart0_cti, wb_m2s_dbg_gpio0_cti}),
+    .wbs_bte_o ({wb_m2s_dbg_sdram_dbus_bte, wb_m2s_dbg_uart0_bte, wb_m2s_dbg_gpio0_bte}),
+    .wbs_dat_i ({wb_s2m_dbg_sdram_dbus_dat, wb_s2m_dbg_uart0_dat, wb_s2m_dbg_gpio0_dat}),
+    .wbs_ack_i ({wb_s2m_dbg_sdram_dbus_ack, wb_s2m_dbg_uart0_ack, wb_s2m_dbg_gpio0_ack}),
+    .wbs_err_i ({wb_s2m_dbg_sdram_dbus_err, wb_s2m_dbg_uart0_err, wb_s2m_dbg_gpio0_err}),
+    .wbs_rty_i ({wb_s2m_dbg_sdram_dbus_rty, wb_s2m_dbg_uart0_rty, wb_s2m_dbg_gpio0_rty}));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_uart0
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_uart0_adr, wb_m2s_dbg_uart0_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_uart0_dat, wb_m2s_dbg_uart0_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_uart0_sel, wb_m2s_dbg_uart0_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_uart0_we, wb_m2s_dbg_uart0_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_uart0_cyc, wb_m2s_dbg_uart0_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_uart0_stb, wb_m2s_dbg_uart0_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_uart0_cti, wb_m2s_dbg_uart0_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_uart0_bte, wb_m2s_dbg_uart0_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_uart0_dat, wb_s2m_dbg_uart0_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}),
+    .wbs_adr_o (wb_uart0_adr_o),
+    .wbs_dat_o (wb_uart0_dat_o),
+    .wbs_sel_o (wb_uart0_sel_o),
+    .wbs_we_o  (wb_uart0_we_o),
+    .wbs_cyc_o (wb_uart0_cyc_o),
+    .wbs_stb_o (wb_uart0_stb_o),
+    .wbs_cti_o (wb_uart0_cti_o),
+    .wbs_bte_o (wb_uart0_bte_o),
+    .wbs_dat_i (wb_uart0_dat_i),
+    .wbs_ack_i (wb_uart0_ack_i),
+    .wbs_err_i (wb_uart0_err_i),
+    .wbs_rty_i (wb_uart0_rty_i));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_sdram_dbus
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_dbg_sdram_dbus_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_dbg_sdram_dbus_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_dbg_sdram_dbus_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_dbg_sdram_dbus_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_dbg_sdram_dbus_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_dbg_sdram_dbus_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_dbg_sdram_dbus_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_dbg_sdram_dbus_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_dbg_sdram_dbus_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_dbg_sdram_dbus_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_dbg_sdram_dbus_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_dbg_sdram_dbus_rty}),
+    .wbs_adr_o (wb_sdram_dbus_adr_o),
+    .wbs_dat_o (wb_sdram_dbus_dat_o),
+    .wbs_sel_o (wb_sdram_dbus_sel_o),
+    .wbs_we_o  (wb_sdram_dbus_we_o),
+    .wbs_cyc_o (wb_sdram_dbus_cyc_o),
+    .wbs_stb_o (wb_sdram_dbus_stb_o),
+    .wbs_cti_o (wb_sdram_dbus_cti_o),
+    .wbs_bte_o (wb_sdram_dbus_bte_o),
+    .wbs_dat_i (wb_sdram_dbus_dat_i),
+    .wbs_ack_i (wb_sdram_dbus_ack_i),
+    .wbs_err_i (wb_sdram_dbus_err_i),
+    .wbs_rty_i (wb_sdram_dbus_rty_i));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_gpio0
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}),
+    .wbs_adr_o (wb_gpio0_adr_o),
+    .wbs_dat_o (wb_gpio0_dat_o),
+    .wbs_sel_o (wb_gpio0_sel_o),
+    .wbs_we_o  (wb_gpio0_we_o),
+    .wbs_cyc_o (wb_gpio0_cyc_o),
+    .wbs_stb_o (wb_gpio0_stb_o),
+    .wbs_cti_o (wb_gpio0_cti_o),
+    .wbs_bte_o (wb_gpio0_bte_o),
+    .wbs_dat_i (wb_gpio0_dat_i),
+    .wbs_ack_i (wb_gpio0_ack_i),
+    .wbs_err_i (wb_gpio0_err_i),
+    .wbs_rty_i (wb_gpio0_rty_i));
+
+endmodule
diff --git a/systems/de2/rtl/verilog/wb_intercon.vh b/systems/de2/rtl/verilog/wb_intercon.vh
new file mode 100755
index 00000000..e81420ee
--- /dev/null
+++ b/systems/de2/rtl/verilog/wb_intercon.vh
@@ -0,0 +1,197 @@
+wire [31:0] wb_m2s_or1k_i_adr;
+wire [31:0] wb_m2s_or1k_i_dat;
+wire  [3:0] wb_m2s_or1k_i_sel;
+wire        wb_m2s_or1k_i_we;
+wire        wb_m2s_or1k_i_cyc;
+wire        wb_m2s_or1k_i_stb;
+wire  [2:0] wb_m2s_or1k_i_cti;
+wire  [1:0] wb_m2s_or1k_i_bte;
+wire [31:0] wb_s2m_or1k_i_dat;
+wire        wb_s2m_or1k_i_ack;
+wire        wb_s2m_or1k_i_err;
+wire        wb_s2m_or1k_i_rty;
+wire [31:0] wb_m2s_or1k_d_adr;
+wire [31:0] wb_m2s_or1k_d_dat;
+wire  [3:0] wb_m2s_or1k_d_sel;
+wire        wb_m2s_or1k_d_we;
+wire        wb_m2s_or1k_d_cyc;
+wire        wb_m2s_or1k_d_stb;
+wire  [2:0] wb_m2s_or1k_d_cti;
+wire  [1:0] wb_m2s_or1k_d_bte;
+wire [31:0] wb_s2m_or1k_d_dat;
+wire        wb_s2m_or1k_d_ack;
+wire        wb_s2m_or1k_d_err;
+wire        wb_s2m_or1k_d_rty;
+wire [31:0] wb_m2s_dbg_adr;
+wire [31:0] wb_m2s_dbg_dat;
+wire  [3:0] wb_m2s_dbg_sel;
+wire        wb_m2s_dbg_we;
+wire        wb_m2s_dbg_cyc;
+wire        wb_m2s_dbg_stb;
+wire  [2:0] wb_m2s_dbg_cti;
+wire  [1:0] wb_m2s_dbg_bte;
+wire [31:0] wb_s2m_dbg_dat;
+wire        wb_s2m_dbg_ack;
+wire        wb_s2m_dbg_err;
+wire        wb_s2m_dbg_rty;
+wire [31:0] wb_m2s_uart0_adr;
+wire [31:0] wb_m2s_uart0_dat;
+wire  [3:0] wb_m2s_uart0_sel;
+wire        wb_m2s_uart0_we;
+wire        wb_m2s_uart0_cyc;
+wire        wb_m2s_uart0_stb;
+wire  [2:0] wb_m2s_uart0_cti;
+wire  [1:0] wb_m2s_uart0_bte;
+wire [31:0] wb_s2m_uart0_dat;
+wire        wb_s2m_uart0_ack;
+wire        wb_s2m_uart0_err;
+wire        wb_s2m_uart0_rty;
+wire [31:0] wb_m2s_sdram_dbus_adr;
+wire [31:0] wb_m2s_sdram_dbus_dat;
+wire  [3:0] wb_m2s_sdram_dbus_sel;
+wire        wb_m2s_sdram_dbus_we;
+wire        wb_m2s_sdram_dbus_cyc;
+wire        wb_m2s_sdram_dbus_stb;
+wire  [2:0] wb_m2s_sdram_dbus_cti;
+wire  [1:0] wb_m2s_sdram_dbus_bte;
+wire [31:0] wb_s2m_sdram_dbus_dat;
+wire        wb_s2m_sdram_dbus_ack;
+wire        wb_s2m_sdram_dbus_err;
+wire        wb_s2m_sdram_dbus_rty;
+wire [31:0] wb_m2s_gpio0_adr;
+wire [31:0] wb_m2s_gpio0_dat;
+wire  [3:0] wb_m2s_gpio0_sel;
+wire        wb_m2s_gpio0_we;
+wire        wb_m2s_gpio0_cyc;
+wire        wb_m2s_gpio0_stb;
+wire  [2:0] wb_m2s_gpio0_cti;
+wire  [1:0] wb_m2s_gpio0_bte;
+wire [31:0] wb_s2m_gpio0_dat;
+wire        wb_s2m_gpio0_ack;
+wire        wb_s2m_gpio0_err;
+wire        wb_s2m_gpio0_rty;
+wire [31:0] wb_m2s_rom0_adr;
+wire [31:0] wb_m2s_rom0_dat;
+wire  [3:0] wb_m2s_rom0_sel;
+wire        wb_m2s_rom0_we;
+wire        wb_m2s_rom0_cyc;
+wire        wb_m2s_rom0_stb;
+wire  [2:0] wb_m2s_rom0_cti;
+wire  [1:0] wb_m2s_rom0_bte;
+wire [31:0] wb_s2m_rom0_dat;
+wire        wb_s2m_rom0_ack;
+wire        wb_s2m_rom0_err;
+wire        wb_s2m_rom0_rty;
+wire [31:0] wb_m2s_sdram_ibus_adr;
+wire [31:0] wb_m2s_sdram_ibus_dat;
+wire  [3:0] wb_m2s_sdram_ibus_sel;
+wire        wb_m2s_sdram_ibus_we;
+wire        wb_m2s_sdram_ibus_cyc;
+wire        wb_m2s_sdram_ibus_stb;
+wire  [2:0] wb_m2s_sdram_ibus_cti;
+wire  [1:0] wb_m2s_sdram_ibus_bte;
+wire [31:0] wb_s2m_sdram_ibus_dat;
+wire        wb_s2m_sdram_ibus_ack;
+wire        wb_s2m_sdram_ibus_err;
+wire        wb_s2m_sdram_ibus_rty;
+
+wb_intercon wb_intercon0
+   (.wb_clk_i            (wb_clk),
+    .wb_rst_i            (wb_rst),
+    .wb_or1k_i_adr_i     (wb_m2s_or1k_i_adr),
+    .wb_or1k_i_dat_i     (wb_m2s_or1k_i_dat),
+    .wb_or1k_i_sel_i     (wb_m2s_or1k_i_sel),
+    .wb_or1k_i_we_i      (wb_m2s_or1k_i_we),
+    .wb_or1k_i_cyc_i     (wb_m2s_or1k_i_cyc),
+    .wb_or1k_i_stb_i     (wb_m2s_or1k_i_stb),
+    .wb_or1k_i_cti_i     (wb_m2s_or1k_i_cti),
+    .wb_or1k_i_bte_i     (wb_m2s_or1k_i_bte),
+    .wb_or1k_i_dat_o     (wb_s2m_or1k_i_dat),
+    .wb_or1k_i_ack_o     (wb_s2m_or1k_i_ack),
+    .wb_or1k_i_err_o     (wb_s2m_or1k_i_err),
+    .wb_or1k_i_rty_o     (wb_s2m_or1k_i_rty),
+    .wb_or1k_d_adr_i     (wb_m2s_or1k_d_adr),
+    .wb_or1k_d_dat_i     (wb_m2s_or1k_d_dat),
+    .wb_or1k_d_sel_i     (wb_m2s_or1k_d_sel),
+    .wb_or1k_d_we_i      (wb_m2s_or1k_d_we),
+    .wb_or1k_d_cyc_i     (wb_m2s_or1k_d_cyc),
+    .wb_or1k_d_stb_i     (wb_m2s_or1k_d_stb),
+    .wb_or1k_d_cti_i     (wb_m2s_or1k_d_cti),
+    .wb_or1k_d_bte_i     (wb_m2s_or1k_d_bte),
+    .wb_or1k_d_dat_o     (wb_s2m_or1k_d_dat),
+    .wb_or1k_d_ack_o     (wb_s2m_or1k_d_ack),
+    .wb_or1k_d_err_o     (wb_s2m_or1k_d_err),
+    .wb_or1k_d_rty_o     (wb_s2m_or1k_d_rty),
+    .wb_dbg_adr_i        (wb_m2s_dbg_adr),
+    .wb_dbg_dat_i        (wb_m2s_dbg_dat),
+    .wb_dbg_sel_i        (wb_m2s_dbg_sel),
+    .wb_dbg_we_i         (wb_m2s_dbg_we),
+    .wb_dbg_cyc_i        (wb_m2s_dbg_cyc),
+    .wb_dbg_stb_i        (wb_m2s_dbg_stb),
+    .wb_dbg_cti_i        (wb_m2s_dbg_cti),
+    .wb_dbg_bte_i        (wb_m2s_dbg_bte),
+    .wb_dbg_dat_o        (wb_s2m_dbg_dat),
+    .wb_dbg_ack_o        (wb_s2m_dbg_ack),
+    .wb_dbg_err_o        (wb_s2m_dbg_err),
+    .wb_dbg_rty_o        (wb_s2m_dbg_rty),
+    .wb_uart0_adr_o      (wb_m2s_uart0_adr),
+    .wb_uart0_dat_o      (wb_m2s_uart0_dat),
+    .wb_uart0_sel_o      (wb_m2s_uart0_sel),
+    .wb_uart0_we_o       (wb_m2s_uart0_we),
+    .wb_uart0_cyc_o      (wb_m2s_uart0_cyc),
+    .wb_uart0_stb_o      (wb_m2s_uart0_stb),
+    .wb_uart0_cti_o      (wb_m2s_uart0_cti),
+    .wb_uart0_bte_o      (wb_m2s_uart0_bte),
+    .wb_uart0_dat_i      (wb_s2m_uart0_dat),
+    .wb_uart0_ack_i      (wb_s2m_uart0_ack),
+    .wb_uart0_err_i      (wb_s2m_uart0_err),
+    .wb_uart0_rty_i      (wb_s2m_uart0_rty),
+    .wb_sdram_dbus_adr_o (wb_m2s_sdram_dbus_adr),
+    .wb_sdram_dbus_dat_o (wb_m2s_sdram_dbus_dat),
+    .wb_sdram_dbus_sel_o (wb_m2s_sdram_dbus_sel),
+    .wb_sdram_dbus_we_o  (wb_m2s_sdram_dbus_we),
+    .wb_sdram_dbus_cyc_o (wb_m2s_sdram_dbus_cyc),
+    .wb_sdram_dbus_stb_o (wb_m2s_sdram_dbus_stb),
+    .wb_sdram_dbus_cti_o (wb_m2s_sdram_dbus_cti),
+    .wb_sdram_dbus_bte_o (wb_m2s_sdram_dbus_bte),
+    .wb_sdram_dbus_dat_i (wb_s2m_sdram_dbus_dat),
+    .wb_sdram_dbus_ack_i (wb_s2m_sdram_dbus_ack),
+    .wb_sdram_dbus_err_i (wb_s2m_sdram_dbus_err),
+    .wb_sdram_dbus_rty_i (wb_s2m_sdram_dbus_rty),
+    .wb_gpio0_adr_o      (wb_m2s_gpio0_adr),
+    .wb_gpio0_dat_o      (wb_m2s_gpio0_dat),
+    .wb_gpio0_sel_o      (wb_m2s_gpio0_sel),
+    .wb_gpio0_we_o       (wb_m2s_gpio0_we),
+    .wb_gpio0_cyc_o      (wb_m2s_gpio0_cyc),
+    .wb_gpio0_stb_o      (wb_m2s_gpio0_stb),
+    .wb_gpio0_cti_o      (wb_m2s_gpio0_cti),
+    .wb_gpio0_bte_o      (wb_m2s_gpio0_bte),
+    .wb_gpio0_dat_i      (wb_s2m_gpio0_dat),
+    .wb_gpio0_ack_i      (wb_s2m_gpio0_ack),
+    .wb_gpio0_err_i      (wb_s2m_gpio0_err),
+    .wb_gpio0_rty_i      (wb_s2m_gpio0_rty),
+    .wb_rom0_adr_o       (wb_m2s_rom0_adr),
+    .wb_rom0_dat_o       (wb_m2s_rom0_dat),
+    .wb_rom0_sel_o       (wb_m2s_rom0_sel),
+    .wb_rom0_we_o        (wb_m2s_rom0_we),
+    .wb_rom0_cyc_o       (wb_m2s_rom0_cyc),
+    .wb_rom0_stb_o       (wb_m2s_rom0_stb),
+    .wb_rom0_cti_o       (wb_m2s_rom0_cti),
+    .wb_rom0_bte_o       (wb_m2s_rom0_bte),
+    .wb_rom0_dat_i       (wb_s2m_rom0_dat),
+    .wb_rom0_ack_i       (wb_s2m_rom0_ack),
+    .wb_rom0_err_i       (wb_s2m_rom0_err),
+    .wb_rom0_rty_i       (wb_s2m_rom0_rty),
+    .wb_sdram_ibus_adr_o (wb_m2s_sdram_ibus_adr),
+    .wb_sdram_ibus_dat_o (wb_m2s_sdram_ibus_dat),
+    .wb_sdram_ibus_sel_o (wb_m2s_sdram_ibus_sel),
+    .wb_sdram_ibus_we_o  (wb_m2s_sdram_ibus_we),
+    .wb_sdram_ibus_cyc_o (wb_m2s_sdram_ibus_cyc),
+    .wb_sdram_ibus_stb_o (wb_m2s_sdram_ibus_stb),
+    .wb_sdram_ibus_cti_o (wb_m2s_sdram_ibus_cti),
+    .wb_sdram_ibus_bte_o (wb_m2s_sdram_ibus_bte),
+    .wb_sdram_ibus_dat_i (wb_s2m_sdram_ibus_dat),
+    .wb_sdram_ibus_ack_i (wb_s2m_sdram_ibus_ack),
+    .wb_sdram_ibus_err_i (wb_s2m_sdram_ibus_err),
+    .wb_sdram_ibus_rty_i (wb_s2m_sdram_ibus_rty));
+
diff --git a/systems/de2/scripts/build_summary b/systems/de2/scripts/build_summary
new file mode 100755
index 00000000..07bb1a6f
--- /dev/null
+++ b/systems/de2/scripts/build_summary
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+FITTER_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nr "; Fitter Summary" | gawk '{print $1}' FS=":")
+FITTER_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nr "; Fitter Settings" | gawk '{print $1}' FS=":")
+
+FITTER_REPORT_START=$(($FITTER_REPORT_START - 1))
+FITTER_REPORT_END=$(($FITTER_REPORT_END - 4))
+
+echo -e "\033[31m"
+sed -n ${FITTER_REPORT_START},${FITTER_REPORT_END}p ${BUILD_ROOT}/bld-quartus/de2.fit.rpt
+
+
+FMAX_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nr "; Slow Model Fmax Summary" | gawk '{print $1}' FS=":")
+FMAX_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nr "This panel reports FMAX" | gawk '{print $1}' FS=":")
+
+FMAX_REPORT_START=$(($FMAX_REPORT_START - 1))
+FMAX_REPORT_END=$(($FMAX_REPORT_END - 1))
+
+echo
+sed -n ${FMAX_REPORT_START},${FMAX_REPORT_END}p ${BUILD_ROOT}/bld-quartus/de2.sta.rpt
+echo -e "\033[0m"

From a912ae436644b081051eb7a40d65f7de3e19a040 Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Wed, 5 Mar 2014 17:56:54 +0700
Subject: [PATCH 08/12] Readme updated

---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index 089a305a..710eda9c 100644
--- a/README.md
+++ b/README.md
@@ -2,3 +2,4 @@ orpsoc-cores
 ============
 
 Core description files for ORPSoCv3.
+Support for Altera DE2 board added (alpha, written by Tran Cong Nam).

From 8e5fddaa342786b04965e1590b9d3bf83ee157d2 Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Thu, 6 Mar 2014 11:14:59 +0700
Subject: [PATCH 09/12] minor updates by Duc

---
 cores/wb_intercon/sw/wb_intercon.v  | 442 ++++++++++++++++++++++++++++
 cores/wb_intercon/sw/wb_intercon.vh | 197 +++++++++++++
 systems/de2/de2.core                |   2 +-
 systems/de2/scripts/build_summary   |   8 +-
 4 files changed, 644 insertions(+), 5 deletions(-)
 create mode 100644 cores/wb_intercon/sw/wb_intercon.v
 create mode 100644 cores/wb_intercon/sw/wb_intercon.vh

diff --git a/cores/wb_intercon/sw/wb_intercon.v b/cores/wb_intercon/sw/wb_intercon.v
new file mode 100644
index 00000000..5358c2c6
--- /dev/null
+++ b/cores/wb_intercon/sw/wb_intercon.v
@@ -0,0 +1,442 @@
+module wb_intercon
+   (input         wb_clk_i,
+    input         wb_rst_i,
+    input  [31:0] wb_or1k_i_adr_i,
+    input  [31:0] wb_or1k_i_dat_i,
+    input   [3:0] wb_or1k_i_sel_i,
+    input         wb_or1k_i_we_i,
+    input         wb_or1k_i_cyc_i,
+    input         wb_or1k_i_stb_i,
+    input   [2:0] wb_or1k_i_cti_i,
+    input   [1:0] wb_or1k_i_bte_i,
+    output [31:0] wb_or1k_i_dat_o,
+    output        wb_or1k_i_ack_o,
+    output        wb_or1k_i_err_o,
+    output        wb_or1k_i_rty_o,
+    input  [31:0] wb_or1k_d_adr_i,
+    input  [31:0] wb_or1k_d_dat_i,
+    input   [3:0] wb_or1k_d_sel_i,
+    input         wb_or1k_d_we_i,
+    input         wb_or1k_d_cyc_i,
+    input         wb_or1k_d_stb_i,
+    input   [2:0] wb_or1k_d_cti_i,
+    input   [1:0] wb_or1k_d_bte_i,
+    output [31:0] wb_or1k_d_dat_o,
+    output        wb_or1k_d_ack_o,
+    output        wb_or1k_d_err_o,
+    output        wb_or1k_d_rty_o,
+    input  [31:0] wb_dbg_adr_i,
+    input  [31:0] wb_dbg_dat_i,
+    input   [3:0] wb_dbg_sel_i,
+    input         wb_dbg_we_i,
+    input         wb_dbg_cyc_i,
+    input         wb_dbg_stb_i,
+    input   [2:0] wb_dbg_cti_i,
+    input   [1:0] wb_dbg_bte_i,
+    output [31:0] wb_dbg_dat_o,
+    output        wb_dbg_ack_o,
+    output        wb_dbg_err_o,
+    output        wb_dbg_rty_o,
+    output [31:0] wb_uart0_adr_o,
+    output [31:0] wb_uart0_dat_o,
+    output  [3:0] wb_uart0_sel_o,
+    output        wb_uart0_we_o,
+    output        wb_uart0_cyc_o,
+    output        wb_uart0_stb_o,
+    output  [2:0] wb_uart0_cti_o,
+    output  [1:0] wb_uart0_bte_o,
+    input  [31:0] wb_uart0_dat_i,
+    input         wb_uart0_ack_i,
+    input         wb_uart0_err_i,
+    input         wb_uart0_rty_i,
+    output [31:0] wb_gpio0_adr_o,
+    output [31:0] wb_gpio0_dat_o,
+    output  [3:0] wb_gpio0_sel_o,
+    output        wb_gpio0_we_o,
+    output        wb_gpio0_cyc_o,
+    output        wb_gpio0_stb_o,
+    output  [2:0] wb_gpio0_cti_o,
+    output  [1:0] wb_gpio0_bte_o,
+    input  [31:0] wb_gpio0_dat_i,
+    input         wb_gpio0_ack_i,
+    input         wb_gpio0_err_i,
+    input         wb_gpio0_rty_i,
+    output [31:0] wb_sdram_dbus_adr_o,
+    output [31:0] wb_sdram_dbus_dat_o,
+    output  [3:0] wb_sdram_dbus_sel_o,
+    output        wb_sdram_dbus_we_o,
+    output        wb_sdram_dbus_cyc_o,
+    output        wb_sdram_dbus_stb_o,
+    output  [2:0] wb_sdram_dbus_cti_o,
+    output  [1:0] wb_sdram_dbus_bte_o,
+    input  [31:0] wb_sdram_dbus_dat_i,
+    input         wb_sdram_dbus_ack_i,
+    input         wb_sdram_dbus_err_i,
+    input         wb_sdram_dbus_rty_i,
+    output [31:0] wb_rom0_adr_o,
+    output [31:0] wb_rom0_dat_o,
+    output  [3:0] wb_rom0_sel_o,
+    output        wb_rom0_we_o,
+    output        wb_rom0_cyc_o,
+    output        wb_rom0_stb_o,
+    output  [2:0] wb_rom0_cti_o,
+    output  [1:0] wb_rom0_bte_o,
+    input  [31:0] wb_rom0_dat_i,
+    input         wb_rom0_ack_i,
+    input         wb_rom0_err_i,
+    input         wb_rom0_rty_i,
+    output [31:0] wb_sdram_ibus_adr_o,
+    output [31:0] wb_sdram_ibus_dat_o,
+    output  [3:0] wb_sdram_ibus_sel_o,
+    output        wb_sdram_ibus_we_o,
+    output        wb_sdram_ibus_cyc_o,
+    output        wb_sdram_ibus_stb_o,
+    output  [2:0] wb_sdram_ibus_cti_o,
+    output  [1:0] wb_sdram_ibus_bte_o,
+    input  [31:0] wb_sdram_ibus_dat_i,
+    input         wb_sdram_ibus_ack_i,
+    input         wb_sdram_ibus_err_i,
+    input         wb_sdram_ibus_rty_i);
+
+wire [31:0] wb_m2s_or1k_d_sdram_dbus_adr;
+wire [31:0] wb_m2s_or1k_d_sdram_dbus_dat;
+wire  [3:0] wb_m2s_or1k_d_sdram_dbus_sel;
+wire        wb_m2s_or1k_d_sdram_dbus_we;
+wire        wb_m2s_or1k_d_sdram_dbus_cyc;
+wire        wb_m2s_or1k_d_sdram_dbus_stb;
+wire  [2:0] wb_m2s_or1k_d_sdram_dbus_cti;
+wire  [1:0] wb_m2s_or1k_d_sdram_dbus_bte;
+wire [31:0] wb_s2m_or1k_d_sdram_dbus_dat;
+wire        wb_s2m_or1k_d_sdram_dbus_ack;
+wire        wb_s2m_or1k_d_sdram_dbus_err;
+wire        wb_s2m_or1k_d_sdram_dbus_rty;
+wire [31:0] wb_m2s_or1k_d_uart0_adr;
+wire [31:0] wb_m2s_or1k_d_uart0_dat;
+wire  [3:0] wb_m2s_or1k_d_uart0_sel;
+wire        wb_m2s_or1k_d_uart0_we;
+wire        wb_m2s_or1k_d_uart0_cyc;
+wire        wb_m2s_or1k_d_uart0_stb;
+wire  [2:0] wb_m2s_or1k_d_uart0_cti;
+wire  [1:0] wb_m2s_or1k_d_uart0_bte;
+wire [31:0] wb_s2m_or1k_d_uart0_dat;
+wire        wb_s2m_or1k_d_uart0_ack;
+wire        wb_s2m_or1k_d_uart0_err;
+wire        wb_s2m_or1k_d_uart0_rty;
+wire [31:0] wb_m2s_or1k_d_gpio0_adr;
+wire [31:0] wb_m2s_or1k_d_gpio0_dat;
+wire  [3:0] wb_m2s_or1k_d_gpio0_sel;
+wire        wb_m2s_or1k_d_gpio0_we;
+wire        wb_m2s_or1k_d_gpio0_cyc;
+wire        wb_m2s_or1k_d_gpio0_stb;
+wire  [2:0] wb_m2s_or1k_d_gpio0_cti;
+wire  [1:0] wb_m2s_or1k_d_gpio0_bte;
+wire [31:0] wb_s2m_or1k_d_gpio0_dat;
+wire        wb_s2m_or1k_d_gpio0_ack;
+wire        wb_s2m_or1k_d_gpio0_err;
+wire        wb_s2m_or1k_d_gpio0_rty;
+wire [31:0] wb_m2s_dbg_sdram_dbus_adr;
+wire [31:0] wb_m2s_dbg_sdram_dbus_dat;
+wire  [3:0] wb_m2s_dbg_sdram_dbus_sel;
+wire        wb_m2s_dbg_sdram_dbus_we;
+wire        wb_m2s_dbg_sdram_dbus_cyc;
+wire        wb_m2s_dbg_sdram_dbus_stb;
+wire  [2:0] wb_m2s_dbg_sdram_dbus_cti;
+wire  [1:0] wb_m2s_dbg_sdram_dbus_bte;
+wire [31:0] wb_s2m_dbg_sdram_dbus_dat;
+wire        wb_s2m_dbg_sdram_dbus_ack;
+wire        wb_s2m_dbg_sdram_dbus_err;
+wire        wb_s2m_dbg_sdram_dbus_rty;
+wire [31:0] wb_m2s_dbg_uart0_adr;
+wire [31:0] wb_m2s_dbg_uart0_dat;
+wire  [3:0] wb_m2s_dbg_uart0_sel;
+wire        wb_m2s_dbg_uart0_we;
+wire        wb_m2s_dbg_uart0_cyc;
+wire        wb_m2s_dbg_uart0_stb;
+wire  [2:0] wb_m2s_dbg_uart0_cti;
+wire  [1:0] wb_m2s_dbg_uart0_bte;
+wire [31:0] wb_s2m_dbg_uart0_dat;
+wire        wb_s2m_dbg_uart0_ack;
+wire        wb_s2m_dbg_uart0_err;
+wire        wb_s2m_dbg_uart0_rty;
+wire [31:0] wb_m2s_dbg_gpio0_adr;
+wire [31:0] wb_m2s_dbg_gpio0_dat;
+wire  [3:0] wb_m2s_dbg_gpio0_sel;
+wire        wb_m2s_dbg_gpio0_we;
+wire        wb_m2s_dbg_gpio0_cyc;
+wire        wb_m2s_dbg_gpio0_stb;
+wire  [2:0] wb_m2s_dbg_gpio0_cti;
+wire  [1:0] wb_m2s_dbg_gpio0_bte;
+wire [31:0] wb_s2m_dbg_gpio0_dat;
+wire        wb_s2m_dbg_gpio0_ack;
+wire        wb_s2m_dbg_gpio0_err;
+wire        wb_s2m_dbg_gpio0_rty;
+wire [31:0] wb_m2s_resize_uart0_adr;
+wire [31:0] wb_m2s_resize_uart0_dat;
+wire  [3:0] wb_m2s_resize_uart0_sel;
+wire        wb_m2s_resize_uart0_we;
+wire        wb_m2s_resize_uart0_cyc;
+wire        wb_m2s_resize_uart0_stb;
+wire  [2:0] wb_m2s_resize_uart0_cti;
+wire  [1:0] wb_m2s_resize_uart0_bte;
+wire [31:0] wb_s2m_resize_uart0_dat;
+wire        wb_s2m_resize_uart0_ack;
+wire        wb_s2m_resize_uart0_err;
+wire        wb_s2m_resize_uart0_rty;
+wire [31:0] wb_m2s_resize_gpio0_adr;
+wire [31:0] wb_m2s_resize_gpio0_dat;
+wire  [3:0] wb_m2s_resize_gpio0_sel;
+wire        wb_m2s_resize_gpio0_we;
+wire        wb_m2s_resize_gpio0_cyc;
+wire        wb_m2s_resize_gpio0_stb;
+wire  [2:0] wb_m2s_resize_gpio0_cti;
+wire  [1:0] wb_m2s_resize_gpio0_bte;
+wire [31:0] wb_s2m_resize_gpio0_dat;
+wire        wb_s2m_resize_gpio0_ack;
+wire        wb_s2m_resize_gpio0_err;
+wire        wb_s2m_resize_gpio0_rty;
+
+wb_mux
+  #(.num_slaves (2),
+    .MATCH_ADDR ({32'h00000000, 32'hf0000100}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffc0}))
+ wb_mux_or1k_i
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_or1k_i_adr_i),
+    .wbm_dat_i (wb_or1k_i_dat_i),
+    .wbm_sel_i (wb_or1k_i_sel_i),
+    .wbm_we_i  (wb_or1k_i_we_i),
+    .wbm_cyc_i (wb_or1k_i_cyc_i),
+    .wbm_stb_i (wb_or1k_i_stb_i),
+    .wbm_cti_i (wb_or1k_i_cti_i),
+    .wbm_bte_i (wb_or1k_i_bte_i),
+    .wbm_dat_o (wb_or1k_i_dat_o),
+    .wbm_ack_o (wb_or1k_i_ack_o),
+    .wbm_err_o (wb_or1k_i_err_o),
+    .wbm_rty_o (wb_or1k_i_rty_o),
+    .wbs_adr_o ({wb_sdram_ibus_adr_o, wb_rom0_adr_o}),
+    .wbs_dat_o ({wb_sdram_ibus_dat_o, wb_rom0_dat_o}),
+    .wbs_sel_o ({wb_sdram_ibus_sel_o, wb_rom0_sel_o}),
+    .wbs_we_o  ({wb_sdram_ibus_we_o, wb_rom0_we_o}),
+    .wbs_cyc_o ({wb_sdram_ibus_cyc_o, wb_rom0_cyc_o}),
+    .wbs_stb_o ({wb_sdram_ibus_stb_o, wb_rom0_stb_o}),
+    .wbs_cti_o ({wb_sdram_ibus_cti_o, wb_rom0_cti_o}),
+    .wbs_bte_o ({wb_sdram_ibus_bte_o, wb_rom0_bte_o}),
+    .wbs_dat_i ({wb_sdram_ibus_dat_i, wb_rom0_dat_i}),
+    .wbs_ack_i ({wb_sdram_ibus_ack_i, wb_rom0_ack_i}),
+    .wbs_err_i ({wb_sdram_ibus_err_i, wb_rom0_err_i}),
+    .wbs_rty_i ({wb_sdram_ibus_rty_i, wb_rom0_rty_i}));
+
+wb_mux
+  #(.num_slaves (3),
+    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
+ wb_mux_or1k_d
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_or1k_d_adr_i),
+    .wbm_dat_i (wb_or1k_d_dat_i),
+    .wbm_sel_i (wb_or1k_d_sel_i),
+    .wbm_we_i  (wb_or1k_d_we_i),
+    .wbm_cyc_i (wb_or1k_d_cyc_i),
+    .wbm_stb_i (wb_or1k_d_stb_i),
+    .wbm_cti_i (wb_or1k_d_cti_i),
+    .wbm_bte_i (wb_or1k_d_bte_i),
+    .wbm_dat_o (wb_or1k_d_dat_o),
+    .wbm_ack_o (wb_or1k_d_ack_o),
+    .wbm_err_o (wb_or1k_d_err_o),
+    .wbm_rty_o (wb_or1k_d_rty_o),
+    .wbs_adr_o ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_or1k_d_uart0_adr, wb_m2s_or1k_d_gpio0_adr}),
+    .wbs_dat_o ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_or1k_d_uart0_dat, wb_m2s_or1k_d_gpio0_dat}),
+    .wbs_sel_o ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_or1k_d_uart0_sel, wb_m2s_or1k_d_gpio0_sel}),
+    .wbs_we_o  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_or1k_d_uart0_we, wb_m2s_or1k_d_gpio0_we}),
+    .wbs_cyc_o ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_or1k_d_uart0_cyc, wb_m2s_or1k_d_gpio0_cyc}),
+    .wbs_stb_o ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_or1k_d_uart0_stb, wb_m2s_or1k_d_gpio0_stb}),
+    .wbs_cti_o ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_or1k_d_uart0_cti, wb_m2s_or1k_d_gpio0_cti}),
+    .wbs_bte_o ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_or1k_d_uart0_bte, wb_m2s_or1k_d_gpio0_bte}),
+    .wbs_dat_i ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_or1k_d_uart0_dat, wb_s2m_or1k_d_gpio0_dat}),
+    .wbs_ack_i ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_or1k_d_uart0_ack, wb_s2m_or1k_d_gpio0_ack}),
+    .wbs_err_i ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_or1k_d_uart0_err, wb_s2m_or1k_d_gpio0_err}),
+    .wbs_rty_i ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_or1k_d_uart0_rty, wb_s2m_or1k_d_gpio0_rty}));
+
+wb_mux
+  #(.num_slaves (3),
+    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
+ wb_mux_dbg
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_dbg_adr_i),
+    .wbm_dat_i (wb_dbg_dat_i),
+    .wbm_sel_i (wb_dbg_sel_i),
+    .wbm_we_i  (wb_dbg_we_i),
+    .wbm_cyc_i (wb_dbg_cyc_i),
+    .wbm_stb_i (wb_dbg_stb_i),
+    .wbm_cti_i (wb_dbg_cti_i),
+    .wbm_bte_i (wb_dbg_bte_i),
+    .wbm_dat_o (wb_dbg_dat_o),
+    .wbm_ack_o (wb_dbg_ack_o),
+    .wbm_err_o (wb_dbg_err_o),
+    .wbm_rty_o (wb_dbg_rty_o),
+    .wbs_adr_o ({wb_m2s_dbg_sdram_dbus_adr, wb_m2s_dbg_uart0_adr, wb_m2s_dbg_gpio0_adr}),
+    .wbs_dat_o ({wb_m2s_dbg_sdram_dbus_dat, wb_m2s_dbg_uart0_dat, wb_m2s_dbg_gpio0_dat}),
+    .wbs_sel_o ({wb_m2s_dbg_sdram_dbus_sel, wb_m2s_dbg_uart0_sel, wb_m2s_dbg_gpio0_sel}),
+    .wbs_we_o  ({wb_m2s_dbg_sdram_dbus_we, wb_m2s_dbg_uart0_we, wb_m2s_dbg_gpio0_we}),
+    .wbs_cyc_o ({wb_m2s_dbg_sdram_dbus_cyc, wb_m2s_dbg_uart0_cyc, wb_m2s_dbg_gpio0_cyc}),
+    .wbs_stb_o ({wb_m2s_dbg_sdram_dbus_stb, wb_m2s_dbg_uart0_stb, wb_m2s_dbg_gpio0_stb}),
+    .wbs_cti_o ({wb_m2s_dbg_sdram_dbus_cti, wb_m2s_dbg_uart0_cti, wb_m2s_dbg_gpio0_cti}),
+    .wbs_bte_o ({wb_m2s_dbg_sdram_dbus_bte, wb_m2s_dbg_uart0_bte, wb_m2s_dbg_gpio0_bte}),
+    .wbs_dat_i ({wb_s2m_dbg_sdram_dbus_dat, wb_s2m_dbg_uart0_dat, wb_s2m_dbg_gpio0_dat}),
+    .wbs_ack_i ({wb_s2m_dbg_sdram_dbus_ack, wb_s2m_dbg_uart0_ack, wb_s2m_dbg_gpio0_ack}),
+    .wbs_err_i ({wb_s2m_dbg_sdram_dbus_err, wb_s2m_dbg_uart0_err, wb_s2m_dbg_gpio0_err}),
+    .wbs_rty_i ({wb_s2m_dbg_sdram_dbus_rty, wb_s2m_dbg_uart0_rty, wb_s2m_dbg_gpio0_rty}));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_uart0
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_uart0_adr, wb_m2s_dbg_uart0_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_uart0_dat, wb_m2s_dbg_uart0_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_uart0_sel, wb_m2s_dbg_uart0_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_uart0_we, wb_m2s_dbg_uart0_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_uart0_cyc, wb_m2s_dbg_uart0_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_uart0_stb, wb_m2s_dbg_uart0_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_uart0_cti, wb_m2s_dbg_uart0_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_uart0_bte, wb_m2s_dbg_uart0_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_uart0_dat, wb_s2m_dbg_uart0_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}),
+    .wbs_adr_o (wb_m2s_resize_uart0_adr),
+    .wbs_dat_o (wb_m2s_resize_uart0_dat),
+    .wbs_sel_o (wb_m2s_resize_uart0_sel),
+    .wbs_we_o  (wb_m2s_resize_uart0_we),
+    .wbs_cyc_o (wb_m2s_resize_uart0_cyc),
+    .wbs_stb_o (wb_m2s_resize_uart0_stb),
+    .wbs_cti_o (wb_m2s_resize_uart0_cti),
+    .wbs_bte_o (wb_m2s_resize_uart0_bte),
+    .wbs_dat_i (wb_s2m_resize_uart0_dat),
+    .wbs_ack_i (wb_s2m_resize_uart0_ack),
+    .wbs_err_i (wb_s2m_resize_uart0_err),
+    .wbs_rty_i (wb_s2m_resize_uart0_rty));
+
+wb_data_resize
+  #(.aw  (32),
+    .mdw (32),
+    .sdw (8))
+ wb_data_resize_uart0
+   (.wbm_adr_i (wb_m2s_resize_uart0_adr),
+    .wbm_dat_i (wb_m2s_resize_uart0_dat),
+    .wbm_sel_i (wb_m2s_resize_uart0_sel),
+    .wbm_we_i  (wb_m2s_resize_uart0_we),
+    .wbm_cyc_i (wb_m2s_resize_uart0_cyc),
+    .wbm_stb_i (wb_m2s_resize_uart0_stb),
+    .wbm_cti_i (wb_m2s_resize_uart0_cti),
+    .wbm_bte_i (wb_m2s_resize_uart0_bte),
+    .wbm_dat_o (wb_s2m_resize_uart0_dat),
+    .wbm_ack_o (wb_s2m_resize_uart0_ack),
+    .wbm_err_o (wb_s2m_resize_uart0_err),
+    .wbm_rty_o (wb_s2m_resize_uart0_rty),
+    .wbs_adr_o (wb_uart0_adr_o),
+    .wbs_dat_o (wb_uart0_dat_o),
+    .wbs_we_o  (wb_uart0_we_o),
+    .wbs_cyc_o (wb_uart0_cyc_o),
+    .wbs_stb_o (wb_uart0_stb_o),
+    .wbs_cti_o (wb_uart0_cti_o),
+    .wbs_bte_o (wb_uart0_bte_o),
+    .wbs_dat_i (wb_uart0_dat_i),
+    .wbs_ack_i (wb_uart0_ack_i),
+    .wbs_err_i (wb_uart0_err_i),
+    .wbs_rty_i (wb_uart0_rty_i));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_gpio0
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}),
+    .wbs_adr_o (wb_m2s_resize_gpio0_adr),
+    .wbs_dat_o (wb_m2s_resize_gpio0_dat),
+    .wbs_sel_o (wb_m2s_resize_gpio0_sel),
+    .wbs_we_o  (wb_m2s_resize_gpio0_we),
+    .wbs_cyc_o (wb_m2s_resize_gpio0_cyc),
+    .wbs_stb_o (wb_m2s_resize_gpio0_stb),
+    .wbs_cti_o (wb_m2s_resize_gpio0_cti),
+    .wbs_bte_o (wb_m2s_resize_gpio0_bte),
+    .wbs_dat_i (wb_s2m_resize_gpio0_dat),
+    .wbs_ack_i (wb_s2m_resize_gpio0_ack),
+    .wbs_err_i (wb_s2m_resize_gpio0_err),
+    .wbs_rty_i (wb_s2m_resize_gpio0_rty));
+
+wb_data_resize
+  #(.aw  (32),
+    .mdw (32),
+    .sdw (8))
+ wb_data_resize_gpio0
+   (.wbm_adr_i (wb_m2s_resize_gpio0_adr),
+    .wbm_dat_i (wb_m2s_resize_gpio0_dat),
+    .wbm_sel_i (wb_m2s_resize_gpio0_sel),
+    .wbm_we_i  (wb_m2s_resize_gpio0_we),
+    .wbm_cyc_i (wb_m2s_resize_gpio0_cyc),
+    .wbm_stb_i (wb_m2s_resize_gpio0_stb),
+    .wbm_cti_i (wb_m2s_resize_gpio0_cti),
+    .wbm_bte_i (wb_m2s_resize_gpio0_bte),
+    .wbm_dat_o (wb_s2m_resize_gpio0_dat),
+    .wbm_ack_o (wb_s2m_resize_gpio0_ack),
+    .wbm_err_o (wb_s2m_resize_gpio0_err),
+    .wbm_rty_o (wb_s2m_resize_gpio0_rty),
+    .wbs_adr_o (wb_gpio0_adr_o),
+    .wbs_dat_o (wb_gpio0_dat_o),
+    .wbs_we_o  (wb_gpio0_we_o),
+    .wbs_cyc_o (wb_gpio0_cyc_o),
+    .wbs_stb_o (wb_gpio0_stb_o),
+    .wbs_cti_o (wb_gpio0_cti_o),
+    .wbs_bte_o (wb_gpio0_bte_o),
+    .wbs_dat_i (wb_gpio0_dat_i),
+    .wbs_ack_i (wb_gpio0_ack_i),
+    .wbs_err_i (wb_gpio0_err_i),
+    .wbs_rty_i (wb_gpio0_rty_i));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_sdram_dbus
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_dbg_sdram_dbus_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_dbg_sdram_dbus_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_dbg_sdram_dbus_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_dbg_sdram_dbus_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_dbg_sdram_dbus_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_dbg_sdram_dbus_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_dbg_sdram_dbus_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_dbg_sdram_dbus_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_dbg_sdram_dbus_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_dbg_sdram_dbus_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_dbg_sdram_dbus_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_dbg_sdram_dbus_rty}),
+    .wbs_adr_o (wb_sdram_dbus_adr_o),
+    .wbs_dat_o (wb_sdram_dbus_dat_o),
+    .wbs_sel_o (wb_sdram_dbus_sel_o),
+    .wbs_we_o  (wb_sdram_dbus_we_o),
+    .wbs_cyc_o (wb_sdram_dbus_cyc_o),
+    .wbs_stb_o (wb_sdram_dbus_stb_o),
+    .wbs_cti_o (wb_sdram_dbus_cti_o),
+    .wbs_bte_o (wb_sdram_dbus_bte_o),
+    .wbs_dat_i (wb_sdram_dbus_dat_i),
+    .wbs_ack_i (wb_sdram_dbus_ack_i),
+    .wbs_err_i (wb_sdram_dbus_err_i),
+    .wbs_rty_i (wb_sdram_dbus_rty_i));
+
+endmodule
diff --git a/cores/wb_intercon/sw/wb_intercon.vh b/cores/wb_intercon/sw/wb_intercon.vh
new file mode 100644
index 00000000..cc8a6714
--- /dev/null
+++ b/cores/wb_intercon/sw/wb_intercon.vh
@@ -0,0 +1,197 @@
+wire [31:0] wb_m2s_or1k_i_adr;
+wire [31:0] wb_m2s_or1k_i_dat;
+wire  [3:0] wb_m2s_or1k_i_sel;
+wire        wb_m2s_or1k_i_we;
+wire        wb_m2s_or1k_i_cyc;
+wire        wb_m2s_or1k_i_stb;
+wire  [2:0] wb_m2s_or1k_i_cti;
+wire  [1:0] wb_m2s_or1k_i_bte;
+wire [31:0] wb_s2m_or1k_i_dat;
+wire        wb_s2m_or1k_i_ack;
+wire        wb_s2m_or1k_i_err;
+wire        wb_s2m_or1k_i_rty;
+wire [31:0] wb_m2s_or1k_d_adr;
+wire [31:0] wb_m2s_or1k_d_dat;
+wire  [3:0] wb_m2s_or1k_d_sel;
+wire        wb_m2s_or1k_d_we;
+wire        wb_m2s_or1k_d_cyc;
+wire        wb_m2s_or1k_d_stb;
+wire  [2:0] wb_m2s_or1k_d_cti;
+wire  [1:0] wb_m2s_or1k_d_bte;
+wire [31:0] wb_s2m_or1k_d_dat;
+wire        wb_s2m_or1k_d_ack;
+wire        wb_s2m_or1k_d_err;
+wire        wb_s2m_or1k_d_rty;
+wire [31:0] wb_m2s_dbg_adr;
+wire [31:0] wb_m2s_dbg_dat;
+wire  [3:0] wb_m2s_dbg_sel;
+wire        wb_m2s_dbg_we;
+wire        wb_m2s_dbg_cyc;
+wire        wb_m2s_dbg_stb;
+wire  [2:0] wb_m2s_dbg_cti;
+wire  [1:0] wb_m2s_dbg_bte;
+wire [31:0] wb_s2m_dbg_dat;
+wire        wb_s2m_dbg_ack;
+wire        wb_s2m_dbg_err;
+wire        wb_s2m_dbg_rty;
+wire [31:0] wb_m2s_uart0_adr;
+wire [31:0] wb_m2s_uart0_dat;
+wire  [3:0] wb_m2s_uart0_sel;
+wire        wb_m2s_uart0_we;
+wire        wb_m2s_uart0_cyc;
+wire        wb_m2s_uart0_stb;
+wire  [2:0] wb_m2s_uart0_cti;
+wire  [1:0] wb_m2s_uart0_bte;
+wire [31:0] wb_s2m_uart0_dat;
+wire        wb_s2m_uart0_ack;
+wire        wb_s2m_uart0_err;
+wire        wb_s2m_uart0_rty;
+wire [31:0] wb_m2s_gpio0_adr;
+wire [31:0] wb_m2s_gpio0_dat;
+wire  [3:0] wb_m2s_gpio0_sel;
+wire        wb_m2s_gpio0_we;
+wire        wb_m2s_gpio0_cyc;
+wire        wb_m2s_gpio0_stb;
+wire  [2:0] wb_m2s_gpio0_cti;
+wire  [1:0] wb_m2s_gpio0_bte;
+wire [31:0] wb_s2m_gpio0_dat;
+wire        wb_s2m_gpio0_ack;
+wire        wb_s2m_gpio0_err;
+wire        wb_s2m_gpio0_rty;
+wire [31:0] wb_m2s_sdram_dbus_adr;
+wire [31:0] wb_m2s_sdram_dbus_dat;
+wire  [3:0] wb_m2s_sdram_dbus_sel;
+wire        wb_m2s_sdram_dbus_we;
+wire        wb_m2s_sdram_dbus_cyc;
+wire        wb_m2s_sdram_dbus_stb;
+wire  [2:0] wb_m2s_sdram_dbus_cti;
+wire  [1:0] wb_m2s_sdram_dbus_bte;
+wire [31:0] wb_s2m_sdram_dbus_dat;
+wire        wb_s2m_sdram_dbus_ack;
+wire        wb_s2m_sdram_dbus_err;
+wire        wb_s2m_sdram_dbus_rty;
+wire [31:0] wb_m2s_rom0_adr;
+wire [31:0] wb_m2s_rom0_dat;
+wire  [3:0] wb_m2s_rom0_sel;
+wire        wb_m2s_rom0_we;
+wire        wb_m2s_rom0_cyc;
+wire        wb_m2s_rom0_stb;
+wire  [2:0] wb_m2s_rom0_cti;
+wire  [1:0] wb_m2s_rom0_bte;
+wire [31:0] wb_s2m_rom0_dat;
+wire        wb_s2m_rom0_ack;
+wire        wb_s2m_rom0_err;
+wire        wb_s2m_rom0_rty;
+wire [31:0] wb_m2s_sdram_ibus_adr;
+wire [31:0] wb_m2s_sdram_ibus_dat;
+wire  [3:0] wb_m2s_sdram_ibus_sel;
+wire        wb_m2s_sdram_ibus_we;
+wire        wb_m2s_sdram_ibus_cyc;
+wire        wb_m2s_sdram_ibus_stb;
+wire  [2:0] wb_m2s_sdram_ibus_cti;
+wire  [1:0] wb_m2s_sdram_ibus_bte;
+wire [31:0] wb_s2m_sdram_ibus_dat;
+wire        wb_s2m_sdram_ibus_ack;
+wire        wb_s2m_sdram_ibus_err;
+wire        wb_s2m_sdram_ibus_rty;
+
+wb_intercon wb_intercon0
+   (.wb_clk_i            (wb_clk),
+    .wb_rst_i            (wb_rst),
+    .wb_or1k_i_adr_i     (wb_m2s_or1k_i_adr),
+    .wb_or1k_i_dat_i     (wb_m2s_or1k_i_dat),
+    .wb_or1k_i_sel_i     (wb_m2s_or1k_i_sel),
+    .wb_or1k_i_we_i      (wb_m2s_or1k_i_we),
+    .wb_or1k_i_cyc_i     (wb_m2s_or1k_i_cyc),
+    .wb_or1k_i_stb_i     (wb_m2s_or1k_i_stb),
+    .wb_or1k_i_cti_i     (wb_m2s_or1k_i_cti),
+    .wb_or1k_i_bte_i     (wb_m2s_or1k_i_bte),
+    .wb_or1k_i_dat_o     (wb_s2m_or1k_i_dat),
+    .wb_or1k_i_ack_o     (wb_s2m_or1k_i_ack),
+    .wb_or1k_i_err_o     (wb_s2m_or1k_i_err),
+    .wb_or1k_i_rty_o     (wb_s2m_or1k_i_rty),
+    .wb_or1k_d_adr_i     (wb_m2s_or1k_d_adr),
+    .wb_or1k_d_dat_i     (wb_m2s_or1k_d_dat),
+    .wb_or1k_d_sel_i     (wb_m2s_or1k_d_sel),
+    .wb_or1k_d_we_i      (wb_m2s_or1k_d_we),
+    .wb_or1k_d_cyc_i     (wb_m2s_or1k_d_cyc),
+    .wb_or1k_d_stb_i     (wb_m2s_or1k_d_stb),
+    .wb_or1k_d_cti_i     (wb_m2s_or1k_d_cti),
+    .wb_or1k_d_bte_i     (wb_m2s_or1k_d_bte),
+    .wb_or1k_d_dat_o     (wb_s2m_or1k_d_dat),
+    .wb_or1k_d_ack_o     (wb_s2m_or1k_d_ack),
+    .wb_or1k_d_err_o     (wb_s2m_or1k_d_err),
+    .wb_or1k_d_rty_o     (wb_s2m_or1k_d_rty),
+    .wb_dbg_adr_i        (wb_m2s_dbg_adr),
+    .wb_dbg_dat_i        (wb_m2s_dbg_dat),
+    .wb_dbg_sel_i        (wb_m2s_dbg_sel),
+    .wb_dbg_we_i         (wb_m2s_dbg_we),
+    .wb_dbg_cyc_i        (wb_m2s_dbg_cyc),
+    .wb_dbg_stb_i        (wb_m2s_dbg_stb),
+    .wb_dbg_cti_i        (wb_m2s_dbg_cti),
+    .wb_dbg_bte_i        (wb_m2s_dbg_bte),
+    .wb_dbg_dat_o        (wb_s2m_dbg_dat),
+    .wb_dbg_ack_o        (wb_s2m_dbg_ack),
+    .wb_dbg_err_o        (wb_s2m_dbg_err),
+    .wb_dbg_rty_o        (wb_s2m_dbg_rty),
+    .wb_uart0_adr_o      (wb_m2s_uart0_adr),
+    .wb_uart0_dat_o      (wb_m2s_uart0_dat),
+    .wb_uart0_sel_o      (wb_m2s_uart0_sel),
+    .wb_uart0_we_o       (wb_m2s_uart0_we),
+    .wb_uart0_cyc_o      (wb_m2s_uart0_cyc),
+    .wb_uart0_stb_o      (wb_m2s_uart0_stb),
+    .wb_uart0_cti_o      (wb_m2s_uart0_cti),
+    .wb_uart0_bte_o      (wb_m2s_uart0_bte),
+    .wb_uart0_dat_i      (wb_s2m_uart0_dat),
+    .wb_uart0_ack_i      (wb_s2m_uart0_ack),
+    .wb_uart0_err_i      (wb_s2m_uart0_err),
+    .wb_uart0_rty_i      (wb_s2m_uart0_rty),
+    .wb_gpio0_adr_o      (wb_m2s_gpio0_adr),
+    .wb_gpio0_dat_o      (wb_m2s_gpio0_dat),
+    .wb_gpio0_sel_o      (wb_m2s_gpio0_sel),
+    .wb_gpio0_we_o       (wb_m2s_gpio0_we),
+    .wb_gpio0_cyc_o      (wb_m2s_gpio0_cyc),
+    .wb_gpio0_stb_o      (wb_m2s_gpio0_stb),
+    .wb_gpio0_cti_o      (wb_m2s_gpio0_cti),
+    .wb_gpio0_bte_o      (wb_m2s_gpio0_bte),
+    .wb_gpio0_dat_i      (wb_s2m_gpio0_dat),
+    .wb_gpio0_ack_i      (wb_s2m_gpio0_ack),
+    .wb_gpio0_err_i      (wb_s2m_gpio0_err),
+    .wb_gpio0_rty_i      (wb_s2m_gpio0_rty),
+    .wb_sdram_dbus_adr_o (wb_m2s_sdram_dbus_adr),
+    .wb_sdram_dbus_dat_o (wb_m2s_sdram_dbus_dat),
+    .wb_sdram_dbus_sel_o (wb_m2s_sdram_dbus_sel),
+    .wb_sdram_dbus_we_o  (wb_m2s_sdram_dbus_we),
+    .wb_sdram_dbus_cyc_o (wb_m2s_sdram_dbus_cyc),
+    .wb_sdram_dbus_stb_o (wb_m2s_sdram_dbus_stb),
+    .wb_sdram_dbus_cti_o (wb_m2s_sdram_dbus_cti),
+    .wb_sdram_dbus_bte_o (wb_m2s_sdram_dbus_bte),
+    .wb_sdram_dbus_dat_i (wb_s2m_sdram_dbus_dat),
+    .wb_sdram_dbus_ack_i (wb_s2m_sdram_dbus_ack),
+    .wb_sdram_dbus_err_i (wb_s2m_sdram_dbus_err),
+    .wb_sdram_dbus_rty_i (wb_s2m_sdram_dbus_rty),
+    .wb_rom0_adr_o       (wb_m2s_rom0_adr),
+    .wb_rom0_dat_o       (wb_m2s_rom0_dat),
+    .wb_rom0_sel_o       (wb_m2s_rom0_sel),
+    .wb_rom0_we_o        (wb_m2s_rom0_we),
+    .wb_rom0_cyc_o       (wb_m2s_rom0_cyc),
+    .wb_rom0_stb_o       (wb_m2s_rom0_stb),
+    .wb_rom0_cti_o       (wb_m2s_rom0_cti),
+    .wb_rom0_bte_o       (wb_m2s_rom0_bte),
+    .wb_rom0_dat_i       (wb_s2m_rom0_dat),
+    .wb_rom0_ack_i       (wb_s2m_rom0_ack),
+    .wb_rom0_err_i       (wb_s2m_rom0_err),
+    .wb_rom0_rty_i       (wb_s2m_rom0_rty),
+    .wb_sdram_ibus_adr_o (wb_m2s_sdram_ibus_adr),
+    .wb_sdram_ibus_dat_o (wb_m2s_sdram_ibus_dat),
+    .wb_sdram_ibus_sel_o (wb_m2s_sdram_ibus_sel),
+    .wb_sdram_ibus_we_o  (wb_m2s_sdram_ibus_we),
+    .wb_sdram_ibus_cyc_o (wb_m2s_sdram_ibus_cyc),
+    .wb_sdram_ibus_stb_o (wb_m2s_sdram_ibus_stb),
+    .wb_sdram_ibus_cti_o (wb_m2s_sdram_ibus_cti),
+    .wb_sdram_ibus_bte_o (wb_m2s_sdram_ibus_bte),
+    .wb_sdram_ibus_dat_i (wb_s2m_sdram_ibus_dat),
+    .wb_sdram_ibus_ack_i (wb_s2m_sdram_ibus_ack),
+    .wb_sdram_ibus_err_i (wb_s2m_sdram_ibus_err),
+    .wb_sdram_ibus_rty_i (wb_s2m_sdram_ibus_rty));
+
diff --git a/systems/de2/de2.core b/systems/de2/de2.core
index 918bf988..db833b2c 100755
--- a/systems/de2/de2.core
+++ b/systems/de2/de2.core
@@ -6,7 +6,7 @@ depend =
  adv_debug_sys
  or1200
  uart16550
- or1k-elf-loader
+ elf-loader
  vlog_tb_utils
  jtag_vpi
  wiredelay
diff --git a/systems/de2/scripts/build_summary b/systems/de2/scripts/build_summary
index 07bb1a6f..a9422658 100755
--- a/systems/de2/scripts/build_summary
+++ b/systems/de2/scripts/build_summary
@@ -1,7 +1,7 @@
 #!/bin/bash
 
-FITTER_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nr "; Fitter Summary" | gawk '{print $1}' FS=":")
-FITTER_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nr "; Fitter Settings" | gawk '{print $1}' FS=":")
+FITTER_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nhr "; Fitter Summary" | gawk '{print $1}' FS=":")
+FITTER_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nhr "; Fitter Settings" | gawk '{print $1}' FS=":")
 
 FITTER_REPORT_START=$(($FITTER_REPORT_START - 1))
 FITTER_REPORT_END=$(($FITTER_REPORT_END - 4))
@@ -10,8 +10,8 @@ echo -e "\033[31m"
 sed -n ${FITTER_REPORT_START},${FITTER_REPORT_END}p ${BUILD_ROOT}/bld-quartus/de2.fit.rpt
 
 
-FMAX_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nr "; Slow Model Fmax Summary" | gawk '{print $1}' FS=":")
-FMAX_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nr "This panel reports FMAX" | gawk '{print $1}' FS=":")
+FMAX_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nhr "; Slow Model Fmax Summary" | gawk '{print $1}' FS=":")
+FMAX_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nhr "This panel reports FMAX" | gawk '{print $1}' FS=":")
 
 FMAX_REPORT_START=$(($FMAX_REPORT_START - 1))
 FMAX_REPORT_END=$(($FMAX_REPORT_END - 1))

From 19296c033f8a169920239d8d756081cf9a854c86 Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Thu, 6 Mar 2014 15:23:19 +0700
Subject: [PATCH 10/12] Edit the conflicted file.

---
 systems/de2/de2.core~origin_master | 44 ++++++++++++++++++++++++++++++
 systems/de2/scripts/build_summary  | 10 -------
 2 files changed, 44 insertions(+), 10 deletions(-)
 create mode 100755 systems/de2/de2.core~origin_master

diff --git a/systems/de2/de2.core~origin_master b/systems/de2/de2.core~origin_master
new file mode 100755
index 00000000..918bf988
--- /dev/null
+++ b/systems/de2/de2.core~origin_master
@@ -0,0 +1,44 @@
+CAPI=1
+[main]
+depend =
+ jtag_tap
+ wb_intercon
+ adv_debug_sys
+ or1200
+ uart16550
+ or1k-elf-loader
+ vlog_tb_utils
+ jtag_vpi
+ wiredelay
+ wb_sdram_ctrl
+ mor1kx
+ mt48lc16m16a2
+ gpio
+ altera_virtual_jtag
+
+simulators =
+ icarus
+ modelsim
+
+[verilog]
+src_files = 
+ rtl/verilog/clkgen.v
+ rtl/verilog/orpsoc_top.v
+ backend/rtl/verilog/pll.v
+ rtl/verilog/rom.v
+ rtl/verilog/wb_intercon.v
+
+
+include_files =
+ rtl/verilog/include/or1200_defines.v
+ rtl/verilog/include/orpsoc-defines.v
+ rtl/verilog/include/timescale.v
+ rtl/verilog/include/uart_defines.v
+ rtl/verilog/wb_intercon.vh
+
+[icarus]
+iverilog_options = -DICARUS_SIM -DSIM
+
+[modelsim]
+vlog_options = +define+SIM +define+MODELSIM_SIM
+vsim_options = -L altera_mf_ver -L altera_mf
diff --git a/systems/de2/scripts/build_summary b/systems/de2/scripts/build_summary
index 7ce0dba6..a9422658 100755
--- a/systems/de2/scripts/build_summary
+++ b/systems/de2/scripts/build_summary
@@ -1,12 +1,7 @@
 #!/bin/bash
 
-<<<<<<< HEAD
 FITTER_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nhr "; Fitter Summary" | gawk '{print $1}' FS=":")
 FITTER_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nhr "; Fitter Settings" | gawk '{print $1}' FS=":")
-=======
-FITTER_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nr "; Fitter Summary" | gawk '{print $1}' FS=":")
-FITTER_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nr "; Fitter Settings" | gawk '{print $1}' FS=":")
->>>>>>> origin/master
 
 FITTER_REPORT_START=$(($FITTER_REPORT_START - 1))
 FITTER_REPORT_END=$(($FITTER_REPORT_END - 4))
@@ -15,13 +10,8 @@ echo -e "\033[31m"
 sed -n ${FITTER_REPORT_START},${FITTER_REPORT_END}p ${BUILD_ROOT}/bld-quartus/de2.fit.rpt
 
 
-<<<<<<< HEAD
 FMAX_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nhr "; Slow Model Fmax Summary" | gawk '{print $1}' FS=":")
 FMAX_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nhr "This panel reports FMAX" | gawk '{print $1}' FS=":")
-=======
-FMAX_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nr "; Slow Model Fmax Summary" | gawk '{print $1}' FS=":")
-FMAX_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nr "This panel reports FMAX" | gawk '{print $1}' FS=":")
->>>>>>> origin/master
 
 FMAX_REPORT_START=$(($FMAX_REPORT_START - 1))
 FMAX_REPORT_END=$(($FMAX_REPORT_END - 1))

From 1089806784c8cedf14f00f378e43cfaaaad3e034 Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Thu, 6 Mar 2014 15:32:04 +0700
Subject: [PATCH 11/12] remove temporary file

---
 cores/wb_intercon/sw/wb_intercon.v  | 442 ----------------------------
 cores/wb_intercon/sw/wb_intercon.vh | 197 -------------
 2 files changed, 639 deletions(-)
 delete mode 100644 cores/wb_intercon/sw/wb_intercon.v
 delete mode 100644 cores/wb_intercon/sw/wb_intercon.vh

diff --git a/cores/wb_intercon/sw/wb_intercon.v b/cores/wb_intercon/sw/wb_intercon.v
deleted file mode 100644
index 5358c2c6..00000000
--- a/cores/wb_intercon/sw/wb_intercon.v
+++ /dev/null
@@ -1,442 +0,0 @@
-module wb_intercon
-   (input         wb_clk_i,
-    input         wb_rst_i,
-    input  [31:0] wb_or1k_i_adr_i,
-    input  [31:0] wb_or1k_i_dat_i,
-    input   [3:0] wb_or1k_i_sel_i,
-    input         wb_or1k_i_we_i,
-    input         wb_or1k_i_cyc_i,
-    input         wb_or1k_i_stb_i,
-    input   [2:0] wb_or1k_i_cti_i,
-    input   [1:0] wb_or1k_i_bte_i,
-    output [31:0] wb_or1k_i_dat_o,
-    output        wb_or1k_i_ack_o,
-    output        wb_or1k_i_err_o,
-    output        wb_or1k_i_rty_o,
-    input  [31:0] wb_or1k_d_adr_i,
-    input  [31:0] wb_or1k_d_dat_i,
-    input   [3:0] wb_or1k_d_sel_i,
-    input         wb_or1k_d_we_i,
-    input         wb_or1k_d_cyc_i,
-    input         wb_or1k_d_stb_i,
-    input   [2:0] wb_or1k_d_cti_i,
-    input   [1:0] wb_or1k_d_bte_i,
-    output [31:0] wb_or1k_d_dat_o,
-    output        wb_or1k_d_ack_o,
-    output        wb_or1k_d_err_o,
-    output        wb_or1k_d_rty_o,
-    input  [31:0] wb_dbg_adr_i,
-    input  [31:0] wb_dbg_dat_i,
-    input   [3:0] wb_dbg_sel_i,
-    input         wb_dbg_we_i,
-    input         wb_dbg_cyc_i,
-    input         wb_dbg_stb_i,
-    input   [2:0] wb_dbg_cti_i,
-    input   [1:0] wb_dbg_bte_i,
-    output [31:0] wb_dbg_dat_o,
-    output        wb_dbg_ack_o,
-    output        wb_dbg_err_o,
-    output        wb_dbg_rty_o,
-    output [31:0] wb_uart0_adr_o,
-    output [31:0] wb_uart0_dat_o,
-    output  [3:0] wb_uart0_sel_o,
-    output        wb_uart0_we_o,
-    output        wb_uart0_cyc_o,
-    output        wb_uart0_stb_o,
-    output  [2:0] wb_uart0_cti_o,
-    output  [1:0] wb_uart0_bte_o,
-    input  [31:0] wb_uart0_dat_i,
-    input         wb_uart0_ack_i,
-    input         wb_uart0_err_i,
-    input         wb_uart0_rty_i,
-    output [31:0] wb_gpio0_adr_o,
-    output [31:0] wb_gpio0_dat_o,
-    output  [3:0] wb_gpio0_sel_o,
-    output        wb_gpio0_we_o,
-    output        wb_gpio0_cyc_o,
-    output        wb_gpio0_stb_o,
-    output  [2:0] wb_gpio0_cti_o,
-    output  [1:0] wb_gpio0_bte_o,
-    input  [31:0] wb_gpio0_dat_i,
-    input         wb_gpio0_ack_i,
-    input         wb_gpio0_err_i,
-    input         wb_gpio0_rty_i,
-    output [31:0] wb_sdram_dbus_adr_o,
-    output [31:0] wb_sdram_dbus_dat_o,
-    output  [3:0] wb_sdram_dbus_sel_o,
-    output        wb_sdram_dbus_we_o,
-    output        wb_sdram_dbus_cyc_o,
-    output        wb_sdram_dbus_stb_o,
-    output  [2:0] wb_sdram_dbus_cti_o,
-    output  [1:0] wb_sdram_dbus_bte_o,
-    input  [31:0] wb_sdram_dbus_dat_i,
-    input         wb_sdram_dbus_ack_i,
-    input         wb_sdram_dbus_err_i,
-    input         wb_sdram_dbus_rty_i,
-    output [31:0] wb_rom0_adr_o,
-    output [31:0] wb_rom0_dat_o,
-    output  [3:0] wb_rom0_sel_o,
-    output        wb_rom0_we_o,
-    output        wb_rom0_cyc_o,
-    output        wb_rom0_stb_o,
-    output  [2:0] wb_rom0_cti_o,
-    output  [1:0] wb_rom0_bte_o,
-    input  [31:0] wb_rom0_dat_i,
-    input         wb_rom0_ack_i,
-    input         wb_rom0_err_i,
-    input         wb_rom0_rty_i,
-    output [31:0] wb_sdram_ibus_adr_o,
-    output [31:0] wb_sdram_ibus_dat_o,
-    output  [3:0] wb_sdram_ibus_sel_o,
-    output        wb_sdram_ibus_we_o,
-    output        wb_sdram_ibus_cyc_o,
-    output        wb_sdram_ibus_stb_o,
-    output  [2:0] wb_sdram_ibus_cti_o,
-    output  [1:0] wb_sdram_ibus_bte_o,
-    input  [31:0] wb_sdram_ibus_dat_i,
-    input         wb_sdram_ibus_ack_i,
-    input         wb_sdram_ibus_err_i,
-    input         wb_sdram_ibus_rty_i);
-
-wire [31:0] wb_m2s_or1k_d_sdram_dbus_adr;
-wire [31:0] wb_m2s_or1k_d_sdram_dbus_dat;
-wire  [3:0] wb_m2s_or1k_d_sdram_dbus_sel;
-wire        wb_m2s_or1k_d_sdram_dbus_we;
-wire        wb_m2s_or1k_d_sdram_dbus_cyc;
-wire        wb_m2s_or1k_d_sdram_dbus_stb;
-wire  [2:0] wb_m2s_or1k_d_sdram_dbus_cti;
-wire  [1:0] wb_m2s_or1k_d_sdram_dbus_bte;
-wire [31:0] wb_s2m_or1k_d_sdram_dbus_dat;
-wire        wb_s2m_or1k_d_sdram_dbus_ack;
-wire        wb_s2m_or1k_d_sdram_dbus_err;
-wire        wb_s2m_or1k_d_sdram_dbus_rty;
-wire [31:0] wb_m2s_or1k_d_uart0_adr;
-wire [31:0] wb_m2s_or1k_d_uart0_dat;
-wire  [3:0] wb_m2s_or1k_d_uart0_sel;
-wire        wb_m2s_or1k_d_uart0_we;
-wire        wb_m2s_or1k_d_uart0_cyc;
-wire        wb_m2s_or1k_d_uart0_stb;
-wire  [2:0] wb_m2s_or1k_d_uart0_cti;
-wire  [1:0] wb_m2s_or1k_d_uart0_bte;
-wire [31:0] wb_s2m_or1k_d_uart0_dat;
-wire        wb_s2m_or1k_d_uart0_ack;
-wire        wb_s2m_or1k_d_uart0_err;
-wire        wb_s2m_or1k_d_uart0_rty;
-wire [31:0] wb_m2s_or1k_d_gpio0_adr;
-wire [31:0] wb_m2s_or1k_d_gpio0_dat;
-wire  [3:0] wb_m2s_or1k_d_gpio0_sel;
-wire        wb_m2s_or1k_d_gpio0_we;
-wire        wb_m2s_or1k_d_gpio0_cyc;
-wire        wb_m2s_or1k_d_gpio0_stb;
-wire  [2:0] wb_m2s_or1k_d_gpio0_cti;
-wire  [1:0] wb_m2s_or1k_d_gpio0_bte;
-wire [31:0] wb_s2m_or1k_d_gpio0_dat;
-wire        wb_s2m_or1k_d_gpio0_ack;
-wire        wb_s2m_or1k_d_gpio0_err;
-wire        wb_s2m_or1k_d_gpio0_rty;
-wire [31:0] wb_m2s_dbg_sdram_dbus_adr;
-wire [31:0] wb_m2s_dbg_sdram_dbus_dat;
-wire  [3:0] wb_m2s_dbg_sdram_dbus_sel;
-wire        wb_m2s_dbg_sdram_dbus_we;
-wire        wb_m2s_dbg_sdram_dbus_cyc;
-wire        wb_m2s_dbg_sdram_dbus_stb;
-wire  [2:0] wb_m2s_dbg_sdram_dbus_cti;
-wire  [1:0] wb_m2s_dbg_sdram_dbus_bte;
-wire [31:0] wb_s2m_dbg_sdram_dbus_dat;
-wire        wb_s2m_dbg_sdram_dbus_ack;
-wire        wb_s2m_dbg_sdram_dbus_err;
-wire        wb_s2m_dbg_sdram_dbus_rty;
-wire [31:0] wb_m2s_dbg_uart0_adr;
-wire [31:0] wb_m2s_dbg_uart0_dat;
-wire  [3:0] wb_m2s_dbg_uart0_sel;
-wire        wb_m2s_dbg_uart0_we;
-wire        wb_m2s_dbg_uart0_cyc;
-wire        wb_m2s_dbg_uart0_stb;
-wire  [2:0] wb_m2s_dbg_uart0_cti;
-wire  [1:0] wb_m2s_dbg_uart0_bte;
-wire [31:0] wb_s2m_dbg_uart0_dat;
-wire        wb_s2m_dbg_uart0_ack;
-wire        wb_s2m_dbg_uart0_err;
-wire        wb_s2m_dbg_uart0_rty;
-wire [31:0] wb_m2s_dbg_gpio0_adr;
-wire [31:0] wb_m2s_dbg_gpio0_dat;
-wire  [3:0] wb_m2s_dbg_gpio0_sel;
-wire        wb_m2s_dbg_gpio0_we;
-wire        wb_m2s_dbg_gpio0_cyc;
-wire        wb_m2s_dbg_gpio0_stb;
-wire  [2:0] wb_m2s_dbg_gpio0_cti;
-wire  [1:0] wb_m2s_dbg_gpio0_bte;
-wire [31:0] wb_s2m_dbg_gpio0_dat;
-wire        wb_s2m_dbg_gpio0_ack;
-wire        wb_s2m_dbg_gpio0_err;
-wire        wb_s2m_dbg_gpio0_rty;
-wire [31:0] wb_m2s_resize_uart0_adr;
-wire [31:0] wb_m2s_resize_uart0_dat;
-wire  [3:0] wb_m2s_resize_uart0_sel;
-wire        wb_m2s_resize_uart0_we;
-wire        wb_m2s_resize_uart0_cyc;
-wire        wb_m2s_resize_uart0_stb;
-wire  [2:0] wb_m2s_resize_uart0_cti;
-wire  [1:0] wb_m2s_resize_uart0_bte;
-wire [31:0] wb_s2m_resize_uart0_dat;
-wire        wb_s2m_resize_uart0_ack;
-wire        wb_s2m_resize_uart0_err;
-wire        wb_s2m_resize_uart0_rty;
-wire [31:0] wb_m2s_resize_gpio0_adr;
-wire [31:0] wb_m2s_resize_gpio0_dat;
-wire  [3:0] wb_m2s_resize_gpio0_sel;
-wire        wb_m2s_resize_gpio0_we;
-wire        wb_m2s_resize_gpio0_cyc;
-wire        wb_m2s_resize_gpio0_stb;
-wire  [2:0] wb_m2s_resize_gpio0_cti;
-wire  [1:0] wb_m2s_resize_gpio0_bte;
-wire [31:0] wb_s2m_resize_gpio0_dat;
-wire        wb_s2m_resize_gpio0_ack;
-wire        wb_s2m_resize_gpio0_err;
-wire        wb_s2m_resize_gpio0_rty;
-
-wb_mux
-  #(.num_slaves (2),
-    .MATCH_ADDR ({32'h00000000, 32'hf0000100}),
-    .MATCH_MASK ({32'hfe000000, 32'hffffffc0}))
- wb_mux_or1k_i
-   (.wb_clk_i  (wb_clk_i),
-    .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i (wb_or1k_i_adr_i),
-    .wbm_dat_i (wb_or1k_i_dat_i),
-    .wbm_sel_i (wb_or1k_i_sel_i),
-    .wbm_we_i  (wb_or1k_i_we_i),
-    .wbm_cyc_i (wb_or1k_i_cyc_i),
-    .wbm_stb_i (wb_or1k_i_stb_i),
-    .wbm_cti_i (wb_or1k_i_cti_i),
-    .wbm_bte_i (wb_or1k_i_bte_i),
-    .wbm_dat_o (wb_or1k_i_dat_o),
-    .wbm_ack_o (wb_or1k_i_ack_o),
-    .wbm_err_o (wb_or1k_i_err_o),
-    .wbm_rty_o (wb_or1k_i_rty_o),
-    .wbs_adr_o ({wb_sdram_ibus_adr_o, wb_rom0_adr_o}),
-    .wbs_dat_o ({wb_sdram_ibus_dat_o, wb_rom0_dat_o}),
-    .wbs_sel_o ({wb_sdram_ibus_sel_o, wb_rom0_sel_o}),
-    .wbs_we_o  ({wb_sdram_ibus_we_o, wb_rom0_we_o}),
-    .wbs_cyc_o ({wb_sdram_ibus_cyc_o, wb_rom0_cyc_o}),
-    .wbs_stb_o ({wb_sdram_ibus_stb_o, wb_rom0_stb_o}),
-    .wbs_cti_o ({wb_sdram_ibus_cti_o, wb_rom0_cti_o}),
-    .wbs_bte_o ({wb_sdram_ibus_bte_o, wb_rom0_bte_o}),
-    .wbs_dat_i ({wb_sdram_ibus_dat_i, wb_rom0_dat_i}),
-    .wbs_ack_i ({wb_sdram_ibus_ack_i, wb_rom0_ack_i}),
-    .wbs_err_i ({wb_sdram_ibus_err_i, wb_rom0_err_i}),
-    .wbs_rty_i ({wb_sdram_ibus_rty_i, wb_rom0_rty_i}));
-
-wb_mux
-  #(.num_slaves (3),
-    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
-    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
- wb_mux_or1k_d
-   (.wb_clk_i  (wb_clk_i),
-    .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i (wb_or1k_d_adr_i),
-    .wbm_dat_i (wb_or1k_d_dat_i),
-    .wbm_sel_i (wb_or1k_d_sel_i),
-    .wbm_we_i  (wb_or1k_d_we_i),
-    .wbm_cyc_i (wb_or1k_d_cyc_i),
-    .wbm_stb_i (wb_or1k_d_stb_i),
-    .wbm_cti_i (wb_or1k_d_cti_i),
-    .wbm_bte_i (wb_or1k_d_bte_i),
-    .wbm_dat_o (wb_or1k_d_dat_o),
-    .wbm_ack_o (wb_or1k_d_ack_o),
-    .wbm_err_o (wb_or1k_d_err_o),
-    .wbm_rty_o (wb_or1k_d_rty_o),
-    .wbs_adr_o ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_or1k_d_uart0_adr, wb_m2s_or1k_d_gpio0_adr}),
-    .wbs_dat_o ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_or1k_d_uart0_dat, wb_m2s_or1k_d_gpio0_dat}),
-    .wbs_sel_o ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_or1k_d_uart0_sel, wb_m2s_or1k_d_gpio0_sel}),
-    .wbs_we_o  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_or1k_d_uart0_we, wb_m2s_or1k_d_gpio0_we}),
-    .wbs_cyc_o ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_or1k_d_uart0_cyc, wb_m2s_or1k_d_gpio0_cyc}),
-    .wbs_stb_o ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_or1k_d_uart0_stb, wb_m2s_or1k_d_gpio0_stb}),
-    .wbs_cti_o ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_or1k_d_uart0_cti, wb_m2s_or1k_d_gpio0_cti}),
-    .wbs_bte_o ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_or1k_d_uart0_bte, wb_m2s_or1k_d_gpio0_bte}),
-    .wbs_dat_i ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_or1k_d_uart0_dat, wb_s2m_or1k_d_gpio0_dat}),
-    .wbs_ack_i ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_or1k_d_uart0_ack, wb_s2m_or1k_d_gpio0_ack}),
-    .wbs_err_i ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_or1k_d_uart0_err, wb_s2m_or1k_d_gpio0_err}),
-    .wbs_rty_i ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_or1k_d_uart0_rty, wb_s2m_or1k_d_gpio0_rty}));
-
-wb_mux
-  #(.num_slaves (3),
-    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
-    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
- wb_mux_dbg
-   (.wb_clk_i  (wb_clk_i),
-    .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i (wb_dbg_adr_i),
-    .wbm_dat_i (wb_dbg_dat_i),
-    .wbm_sel_i (wb_dbg_sel_i),
-    .wbm_we_i  (wb_dbg_we_i),
-    .wbm_cyc_i (wb_dbg_cyc_i),
-    .wbm_stb_i (wb_dbg_stb_i),
-    .wbm_cti_i (wb_dbg_cti_i),
-    .wbm_bte_i (wb_dbg_bte_i),
-    .wbm_dat_o (wb_dbg_dat_o),
-    .wbm_ack_o (wb_dbg_ack_o),
-    .wbm_err_o (wb_dbg_err_o),
-    .wbm_rty_o (wb_dbg_rty_o),
-    .wbs_adr_o ({wb_m2s_dbg_sdram_dbus_adr, wb_m2s_dbg_uart0_adr, wb_m2s_dbg_gpio0_adr}),
-    .wbs_dat_o ({wb_m2s_dbg_sdram_dbus_dat, wb_m2s_dbg_uart0_dat, wb_m2s_dbg_gpio0_dat}),
-    .wbs_sel_o ({wb_m2s_dbg_sdram_dbus_sel, wb_m2s_dbg_uart0_sel, wb_m2s_dbg_gpio0_sel}),
-    .wbs_we_o  ({wb_m2s_dbg_sdram_dbus_we, wb_m2s_dbg_uart0_we, wb_m2s_dbg_gpio0_we}),
-    .wbs_cyc_o ({wb_m2s_dbg_sdram_dbus_cyc, wb_m2s_dbg_uart0_cyc, wb_m2s_dbg_gpio0_cyc}),
-    .wbs_stb_o ({wb_m2s_dbg_sdram_dbus_stb, wb_m2s_dbg_uart0_stb, wb_m2s_dbg_gpio0_stb}),
-    .wbs_cti_o ({wb_m2s_dbg_sdram_dbus_cti, wb_m2s_dbg_uart0_cti, wb_m2s_dbg_gpio0_cti}),
-    .wbs_bte_o ({wb_m2s_dbg_sdram_dbus_bte, wb_m2s_dbg_uart0_bte, wb_m2s_dbg_gpio0_bte}),
-    .wbs_dat_i ({wb_s2m_dbg_sdram_dbus_dat, wb_s2m_dbg_uart0_dat, wb_s2m_dbg_gpio0_dat}),
-    .wbs_ack_i ({wb_s2m_dbg_sdram_dbus_ack, wb_s2m_dbg_uart0_ack, wb_s2m_dbg_gpio0_ack}),
-    .wbs_err_i ({wb_s2m_dbg_sdram_dbus_err, wb_s2m_dbg_uart0_err, wb_s2m_dbg_gpio0_err}),
-    .wbs_rty_i ({wb_s2m_dbg_sdram_dbus_rty, wb_s2m_dbg_uart0_rty, wb_s2m_dbg_gpio0_rty}));
-
-wb_arbiter
-  #(.num_masters (2))
- wb_arbiter_uart0
-   (.wb_clk_i  (wb_clk_i),
-    .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i ({wb_m2s_or1k_d_uart0_adr, wb_m2s_dbg_uart0_adr}),
-    .wbm_dat_i ({wb_m2s_or1k_d_uart0_dat, wb_m2s_dbg_uart0_dat}),
-    .wbm_sel_i ({wb_m2s_or1k_d_uart0_sel, wb_m2s_dbg_uart0_sel}),
-    .wbm_we_i  ({wb_m2s_or1k_d_uart0_we, wb_m2s_dbg_uart0_we}),
-    .wbm_cyc_i ({wb_m2s_or1k_d_uart0_cyc, wb_m2s_dbg_uart0_cyc}),
-    .wbm_stb_i ({wb_m2s_or1k_d_uart0_stb, wb_m2s_dbg_uart0_stb}),
-    .wbm_cti_i ({wb_m2s_or1k_d_uart0_cti, wb_m2s_dbg_uart0_cti}),
-    .wbm_bte_i ({wb_m2s_or1k_d_uart0_bte, wb_m2s_dbg_uart0_bte}),
-    .wbm_dat_o ({wb_s2m_or1k_d_uart0_dat, wb_s2m_dbg_uart0_dat}),
-    .wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}),
-    .wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}),
-    .wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}),
-    .wbs_adr_o (wb_m2s_resize_uart0_adr),
-    .wbs_dat_o (wb_m2s_resize_uart0_dat),
-    .wbs_sel_o (wb_m2s_resize_uart0_sel),
-    .wbs_we_o  (wb_m2s_resize_uart0_we),
-    .wbs_cyc_o (wb_m2s_resize_uart0_cyc),
-    .wbs_stb_o (wb_m2s_resize_uart0_stb),
-    .wbs_cti_o (wb_m2s_resize_uart0_cti),
-    .wbs_bte_o (wb_m2s_resize_uart0_bte),
-    .wbs_dat_i (wb_s2m_resize_uart0_dat),
-    .wbs_ack_i (wb_s2m_resize_uart0_ack),
-    .wbs_err_i (wb_s2m_resize_uart0_err),
-    .wbs_rty_i (wb_s2m_resize_uart0_rty));
-
-wb_data_resize
-  #(.aw  (32),
-    .mdw (32),
-    .sdw (8))
- wb_data_resize_uart0
-   (.wbm_adr_i (wb_m2s_resize_uart0_adr),
-    .wbm_dat_i (wb_m2s_resize_uart0_dat),
-    .wbm_sel_i (wb_m2s_resize_uart0_sel),
-    .wbm_we_i  (wb_m2s_resize_uart0_we),
-    .wbm_cyc_i (wb_m2s_resize_uart0_cyc),
-    .wbm_stb_i (wb_m2s_resize_uart0_stb),
-    .wbm_cti_i (wb_m2s_resize_uart0_cti),
-    .wbm_bte_i (wb_m2s_resize_uart0_bte),
-    .wbm_dat_o (wb_s2m_resize_uart0_dat),
-    .wbm_ack_o (wb_s2m_resize_uart0_ack),
-    .wbm_err_o (wb_s2m_resize_uart0_err),
-    .wbm_rty_o (wb_s2m_resize_uart0_rty),
-    .wbs_adr_o (wb_uart0_adr_o),
-    .wbs_dat_o (wb_uart0_dat_o),
-    .wbs_we_o  (wb_uart0_we_o),
-    .wbs_cyc_o (wb_uart0_cyc_o),
-    .wbs_stb_o (wb_uart0_stb_o),
-    .wbs_cti_o (wb_uart0_cti_o),
-    .wbs_bte_o (wb_uart0_bte_o),
-    .wbs_dat_i (wb_uart0_dat_i),
-    .wbs_ack_i (wb_uart0_ack_i),
-    .wbs_err_i (wb_uart0_err_i),
-    .wbs_rty_i (wb_uart0_rty_i));
-
-wb_arbiter
-  #(.num_masters (2))
- wb_arbiter_gpio0
-   (.wb_clk_i  (wb_clk_i),
-    .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}),
-    .wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}),
-    .wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}),
-    .wbm_we_i  ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}),
-    .wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}),
-    .wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}),
-    .wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}),
-    .wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}),
-    .wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}),
-    .wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}),
-    .wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}),
-    .wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}),
-    .wbs_adr_o (wb_m2s_resize_gpio0_adr),
-    .wbs_dat_o (wb_m2s_resize_gpio0_dat),
-    .wbs_sel_o (wb_m2s_resize_gpio0_sel),
-    .wbs_we_o  (wb_m2s_resize_gpio0_we),
-    .wbs_cyc_o (wb_m2s_resize_gpio0_cyc),
-    .wbs_stb_o (wb_m2s_resize_gpio0_stb),
-    .wbs_cti_o (wb_m2s_resize_gpio0_cti),
-    .wbs_bte_o (wb_m2s_resize_gpio0_bte),
-    .wbs_dat_i (wb_s2m_resize_gpio0_dat),
-    .wbs_ack_i (wb_s2m_resize_gpio0_ack),
-    .wbs_err_i (wb_s2m_resize_gpio0_err),
-    .wbs_rty_i (wb_s2m_resize_gpio0_rty));
-
-wb_data_resize
-  #(.aw  (32),
-    .mdw (32),
-    .sdw (8))
- wb_data_resize_gpio0
-   (.wbm_adr_i (wb_m2s_resize_gpio0_adr),
-    .wbm_dat_i (wb_m2s_resize_gpio0_dat),
-    .wbm_sel_i (wb_m2s_resize_gpio0_sel),
-    .wbm_we_i  (wb_m2s_resize_gpio0_we),
-    .wbm_cyc_i (wb_m2s_resize_gpio0_cyc),
-    .wbm_stb_i (wb_m2s_resize_gpio0_stb),
-    .wbm_cti_i (wb_m2s_resize_gpio0_cti),
-    .wbm_bte_i (wb_m2s_resize_gpio0_bte),
-    .wbm_dat_o (wb_s2m_resize_gpio0_dat),
-    .wbm_ack_o (wb_s2m_resize_gpio0_ack),
-    .wbm_err_o (wb_s2m_resize_gpio0_err),
-    .wbm_rty_o (wb_s2m_resize_gpio0_rty),
-    .wbs_adr_o (wb_gpio0_adr_o),
-    .wbs_dat_o (wb_gpio0_dat_o),
-    .wbs_we_o  (wb_gpio0_we_o),
-    .wbs_cyc_o (wb_gpio0_cyc_o),
-    .wbs_stb_o (wb_gpio0_stb_o),
-    .wbs_cti_o (wb_gpio0_cti_o),
-    .wbs_bte_o (wb_gpio0_bte_o),
-    .wbs_dat_i (wb_gpio0_dat_i),
-    .wbs_ack_i (wb_gpio0_ack_i),
-    .wbs_err_i (wb_gpio0_err_i),
-    .wbs_rty_i (wb_gpio0_rty_i));
-
-wb_arbiter
-  #(.num_masters (2))
- wb_arbiter_sdram_dbus
-   (.wb_clk_i  (wb_clk_i),
-    .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_dbg_sdram_dbus_adr}),
-    .wbm_dat_i ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_dbg_sdram_dbus_dat}),
-    .wbm_sel_i ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_dbg_sdram_dbus_sel}),
-    .wbm_we_i  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_dbg_sdram_dbus_we}),
-    .wbm_cyc_i ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_dbg_sdram_dbus_cyc}),
-    .wbm_stb_i ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_dbg_sdram_dbus_stb}),
-    .wbm_cti_i ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_dbg_sdram_dbus_cti}),
-    .wbm_bte_i ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_dbg_sdram_dbus_bte}),
-    .wbm_dat_o ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_dbg_sdram_dbus_dat}),
-    .wbm_ack_o ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_dbg_sdram_dbus_ack}),
-    .wbm_err_o ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_dbg_sdram_dbus_err}),
-    .wbm_rty_o ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_dbg_sdram_dbus_rty}),
-    .wbs_adr_o (wb_sdram_dbus_adr_o),
-    .wbs_dat_o (wb_sdram_dbus_dat_o),
-    .wbs_sel_o (wb_sdram_dbus_sel_o),
-    .wbs_we_o  (wb_sdram_dbus_we_o),
-    .wbs_cyc_o (wb_sdram_dbus_cyc_o),
-    .wbs_stb_o (wb_sdram_dbus_stb_o),
-    .wbs_cti_o (wb_sdram_dbus_cti_o),
-    .wbs_bte_o (wb_sdram_dbus_bte_o),
-    .wbs_dat_i (wb_sdram_dbus_dat_i),
-    .wbs_ack_i (wb_sdram_dbus_ack_i),
-    .wbs_err_i (wb_sdram_dbus_err_i),
-    .wbs_rty_i (wb_sdram_dbus_rty_i));
-
-endmodule
diff --git a/cores/wb_intercon/sw/wb_intercon.vh b/cores/wb_intercon/sw/wb_intercon.vh
deleted file mode 100644
index cc8a6714..00000000
--- a/cores/wb_intercon/sw/wb_intercon.vh
+++ /dev/null
@@ -1,197 +0,0 @@
-wire [31:0] wb_m2s_or1k_i_adr;
-wire [31:0] wb_m2s_or1k_i_dat;
-wire  [3:0] wb_m2s_or1k_i_sel;
-wire        wb_m2s_or1k_i_we;
-wire        wb_m2s_or1k_i_cyc;
-wire        wb_m2s_or1k_i_stb;
-wire  [2:0] wb_m2s_or1k_i_cti;
-wire  [1:0] wb_m2s_or1k_i_bte;
-wire [31:0] wb_s2m_or1k_i_dat;
-wire        wb_s2m_or1k_i_ack;
-wire        wb_s2m_or1k_i_err;
-wire        wb_s2m_or1k_i_rty;
-wire [31:0] wb_m2s_or1k_d_adr;
-wire [31:0] wb_m2s_or1k_d_dat;
-wire  [3:0] wb_m2s_or1k_d_sel;
-wire        wb_m2s_or1k_d_we;
-wire        wb_m2s_or1k_d_cyc;
-wire        wb_m2s_or1k_d_stb;
-wire  [2:0] wb_m2s_or1k_d_cti;
-wire  [1:0] wb_m2s_or1k_d_bte;
-wire [31:0] wb_s2m_or1k_d_dat;
-wire        wb_s2m_or1k_d_ack;
-wire        wb_s2m_or1k_d_err;
-wire        wb_s2m_or1k_d_rty;
-wire [31:0] wb_m2s_dbg_adr;
-wire [31:0] wb_m2s_dbg_dat;
-wire  [3:0] wb_m2s_dbg_sel;
-wire        wb_m2s_dbg_we;
-wire        wb_m2s_dbg_cyc;
-wire        wb_m2s_dbg_stb;
-wire  [2:0] wb_m2s_dbg_cti;
-wire  [1:0] wb_m2s_dbg_bte;
-wire [31:0] wb_s2m_dbg_dat;
-wire        wb_s2m_dbg_ack;
-wire        wb_s2m_dbg_err;
-wire        wb_s2m_dbg_rty;
-wire [31:0] wb_m2s_uart0_adr;
-wire [31:0] wb_m2s_uart0_dat;
-wire  [3:0] wb_m2s_uart0_sel;
-wire        wb_m2s_uart0_we;
-wire        wb_m2s_uart0_cyc;
-wire        wb_m2s_uart0_stb;
-wire  [2:0] wb_m2s_uart0_cti;
-wire  [1:0] wb_m2s_uart0_bte;
-wire [31:0] wb_s2m_uart0_dat;
-wire        wb_s2m_uart0_ack;
-wire        wb_s2m_uart0_err;
-wire        wb_s2m_uart0_rty;
-wire [31:0] wb_m2s_gpio0_adr;
-wire [31:0] wb_m2s_gpio0_dat;
-wire  [3:0] wb_m2s_gpio0_sel;
-wire        wb_m2s_gpio0_we;
-wire        wb_m2s_gpio0_cyc;
-wire        wb_m2s_gpio0_stb;
-wire  [2:0] wb_m2s_gpio0_cti;
-wire  [1:0] wb_m2s_gpio0_bte;
-wire [31:0] wb_s2m_gpio0_dat;
-wire        wb_s2m_gpio0_ack;
-wire        wb_s2m_gpio0_err;
-wire        wb_s2m_gpio0_rty;
-wire [31:0] wb_m2s_sdram_dbus_adr;
-wire [31:0] wb_m2s_sdram_dbus_dat;
-wire  [3:0] wb_m2s_sdram_dbus_sel;
-wire        wb_m2s_sdram_dbus_we;
-wire        wb_m2s_sdram_dbus_cyc;
-wire        wb_m2s_sdram_dbus_stb;
-wire  [2:0] wb_m2s_sdram_dbus_cti;
-wire  [1:0] wb_m2s_sdram_dbus_bte;
-wire [31:0] wb_s2m_sdram_dbus_dat;
-wire        wb_s2m_sdram_dbus_ack;
-wire        wb_s2m_sdram_dbus_err;
-wire        wb_s2m_sdram_dbus_rty;
-wire [31:0] wb_m2s_rom0_adr;
-wire [31:0] wb_m2s_rom0_dat;
-wire  [3:0] wb_m2s_rom0_sel;
-wire        wb_m2s_rom0_we;
-wire        wb_m2s_rom0_cyc;
-wire        wb_m2s_rom0_stb;
-wire  [2:0] wb_m2s_rom0_cti;
-wire  [1:0] wb_m2s_rom0_bte;
-wire [31:0] wb_s2m_rom0_dat;
-wire        wb_s2m_rom0_ack;
-wire        wb_s2m_rom0_err;
-wire        wb_s2m_rom0_rty;
-wire [31:0] wb_m2s_sdram_ibus_adr;
-wire [31:0] wb_m2s_sdram_ibus_dat;
-wire  [3:0] wb_m2s_sdram_ibus_sel;
-wire        wb_m2s_sdram_ibus_we;
-wire        wb_m2s_sdram_ibus_cyc;
-wire        wb_m2s_sdram_ibus_stb;
-wire  [2:0] wb_m2s_sdram_ibus_cti;
-wire  [1:0] wb_m2s_sdram_ibus_bte;
-wire [31:0] wb_s2m_sdram_ibus_dat;
-wire        wb_s2m_sdram_ibus_ack;
-wire        wb_s2m_sdram_ibus_err;
-wire        wb_s2m_sdram_ibus_rty;
-
-wb_intercon wb_intercon0
-   (.wb_clk_i            (wb_clk),
-    .wb_rst_i            (wb_rst),
-    .wb_or1k_i_adr_i     (wb_m2s_or1k_i_adr),
-    .wb_or1k_i_dat_i     (wb_m2s_or1k_i_dat),
-    .wb_or1k_i_sel_i     (wb_m2s_or1k_i_sel),
-    .wb_or1k_i_we_i      (wb_m2s_or1k_i_we),
-    .wb_or1k_i_cyc_i     (wb_m2s_or1k_i_cyc),
-    .wb_or1k_i_stb_i     (wb_m2s_or1k_i_stb),
-    .wb_or1k_i_cti_i     (wb_m2s_or1k_i_cti),
-    .wb_or1k_i_bte_i     (wb_m2s_or1k_i_bte),
-    .wb_or1k_i_dat_o     (wb_s2m_or1k_i_dat),
-    .wb_or1k_i_ack_o     (wb_s2m_or1k_i_ack),
-    .wb_or1k_i_err_o     (wb_s2m_or1k_i_err),
-    .wb_or1k_i_rty_o     (wb_s2m_or1k_i_rty),
-    .wb_or1k_d_adr_i     (wb_m2s_or1k_d_adr),
-    .wb_or1k_d_dat_i     (wb_m2s_or1k_d_dat),
-    .wb_or1k_d_sel_i     (wb_m2s_or1k_d_sel),
-    .wb_or1k_d_we_i      (wb_m2s_or1k_d_we),
-    .wb_or1k_d_cyc_i     (wb_m2s_or1k_d_cyc),
-    .wb_or1k_d_stb_i     (wb_m2s_or1k_d_stb),
-    .wb_or1k_d_cti_i     (wb_m2s_or1k_d_cti),
-    .wb_or1k_d_bte_i     (wb_m2s_or1k_d_bte),
-    .wb_or1k_d_dat_o     (wb_s2m_or1k_d_dat),
-    .wb_or1k_d_ack_o     (wb_s2m_or1k_d_ack),
-    .wb_or1k_d_err_o     (wb_s2m_or1k_d_err),
-    .wb_or1k_d_rty_o     (wb_s2m_or1k_d_rty),
-    .wb_dbg_adr_i        (wb_m2s_dbg_adr),
-    .wb_dbg_dat_i        (wb_m2s_dbg_dat),
-    .wb_dbg_sel_i        (wb_m2s_dbg_sel),
-    .wb_dbg_we_i         (wb_m2s_dbg_we),
-    .wb_dbg_cyc_i        (wb_m2s_dbg_cyc),
-    .wb_dbg_stb_i        (wb_m2s_dbg_stb),
-    .wb_dbg_cti_i        (wb_m2s_dbg_cti),
-    .wb_dbg_bte_i        (wb_m2s_dbg_bte),
-    .wb_dbg_dat_o        (wb_s2m_dbg_dat),
-    .wb_dbg_ack_o        (wb_s2m_dbg_ack),
-    .wb_dbg_err_o        (wb_s2m_dbg_err),
-    .wb_dbg_rty_o        (wb_s2m_dbg_rty),
-    .wb_uart0_adr_o      (wb_m2s_uart0_adr),
-    .wb_uart0_dat_o      (wb_m2s_uart0_dat),
-    .wb_uart0_sel_o      (wb_m2s_uart0_sel),
-    .wb_uart0_we_o       (wb_m2s_uart0_we),
-    .wb_uart0_cyc_o      (wb_m2s_uart0_cyc),
-    .wb_uart0_stb_o      (wb_m2s_uart0_stb),
-    .wb_uart0_cti_o      (wb_m2s_uart0_cti),
-    .wb_uart0_bte_o      (wb_m2s_uart0_bte),
-    .wb_uart0_dat_i      (wb_s2m_uart0_dat),
-    .wb_uart0_ack_i      (wb_s2m_uart0_ack),
-    .wb_uart0_err_i      (wb_s2m_uart0_err),
-    .wb_uart0_rty_i      (wb_s2m_uart0_rty),
-    .wb_gpio0_adr_o      (wb_m2s_gpio0_adr),
-    .wb_gpio0_dat_o      (wb_m2s_gpio0_dat),
-    .wb_gpio0_sel_o      (wb_m2s_gpio0_sel),
-    .wb_gpio0_we_o       (wb_m2s_gpio0_we),
-    .wb_gpio0_cyc_o      (wb_m2s_gpio0_cyc),
-    .wb_gpio0_stb_o      (wb_m2s_gpio0_stb),
-    .wb_gpio0_cti_o      (wb_m2s_gpio0_cti),
-    .wb_gpio0_bte_o      (wb_m2s_gpio0_bte),
-    .wb_gpio0_dat_i      (wb_s2m_gpio0_dat),
-    .wb_gpio0_ack_i      (wb_s2m_gpio0_ack),
-    .wb_gpio0_err_i      (wb_s2m_gpio0_err),
-    .wb_gpio0_rty_i      (wb_s2m_gpio0_rty),
-    .wb_sdram_dbus_adr_o (wb_m2s_sdram_dbus_adr),
-    .wb_sdram_dbus_dat_o (wb_m2s_sdram_dbus_dat),
-    .wb_sdram_dbus_sel_o (wb_m2s_sdram_dbus_sel),
-    .wb_sdram_dbus_we_o  (wb_m2s_sdram_dbus_we),
-    .wb_sdram_dbus_cyc_o (wb_m2s_sdram_dbus_cyc),
-    .wb_sdram_dbus_stb_o (wb_m2s_sdram_dbus_stb),
-    .wb_sdram_dbus_cti_o (wb_m2s_sdram_dbus_cti),
-    .wb_sdram_dbus_bte_o (wb_m2s_sdram_dbus_bte),
-    .wb_sdram_dbus_dat_i (wb_s2m_sdram_dbus_dat),
-    .wb_sdram_dbus_ack_i (wb_s2m_sdram_dbus_ack),
-    .wb_sdram_dbus_err_i (wb_s2m_sdram_dbus_err),
-    .wb_sdram_dbus_rty_i (wb_s2m_sdram_dbus_rty),
-    .wb_rom0_adr_o       (wb_m2s_rom0_adr),
-    .wb_rom0_dat_o       (wb_m2s_rom0_dat),
-    .wb_rom0_sel_o       (wb_m2s_rom0_sel),
-    .wb_rom0_we_o        (wb_m2s_rom0_we),
-    .wb_rom0_cyc_o       (wb_m2s_rom0_cyc),
-    .wb_rom0_stb_o       (wb_m2s_rom0_stb),
-    .wb_rom0_cti_o       (wb_m2s_rom0_cti),
-    .wb_rom0_bte_o       (wb_m2s_rom0_bte),
-    .wb_rom0_dat_i       (wb_s2m_rom0_dat),
-    .wb_rom0_ack_i       (wb_s2m_rom0_ack),
-    .wb_rom0_err_i       (wb_s2m_rom0_err),
-    .wb_rom0_rty_i       (wb_s2m_rom0_rty),
-    .wb_sdram_ibus_adr_o (wb_m2s_sdram_ibus_adr),
-    .wb_sdram_ibus_dat_o (wb_m2s_sdram_ibus_dat),
-    .wb_sdram_ibus_sel_o (wb_m2s_sdram_ibus_sel),
-    .wb_sdram_ibus_we_o  (wb_m2s_sdram_ibus_we),
-    .wb_sdram_ibus_cyc_o (wb_m2s_sdram_ibus_cyc),
-    .wb_sdram_ibus_stb_o (wb_m2s_sdram_ibus_stb),
-    .wb_sdram_ibus_cti_o (wb_m2s_sdram_ibus_cti),
-    .wb_sdram_ibus_bte_o (wb_m2s_sdram_ibus_bte),
-    .wb_sdram_ibus_dat_i (wb_s2m_sdram_ibus_dat),
-    .wb_sdram_ibus_ack_i (wb_s2m_sdram_ibus_ack),
-    .wb_sdram_ibus_err_i (wb_s2m_sdram_ibus_err),
-    .wb_sdram_ibus_rty_i (wb_s2m_sdram_ibus_rty));
-

From cd9d0aa68ed0e76add9e3bd04de05587e09c7c15 Mon Sep 17 00:00:00 2001
From: tmd-set <tranminhduc.set@live.com>
Date: Thu, 6 Mar 2014 16:42:50 +0700
Subject: [PATCH 12/12] Newly generated wb_intercon files

---
 systems/de2/rtl/verilog/wb_intercon.old.v  | 360 +++++++++++++++++++++
 systems/de2/rtl/verilog/wb_intercon.old.vh | 197 +++++++++++
 systems/de2/rtl/verilog/wb_intercon.v      | 168 +++++++---
 systems/de2/rtl/verilog/wb_intercon.vh     |  48 +--
 4 files changed, 706 insertions(+), 67 deletions(-)
 create mode 100755 systems/de2/rtl/verilog/wb_intercon.old.v
 create mode 100755 systems/de2/rtl/verilog/wb_intercon.old.vh
 mode change 100755 => 100644 systems/de2/rtl/verilog/wb_intercon.v
 mode change 100755 => 100644 systems/de2/rtl/verilog/wb_intercon.vh

diff --git a/systems/de2/rtl/verilog/wb_intercon.old.v b/systems/de2/rtl/verilog/wb_intercon.old.v
new file mode 100755
index 00000000..aa04cde6
--- /dev/null
+++ b/systems/de2/rtl/verilog/wb_intercon.old.v
@@ -0,0 +1,360 @@
+module wb_intercon
+   (input         wb_clk_i,
+    input         wb_rst_i,
+    input  [31:0] wb_or1k_i_adr_i,
+    input  [31:0] wb_or1k_i_dat_i,
+    input   [3:0] wb_or1k_i_sel_i,
+    input         wb_or1k_i_we_i,
+    input         wb_or1k_i_cyc_i,
+    input         wb_or1k_i_stb_i,
+    input   [2:0] wb_or1k_i_cti_i,
+    input   [1:0] wb_or1k_i_bte_i,
+    output [31:0] wb_or1k_i_dat_o,
+    output        wb_or1k_i_ack_o,
+    output        wb_or1k_i_err_o,
+    output        wb_or1k_i_rty_o,
+    input  [31:0] wb_or1k_d_adr_i,
+    input  [31:0] wb_or1k_d_dat_i,
+    input   [3:0] wb_or1k_d_sel_i,
+    input         wb_or1k_d_we_i,
+    input         wb_or1k_d_cyc_i,
+    input         wb_or1k_d_stb_i,
+    input   [2:0] wb_or1k_d_cti_i,
+    input   [1:0] wb_or1k_d_bte_i,
+    output [31:0] wb_or1k_d_dat_o,
+    output        wb_or1k_d_ack_o,
+    output        wb_or1k_d_err_o,
+    output        wb_or1k_d_rty_o,
+    input  [31:0] wb_dbg_adr_i,
+    input  [31:0] wb_dbg_dat_i,
+    input   [3:0] wb_dbg_sel_i,
+    input         wb_dbg_we_i,
+    input         wb_dbg_cyc_i,
+    input         wb_dbg_stb_i,
+    input   [2:0] wb_dbg_cti_i,
+    input   [1:0] wb_dbg_bte_i,
+    output [31:0] wb_dbg_dat_o,
+    output        wb_dbg_ack_o,
+    output        wb_dbg_err_o,
+    output        wb_dbg_rty_o,
+    output [31:0] wb_uart0_adr_o,
+    output [31:0] wb_uart0_dat_o,
+    output  [3:0] wb_uart0_sel_o,
+    output        wb_uart0_we_o,
+    output        wb_uart0_cyc_o,
+    output        wb_uart0_stb_o,
+    output  [2:0] wb_uart0_cti_o,
+    output  [1:0] wb_uart0_bte_o,
+    input  [31:0] wb_uart0_dat_i,
+    input         wb_uart0_ack_i,
+    input         wb_uart0_err_i,
+    input         wb_uart0_rty_i,
+    output [31:0] wb_sdram_dbus_adr_o,
+    output [31:0] wb_sdram_dbus_dat_o,
+    output  [3:0] wb_sdram_dbus_sel_o,
+    output        wb_sdram_dbus_we_o,
+    output        wb_sdram_dbus_cyc_o,
+    output        wb_sdram_dbus_stb_o,
+    output  [2:0] wb_sdram_dbus_cti_o,
+    output  [1:0] wb_sdram_dbus_bte_o,
+    input  [31:0] wb_sdram_dbus_dat_i,
+    input         wb_sdram_dbus_ack_i,
+    input         wb_sdram_dbus_err_i,
+    input         wb_sdram_dbus_rty_i,
+    output [31:0] wb_gpio0_adr_o,
+    output [31:0] wb_gpio0_dat_o,
+    output  [3:0] wb_gpio0_sel_o,
+    output        wb_gpio0_we_o,
+    output        wb_gpio0_cyc_o,
+    output        wb_gpio0_stb_o,
+    output  [2:0] wb_gpio0_cti_o,
+    output  [1:0] wb_gpio0_bte_o,
+    input  [31:0] wb_gpio0_dat_i,
+    input         wb_gpio0_ack_i,
+    input         wb_gpio0_err_i,
+    input         wb_gpio0_rty_i,
+    output [31:0] wb_rom0_adr_o,
+    output [31:0] wb_rom0_dat_o,
+    output  [3:0] wb_rom0_sel_o,
+    output        wb_rom0_we_o,
+    output        wb_rom0_cyc_o,
+    output        wb_rom0_stb_o,
+    output  [2:0] wb_rom0_cti_o,
+    output  [1:0] wb_rom0_bte_o,
+    input  [31:0] wb_rom0_dat_i,
+    input         wb_rom0_ack_i,
+    input         wb_rom0_err_i,
+    input         wb_rom0_rty_i,
+    output [31:0] wb_sdram_ibus_adr_o,
+    output [31:0] wb_sdram_ibus_dat_o,
+    output  [3:0] wb_sdram_ibus_sel_o,
+    output        wb_sdram_ibus_we_o,
+    output        wb_sdram_ibus_cyc_o,
+    output        wb_sdram_ibus_stb_o,
+    output  [2:0] wb_sdram_ibus_cti_o,
+    output  [1:0] wb_sdram_ibus_bte_o,
+    input  [31:0] wb_sdram_ibus_dat_i,
+    input         wb_sdram_ibus_ack_i,
+    input         wb_sdram_ibus_err_i,
+    input         wb_sdram_ibus_rty_i);
+
+wire [31:0] wb_m2s_or1k_d_sdram_dbus_adr;
+wire [31:0] wb_m2s_or1k_d_sdram_dbus_dat;
+wire  [3:0] wb_m2s_or1k_d_sdram_dbus_sel;
+wire        wb_m2s_or1k_d_sdram_dbus_we;
+wire        wb_m2s_or1k_d_sdram_dbus_cyc;
+wire        wb_m2s_or1k_d_sdram_dbus_stb;
+wire  [2:0] wb_m2s_or1k_d_sdram_dbus_cti;
+wire  [1:0] wb_m2s_or1k_d_sdram_dbus_bte;
+wire [31:0] wb_s2m_or1k_d_sdram_dbus_dat;
+wire        wb_s2m_or1k_d_sdram_dbus_ack;
+wire        wb_s2m_or1k_d_sdram_dbus_err;
+wire        wb_s2m_or1k_d_sdram_dbus_rty;
+wire [31:0] wb_m2s_or1k_d_uart0_adr;
+wire [31:0] wb_m2s_or1k_d_uart0_dat;
+wire  [3:0] wb_m2s_or1k_d_uart0_sel;
+wire        wb_m2s_or1k_d_uart0_we;
+wire        wb_m2s_or1k_d_uart0_cyc;
+wire        wb_m2s_or1k_d_uart0_stb;
+wire  [2:0] wb_m2s_or1k_d_uart0_cti;
+wire  [1:0] wb_m2s_or1k_d_uart0_bte;
+wire [31:0] wb_s2m_or1k_d_uart0_dat;
+wire        wb_s2m_or1k_d_uart0_ack;
+wire        wb_s2m_or1k_d_uart0_err;
+wire        wb_s2m_or1k_d_uart0_rty;
+wire [31:0] wb_m2s_or1k_d_gpio0_adr;
+wire [31:0] wb_m2s_or1k_d_gpio0_dat;
+wire  [3:0] wb_m2s_or1k_d_gpio0_sel;
+wire        wb_m2s_or1k_d_gpio0_we;
+wire        wb_m2s_or1k_d_gpio0_cyc;
+wire        wb_m2s_or1k_d_gpio0_stb;
+wire  [2:0] wb_m2s_or1k_d_gpio0_cti;
+wire  [1:0] wb_m2s_or1k_d_gpio0_bte;
+wire [31:0] wb_s2m_or1k_d_gpio0_dat;
+wire        wb_s2m_or1k_d_gpio0_ack;
+wire        wb_s2m_or1k_d_gpio0_err;
+wire        wb_s2m_or1k_d_gpio0_rty;
+wire [31:0] wb_m2s_dbg_sdram_dbus_adr;
+wire [31:0] wb_m2s_dbg_sdram_dbus_dat;
+wire  [3:0] wb_m2s_dbg_sdram_dbus_sel;
+wire        wb_m2s_dbg_sdram_dbus_we;
+wire        wb_m2s_dbg_sdram_dbus_cyc;
+wire        wb_m2s_dbg_sdram_dbus_stb;
+wire  [2:0] wb_m2s_dbg_sdram_dbus_cti;
+wire  [1:0] wb_m2s_dbg_sdram_dbus_bte;
+wire [31:0] wb_s2m_dbg_sdram_dbus_dat;
+wire        wb_s2m_dbg_sdram_dbus_ack;
+wire        wb_s2m_dbg_sdram_dbus_err;
+wire        wb_s2m_dbg_sdram_dbus_rty;
+wire [31:0] wb_m2s_dbg_uart0_adr;
+wire [31:0] wb_m2s_dbg_uart0_dat;
+wire  [3:0] wb_m2s_dbg_uart0_sel;
+wire        wb_m2s_dbg_uart0_we;
+wire        wb_m2s_dbg_uart0_cyc;
+wire        wb_m2s_dbg_uart0_stb;
+wire  [2:0] wb_m2s_dbg_uart0_cti;
+wire  [1:0] wb_m2s_dbg_uart0_bte;
+wire [31:0] wb_s2m_dbg_uart0_dat;
+wire        wb_s2m_dbg_uart0_ack;
+wire        wb_s2m_dbg_uart0_err;
+wire        wb_s2m_dbg_uart0_rty;
+wire [31:0] wb_m2s_dbg_gpio0_adr;
+wire [31:0] wb_m2s_dbg_gpio0_dat;
+wire  [3:0] wb_m2s_dbg_gpio0_sel;
+wire        wb_m2s_dbg_gpio0_we;
+wire        wb_m2s_dbg_gpio0_cyc;
+wire        wb_m2s_dbg_gpio0_stb;
+wire  [2:0] wb_m2s_dbg_gpio0_cti;
+wire  [1:0] wb_m2s_dbg_gpio0_bte;
+wire [31:0] wb_s2m_dbg_gpio0_dat;
+wire        wb_s2m_dbg_gpio0_ack;
+wire        wb_s2m_dbg_gpio0_err;
+wire        wb_s2m_dbg_gpio0_rty;
+
+wb_mux
+  #(.num_slaves (2),
+    .MATCH_ADDR ({32'h00000000, 32'hf0000100}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffc0}))
+ wb_mux_or1k_i
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_or1k_i_adr_i),
+    .wbm_dat_i (wb_or1k_i_dat_i),
+    .wbm_sel_i (wb_or1k_i_sel_i),
+    .wbm_we_i  (wb_or1k_i_we_i),
+    .wbm_cyc_i (wb_or1k_i_cyc_i),
+    .wbm_stb_i (wb_or1k_i_stb_i),
+    .wbm_cti_i (wb_or1k_i_cti_i),
+    .wbm_bte_i (wb_or1k_i_bte_i),
+    .wbm_dat_o (wb_or1k_i_dat_o),
+    .wbm_ack_o (wb_or1k_i_ack_o),
+    .wbm_err_o (wb_or1k_i_err_o),
+    .wbm_rty_o (wb_or1k_i_rty_o),
+    .wbs_adr_o ({wb_sdram_ibus_adr_o, wb_rom0_adr_o}),
+    .wbs_dat_o ({wb_sdram_ibus_dat_o, wb_rom0_dat_o}),
+    .wbs_sel_o ({wb_sdram_ibus_sel_o, wb_rom0_sel_o}),
+    .wbs_we_o  ({wb_sdram_ibus_we_o, wb_rom0_we_o}),
+    .wbs_cyc_o ({wb_sdram_ibus_cyc_o, wb_rom0_cyc_o}),
+    .wbs_stb_o ({wb_sdram_ibus_stb_o, wb_rom0_stb_o}),
+    .wbs_cti_o ({wb_sdram_ibus_cti_o, wb_rom0_cti_o}),
+    .wbs_bte_o ({wb_sdram_ibus_bte_o, wb_rom0_bte_o}),
+    .wbs_dat_i ({wb_sdram_ibus_dat_i, wb_rom0_dat_i}),
+    .wbs_ack_i ({wb_sdram_ibus_ack_i, wb_rom0_ack_i}),
+    .wbs_err_i ({wb_sdram_ibus_err_i, wb_rom0_err_i}),
+    .wbs_rty_i ({wb_sdram_ibus_rty_i, wb_rom0_rty_i}));
+
+wb_mux
+  #(.num_slaves (3),
+    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
+ wb_mux_or1k_d
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_or1k_d_adr_i),
+    .wbm_dat_i (wb_or1k_d_dat_i),
+    .wbm_sel_i (wb_or1k_d_sel_i),
+    .wbm_we_i  (wb_or1k_d_we_i),
+    .wbm_cyc_i (wb_or1k_d_cyc_i),
+    .wbm_stb_i (wb_or1k_d_stb_i),
+    .wbm_cti_i (wb_or1k_d_cti_i),
+    .wbm_bte_i (wb_or1k_d_bte_i),
+    .wbm_dat_o (wb_or1k_d_dat_o),
+    .wbm_ack_o (wb_or1k_d_ack_o),
+    .wbm_err_o (wb_or1k_d_err_o),
+    .wbm_rty_o (wb_or1k_d_rty_o),
+    .wbs_adr_o ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_or1k_d_uart0_adr, wb_m2s_or1k_d_gpio0_adr}),
+    .wbs_dat_o ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_or1k_d_uart0_dat, wb_m2s_or1k_d_gpio0_dat}),
+    .wbs_sel_o ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_or1k_d_uart0_sel, wb_m2s_or1k_d_gpio0_sel}),
+    .wbs_we_o  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_or1k_d_uart0_we, wb_m2s_or1k_d_gpio0_we}),
+    .wbs_cyc_o ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_or1k_d_uart0_cyc, wb_m2s_or1k_d_gpio0_cyc}),
+    .wbs_stb_o ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_or1k_d_uart0_stb, wb_m2s_or1k_d_gpio0_stb}),
+    .wbs_cti_o ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_or1k_d_uart0_cti, wb_m2s_or1k_d_gpio0_cti}),
+    .wbs_bte_o ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_or1k_d_uart0_bte, wb_m2s_or1k_d_gpio0_bte}),
+    .wbs_dat_i ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_or1k_d_uart0_dat, wb_s2m_or1k_d_gpio0_dat}),
+    .wbs_ack_i ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_or1k_d_uart0_ack, wb_s2m_or1k_d_gpio0_ack}),
+    .wbs_err_i ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_or1k_d_uart0_err, wb_s2m_or1k_d_gpio0_err}),
+    .wbs_rty_i ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_or1k_d_uart0_rty, wb_s2m_or1k_d_gpio0_rty}));
+
+wb_mux
+  #(.num_slaves (3),
+    .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
+    .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
+ wb_mux_dbg
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_dbg_adr_i),
+    .wbm_dat_i (wb_dbg_dat_i),
+    .wbm_sel_i (wb_dbg_sel_i),
+    .wbm_we_i  (wb_dbg_we_i),
+    .wbm_cyc_i (wb_dbg_cyc_i),
+    .wbm_stb_i (wb_dbg_stb_i),
+    .wbm_cti_i (wb_dbg_cti_i),
+    .wbm_bte_i (wb_dbg_bte_i),
+    .wbm_dat_o (wb_dbg_dat_o),
+    .wbm_ack_o (wb_dbg_ack_o),
+    .wbm_err_o (wb_dbg_err_o),
+    .wbm_rty_o (wb_dbg_rty_o),
+    .wbs_adr_o ({wb_m2s_dbg_sdram_dbus_adr, wb_m2s_dbg_uart0_adr, wb_m2s_dbg_gpio0_adr}),
+    .wbs_dat_o ({wb_m2s_dbg_sdram_dbus_dat, wb_m2s_dbg_uart0_dat, wb_m2s_dbg_gpio0_dat}),
+    .wbs_sel_o ({wb_m2s_dbg_sdram_dbus_sel, wb_m2s_dbg_uart0_sel, wb_m2s_dbg_gpio0_sel}),
+    .wbs_we_o  ({wb_m2s_dbg_sdram_dbus_we, wb_m2s_dbg_uart0_we, wb_m2s_dbg_gpio0_we}),
+    .wbs_cyc_o ({wb_m2s_dbg_sdram_dbus_cyc, wb_m2s_dbg_uart0_cyc, wb_m2s_dbg_gpio0_cyc}),
+    .wbs_stb_o ({wb_m2s_dbg_sdram_dbus_stb, wb_m2s_dbg_uart0_stb, wb_m2s_dbg_gpio0_stb}),
+    .wbs_cti_o ({wb_m2s_dbg_sdram_dbus_cti, wb_m2s_dbg_uart0_cti, wb_m2s_dbg_gpio0_cti}),
+    .wbs_bte_o ({wb_m2s_dbg_sdram_dbus_bte, wb_m2s_dbg_uart0_bte, wb_m2s_dbg_gpio0_bte}),
+    .wbs_dat_i ({wb_s2m_dbg_sdram_dbus_dat, wb_s2m_dbg_uart0_dat, wb_s2m_dbg_gpio0_dat}),
+    .wbs_ack_i ({wb_s2m_dbg_sdram_dbus_ack, wb_s2m_dbg_uart0_ack, wb_s2m_dbg_gpio0_ack}),
+    .wbs_err_i ({wb_s2m_dbg_sdram_dbus_err, wb_s2m_dbg_uart0_err, wb_s2m_dbg_gpio0_err}),
+    .wbs_rty_i ({wb_s2m_dbg_sdram_dbus_rty, wb_s2m_dbg_uart0_rty, wb_s2m_dbg_gpio0_rty}));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_uart0
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_uart0_adr, wb_m2s_dbg_uart0_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_uart0_dat, wb_m2s_dbg_uart0_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_uart0_sel, wb_m2s_dbg_uart0_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_uart0_we, wb_m2s_dbg_uart0_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_uart0_cyc, wb_m2s_dbg_uart0_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_uart0_stb, wb_m2s_dbg_uart0_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_uart0_cti, wb_m2s_dbg_uart0_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_uart0_bte, wb_m2s_dbg_uart0_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_uart0_dat, wb_s2m_dbg_uart0_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}),
+    .wbs_adr_o (wb_uart0_adr_o),
+    .wbs_dat_o (wb_uart0_dat_o),
+    .wbs_sel_o (wb_uart0_sel_o),
+    .wbs_we_o  (wb_uart0_we_o),
+    .wbs_cyc_o (wb_uart0_cyc_o),
+    .wbs_stb_o (wb_uart0_stb_o),
+    .wbs_cti_o (wb_uart0_cti_o),
+    .wbs_bte_o (wb_uart0_bte_o),
+    .wbs_dat_i (wb_uart0_dat_i),
+    .wbs_ack_i (wb_uart0_ack_i),
+    .wbs_err_i (wb_uart0_err_i),
+    .wbs_rty_i (wb_uart0_rty_i));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_sdram_dbus
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_dbg_sdram_dbus_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_dbg_sdram_dbus_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_dbg_sdram_dbus_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_dbg_sdram_dbus_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_dbg_sdram_dbus_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_dbg_sdram_dbus_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_dbg_sdram_dbus_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_dbg_sdram_dbus_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_dbg_sdram_dbus_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_dbg_sdram_dbus_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_dbg_sdram_dbus_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_dbg_sdram_dbus_rty}),
+    .wbs_adr_o (wb_sdram_dbus_adr_o),
+    .wbs_dat_o (wb_sdram_dbus_dat_o),
+    .wbs_sel_o (wb_sdram_dbus_sel_o),
+    .wbs_we_o  (wb_sdram_dbus_we_o),
+    .wbs_cyc_o (wb_sdram_dbus_cyc_o),
+    .wbs_stb_o (wb_sdram_dbus_stb_o),
+    .wbs_cti_o (wb_sdram_dbus_cti_o),
+    .wbs_bte_o (wb_sdram_dbus_bte_o),
+    .wbs_dat_i (wb_sdram_dbus_dat_i),
+    .wbs_ack_i (wb_sdram_dbus_ack_i),
+    .wbs_err_i (wb_sdram_dbus_err_i),
+    .wbs_rty_i (wb_sdram_dbus_rty_i));
+
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_gpio0
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}),
+    .wbs_adr_o (wb_gpio0_adr_o),
+    .wbs_dat_o (wb_gpio0_dat_o),
+    .wbs_sel_o (wb_gpio0_sel_o),
+    .wbs_we_o  (wb_gpio0_we_o),
+    .wbs_cyc_o (wb_gpio0_cyc_o),
+    .wbs_stb_o (wb_gpio0_stb_o),
+    .wbs_cti_o (wb_gpio0_cti_o),
+    .wbs_bte_o (wb_gpio0_bte_o),
+    .wbs_dat_i (wb_gpio0_dat_i),
+    .wbs_ack_i (wb_gpio0_ack_i),
+    .wbs_err_i (wb_gpio0_err_i),
+    .wbs_rty_i (wb_gpio0_rty_i));
+
+endmodule
diff --git a/systems/de2/rtl/verilog/wb_intercon.old.vh b/systems/de2/rtl/verilog/wb_intercon.old.vh
new file mode 100755
index 00000000..e81420ee
--- /dev/null
+++ b/systems/de2/rtl/verilog/wb_intercon.old.vh
@@ -0,0 +1,197 @@
+wire [31:0] wb_m2s_or1k_i_adr;
+wire [31:0] wb_m2s_or1k_i_dat;
+wire  [3:0] wb_m2s_or1k_i_sel;
+wire        wb_m2s_or1k_i_we;
+wire        wb_m2s_or1k_i_cyc;
+wire        wb_m2s_or1k_i_stb;
+wire  [2:0] wb_m2s_or1k_i_cti;
+wire  [1:0] wb_m2s_or1k_i_bte;
+wire [31:0] wb_s2m_or1k_i_dat;
+wire        wb_s2m_or1k_i_ack;
+wire        wb_s2m_or1k_i_err;
+wire        wb_s2m_or1k_i_rty;
+wire [31:0] wb_m2s_or1k_d_adr;
+wire [31:0] wb_m2s_or1k_d_dat;
+wire  [3:0] wb_m2s_or1k_d_sel;
+wire        wb_m2s_or1k_d_we;
+wire        wb_m2s_or1k_d_cyc;
+wire        wb_m2s_or1k_d_stb;
+wire  [2:0] wb_m2s_or1k_d_cti;
+wire  [1:0] wb_m2s_or1k_d_bte;
+wire [31:0] wb_s2m_or1k_d_dat;
+wire        wb_s2m_or1k_d_ack;
+wire        wb_s2m_or1k_d_err;
+wire        wb_s2m_or1k_d_rty;
+wire [31:0] wb_m2s_dbg_adr;
+wire [31:0] wb_m2s_dbg_dat;
+wire  [3:0] wb_m2s_dbg_sel;
+wire        wb_m2s_dbg_we;
+wire        wb_m2s_dbg_cyc;
+wire        wb_m2s_dbg_stb;
+wire  [2:0] wb_m2s_dbg_cti;
+wire  [1:0] wb_m2s_dbg_bte;
+wire [31:0] wb_s2m_dbg_dat;
+wire        wb_s2m_dbg_ack;
+wire        wb_s2m_dbg_err;
+wire        wb_s2m_dbg_rty;
+wire [31:0] wb_m2s_uart0_adr;
+wire [31:0] wb_m2s_uart0_dat;
+wire  [3:0] wb_m2s_uart0_sel;
+wire        wb_m2s_uart0_we;
+wire        wb_m2s_uart0_cyc;
+wire        wb_m2s_uart0_stb;
+wire  [2:0] wb_m2s_uart0_cti;
+wire  [1:0] wb_m2s_uart0_bte;
+wire [31:0] wb_s2m_uart0_dat;
+wire        wb_s2m_uart0_ack;
+wire        wb_s2m_uart0_err;
+wire        wb_s2m_uart0_rty;
+wire [31:0] wb_m2s_sdram_dbus_adr;
+wire [31:0] wb_m2s_sdram_dbus_dat;
+wire  [3:0] wb_m2s_sdram_dbus_sel;
+wire        wb_m2s_sdram_dbus_we;
+wire        wb_m2s_sdram_dbus_cyc;
+wire        wb_m2s_sdram_dbus_stb;
+wire  [2:0] wb_m2s_sdram_dbus_cti;
+wire  [1:0] wb_m2s_sdram_dbus_bte;
+wire [31:0] wb_s2m_sdram_dbus_dat;
+wire        wb_s2m_sdram_dbus_ack;
+wire        wb_s2m_sdram_dbus_err;
+wire        wb_s2m_sdram_dbus_rty;
+wire [31:0] wb_m2s_gpio0_adr;
+wire [31:0] wb_m2s_gpio0_dat;
+wire  [3:0] wb_m2s_gpio0_sel;
+wire        wb_m2s_gpio0_we;
+wire        wb_m2s_gpio0_cyc;
+wire        wb_m2s_gpio0_stb;
+wire  [2:0] wb_m2s_gpio0_cti;
+wire  [1:0] wb_m2s_gpio0_bte;
+wire [31:0] wb_s2m_gpio0_dat;
+wire        wb_s2m_gpio0_ack;
+wire        wb_s2m_gpio0_err;
+wire        wb_s2m_gpio0_rty;
+wire [31:0] wb_m2s_rom0_adr;
+wire [31:0] wb_m2s_rom0_dat;
+wire  [3:0] wb_m2s_rom0_sel;
+wire        wb_m2s_rom0_we;
+wire        wb_m2s_rom0_cyc;
+wire        wb_m2s_rom0_stb;
+wire  [2:0] wb_m2s_rom0_cti;
+wire  [1:0] wb_m2s_rom0_bte;
+wire [31:0] wb_s2m_rom0_dat;
+wire        wb_s2m_rom0_ack;
+wire        wb_s2m_rom0_err;
+wire        wb_s2m_rom0_rty;
+wire [31:0] wb_m2s_sdram_ibus_adr;
+wire [31:0] wb_m2s_sdram_ibus_dat;
+wire  [3:0] wb_m2s_sdram_ibus_sel;
+wire        wb_m2s_sdram_ibus_we;
+wire        wb_m2s_sdram_ibus_cyc;
+wire        wb_m2s_sdram_ibus_stb;
+wire  [2:0] wb_m2s_sdram_ibus_cti;
+wire  [1:0] wb_m2s_sdram_ibus_bte;
+wire [31:0] wb_s2m_sdram_ibus_dat;
+wire        wb_s2m_sdram_ibus_ack;
+wire        wb_s2m_sdram_ibus_err;
+wire        wb_s2m_sdram_ibus_rty;
+
+wb_intercon wb_intercon0
+   (.wb_clk_i            (wb_clk),
+    .wb_rst_i            (wb_rst),
+    .wb_or1k_i_adr_i     (wb_m2s_or1k_i_adr),
+    .wb_or1k_i_dat_i     (wb_m2s_or1k_i_dat),
+    .wb_or1k_i_sel_i     (wb_m2s_or1k_i_sel),
+    .wb_or1k_i_we_i      (wb_m2s_or1k_i_we),
+    .wb_or1k_i_cyc_i     (wb_m2s_or1k_i_cyc),
+    .wb_or1k_i_stb_i     (wb_m2s_or1k_i_stb),
+    .wb_or1k_i_cti_i     (wb_m2s_or1k_i_cti),
+    .wb_or1k_i_bte_i     (wb_m2s_or1k_i_bte),
+    .wb_or1k_i_dat_o     (wb_s2m_or1k_i_dat),
+    .wb_or1k_i_ack_o     (wb_s2m_or1k_i_ack),
+    .wb_or1k_i_err_o     (wb_s2m_or1k_i_err),
+    .wb_or1k_i_rty_o     (wb_s2m_or1k_i_rty),
+    .wb_or1k_d_adr_i     (wb_m2s_or1k_d_adr),
+    .wb_or1k_d_dat_i     (wb_m2s_or1k_d_dat),
+    .wb_or1k_d_sel_i     (wb_m2s_or1k_d_sel),
+    .wb_or1k_d_we_i      (wb_m2s_or1k_d_we),
+    .wb_or1k_d_cyc_i     (wb_m2s_or1k_d_cyc),
+    .wb_or1k_d_stb_i     (wb_m2s_or1k_d_stb),
+    .wb_or1k_d_cti_i     (wb_m2s_or1k_d_cti),
+    .wb_or1k_d_bte_i     (wb_m2s_or1k_d_bte),
+    .wb_or1k_d_dat_o     (wb_s2m_or1k_d_dat),
+    .wb_or1k_d_ack_o     (wb_s2m_or1k_d_ack),
+    .wb_or1k_d_err_o     (wb_s2m_or1k_d_err),
+    .wb_or1k_d_rty_o     (wb_s2m_or1k_d_rty),
+    .wb_dbg_adr_i        (wb_m2s_dbg_adr),
+    .wb_dbg_dat_i        (wb_m2s_dbg_dat),
+    .wb_dbg_sel_i        (wb_m2s_dbg_sel),
+    .wb_dbg_we_i         (wb_m2s_dbg_we),
+    .wb_dbg_cyc_i        (wb_m2s_dbg_cyc),
+    .wb_dbg_stb_i        (wb_m2s_dbg_stb),
+    .wb_dbg_cti_i        (wb_m2s_dbg_cti),
+    .wb_dbg_bte_i        (wb_m2s_dbg_bte),
+    .wb_dbg_dat_o        (wb_s2m_dbg_dat),
+    .wb_dbg_ack_o        (wb_s2m_dbg_ack),
+    .wb_dbg_err_o        (wb_s2m_dbg_err),
+    .wb_dbg_rty_o        (wb_s2m_dbg_rty),
+    .wb_uart0_adr_o      (wb_m2s_uart0_adr),
+    .wb_uart0_dat_o      (wb_m2s_uart0_dat),
+    .wb_uart0_sel_o      (wb_m2s_uart0_sel),
+    .wb_uart0_we_o       (wb_m2s_uart0_we),
+    .wb_uart0_cyc_o      (wb_m2s_uart0_cyc),
+    .wb_uart0_stb_o      (wb_m2s_uart0_stb),
+    .wb_uart0_cti_o      (wb_m2s_uart0_cti),
+    .wb_uart0_bte_o      (wb_m2s_uart0_bte),
+    .wb_uart0_dat_i      (wb_s2m_uart0_dat),
+    .wb_uart0_ack_i      (wb_s2m_uart0_ack),
+    .wb_uart0_err_i      (wb_s2m_uart0_err),
+    .wb_uart0_rty_i      (wb_s2m_uart0_rty),
+    .wb_sdram_dbus_adr_o (wb_m2s_sdram_dbus_adr),
+    .wb_sdram_dbus_dat_o (wb_m2s_sdram_dbus_dat),
+    .wb_sdram_dbus_sel_o (wb_m2s_sdram_dbus_sel),
+    .wb_sdram_dbus_we_o  (wb_m2s_sdram_dbus_we),
+    .wb_sdram_dbus_cyc_o (wb_m2s_sdram_dbus_cyc),
+    .wb_sdram_dbus_stb_o (wb_m2s_sdram_dbus_stb),
+    .wb_sdram_dbus_cti_o (wb_m2s_sdram_dbus_cti),
+    .wb_sdram_dbus_bte_o (wb_m2s_sdram_dbus_bte),
+    .wb_sdram_dbus_dat_i (wb_s2m_sdram_dbus_dat),
+    .wb_sdram_dbus_ack_i (wb_s2m_sdram_dbus_ack),
+    .wb_sdram_dbus_err_i (wb_s2m_sdram_dbus_err),
+    .wb_sdram_dbus_rty_i (wb_s2m_sdram_dbus_rty),
+    .wb_gpio0_adr_o      (wb_m2s_gpio0_adr),
+    .wb_gpio0_dat_o      (wb_m2s_gpio0_dat),
+    .wb_gpio0_sel_o      (wb_m2s_gpio0_sel),
+    .wb_gpio0_we_o       (wb_m2s_gpio0_we),
+    .wb_gpio0_cyc_o      (wb_m2s_gpio0_cyc),
+    .wb_gpio0_stb_o      (wb_m2s_gpio0_stb),
+    .wb_gpio0_cti_o      (wb_m2s_gpio0_cti),
+    .wb_gpio0_bte_o      (wb_m2s_gpio0_bte),
+    .wb_gpio0_dat_i      (wb_s2m_gpio0_dat),
+    .wb_gpio0_ack_i      (wb_s2m_gpio0_ack),
+    .wb_gpio0_err_i      (wb_s2m_gpio0_err),
+    .wb_gpio0_rty_i      (wb_s2m_gpio0_rty),
+    .wb_rom0_adr_o       (wb_m2s_rom0_adr),
+    .wb_rom0_dat_o       (wb_m2s_rom0_dat),
+    .wb_rom0_sel_o       (wb_m2s_rom0_sel),
+    .wb_rom0_we_o        (wb_m2s_rom0_we),
+    .wb_rom0_cyc_o       (wb_m2s_rom0_cyc),
+    .wb_rom0_stb_o       (wb_m2s_rom0_stb),
+    .wb_rom0_cti_o       (wb_m2s_rom0_cti),
+    .wb_rom0_bte_o       (wb_m2s_rom0_bte),
+    .wb_rom0_dat_i       (wb_s2m_rom0_dat),
+    .wb_rom0_ack_i       (wb_s2m_rom0_ack),
+    .wb_rom0_err_i       (wb_s2m_rom0_err),
+    .wb_rom0_rty_i       (wb_s2m_rom0_rty),
+    .wb_sdram_ibus_adr_o (wb_m2s_sdram_ibus_adr),
+    .wb_sdram_ibus_dat_o (wb_m2s_sdram_ibus_dat),
+    .wb_sdram_ibus_sel_o (wb_m2s_sdram_ibus_sel),
+    .wb_sdram_ibus_we_o  (wb_m2s_sdram_ibus_we),
+    .wb_sdram_ibus_cyc_o (wb_m2s_sdram_ibus_cyc),
+    .wb_sdram_ibus_stb_o (wb_m2s_sdram_ibus_stb),
+    .wb_sdram_ibus_cti_o (wb_m2s_sdram_ibus_cti),
+    .wb_sdram_ibus_bte_o (wb_m2s_sdram_ibus_bte),
+    .wb_sdram_ibus_dat_i (wb_s2m_sdram_ibus_dat),
+    .wb_sdram_ibus_ack_i (wb_s2m_sdram_ibus_ack),
+    .wb_sdram_ibus_err_i (wb_s2m_sdram_ibus_err),
+    .wb_sdram_ibus_rty_i (wb_s2m_sdram_ibus_rty));
+
diff --git a/systems/de2/rtl/verilog/wb_intercon.v b/systems/de2/rtl/verilog/wb_intercon.v
old mode 100755
new mode 100644
index aa04cde6..5358c2c6
--- a/systems/de2/rtl/verilog/wb_intercon.v
+++ b/systems/de2/rtl/verilog/wb_intercon.v
@@ -49,18 +49,6 @@ module wb_intercon
     input         wb_uart0_ack_i,
     input         wb_uart0_err_i,
     input         wb_uart0_rty_i,
-    output [31:0] wb_sdram_dbus_adr_o,
-    output [31:0] wb_sdram_dbus_dat_o,
-    output  [3:0] wb_sdram_dbus_sel_o,
-    output        wb_sdram_dbus_we_o,
-    output        wb_sdram_dbus_cyc_o,
-    output        wb_sdram_dbus_stb_o,
-    output  [2:0] wb_sdram_dbus_cti_o,
-    output  [1:0] wb_sdram_dbus_bte_o,
-    input  [31:0] wb_sdram_dbus_dat_i,
-    input         wb_sdram_dbus_ack_i,
-    input         wb_sdram_dbus_err_i,
-    input         wb_sdram_dbus_rty_i,
     output [31:0] wb_gpio0_adr_o,
     output [31:0] wb_gpio0_dat_o,
     output  [3:0] wb_gpio0_sel_o,
@@ -73,6 +61,18 @@ module wb_intercon
     input         wb_gpio0_ack_i,
     input         wb_gpio0_err_i,
     input         wb_gpio0_rty_i,
+    output [31:0] wb_sdram_dbus_adr_o,
+    output [31:0] wb_sdram_dbus_dat_o,
+    output  [3:0] wb_sdram_dbus_sel_o,
+    output        wb_sdram_dbus_we_o,
+    output        wb_sdram_dbus_cyc_o,
+    output        wb_sdram_dbus_stb_o,
+    output  [2:0] wb_sdram_dbus_cti_o,
+    output  [1:0] wb_sdram_dbus_bte_o,
+    input  [31:0] wb_sdram_dbus_dat_i,
+    input         wb_sdram_dbus_ack_i,
+    input         wb_sdram_dbus_err_i,
+    input         wb_sdram_dbus_rty_i,
     output [31:0] wb_rom0_adr_o,
     output [31:0] wb_rom0_dat_o,
     output  [3:0] wb_rom0_sel_o,
@@ -170,6 +170,30 @@ wire [31:0] wb_s2m_dbg_gpio0_dat;
 wire        wb_s2m_dbg_gpio0_ack;
 wire        wb_s2m_dbg_gpio0_err;
 wire        wb_s2m_dbg_gpio0_rty;
+wire [31:0] wb_m2s_resize_uart0_adr;
+wire [31:0] wb_m2s_resize_uart0_dat;
+wire  [3:0] wb_m2s_resize_uart0_sel;
+wire        wb_m2s_resize_uart0_we;
+wire        wb_m2s_resize_uart0_cyc;
+wire        wb_m2s_resize_uart0_stb;
+wire  [2:0] wb_m2s_resize_uart0_cti;
+wire  [1:0] wb_m2s_resize_uart0_bte;
+wire [31:0] wb_s2m_resize_uart0_dat;
+wire        wb_s2m_resize_uart0_ack;
+wire        wb_s2m_resize_uart0_err;
+wire        wb_s2m_resize_uart0_rty;
+wire [31:0] wb_m2s_resize_gpio0_adr;
+wire [31:0] wb_m2s_resize_gpio0_dat;
+wire  [3:0] wb_m2s_resize_gpio0_sel;
+wire        wb_m2s_resize_gpio0_we;
+wire        wb_m2s_resize_gpio0_cyc;
+wire        wb_m2s_resize_gpio0_stb;
+wire  [2:0] wb_m2s_resize_gpio0_cti;
+wire  [1:0] wb_m2s_resize_gpio0_bte;
+wire [31:0] wb_s2m_resize_gpio0_dat;
+wire        wb_s2m_resize_gpio0_ack;
+wire        wb_s2m_resize_gpio0_err;
+wire        wb_s2m_resize_gpio0_rty;
 
 wb_mux
   #(.num_slaves (2),
@@ -284,9 +308,38 @@ wb_arbiter
     .wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}),
     .wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}),
     .wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}),
+    .wbs_adr_o (wb_m2s_resize_uart0_adr),
+    .wbs_dat_o (wb_m2s_resize_uart0_dat),
+    .wbs_sel_o (wb_m2s_resize_uart0_sel),
+    .wbs_we_o  (wb_m2s_resize_uart0_we),
+    .wbs_cyc_o (wb_m2s_resize_uart0_cyc),
+    .wbs_stb_o (wb_m2s_resize_uart0_stb),
+    .wbs_cti_o (wb_m2s_resize_uart0_cti),
+    .wbs_bte_o (wb_m2s_resize_uart0_bte),
+    .wbs_dat_i (wb_s2m_resize_uart0_dat),
+    .wbs_ack_i (wb_s2m_resize_uart0_ack),
+    .wbs_err_i (wb_s2m_resize_uart0_err),
+    .wbs_rty_i (wb_s2m_resize_uart0_rty));
+
+wb_data_resize
+  #(.aw  (32),
+    .mdw (32),
+    .sdw (8))
+ wb_data_resize_uart0
+   (.wbm_adr_i (wb_m2s_resize_uart0_adr),
+    .wbm_dat_i (wb_m2s_resize_uart0_dat),
+    .wbm_sel_i (wb_m2s_resize_uart0_sel),
+    .wbm_we_i  (wb_m2s_resize_uart0_we),
+    .wbm_cyc_i (wb_m2s_resize_uart0_cyc),
+    .wbm_stb_i (wb_m2s_resize_uart0_stb),
+    .wbm_cti_i (wb_m2s_resize_uart0_cti),
+    .wbm_bte_i (wb_m2s_resize_uart0_bte),
+    .wbm_dat_o (wb_s2m_resize_uart0_dat),
+    .wbm_ack_o (wb_s2m_resize_uart0_ack),
+    .wbm_err_o (wb_s2m_resize_uart0_err),
+    .wbm_rty_o (wb_s2m_resize_uart0_rty),
     .wbs_adr_o (wb_uart0_adr_o),
     .wbs_dat_o (wb_uart0_dat_o),
-    .wbs_sel_o (wb_uart0_sel_o),
     .wbs_we_o  (wb_uart0_we_o),
     .wbs_cyc_o (wb_uart0_cyc_o),
     .wbs_stb_o (wb_uart0_stb_o),
@@ -297,6 +350,65 @@ wb_arbiter
     .wbs_err_i (wb_uart0_err_i),
     .wbs_rty_i (wb_uart0_rty_i));
 
+wb_arbiter
+  #(.num_masters (2))
+ wb_arbiter_gpio0
+   (.wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}),
+    .wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}),
+    .wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}),
+    .wbm_we_i  ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}),
+    .wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}),
+    .wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}),
+    .wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}),
+    .wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}),
+    .wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}),
+    .wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}),
+    .wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}),
+    .wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}),
+    .wbs_adr_o (wb_m2s_resize_gpio0_adr),
+    .wbs_dat_o (wb_m2s_resize_gpio0_dat),
+    .wbs_sel_o (wb_m2s_resize_gpio0_sel),
+    .wbs_we_o  (wb_m2s_resize_gpio0_we),
+    .wbs_cyc_o (wb_m2s_resize_gpio0_cyc),
+    .wbs_stb_o (wb_m2s_resize_gpio0_stb),
+    .wbs_cti_o (wb_m2s_resize_gpio0_cti),
+    .wbs_bte_o (wb_m2s_resize_gpio0_bte),
+    .wbs_dat_i (wb_s2m_resize_gpio0_dat),
+    .wbs_ack_i (wb_s2m_resize_gpio0_ack),
+    .wbs_err_i (wb_s2m_resize_gpio0_err),
+    .wbs_rty_i (wb_s2m_resize_gpio0_rty));
+
+wb_data_resize
+  #(.aw  (32),
+    .mdw (32),
+    .sdw (8))
+ wb_data_resize_gpio0
+   (.wbm_adr_i (wb_m2s_resize_gpio0_adr),
+    .wbm_dat_i (wb_m2s_resize_gpio0_dat),
+    .wbm_sel_i (wb_m2s_resize_gpio0_sel),
+    .wbm_we_i  (wb_m2s_resize_gpio0_we),
+    .wbm_cyc_i (wb_m2s_resize_gpio0_cyc),
+    .wbm_stb_i (wb_m2s_resize_gpio0_stb),
+    .wbm_cti_i (wb_m2s_resize_gpio0_cti),
+    .wbm_bte_i (wb_m2s_resize_gpio0_bte),
+    .wbm_dat_o (wb_s2m_resize_gpio0_dat),
+    .wbm_ack_o (wb_s2m_resize_gpio0_ack),
+    .wbm_err_o (wb_s2m_resize_gpio0_err),
+    .wbm_rty_o (wb_s2m_resize_gpio0_rty),
+    .wbs_adr_o (wb_gpio0_adr_o),
+    .wbs_dat_o (wb_gpio0_dat_o),
+    .wbs_we_o  (wb_gpio0_we_o),
+    .wbs_cyc_o (wb_gpio0_cyc_o),
+    .wbs_stb_o (wb_gpio0_stb_o),
+    .wbs_cti_o (wb_gpio0_cti_o),
+    .wbs_bte_o (wb_gpio0_bte_o),
+    .wbs_dat_i (wb_gpio0_dat_i),
+    .wbs_ack_i (wb_gpio0_ack_i),
+    .wbs_err_i (wb_gpio0_err_i),
+    .wbs_rty_i (wb_gpio0_rty_i));
+
 wb_arbiter
   #(.num_masters (2))
  wb_arbiter_sdram_dbus
@@ -327,34 +439,4 @@ wb_arbiter
     .wbs_err_i (wb_sdram_dbus_err_i),
     .wbs_rty_i (wb_sdram_dbus_rty_i));
 
-wb_arbiter
-  #(.num_masters (2))
- wb_arbiter_gpio0
-   (.wb_clk_i  (wb_clk_i),
-    .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}),
-    .wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}),
-    .wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}),
-    .wbm_we_i  ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}),
-    .wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}),
-    .wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}),
-    .wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}),
-    .wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}),
-    .wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}),
-    .wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}),
-    .wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}),
-    .wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}),
-    .wbs_adr_o (wb_gpio0_adr_o),
-    .wbs_dat_o (wb_gpio0_dat_o),
-    .wbs_sel_o (wb_gpio0_sel_o),
-    .wbs_we_o  (wb_gpio0_we_o),
-    .wbs_cyc_o (wb_gpio0_cyc_o),
-    .wbs_stb_o (wb_gpio0_stb_o),
-    .wbs_cti_o (wb_gpio0_cti_o),
-    .wbs_bte_o (wb_gpio0_bte_o),
-    .wbs_dat_i (wb_gpio0_dat_i),
-    .wbs_ack_i (wb_gpio0_ack_i),
-    .wbs_err_i (wb_gpio0_err_i),
-    .wbs_rty_i (wb_gpio0_rty_i));
-
 endmodule
diff --git a/systems/de2/rtl/verilog/wb_intercon.vh b/systems/de2/rtl/verilog/wb_intercon.vh
old mode 100755
new mode 100644
index e81420ee..cc8a6714
--- a/systems/de2/rtl/verilog/wb_intercon.vh
+++ b/systems/de2/rtl/verilog/wb_intercon.vh
@@ -46,18 +46,6 @@ wire [31:0] wb_s2m_uart0_dat;
 wire        wb_s2m_uart0_ack;
 wire        wb_s2m_uart0_err;
 wire        wb_s2m_uart0_rty;
-wire [31:0] wb_m2s_sdram_dbus_adr;
-wire [31:0] wb_m2s_sdram_dbus_dat;
-wire  [3:0] wb_m2s_sdram_dbus_sel;
-wire        wb_m2s_sdram_dbus_we;
-wire        wb_m2s_sdram_dbus_cyc;
-wire        wb_m2s_sdram_dbus_stb;
-wire  [2:0] wb_m2s_sdram_dbus_cti;
-wire  [1:0] wb_m2s_sdram_dbus_bte;
-wire [31:0] wb_s2m_sdram_dbus_dat;
-wire        wb_s2m_sdram_dbus_ack;
-wire        wb_s2m_sdram_dbus_err;
-wire        wb_s2m_sdram_dbus_rty;
 wire [31:0] wb_m2s_gpio0_adr;
 wire [31:0] wb_m2s_gpio0_dat;
 wire  [3:0] wb_m2s_gpio0_sel;
@@ -70,6 +58,18 @@ wire [31:0] wb_s2m_gpio0_dat;
 wire        wb_s2m_gpio0_ack;
 wire        wb_s2m_gpio0_err;
 wire        wb_s2m_gpio0_rty;
+wire [31:0] wb_m2s_sdram_dbus_adr;
+wire [31:0] wb_m2s_sdram_dbus_dat;
+wire  [3:0] wb_m2s_sdram_dbus_sel;
+wire        wb_m2s_sdram_dbus_we;
+wire        wb_m2s_sdram_dbus_cyc;
+wire        wb_m2s_sdram_dbus_stb;
+wire  [2:0] wb_m2s_sdram_dbus_cti;
+wire  [1:0] wb_m2s_sdram_dbus_bte;
+wire [31:0] wb_s2m_sdram_dbus_dat;
+wire        wb_s2m_sdram_dbus_ack;
+wire        wb_s2m_sdram_dbus_err;
+wire        wb_s2m_sdram_dbus_rty;
 wire [31:0] wb_m2s_rom0_adr;
 wire [31:0] wb_m2s_rom0_dat;
 wire  [3:0] wb_m2s_rom0_sel;
@@ -146,18 +146,6 @@ wb_intercon wb_intercon0
     .wb_uart0_ack_i      (wb_s2m_uart0_ack),
     .wb_uart0_err_i      (wb_s2m_uart0_err),
     .wb_uart0_rty_i      (wb_s2m_uart0_rty),
-    .wb_sdram_dbus_adr_o (wb_m2s_sdram_dbus_adr),
-    .wb_sdram_dbus_dat_o (wb_m2s_sdram_dbus_dat),
-    .wb_sdram_dbus_sel_o (wb_m2s_sdram_dbus_sel),
-    .wb_sdram_dbus_we_o  (wb_m2s_sdram_dbus_we),
-    .wb_sdram_dbus_cyc_o (wb_m2s_sdram_dbus_cyc),
-    .wb_sdram_dbus_stb_o (wb_m2s_sdram_dbus_stb),
-    .wb_sdram_dbus_cti_o (wb_m2s_sdram_dbus_cti),
-    .wb_sdram_dbus_bte_o (wb_m2s_sdram_dbus_bte),
-    .wb_sdram_dbus_dat_i (wb_s2m_sdram_dbus_dat),
-    .wb_sdram_dbus_ack_i (wb_s2m_sdram_dbus_ack),
-    .wb_sdram_dbus_err_i (wb_s2m_sdram_dbus_err),
-    .wb_sdram_dbus_rty_i (wb_s2m_sdram_dbus_rty),
     .wb_gpio0_adr_o      (wb_m2s_gpio0_adr),
     .wb_gpio0_dat_o      (wb_m2s_gpio0_dat),
     .wb_gpio0_sel_o      (wb_m2s_gpio0_sel),
@@ -170,6 +158,18 @@ wb_intercon wb_intercon0
     .wb_gpio0_ack_i      (wb_s2m_gpio0_ack),
     .wb_gpio0_err_i      (wb_s2m_gpio0_err),
     .wb_gpio0_rty_i      (wb_s2m_gpio0_rty),
+    .wb_sdram_dbus_adr_o (wb_m2s_sdram_dbus_adr),
+    .wb_sdram_dbus_dat_o (wb_m2s_sdram_dbus_dat),
+    .wb_sdram_dbus_sel_o (wb_m2s_sdram_dbus_sel),
+    .wb_sdram_dbus_we_o  (wb_m2s_sdram_dbus_we),
+    .wb_sdram_dbus_cyc_o (wb_m2s_sdram_dbus_cyc),
+    .wb_sdram_dbus_stb_o (wb_m2s_sdram_dbus_stb),
+    .wb_sdram_dbus_cti_o (wb_m2s_sdram_dbus_cti),
+    .wb_sdram_dbus_bte_o (wb_m2s_sdram_dbus_bte),
+    .wb_sdram_dbus_dat_i (wb_s2m_sdram_dbus_dat),
+    .wb_sdram_dbus_ack_i (wb_s2m_sdram_dbus_ack),
+    .wb_sdram_dbus_err_i (wb_s2m_sdram_dbus_err),
+    .wb_sdram_dbus_rty_i (wb_s2m_sdram_dbus_rty),
     .wb_rom0_adr_o       (wb_m2s_rom0_adr),
     .wb_rom0_dat_o       (wb_m2s_rom0_dat),
     .wb_rom0_sel_o       (wb_m2s_rom0_sel),