Note About Vivado Resource Sharing

[calebmkim]

Just a quick note about resource sharing in Vivado.

If you have a large Calyx design, you should map memories to map to either URAM or BRAM. This requires using seq_mems in Calyx instead of std_mems. Also, the device you are targeting should support URAM/BRAM. Since havarti gets alveo boards, I used the specific part name xcu250-figd2104-2-e.

The reason why you want to map memories to URAM/BRAM is because it significantly speeds up how long resource estimates take. LeNet w/ memories mapped to URAM and targeting alveo boards takes about 10 minutes to get resource estimates, whereas LeNet w/ out memories mapped to URAM and targeting a smaller board takes > 24 hours to get resource estimates.

[rachitnigam]

Woo! Makes a lot of sense and this makes a strong case for deprecating std_mem completely in my opinion