Getting set up with Calyx #1356
Replies: 1 comment 4 replies
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I'll take a stab at answering a few of these, though @rachitnigam may need to chime in as well. 1
So Invoke, to the best of my knowledge, was added after the original paper. The basic idea is that Invoke fulfills a sort of function call like roll in the language and is the sort of defacto way for working with Calyx defined sub-components since it frees the user from needing to manually interact with the go-done interface. It is also possible to use invoke with primitives which can make for easier analyses on certain groups with clearly defined rolls (e.g. write this value to this register). Currently (please correct me if I'm wrong @rachitnigam) I believe it is the only way to use sub-components with Thanks for the note about the language reference! If you wouldn't mind opening an issue that would be helpful, otherwise I can try to open one a bit later. 2
Hmm, I am not sure what the prevailing attitude is on this, but there are two possible apporaches to take. Either these can be added to the list of reserved keywords or the iverilog backend could be adjusted to check for naming conflicts only when being output to verilog. @rachitnigam thoughts? Regardless, please open an issue with the keywords you ran into so we can either resolve this or make a proper error! 3
This is currently not supported. Though there is nothing preventing it from being added in the long term! If this would be useful to you, please open an issue! |
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Hello!
I've started experimenting with Calyx recently and I've accumulated some questions while setting things up. Also, I've encountered a few (minor) issues with the instructions which I've noted below. Hopefully the latter is useful.
Questions
invoke
. I don't see it mentioned in the original Calyx paper; all the examples there appear to use the go-done interface directly. I understand that it is used for passing cells by reference. In what other cases is it necessary? Or is it just syntactic sugar? Interestingly the group2invoke pass seems to transform in the opposite direction, but Implement group2invoke pass #679 indicates that this is done only to make analysis easier. As an aside, the format ofref cells
,inputs
, andoutputs
isn't specified in the Language Reference (there are examples elsewhere in the documentation, but it would be helpful to have it fully specified here).iverilog
when using port names in Calyx that are reserved words in SystemVerilog. Are these intended to be reserved words in Calyx as well? I don't recall seeing any mention of such in the documentation.std_const
.)Thanks!
Issues
Also, in case these notes are helpful...
while
refers only to the port being non-zero. This reads to me as though multi-bit ports are allowed, but experimentation (and the original Calyx paper) indicates that this is not the case. When running with Icarus Verilog it appears that the port is silently sliced; when running with the interpreter, the interpreter panics. I think it would be good to clarify in the docs (or, better perhaps, to add compiler warnings where appropriate).fud config global.futil_directory <path>
needs to be run with--create
.$HOME/.vscode/extensions/extensions.json
does not get updated even after a restart). I was able to install via the Command Palette usingDeveloper: Install Extension from Location...
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