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@Mark1626 this is unbelievably exciting!!! We've discussed adding posit support to Calyx internally for a while but hadn't had the time. It is super exciting to see the prototype working. A couple of recommendations:
Apart from that, a couple of relevant ongoing efforts:
I'm curious to hear what you think the next steps are but overall, I'd be super excited to figure out how to upstream these changes and use them with various Calyx frontends. |
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I'm having a limitation if I'm converting Chisel to SV to use in my bindings. All my module names are the same so I can either have a 32 or 64 bit (or 8/16 bit) posits. As far as I know Chisel doesn't have a way to create Verilog module parameters.
Is there anything in the FIRRTL backend that can help with this? I'm curious if this came up for #1928 , as the hardfloat repo is also in Chisel. |
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Background:
Unum-III/Posits is a number format that is similar to IEEE 754 format. It can be used as a drop in replacement for floats. Posits are hardware friendly to implement and are accurate than floats.
I'm the maintainer of Chisel hardposit. This repo is a Chisel HDL based implementation of Posits. It's part of the work my research group did for CARRV20
Posit accelerators generated using Calyx
What I have been doing
My goal was to create accelerators with the Calyx infrastructure that would use Posits. So I made Calyx bindings for the RTL generated from Chisel. These bindings would then be emitted from a Calyx frontend like Dahlia. This could be either generated when using a custom datatype or float could be swapped to use posits.
PoC replacing floats in Dahlia with posits
To test these binding I added support for floats in Dahlia (in my fork) when targeting the Calyx back-end. This will generate my Calyx binding of the RTL Posit blocks when using floats.
eg) When the following Dahlia code targets the Calyx backend
fuse scratch.fuse --lower -b calyx
It would generate Calyx IR, with
Simulation and Synthesis
This worked out of the box, I managed to get it running in simulation with Verilator. I'm current exploring how I can put this on an FPGA.
Observation
Chisel <--> Calyx
Chisel
when exported from
Chisel->FIRRTL->SV
In my Calyx binding I have to define a fixed 32 bit-width. Further in my case I will be having a separate binding for 16bit and 64bit posits, but the primitive names are all going to be
PositAdd
.Questions
There are a couple of experiments that I'm running right now, which I will be making public once it's done. I'll be happy to discuss and share more information about this.
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